From: andy.hu <andy.hu@starfivetech.com>
Date: Sun, 24 Apr 2022 13:55:18 +0000 (+0000)
Subject: Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=279522d7c9af2e41da929a7b3c54318e44396ef7;p=platform%2Fkernel%2Flinux-starfive.git

Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'

risv:dts:starfive:Add timer clocktree

See merge request sdk/sft-riscvpi-linux-5.10!26
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279522d7c9af2e41da929a7b3c54318e44396ef7