From: Alex Deucher Date: Tue, 17 Jul 2012 18:02:43 +0000 (-0400) Subject: drm/radeon: fix up pll selection on DCE5/6 X-Git-Tag: v3.12-rc1~2665^2~34^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=26fe45a0a76f165425f332a5aaa298f149f9db22;p=kernel%2Fkernel-generic.git drm/radeon: fix up pll selection on DCE5/6 Selecting ATOM_PPLL_INVALID should be equivalent as the DCPLL or PPLL0 are already programmed for the DISPCLK, but the preferred method is to always specify the PLL selected. SetPixelClock will check the parameters and skip the programming if the PLL is already set up. Signed-off-by: Alex Deucher Reviewed-by: Christian König --- diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 3904d79..bbbeb98 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1539,7 +1539,11 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) * crtc virtual pixel clock. */ if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { - if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) + if (ASIC_IS_DCE5(rdev)) + return ATOM_DCPLL; + else if (ASIC_IS_DCE6(rdev)) + return ATOM_PPLL0; + else if (rdev->clock.dp_extclk) return ATOM_PPLL_INVALID; } }