From: Aaron Sierra <asierra@xes-inc.com>
Date: Fri, 15 Aug 2014 21:07:48 +0000 (-0500)
Subject: fsl_ifc: Fix csor_ext position in fsl_ifc_regs
X-Git-Tag: v4.9.8~5473^2~44^2~21
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=26ae4980b5e4739af93543a147facb421fb78ae8;p=platform%2Fkernel%2Flinux-rpi3.git

fsl_ifc: Fix csor_ext position in fsl_ifc_regs

According to Freescale manuals, the IFC_CSORn_EXT register is located
immediately _after_ the bank's IFC_CSORn register.

This patch adjusts the csor_ext member of and reserved register arrays
immediately surrounding the csor_cs structure to provide proper access
to this register.

Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Acked-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---

diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index f49ddb1..84d60cb 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -781,13 +781,13 @@ struct fsl_ifc_regs {
 		__be32 amask;
 		u32 res4[0x2];
 	} amask_cs[FSL_IFC_BANK_COUNT];
-	u32 res5[0x17];
+	u32 res5[0x18];
 	struct {
-		__be32 csor_ext;
 		__be32 csor;
+		__be32 csor_ext;
 		u32 res6;
 	} csor_cs[FSL_IFC_BANK_COUNT];
-	u32 res7[0x19];
+	u32 res7[0x18];
 	struct {
 		__be32 ftim[4];
 		u32 res8[0x8];