From: Zong Li Date: Wed, 9 Dec 2020 09:49:15 +0000 (+0800) Subject: clk: sifive: Fix the wrong bit field shift X-Git-Tag: accepted/tizen/unified/20230118.172025~8196^2~2^4~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=263ac3908516abb0392747bbf595af2b13df5fa2;p=platform%2Fkernel%2Flinux-rpi.git clk: sifive: Fix the wrong bit field shift The clk enable bit should be 31 instead of 24. Signed-off-by: Zong Li Reported-by: Pragnesh Patel Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 7e509df..88493f3 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -59,7 +59,7 @@ /* DDRPLLCFG1 */ #define PRCI_DDRPLLCFG1_OFFSET 0x10 -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) /* GEMGXLPLLCFG0 */ @@ -81,7 +81,7 @@ /* GEMGXLPLLCFG1 */ #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) /* CORECLKSEL */