From: sunghan <sh924.chang@samsung.com>
Date: Thu, 30 Mar 2017 06:01:33 +0000 (+0900)
Subject: refactoring programming scripts for sidk_s5jt200
X-Git-Tag: 1.1_Public_Release~640
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=263291d58d30d48b47137ebb0ddc718c2f5c2b4c;p=rtos%2Ftinyara.git

refactoring programming scripts for sidk_s5jt200

remove CR, spaces and codes
---

diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4.cfg
index 831042f..1b58605 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4.cfg
@@ -1,65 +1,65 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-#gdb_memory_map enable
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-$_TARGETNAME configure -event gdb-attach { cortex_r4 dbginit }
-
-gdb_breakpoint_override hard
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cortex_r4 maskisr on
-	gdb_breakpoint_override on
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+#gdb_memory_map enable
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+$_TARGETNAME configure -event gdb-attach { cortex_r4 dbginit }
+
+gdb_breakpoint_override hard
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cortex_r4 maskisr on
+	gdb_breakpoint_override on
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4_debug.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4_debug.cfg
index df35e09..2356cf9 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4_debug.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_attach_cr4_debug.cfg
@@ -1,68 +1,68 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-#gdb_memory_map enable
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-$_TARGETNAME configure -event gdb-attach { cortex_r4 dbginit }
-
-gdb_breakpoint_override hard
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cortex_r4 maskisr on
-	gdb_breakpoint_override on
-
-	# set entry address
-	reg pc 0x04004060
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+#gdb_memory_map enable
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+$_TARGETNAME configure -event gdb-attach { cortex_r4 dbginit }
+
+gdb_breakpoint_override hard
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cortex_r4 maskisr on
+	gdb_breakpoint_override on
+
+	# set entry address
+	reg pc 0x04004060
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_all_fota.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_all_fota.cfg
index 722b206..5a21fc3 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_all_fota.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_all_fota.cfg
@@ -1,6 +1,6 @@
 ###########################################################################
 #
-# Copyright 2016 Samsung Electronics All Rights Reserved.
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -163,7 +163,7 @@ proc fusing_image_boot {} {
 
 proc fusing_image_os_ota0 {} {
 	echo "----------------------------------------------------------------------"
-	echo "Fusing Tinyara OTA0"
+	echo "Fusing TinyAra OTA0"
 	echo "----------------------------------------------------------------------"
 	set OS_PATH "../../../output/bin/tinyara_head.bin"
 	load_image $OS_PATH 0x6000C000
@@ -190,7 +190,7 @@ proc fusing_image_wlan {} {
 
 proc fusing_image_os_ota1 {} {
 	echo "----------------------------------------------------------------------"
-	echo "Fusing Tinyara OTA1"
+	echo "Fusing TinyAra OTA1"
 	echo "----------------------------------------------------------------------"
 	set OS_PATH "../../../output/bin/tinyara_ota1_head.bin"
 	load_image $OS_PATH 0x60400000
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_romfs.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_romfs.cfg
index 44b3559..b5bb83c 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_romfs.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_romfs.cfg
@@ -1,146 +1,146 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cmu_init
-	enable_region
-	flash_erase_romfs
-	fusing_image_romfs
-	reset
-	shutdown
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc flash_erase_romfs {} {
-	echo "Erase ROMFS region @ mirror_addr 0x60690000 (phy_addr:0x04690000) size 512K"
-	echo "Please confirm romfs partition phy addr in bootup log"
-	flash_erase 0x60690000 0x80000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
-
-proc fusing_image_romfs {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing ROMFS @ mirror_addr 0x60690000 (phy_addr:0x04690000) "
-	echo "----------------------------------------------------------------------"
-	set ROMFS_PATH "../../../../../tinyara/build/output/bin/romfs.img"
-	load_image $ROMFS_PATH 0x60690000
-	echo "Done"
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cmu_init
+	enable_region
+	flash_erase_romfs
+	fusing_image_romfs
+	reset
+	shutdown
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc flash_erase_romfs {} {
+	echo "Erase ROMFS region @ mirror_addr 0x60690000 (phy_addr:0x04690000) size 512K"
+	echo "Please confirm romfs partition phy addr in bootup log"
+	flash_erase 0x60690000 0x80000
+}
+
+proc flash_erase {write_addr write_size} {
+	global flash_write_addr flash_base target_addr end_addr
+	set flash_write_addr $write_addr
+	set flash_base 0x04000000
+	set target_addr [expr $flash_write_addr-$flash_base]
+	set end_addr [expr $target_addr+$write_size]
+	while {$target_addr<$end_addr} {
+		mww 0x80310010 $target_addr
+		mwb 0x8031005E 0xff
+		set target_addr [expr $target_addr+0x1000]
+		flash_erase_wait
+	}
+}
+
+proc flash_erase_wait {} {
+	set SFLASH_RDSR	0x803100dc
+	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	mem2array value 32 $reg 1
+	return $value(0)
+}
+
+proc fusing_image_romfs {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing ROMFS @ mirror_addr 0x60690000 (phy_addr:0x04690000) "
+	echo "----------------------------------------------------------------------"
+	set ROMFS_PATH "../../../output/bin/romfs.img"
+	load_image $ROMFS_PATH 0x60690000
+	echo "Done"
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota0.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota0.cfg
index 0b03f9a..751e778 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota0.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota0.cfg
@@ -1,6 +1,6 @@
 ###########################################################################
 #
-# Copyright 2016 Samsung Electronics All Rights Reserved.
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -151,7 +151,7 @@ proc mrb {reg} {
 
 proc fusing_image_os_ota0 {} {
 	echo "----------------------------------------------------------------------"
-	echo "Fusing Tinyara OTA0"
+	echo "Fusing TinyAra OTA0"
 	echo "----------------------------------------------------------------------"
 	set OS_PATH "../../../output/bin/tinyara_head.bin"
 	load_image $OS_PATH 0x6000C000
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota1.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota1.cfg
index c3b60a1..baf9199 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota1.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_evt0_flash_tinyara_ota1.cfg
@@ -1,6 +1,6 @@
 ###########################################################################
 #
-# Copyright 2016 Samsung Electronics All Rights Reserved.
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -151,7 +151,7 @@ proc mrb {reg} {
 
 proc fusing_image_os_ota1 {} {
 	echo "----------------------------------------------------------------------"
-	echo "Fusing Tinyara OTA1"
+	echo "Fusing TinyAra OTA1"
 	echo "----------------------------------------------------------------------"
 	set OS_PATH "../../../output/bin/tinyara_ota1_head.bin"
 	load_image $OS_PATH 0x60400000
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_boot_tinyara.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_boot_tinyara.cfg
index 743fb19..f3cfb61 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_boot_tinyara.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_boot_tinyara.cfg
@@ -1,167 +1,166 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { 	
-	echo "GDB connected.."		
-}
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	halt
-	#reg	
-	flash_init
-	flash_erase_boot	
-	flash_erase_os	
-	sleep 500		
-	fusing_image_os	
-	reg pc 0x04004020
-	echo "now Attach GDB..(gdb target remote localhost:3333"
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc flash_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash initialize"
-	echo "----------------------------------------------------------------------"
-	mww	0x80040020 0x00222222
-	mww	0x80040028 0x00333333
-	sleep 100
-	mww	0x80310004 0x8010001A
-	echo "Done"
-}
-
-proc flash_erase_boot {} {
-	echo "erase bootloader in flash"
-	flash_erase 0x04000000 0x4000
-}
-
-proc flash_erase_os {} {
-	echo "erase flash 2MB for tinyara_head.bin, check bin size"
-	flash_erase 0x04004000 0x200000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
-
-proc fusing_image_os {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing Tinyara"
-	echo "----------------------------------------------------------------------"
-	set OS_PATH "../../../bin/tinyara_head.bin"
-	load_image $OS_PATH 0x0400C000
-	echo "Done"
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init {
+	echo "GDB connected.."
+}
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	halt
+	flash_init
+	flash_erase_boot
+	flash_erase_os
+	sleep 500
+	fusing_image_os
+	reg pc 0x04004020
+	echo "now Attach GDB..(gdb target remote localhost:3333"
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc flash_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash initialize"
+	echo "----------------------------------------------------------------------"
+	mww	0x80040020 0x00222222
+	mww	0x80040028 0x00333333
+	sleep 100
+	mww	0x80310004 0x8010001A
+	echo "Done"
+}
+
+proc flash_erase_boot {} {
+	echo "erase bootloader in flash"
+	flash_erase 0x04000000 0x4000
+}
+
+proc flash_erase_os {} {
+	echo "erase flash 2MB for tinyara_head.bin, check bin size"
+	flash_erase 0x04004000 0x200000
+}
+
+proc flash_erase {write_addr write_size} {
+	global flash_write_addr flash_base target_addr end_addr
+	set flash_write_addr $write_addr
+	set flash_base 0x04000000
+	set target_addr [expr $flash_write_addr-$flash_base]
+	set end_addr [expr $target_addr+$write_size]
+	while {$target_addr<$end_addr} {
+		mww 0x80310010 $target_addr
+		mwb 0x8031005E 0xff
+		set target_addr [expr $target_addr+0x1000]
+		flash_erase_wait
+	}
+}
+
+proc flash_erase_wait {} {
+	set SFLASH_RDSR	0x803100dc
+	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	mem2array value 32 $reg 1
+	return $value(0)
+}
+
+proc fusing_image_os {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing TinyAra"
+	echo "----------------------------------------------------------------------"
+	set OS_PATH "../../../output/bin/tinyara_head.bin"
+	load_image $OS_PATH 0x0400C000
+	echo "Done"
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_all.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_all.cfg
index 7ecb8db..cc8f85f 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_all.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_all.cfg
@@ -1,167 +1,167 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 3000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cmu_init
-	enable_region
-	flash_init
-	flash_erase_all
-	reset
-	shutdown
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc flash_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash initialize"
-	echo "----------------------------------------------------------------------"
-	mww	0x80040020 0x00222222
-	mww	0x80040028 0x00333333
-	sleep 100
-	mww	0x80310004 0x8010001A
-	echo "Done"
-}
-
-proc flash_erase_all {} {
-	echo "----------------------------------------------------------------------"
-	echo "Flash erase"
-	echo "----------------------------------------------------------------------"
-	flash_erase_boot
-	flash_erase_os
-	flash_erase_wlan
-	echo "Done"
-}
-
-proc flash_erase_boot {} {
-	echo "erase bootloader in flash"
-	flash_erase 0x60000000 0x4000
-}
-
-proc flash_erase_os {} {
-	echo "erase flash 3MB for tinyara_head.bin, check bin size"
-	flash_erase 0x60004000 0x300000
-}
-
-proc flash_erase_wlan {} {
-	echo "erase WLAN F/W region"
-	flash_erase 0x60304000 0x80000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 3000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cmu_init
+	enable_region
+	flash_init
+	flash_erase_all
+	reset
+	shutdown
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc flash_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash initialize"
+	echo "----------------------------------------------------------------------"
+	mww	0x80040020 0x00222222
+	mww	0x80040028 0x00333333
+	sleep 100
+	mww	0x80310004 0x8010001A
+	echo "Done"
+}
+
+proc flash_erase_all {} {
+	echo "----------------------------------------------------------------------"
+	echo "Flash erase"
+	echo "----------------------------------------------------------------------"
+	flash_erase_boot
+	flash_erase_os
+	flash_erase_wlan
+	echo "Done"
+}
+
+proc flash_erase_boot {} {
+	echo "erase bootloader in flash"
+	flash_erase 0x60000000 0x4000
+}
+
+proc flash_erase_os {} {
+	echo "erase flash 3MB for tinyara_head.bin, check bin size"
+	flash_erase 0x60004000 0x300000
+}
+
+proc flash_erase_wlan {} {
+	echo "erase WLAN F/W region"
+	flash_erase 0x60304000 0x80000
+}
+
+proc flash_erase {write_addr write_size} {
+	global flash_write_addr flash_base target_addr end_addr
+	set flash_write_addr $write_addr
+	set flash_base 0x04000000
+	set target_addr [expr $flash_write_addr-$flash_base]
+	set end_addr [expr $target_addr+$write_size]
+	while {$target_addr<$end_addr} {
+		mww 0x80310010 $target_addr
+		mwb 0x8031005E 0xff
+		set target_addr [expr $target_addr+0x1000]
+		flash_erase_wait
+	}
+}
+
+proc flash_erase_wait {} {
+	set SFLASH_RDSR	0x803100dc
+	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	mem2array value 32 $reg 1
+	return $value(0)
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_boot.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_boot.cfg
index c940de0..7d5aa46 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_boot.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_boot.cfg
@@ -1,147 +1,147 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cmu_init
-	enable_region
-	flash_init
-	flash_erase_boot
-	reset
-	shutdown
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc flash_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash initialize"
-	echo "----------------------------------------------------------------------"
-	mww	0x80040020 0x00222222
-	mww	0x80040028 0x00333333
-	sleep 100
-	mww	0x80310004 0x8010001A
-	echo "Done"
-}
-
-proc flash_erase_boot {} {
-	echo "erase bootloader in flash"
-	flash_erase 0x60000000 0x4000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cmu_init
+	enable_region
+	flash_init
+	flash_erase_boot
+	reset
+	shutdown
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc flash_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash initialize"
+	echo "----------------------------------------------------------------------"
+	mww	0x80040020 0x00222222
+	mww	0x80040028 0x00333333
+	sleep 100
+	mww	0x80310004 0x8010001A
+	echo "Done"
+}
+
+proc flash_erase_boot {} {
+	echo "erase bootloader in flash"
+	flash_erase 0x60000000 0x4000
+}
+
+proc flash_erase {write_addr write_size} {
+	global flash_write_addr flash_base target_addr end_addr
+	set flash_write_addr $write_addr
+	set flash_base 0x04000000
+	set target_addr [expr $flash_write_addr-$flash_base]
+	set end_addr [expr $target_addr+$write_size]
+	while {$target_addr<$end_addr} {
+		mww 0x80310010 $target_addr
+		mwb 0x8031005E 0xff
+		set target_addr [expr $target_addr+0x1000]
+		flash_erase_wait
+	}
+}
+
+proc flash_erase_wait {} {
+	set SFLASH_RDSR	0x803100dc
+	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	mem2array value 32 $reg 1
+	return $value(0)
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_tinyara.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_tinyara.cfg
index 27ba2cb..424c948 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_tinyara.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_flash_erase_tinyara.cfg
@@ -1,157 +1,157 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 3000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cmu_init
-	enable_region
-	flash_init
-	flash_erase_os
-	reset
-	shutdown
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc flash_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash initialize"
-	echo "----------------------------------------------------------------------"
-	mww	0x80040020 0x00222222
-	mww	0x80040028 0x00333333
-	sleep 100
-	mww	0x80310004 0x8010001A
-	echo "Done"
-}
-
-proc flash_chiperase {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash Chiperase(Entire flash)"
-	echo "----------------------------------------------------------------------"
-	mww 0x803100CE 0xFF
-
-	flash_erase_wait
-	echo "Done"
-}
-
-proc flash_erase_os {} {
-	echo "erase flash 3MB for tinyara_head.bin, check bin size"
-	flash_erase 0x60004000 0x300000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 3000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cmu_init
+	enable_region
+	flash_init
+	flash_erase_os
+	reset
+	shutdown
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc flash_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash initialize"
+	echo "----------------------------------------------------------------------"
+	mww	0x80040020 0x00222222
+	mww	0x80040028 0x00333333
+	sleep 100
+	mww	0x80310004 0x8010001A
+	echo "Done"
+}
+
+proc flash_chiperase {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash Chiperase(Entire flash)"
+	echo "----------------------------------------------------------------------"
+	mww 0x803100CE 0xFF
+
+	flash_erase_wait
+	echo "Done"
+}
+
+proc flash_erase_os {} {
+	echo "erase flash 3MB for tinyara_head.bin, check bin size"
+	flash_erase 0x60004000 0x300000
+}
+
+proc flash_erase {write_addr write_size} {
+	global flash_write_addr flash_base target_addr end_addr
+	set flash_write_addr $write_addr
+	set flash_base 0x04000000
+	set target_addr [expr $flash_write_addr-$flash_base]
+	set end_addr [expr $target_addr+$write_size]
+	while {$target_addr<$end_addr} {
+		mww 0x80310010 $target_addr
+		mwb 0x8031005E 0xff
+		set target_addr [expr $target_addr+0x1000]
+		flash_erase_wait
+	}
+}
+
+proc flash_erase_wait {} {
+	set SFLASH_RDSR	0x803100dc
+	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	mem2array value 32 $reg 1
+	return $value(0)
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_all.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_all.cfg
index baa2f4d..b189cb8 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_all.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_all.cfg
@@ -1,313 +1,237 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	wdt_disable
-	cmu_init
-	enable_region
-	flash_init
-	#flash_erase_all
-	flash_chiperase
-	#set scriptDir [ getScriptDirectory ]
-	fusing_image_all
-	reset
-}
-
-proc s5j_set_ft2232_serial { arg1 } {
-	echo "----------------------------------------------------------------------"
-	echo "set serial number $arg1"
-	echo "----------------------------------------------------------------------"	
-	ft2232_serial $arg1	
-}
-
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc wdt_disable {} {
-	echo "----------------------------------------------------------------------"
-	echo "DISABLE Watchdog reset"
-	echo "----------------------------------------------------------------------"
-	mww 0x80030000 0x00000000
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-#initialize mpu setting
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x1
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x2
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x3
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x5
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x6
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x7
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x8
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0x9
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0xA
-	arm mcr 15 0 6 1 2 0x8
-	arm mcr 15 0 6 2 0 0xB
-	arm mcr 15 0 6 1 2 0x8	
-	
-	
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-	
-	
-}
-
-proc flash_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash initialize"
-	echo "----------------------------------------------------------------------"
-	mww	0x80040020 0x00222222
-	mww	0x80040028 0x00333333
-	sleep 100
-	mww	0x80310004 0x8010000A
-	echo "Done"
-}
-
-proc flash_chiperase {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash Chiperase(Entire flash)"
-	echo "----------------------------------------------------------------------"
-	mwb 0x803100CE 0xFF
-	
-	flash_erase_wait_echo_sec
-	echo "Done"
-}
-
-proc flash_erase_all {} {
-	echo "----------------------------------------------------------------------"
-	echo "Flash erase"
-	echo "----------------------------------------------------------------------"
-	flash_erase_boot
-	flash_erase_os
-	flash_erase_sss
-	flash_erase_wlan
-	echo "Done"
-}
-
-proc flash_erase_boot {} {
-	echo "erase bootloader in flash"
-	flash_erase 0x60000000 0x4000
-}
-
-proc flash_erase_os {} {
-	echo "erase flash 3MB for tinyara_head.bin, check bin size"
-	flash_erase 0x6000C000 0x2F8000
-}
-
-proc flash_erase_sss {} {
-	echo "erase SSS F/W region"
-	flash_erase 0x602FC000 0x8000
-}
-
-proc flash_erase_wlan {} {
-	echo "erase WLAN F/W region"
-	flash_erase 0x60304000 0x80000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrb $SFLASH_RDSR] & 0x01] != 0} {sleep 1}
-}
-
-proc flash_erase_wait_echo_sec {} {
-	set SFLASH_RDSR	0x803100dc
-	global count
-	set count 0
-	while {[expr [mrb $SFLASH_RDSR] & 0x01] != 0} {
-		sleep 1000
-		set count [expr $count+1]
-		echo "please wait ($count)sec"
-	}
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
-
-# mrb: "memory read byte", returns value of $reg
-proc mrb {reg} {
-	set value ""
-	mem2array value 8 $reg 1
-	return $value(0)
-}
-
-proc getScriptDirectory {} {
-	set dispScriptFile [file normalize [info script]]
-	set scriptFolder [file dirname $dispScriptFile]
-	return $scriptFolder
-}
-
-proc fusing_image_all {} {
-	fusing_image_boot
-	fusing_image_os
-	fusing_image_sss
-	fusing_image_wlan
-}
-
-proc fusing_image_boot {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing nBL1"
-	echo "----------------------------------------------------------------------"
-	set BL1_PATH "../boot_bin/t20.nbl1.bin"
-	load_image $BL1_PATH 0x60000000
-	echo "Done"
-
-	echo "----------------------------------------------------------------------"
-	echo "Fusing BL2"
-	echo "----------------------------------------------------------------------"
-	set BL2_PATH "../boot_bin/t20.bl2.head.bin"
-	load_image $BL2_PATH 0x60004000
-	
-	echo "Done"
-}
-
-proc fusing_image_os {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing Tizen RT"
-	echo "----------------------------------------------------------------------"
-	set OS_PATH "../../../output/bin/tinyara_head.bin"
-	load_image $OS_PATH 0x6000C000
-	echo "Done"
-}
-
-proc fusing_image_sss {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing SSS F/W..(size under 32KB)"
-	echo "----------------------------------------------------------------------"
-	set SSS_PATH "../boot_bin/t20.sss.fw.bin"
-	load_image $SSS_PATH 0x602FC000
-	echo "Done"
-}
-
-proc fusing_image_wlan {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing WLAN F/W..(size under 500KB)"
-	echo "----------------------------------------------------------------------"
-	set WLAN_PATH "../boot_bin/t20.wlan.bin"
-	load_image $WLAN_PATH 0x60304000
-	echo "Done"
-}
-
-proc s5jt200_shutdown {} {
-	init
-	catch {halt}
-	echo "s5jt200_shutdown"
-	shutdown
-}
-s5jt200_shutdown
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	wdt_disable
+	cmu_init
+	enable_region
+	flash_init
+	flash_chiperase
+	fusing_image_all
+	reset
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc wdt_disable {} {
+	echo "----------------------------------------------------------------------"
+	echo "DISABLE Watchdog reset"
+	echo "----------------------------------------------------------------------"
+	mww 0x80030000 0x00000000
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+#initialize mpu setting
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x1
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x2
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x3
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x5
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x6
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x7
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x8
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0x9
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0xA
+	arm mcr 15 0 6 1 2 0x8
+	arm mcr 15 0 6 2 0 0xB
+	arm mcr 15 0 6 1 2 0x8
+
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc flash_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash initialize"
+	echo "----------------------------------------------------------------------"
+	mww	0x80040020 0x00222222
+	mww	0x80040028 0x00333333
+	sleep 100
+	mww	0x80310004 0x8010000A
+	echo "Done"
+}
+
+proc flash_chiperase {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash Chiperase(Entire flash)"
+	echo "----------------------------------------------------------------------"
+	mwb 0x803100CE 0xFF
+	
+	flash_erase_wait_echo_sec
+	echo "Done"
+}
+
+proc flash_erase_wait_echo_sec {} {
+	set SFLASH_RDSR	0x803100dc
+	global count
+	set count 0
+	while {[expr [mrb $SFLASH_RDSR] & 0x01] != 0} {
+		sleep 1000
+		set count [expr $count+1]
+		echo "please wait ($count)sec"
+	}
+}
+
+# mrb: "memory read byte", returns value of $reg
+proc mrb {reg} {
+	set value ""
+	mem2array value 8 $reg 1
+	return $value(0)
+}
+
+proc fusing_image_all {} {
+	fusing_image_boot
+	fusing_image_os
+	fusing_image_sss
+	fusing_image_wlan
+}
+
+proc fusing_image_boot {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing nBL1"
+	echo "----------------------------------------------------------------------"
+	set BL1_PATH "../boot_bin/t20.nbl1.bin"
+	load_image $BL1_PATH 0x60000000
+	echo "Done"
+
+	echo "----------------------------------------------------------------------"
+	echo "Fusing BL2"
+	echo "----------------------------------------------------------------------"
+	set BL2_PATH "../boot_bin/t20.bl2.head.bin"
+	load_image $BL2_PATH 0x60004000
+	
+	echo "Done"
+}
+
+proc fusing_image_os {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing TinyAra"
+	echo "----------------------------------------------------------------------"
+	set OS_PATH "../../../output/bin/tinyara_head.bin"
+	load_image $OS_PATH 0x6000C000
+	echo "Done"
+}
+
+proc fusing_image_sss {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing SSS F/W..(size under 32KB)"
+	echo "----------------------------------------------------------------------"
+	set SSS_PATH "../boot_bin/t20.sss.fw.bin"
+	load_image $SSS_PATH 0x602FC000
+	echo "Done"
+}
+
+proc fusing_image_wlan {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing WLAN F/W..(size under 500KB)"
+	echo "----------------------------------------------------------------------"
+	set WLAN_PATH "../boot_bin/t20.wlan.bin"
+	load_image $WLAN_PATH 0x60304000
+	echo "Done"
+}
+
+proc s5jt200_shutdown {} {
+	init
+	catch {halt}
+	echo "s5jt200_shutdown"
+	shutdown
+}
+s5jt200_shutdown
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_boot.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_boot.cfg
index c27f0b4..2b9a45a 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_boot.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_boot.cfg
@@ -1,130 +1,130 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	wdt_disable	
-	cmu_init
-	enable_region
-	fusing_image_boot
-	reset
-	shutdown
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc wdt_disable {} {
-	echo "----------------------------------------------------------------------"
-	echo "DISABLE Watchdog reset"
-	echo "----------------------------------------------------------------------"
-	mww 0x80030000 0x00000000
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc fusing_image_boot {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing nBL1"
-	echo "----------------------------------------------------------------------"
-	set BL1_PATH "../boot_bin/t20.nbl1.bin"
-	load_image $BL1_PATH 0x60000000
-	echo "Done"
-
-	echo "----------------------------------------------------------------------"
-	echo "Fusing BL2"
-	echo "----------------------------------------------------------------------"
-	set BL2_PATH "../boot_bin/t20.bl2.head.bin"
-	load_image $BL2_PATH 0x60004000
-	
-	echo "Done"
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	wdt_disable
+	cmu_init
+	enable_region
+	fusing_image_boot
+	reset
+	shutdown
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc wdt_disable {} {
+	echo "----------------------------------------------------------------------"
+	echo "DISABLE Watchdog reset"
+	echo "----------------------------------------------------------------------"
+	mww 0x80030000 0x00000000
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc fusing_image_boot {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing nBL1"
+	echo "----------------------------------------------------------------------"
+	set BL1_PATH "../boot_bin/t20.nbl1.bin"
+	load_image $BL1_PATH 0x60000000
+	echo "Done"
+
+	echo "----------------------------------------------------------------------"
+	echo "Fusing BL2"
+	echo "----------------------------------------------------------------------"
+	set BL2_PATH "../boot_bin/t20.bl2.head.bin"
+	load_image $BL2_PATH 0x60004000
+	
+	echo "Done"
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_tinyara.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_tinyara.cfg
index 85cbea8..ec13b37 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_tinyara.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_fusing_flash_tinyara.cfg
@@ -1,113 +1,113 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	reset halt
-	cmu_init
-	enable_region
-	fusing_image_os
-	reset
-	shutdown
-}
-
-proc cmu_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "CMU initialize"
-	echo "----------------------------------------------------------------------"
-	mww 0x80081818 0x00000002
-	mww 0x8008181c 0x00000001
-	mww 0x80081814 0x00000001
-	mww 0x80081804 0x00000000
-	mww 0x80081808 0x00000000
-	mww 0x8008180c 0x00000000
-	mww 0x80081810 0x00000000
-	mww 0x80081800 0x00000003
-	mww 0x80080000 0x007f0000
-	mww 0x80080004 0x03104000
-	mww 0x80080014 0x1071bf00
-	mww 0x80081000 0x00000000
-	mww 0x8008100c 0x00000000
-	mww 0x80080180 0x00000010
-	echo "Done"
-}
-
-proc enable_region {} {
-	echo "----------------------------------------------------------------------"
-	echo "Region enable"
-	echo "----------------------------------------------------------------------"
-	arm mcr 15 0 6 2 0 0x0
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x0
-	
-	arm mcr 15 0 6 2 0 0x4
-	arm mcr 15 0 6 1 4 0x300
-	arm mcr 15 0 6 1 2 0x3F
-	arm mcr 15 0 6 1 0 0x60000000
-	
-	arm mcr 15 0 1 0 0 0x00e50879
-	echo "Done"
-}
-
-proc fusing_image_os {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing Tizen RT"
-	echo "----------------------------------------------------------------------"
-	set OS_PATH "../../../output/bin/tinyara_head.bin"
-	load_image $OS_PATH 0x6000C000
-	echo "Done"
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	reset halt
+	cmu_init
+	enable_region
+	fusing_image_os
+	reset
+	shutdown
+}
+
+proc cmu_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "CMU initialize"
+	echo "----------------------------------------------------------------------"
+	mww 0x80081818 0x00000002
+	mww 0x8008181c 0x00000001
+	mww 0x80081814 0x00000001
+	mww 0x80081804 0x00000000
+	mww 0x80081808 0x00000000
+	mww 0x8008180c 0x00000000
+	mww 0x80081810 0x00000000
+	mww 0x80081800 0x00000003
+	mww 0x80080000 0x007f0000
+	mww 0x80080004 0x03104000
+	mww 0x80080014 0x1071bf00
+	mww 0x80081000 0x00000000
+	mww 0x8008100c 0x00000000
+	mww 0x80080180 0x00000010
+	echo "Done"
+}
+
+proc enable_region {} {
+	echo "----------------------------------------------------------------------"
+	echo "Region enable"
+	echo "----------------------------------------------------------------------"
+	arm mcr 15 0 6 2 0 0x0
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x0
+	
+	arm mcr 15 0 6 2 0 0x4
+	arm mcr 15 0 6 1 4 0x300
+	arm mcr 15 0 6 1 2 0x3F
+	arm mcr 15 0 6 1 0 0x60000000
+	
+	arm mcr 15 0 1 0 0 0x00e50879
+	echo "Done"
+}
+
+proc fusing_image_os {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing TinyAra"
+	echo "----------------------------------------------------------------------"
+	set OS_PATH "../../../output/bin/tinyara_head.bin"
+	load_image $OS_PATH 0x6000C000
+	echo "Done"
+}
diff --git a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_sram_boot_tinyara.cfg b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_sram_boot_tinyara.cfg
index de72f95..104bb6d 100644
--- a/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_sram_boot_tinyara.cfg
+++ b/build/configs/sidk_s5jt200/openocd/s5jt200_silicon_evt0_sram_boot_tinyara.cfg
@@ -1,129 +1,128 @@
-###########################################################################
-#
-# Copyright 2016 Samsung Electronics All Rights Reserved.
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific
-# language governing permissions and limitations under the License.
-#
-###########################################################################
-
-# OpenOCD config used to write firmware to
-# S5J internal flash memory via FTDI
-# USB FT2232H (SIDK S5JT200 Board)
-
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-#interface
-interface ft2232
-ft2232_layout "usbjtag"
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232-HS A"
-
-#ft2232_serial SIDK_S5JT200_8A
-reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
-
-set _CHIPNAME s5jt200
-set _ENDIAN little
-set _CPUTAPID 0x4BA00477
-
-adapter_khz 2000
-
-# jtag scan chain
-set _ARM_CR4_JTAGID1 0x3ba00477
-set _ARM_CR4_JTAGID2 0x4ba00477
-set _ARM_CR4_JTAGID3 0x5ba00477
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { 	
-	echo "GDB connected.."		
-}
-
-proc jtag_init {} {
-	debug_level -1
-	global _TARGETNAME
-	jtag_reset 0 0
-	jtag arp_init
-	$_TARGETNAME arp_examine
-	halt
-	wdt_disable		
-	#reg	
-	flash_init
-	flash_erase_boot	
-	fusing_image_os		
-	echo "now Attach GDB..(gdb target remote localhost:3333"
-}
-
-proc wdt_disable {} {
-	echo "----------------------------------------------------------------------"
-	echo "DISABLE Watchdog reset"
-	echo "----------------------------------------------------------------------"
-	mww 0x80030000 0x00000000
-	echo "Done"
-}
-
-proc flash_init {} {
-	echo "----------------------------------------------------------------------"
-	echo "SFlash initialize"
-	echo "----------------------------------------------------------------------"
-	mww	0x80040020 0x00222222
-	mww	0x80040028 0x00333333
-	sleep 100
-	mww	0x80310004 0x8010001A
-	echo "Done"
-}
-
-proc flash_erase_boot {} {
-	echo "erase bootloader in flash"
-	flash_erase 0x04000000 0x4000
-}
-
-proc flash_erase {write_addr write_size} {
-	global flash_write_addr flash_base target_addr end_addr
-	set flash_write_addr $write_addr
-	set flash_base 0x04000000
-	set target_addr [expr $flash_write_addr-$flash_base]
-	set end_addr [expr $target_addr+$write_size]
-	while {$target_addr<$end_addr} {
-		mww 0x80310010 $target_addr
-		mwb 0x8031005E 0xff
-		set target_addr [expr $target_addr+0x1000]
-		flash_erase_wait
-	}
-}
-
-proc flash_erase_wait {} {
-	set SFLASH_RDSR	0x803100dc
-	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
-	set value ""
-	mem2array value 32 $reg 1
-	return $value(0)
-}
-
-proc fusing_image_os {} {
-	echo "----------------------------------------------------------------------"
-	echo "Fusing Tinyara"
-	echo "----------------------------------------------------------------------"
-	set OS_PATH "../../../output/bin/tinyara.bin"
-	load_image $OS_PATH 0x02020000
-	echo "Done"
-}
+###########################################################################
+#
+# Copyright 2016-2017 Samsung Electronics All Rights Reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the License.
+#
+###########################################################################
+
+# OpenOCD config used to write firmware to
+# S5J internal flash memory via FTDI
+# USB FT2232H (SIDK S5JT200 Board)
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_layout "usbjtag"
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS A"
+
+#ft2232_serial SIDK_S5JT200_8A
+reset_config trst_and_srst srst_push_pull srst_nogate connect_assert_srst
+
+set _CHIPNAME s5jt200
+set _ENDIAN little
+set _CPUTAPID 0x4BA00477
+
+adapter_khz 2000
+
+# jtag scan chain
+set _ARM_CR4_JTAGID1 0x3ba00477
+set _ARM_CR4_JTAGID2 0x4ba00477
+set _ARM_CR4_JTAGID3 0x5ba00477
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME cortex_r4 -endian $_ENDIAN -chain-position $_TARGETNAME -dbgbase 0x801E0000
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { 	
+	echo "GDB connected.."		
+}
+
+proc jtag_init {} {
+	debug_level -1
+	global _TARGETNAME
+	jtag_reset 0 0
+	jtag arp_init
+	$_TARGETNAME arp_examine
+	halt
+	wdt_disable
+	flash_init
+	flash_erase_boot
+	fusing_image_os
+	echo "now Attach GDB..(gdb target remote localhost:3333"
+}
+
+proc wdt_disable {} {
+	echo "----------------------------------------------------------------------"
+	echo "DISABLE Watchdog reset"
+	echo "----------------------------------------------------------------------"
+	mww 0x80030000 0x00000000
+	echo "Done"
+}
+
+proc flash_init {} {
+	echo "----------------------------------------------------------------------"
+	echo "SFlash initialize"
+	echo "----------------------------------------------------------------------"
+	mww	0x80040020 0x00222222
+	mww	0x80040028 0x00333333
+	sleep 100
+	mww	0x80310004 0x8010001A
+	echo "Done"
+}
+
+proc flash_erase_boot {} {
+	echo "erase bootloader in flash"
+	flash_erase 0x04000000 0x4000
+}
+
+proc flash_erase {write_addr write_size} {
+	global flash_write_addr flash_base target_addr end_addr
+	set flash_write_addr $write_addr
+	set flash_base 0x04000000
+	set target_addr [expr $flash_write_addr-$flash_base]
+	set end_addr [expr $target_addr+$write_size]
+	while {$target_addr<$end_addr} {
+		mww 0x80310010 $target_addr
+		mwb 0x8031005E 0xff
+		set target_addr [expr $target_addr+0x1000]
+		flash_erase_wait
+	}
+}
+
+proc flash_erase_wait {} {
+	set SFLASH_RDSR	0x803100dc
+	while {[expr [mrw $SFLASH_RDSR] & 0x01] != 0} { sleep 1 }
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	mem2array value 32 $reg 1
+	return $value(0)
+}
+
+proc fusing_image_os {} {
+	echo "----------------------------------------------------------------------"
+	echo "Fusing TinyAra"
+	echo "----------------------------------------------------------------------"
+	set OS_PATH "../../../output/bin/tinyara.bin"
+	load_image $OS_PATH 0x02020000
+	echo "Done"
+}