From: Russell King Date: Fri, 26 Aug 2011 21:44:59 +0000 (+0100) Subject: ARM: pm: avoid writing the auxillary control register for ARMv7 X-Git-Tag: accepted/tizen/common/20141203.182822~6301^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=25904157168ddc8841748a729914f00e53d7e049;p=platform%2Fkernel%2Flinux-arm64.git ARM: pm: avoid writing the auxillary control register for ARMv7 For ARMv7 kernels running in the non-secure world, writing to the auxillary control register causes an abort, so we must avoid directly writing the auxillary control register. If the ACR has already been reinitialized by SoC code, don't try to restore it. Signed-off-by: Russell King --- diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index a773f4e..9049c07 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -248,7 +248,9 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register + teq r4, r10 @ Is it already set? + mcrne p15, 0, r10, c1, c0, 1 @ No, so write it mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR