From: Aleksandr Shaurtaev <38426614+ashaurtaev@users.noreply.github.com>
Date: Wed, 18 Oct 2023 15:31:17 +0000 (+0300)
Subject: [RISC-V] Fix CodeGen::instGen_Set_Reg_To_Imm (#93411)
X-Git-Tag: accepted/tizen/unified/riscv/20231226.055536~30
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=25868e7ff8acd505f9331b0f95fb7854286844e2;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

[RISC-V] Fix CodeGen::instGen_Set_Reg_To_Imm (#93411)
---

diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp
index f2d8efa..a11d3ce 100644
--- a/src/coreclr/jit/codegenriscv64.cpp
+++ b/src/coreclr/jit/codegenriscv64.cpp
@@ -1226,7 +1226,8 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr  size,
 
     if (EA_IS_RELOC(size))
     {
-        NYI_RISCV64("EA_IS_RELOC in instGen_Set_Reg_To_Imm-----unimplemented on RISCV64 yet----");
+        assert(genIsValidIntReg(reg));
+        GetEmitter()->emitIns_R_AI(INS_jal, size, reg, imm);
     }
     else
     {