From: Stephen Boyd <sboyd@kernel.org>
Date: Tue, 16 Feb 2021 22:09:08 +0000 (-0800)
Subject: Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into clk-next
X-Git-Tag: accepted/tizen/unified/20230118.172025~7811^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=242d8cf626877f5fa43d7d574fa39a6b4e9c74a9;p=platform%2Fkernel%2Flinux-rpi.git

Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into clk-next

* clk-mediatek:
  clk: mediatek: mux: Update parent at enable time
  clk: mediatek: mux: Drop unused clock ops
  clk: mediatek: Select all the MT8183 clocks by default

* clk-imx:
  dt-bindings: clock: imx: Switch to my personal address
  MAINTAINERS: Add section for NXP i.MX clock drivers
  clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header
  clk: imx8mn: add clkout1/2 support
  clk: imx8mm: add clkout1/2 support
  clk: imx8mq: add PLL monitor output
  clk: imx: clk-imx31: Remove unused static const table 'uart_clks'
  clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting
  clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems
  clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks

* clk-amlogic:
  clk: meson: axg: Remove MIPI enable clock gate
  clk: meson-axg: remove CLKID_MIPI_ENABLE
  dt-bindings: clock: meson8b: remove non-existing clock macros
  clk: meson: meson8b: remove compatibility code for old .dtbs
  clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
  clk: meson: clk-pll: make "ret" a signed integer
  clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL

* clk-at91:
  clk: at91: Fix the declaration of the clocks
---

242d8cf626877f5fa43d7d574fa39a6b4e9c74a9