From: Marek Olšák <marek.olsak@amd.com>
Date: Fri, 19 Mar 2021 20:05:40 +0000 (-0400)
Subject: ac/surface/tests: test Sienna Cichlid and Navy Flounder
X-Git-Tag: upstream/21.2.3~5052
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=23b2cf032ae733844693a0f67079e3414178510f;p=platform%2Fupstream%2Fmesa.git

ac/surface/tests: test Sienna Cichlid and Navy Flounder

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
---

diff --git a/src/amd/common/ac_surface_test_common.h b/src/amd/common/ac_surface_test_common.h
index 60ac87d..6e961c0 100644
--- a/src/amd/common/ac_surface_test_common.h
+++ b/src/amd/common/ac_surface_test_common.h
@@ -117,6 +117,38 @@ static void init_navi14(struct radeon_info *info)
    info->gb_addr_config = 0x00000043;
 }
 
+static void init_sienna_cichlid(struct radeon_info *info)
+{
+   info->family = CHIP_SIENNA_CICHLID;
+   info->chip_class = GFX10_3;
+   info->family_id = AMDGPU_FAMILY_NV;
+   info->chip_external_rev = 0x28;
+   info->use_display_dcc_unaligned = false;
+   info->use_display_dcc_with_retile_blit = true;
+   info->has_graphics = true;
+   info->tcc_cache_line_size = 128;
+   info->has_rbplus = true;
+   info->rbplus_allowed = true;
+
+   info->gb_addr_config = 0x00000444;
+}
+
+static void init_navy_flounder(struct radeon_info *info)
+{
+   info->family = CHIP_NAVY_FLOUNDER;
+   info->chip_class = GFX10_3;
+   info->family_id = AMDGPU_FAMILY_NV;
+   info->chip_external_rev = 0x32;
+   info->use_display_dcc_unaligned = false;
+   info->use_display_dcc_with_retile_blit = true;
+   info->has_graphics = true;
+   info->tcc_cache_line_size = 128;
+   info->has_rbplus = true;
+   info->rbplus_allowed = true;
+
+   info->gb_addr_config = 0x00000344;
+}
+
 struct testcase {
    const char *name;
    gpu_init_func init;
@@ -138,7 +170,9 @@ static struct testcase testcases[] = {
    {"navi10", init_navi10, 0, 4, 1, 0},
    {"navi10_diff_pipe", init_navi10, 0, 3, 1, 0},
    {"navi10_diff_pkr", init_navi10, 1, 4, 1, 0},
-   {"navi14", init_navi14, 1, 3, 1, 0}
+   {"navi14", init_navi14, 1, 3, 1, 0},
+   {"sienna_cichlid", init_sienna_cichlid},
+   {"navy_flounder", init_navy_flounder},
 };
 
 static struct radeon_info get_radeon_info(struct testcase *testcase)
@@ -153,8 +187,9 @@ static struct radeon_info get_radeon_info(struct testcase *testcase)
    info.max_render_backends = 1u << (testcase->se +
                                      testcase->rb_per_se);
    switch(info.chip_class) {
-   case GFX10:
    case GFX10_3:
+      break;
+   case GFX10:
       info.gb_addr_config = (info.gb_addr_config &
                              C_0098F8_NUM_PIPES &
                              C_0098F8_NUM_PKRS) |