From: Tom Rini Date: Wed, 21 Jun 2017 12:01:07 +0000 (-0400) Subject: Merge branch 'master' of git://git.denx.de/u-boot-samsung X-Git-Tag: v2017.07-rc3~52 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=235c5b8315c6a9eb566fd3d99a098cc6db869fc5;hp=2c62e313b14186d67f5bf26095f36a246cb0c3a4;p=platform%2Fkernel%2Fu-boot.git Merge branch 'master' of git://git.denx.de/u-boot-samsung --- diff --git a/.travis.yml b/.travis.yml index d7094e3..a534743 100644 --- a/.travis.yml +++ b/.travis.yml @@ -194,14 +194,6 @@ matrix: - BUILDMAN="mips" TOOLCHAIN="mips" - env: - - BUILDMAN="mpc512x" - - env: - - BUILDMAN="mpc5xx" - - env: - - BUILDMAN="mpc5xxx" - - env: - - BUILDMAN="mpc8260" - - env: - BUILDMAN="mpc83xx" - env: - BUILDMAN="mpc85xx -x freescale" @@ -218,8 +210,6 @@ matrix: - env: - BUILDMAN="mpc86xx" - env: - - BUILDMAN="mpc8xx" - - env: - BUILDMAN="siemens" - env: - BUILDMAN="tegra" diff --git a/MAINTAINERS b/MAINTAINERS index 0962b47..37cefdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -89,6 +89,7 @@ F: include/dm/platform_data/serial_bcm283x_mu.h ARM FREESCALE IMX M: Stefano Babic +M: Fabio Estevam S: Maintained T: git git://git.denx.de/u-boot-imx.git F: arch/arm/cpu/arm1136/mx*/ @@ -135,6 +136,7 @@ M: Simon Glass S: Maintained T: git git://git.denx.de/u-boot-rockchip.git F: arch/arm/mach-rockchip/ +F: board/rockchip/ ARM SAMSUNG M: Minkyu Kang @@ -320,12 +322,6 @@ M: Wolfgang Denk S: Maintained F: arch/powerpc/ -POWERPC MPC5XXX -M: Wolfgang Denk -S: Maintained -T: git git://git.denx.de/u-boot-mpc5xxx.git -F: arch/powerpc/cpu/mpc5*/ - POWERPC MPC8XX M: Wolfgang Denk S: Maintained @@ -339,8 +335,8 @@ T: git git://git.denx.de/u-boot-mpc82xx.git F: arch/powerpc/cpu/mpc82*/ POWERPC MPC83XX -#M: Kim Phillips -S: Orphaned (Since 2016-02) +M: Mario Six +S: Maintained T: git git://git.denx.de/u-boot-mpc83xx.git F: arch/powerpc/cpu/mpc83xx/ F: arch/powerpc/include/asm/arch-mpc83xx/ diff --git a/Makefile b/Makefile index 1b7cab2..2385285 100644 --- a/Makefile +++ b/Makefile @@ -3,9 +3,9 @@ # VERSION = 2017 -PATCHLEVEL = 05 +PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* @@ -1116,7 +1116,7 @@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \ u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \ $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \ - $(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE + $(if $(CONFIG_HAVE_REFCODE),refcode.bin) checkbinman FORCE $(call if_changed,binman) OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec @@ -1125,7 +1125,8 @@ u-boot-x86-16bit.bin: u-boot FORCE endif ifneq ($(CONFIG_ARCH_SUNXI),) -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb \ + checkbinman FORCE $(call if_changed,binman) endif @@ -1354,6 +1355,18 @@ $(version_h): include/config/uboot.release FORCE $(timestamp_h): $(srctree)/Makefile FORCE $(call filechk,timestamp.h) +checkbinman: tools + @if ! ( echo 'import libfdt' | ( PYTHONPATH=tools python )); then \ + echo >&2; \ + echo >&2 '*** binman needs the Python libfdt library.'; \ + echo >&2 '*** Either install it on your system, or try:'; \ + echo >&2 '***'; \ + echo >&2 '*** sudo apt-get install swig libpython-dev'; \ + echo >&2 '***'; \ + echo >&2 '*** to have U-Boot build its own version.'; \ + false; \ + fi + # --------------------------------------------------------------------------- quiet_cmd_cpp_lds = LDS $@ cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) \ diff --git a/README b/README index 075d919..2abba91 100644 --- a/README +++ b/README @@ -328,34 +328,6 @@ The following options need to be configured: multiple fs option at one time for marvell soc family -- 8xx CPU Options: (if using an MPC8xx CPU) - CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if - get_gclk_freq() cannot work - e.g. if there is no 32KHz - reference PIT/RTC clock - CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK - or XTAL/EXTAL) - -- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): - CONFIG_SYS_8xx_CPUCLK_MIN - CONFIG_SYS_8xx_CPUCLK_MAX - CONFIG_8xx_CPUCLK_DEFAULT - See doc/README.MPC866 - - CONFIG_SYS_MEASURE_CPUCLK - - Define this to measure the actual CPU clock instead - of relying on the correctness of the configured - values. Mostly useful for board bringup to make sure - the PLL is locked at the intended frequency. Note - that this requires a (stable) reference clock (32 kHz - RTC clock or CONFIG_SYS_8XX_XIN) - - CONFIG_SYS_DELAYED_ICACHE - - Define this option if you want to enable the - ICache only when Code runs from RAM. - - 85xx CPU Options: CONFIG_SYS_PPC64 @@ -636,10 +608,6 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - OF_CPU - The proper name of the cpus node (only required for - MPC512X and MPC5xxx based boards). - OF_SOC - The proper name of the soc node (only required for - MPC512X and MPC5xxx based boards). OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device @@ -723,29 +691,10 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver -- Console Interface: - Depending on board, define exactly one serial port - (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, - CONFIG_8xx_CONS_SCC1, ...), or switch off the serial - console by defining CONFIG_8xx_CONS_NONE - - Note: if CONFIG_8xx_CONS_NONE is defined, the serial - port routines must be defined elsewhere - (i.e. serial_init(), serial_getc(), ...) - - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below. - CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale - -- Console Rx buffer length - With CONFIG_SYS_SMC_RXBUFLEN it is possible to define - the maximum receive buffer length for the SMC. - This option is actual only for 82xx and 8xx possible. - If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE - must be defined, to setup the maximum idle timeout for - the SMC. - Autoboot Command: CONFIG_BOOTCOMMAND @@ -912,7 +861,7 @@ The following options need to be configured: Note: Don't enable the "icache" and "dcache" commands (configuration option CONFIG_CMD_CACHE) unless you know what you (and your U-Boot users) are doing. Data - cache cannot be enabled on systems like the 8xx or + cache cannot be enabled on systems like the 8260 (where accesses to the IMMR region must be uncached), and it cannot be disabled on all other systems where we (mis-) use the data cache to hold an @@ -976,11 +925,9 @@ The following options need to be configured: CONFIG_WATCHDOG If this variable is defined, it enables watchdog support for the SoC. There must be support in the SoC - specific code for a watchdog. For the 8xx and 8260 - CPUs, the SIU Watchdog feature is enabled in the SYPCR - register. When supported for a specific SoC is - available, then no further board specific code should - be needed to use it. + specific code for a watchdog. When supported for a + specific SoC is available, then no further board specific + code should be needed to use it. CONFIG_HW_WATCHDOG When using a watchdog circuitry external to the used @@ -1004,7 +951,6 @@ The following options need to be configured: has to be selected, too. Define exactly one of the following options: - CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC CONFIG_RTC_MC146818 - use MC146818 RTC @@ -1015,7 +961,7 @@ The following options need to be configured: CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC - CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 + CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 CONFIG_SYS_RV3029_TCR - enable trickle charger on RV3029 RTC. @@ -1282,7 +1228,7 @@ The following options need to be configured: - USB Support: At the moment only the UHCI host controller is - supported (PIP405, MIP405, MPC5200); define + supported (PIP405, MIP405); define CONFIG_USB_UHCI to enable it. define CONFIG_USB_KEYBOARD to enable the USB Keyboard and define CONFIG_USB_STORAGE to enable the USB @@ -1290,19 +1236,6 @@ The following options need to be configured: Note: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). - MPC5200 USB requires additional defines: - CONFIG_USB_CLOCK - for 528 MHz Clock: 0x0001bbbb - CONFIG_PSC3_USB - for USB on PSC3 - CONFIG_USB_CONFIG - for differential drivers: 0x00001000 - for single ended drivers: 0x00005000 - for differential drivers on PSC3: 0x00000100 - for single ended drivers on PSC3: 0x00004100 - CONFIG_SYS_USB_EVENT_POLL - May be defined to allow interrupt polling - instead of using asynchronous interrupts CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. @@ -1345,11 +1278,6 @@ The following options need to be configured: Define this if you want stdin, stdout &/or stderr to be set to usbtty. - mpc8xx: - CONFIG_SYS_USB_EXTC_CLK 0xBLAH - Derive USB clock from external clock "blah" - - CONFIG_SYS_USB_EXTC_CLK 0x02 - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define @@ -1949,12 +1877,6 @@ The following options need to be configured: In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined with a list of GPIO LEDs that have inverted polarity. -- CAN Support: CONFIG_CAN_DRIVER - - Defining CONFIG_CAN_DRIVER enables CAN driver support - on those systems that support this (optional) - feature, like the TQM8xxL modules. - - I2C Support: CONFIG_SYS_I2C This enable the NEW i2c subsystem, and will allow you to use @@ -2153,12 +2075,6 @@ The following options need to be configured: eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) - I2C_PORT - - (Only for MPC8260 CPU). The I/O port to use (the code - assumes both bits are on the same port). Valid values - are 0..3 for ports A..D. - I2C_ACTIVE The code necessary to make the I2C data line active @@ -2445,9 +2361,9 @@ The following options need to be configured: following board configurations are known to be "pRAM-clean": - IVMS8, IVML24, SPD8xx, TQM8xxL, + IVMS8, IVML24, SPD8xx, HERMES, IP860, RPXlite, LWMON, - FLAGADM, TQM8260 + FLAGADM - Access to physical memory region (> 4GB) Some basic support is provided for operations on memory not @@ -2618,12 +2534,6 @@ The following options need to be configured: Define this option to include a destructive SPI flash test ('sf test'). - CONFIG_SF_DUAL_FLASH Dual flash memories - - Define this option to use dual flash support where two flash - memories can be connected with a given cs line. - Currently Xilinx Zynq qspi supports these type of connections. - - SystemACE Support: CONFIG_SYSTEMACE @@ -3905,16 +3815,6 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface. set. If this value is set, it must be set to the same value as CONFIG_ENV_SIZE. -- CONFIG_SYS_SPI_INIT_OFFSET - - Defines offset to the initial SPI buffer area in DPRAM. The - area is used at an early stage (ROM part) if the environment - is configured to reside in the SPI EEPROM: We need a 520 byte - scratch DPRAM area. It is used between the two initialization - calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems - to be a good choice since it makes it far enough from the - start of the data area as well as from the stack pointer. - Please note that the environment is read-only until the monitor has been relocated to RAM and a RAM copy of the environment has been created; also, when using EEPROM you will have to use getenv_f() @@ -3968,13 +3868,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_CACHELINE_SIZE: Cache Line Size of the CPU. -- CONFIG_SYS_DEFAULT_IMMR: - Default address of the IMMR after system reset. - - Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, - and RPXsuper) to be able to adjust the position of - the IMMR register after a reset. - - CONFIG_SYS_CCSRBAR_DEFAULT: Default (power-on reset) physical address of CCSR on Freescale PowerPC SOCs. @@ -3983,9 +3876,6 @@ Low Level (hardware related) configuration options: Virtual address of CCSR. On a 32-bit build, this is typically the same value as CONFIG_SYS_CCSRBAR_DEFAULT. - CONFIG_SYS_DEFAULT_IMMR must also be set to this value, - for cross-platform code that uses that macro instead. - - CONFIG_SYS_CCSRBAR_PHYS: Physical address of CCSR. CCSR can be relocated to a new physical address, if desired. In this case, this macro should @@ -4048,7 +3938,7 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're - doing! (11-4) [MPC8xx/82xx systems only] + doing! (11-4) [82xx systems only] - CONFIG_SYS_INIT_RAM_ADDR: @@ -4061,8 +3951,6 @@ Low Level (hardware related) configuration options: sequences. U-Boot uses the following memory types: - - MPC8xx and MPC8260: IMMR (internal memory of the CPU) - - MPC824X: data cache - PPC4xx: data cache - CONFIG_SYS_GBL_DATA_OFFSET: @@ -4083,16 +3971,6 @@ Low Level (hardware related) configuration options: point to an otherwise UNUSED address space between the top of RAM and the start of the PCI space. -- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) - -- CONFIG_SYS_SYPCR: System Protection Control (11-9) - -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) - -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) - -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) - - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27) - CONFIG_SYS_OR_TIMING_SDRAM: @@ -4101,8 +3979,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_MAMR_PTA: periodic timer for refresh -- CONFIG_SYS_DER: Debug Event Register (37-47) - - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, @@ -4114,39 +3990,6 @@ Low Level (hardware related) configuration options: CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM: Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) -- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K, - CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL: - Machine Mode Register and Memory Periodic Timer - Prescaler definitions (SDRAM timing) - -- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]: - enable I2C microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [DSP2] - -- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]: - enable SMC microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SMC1] - -- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]: - enable SPI microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SCC4] - -- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) - Offset of the bootmode word in DPRAM used by post - (Power On Self Tests). This definition overrides - #define'd default value in commproc.h resp. - cpm_8260.h. - -- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB, - CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL, - CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS, - CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB, - CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, - CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, - CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, - CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) - Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set. - - CONFIG_PCI_DISABLE_PCIE: Disable PCI-Express on systems where it is supported but not required. @@ -4225,21 +4068,6 @@ Low Level (hardware related) configuration options: Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. -- CONFIG_ETHER_ON_FEC[12] - Define to enable FEC[12] on a 8xx series processor. - -- CONFIG_FEC[12]_PHY - Define to the hardcoded PHY address which corresponds - to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 - means that the PHY with address 4 is connected to FEC1 - - When set to -1, means to probe for first available. - -- CONFIG_FEC[12]_PHY_NORXERR - The PHY does not have a RXERR line (RMII only). - (so program the FEC to ignore it). - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't @@ -5782,9 +5610,9 @@ configuration for CS0# this is a mirror of the on board Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) initial stack is set up in the internal Dual Ported RAM (in case CPUs -which provide such a feature like MPC8xx or MPC8260), or in a locked -part of the data cache. After that, U-Boot initializes the CPU core, -the caches and the SIU. +which provide such a feature like), or in a locked part of the data +cache. After that, U-Boot initializes the CPU core, the caches and +the SIU. Next, all (potentially) available memory banks are mapped using a preliminary mapping. For example, we put them on 512 MB boundaries diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index f23f175..d1b54ea 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -30,11 +30,8 @@ int platform_sys_info(struct sys_info *si) si->clk_bus = gd->bus_clk; si->clk_cpu = gd->cpu_clk; -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || \ - defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define bi_bar bi_immr_base -#elif defined(CONFIG_MPC5xxx) -#define bi_bar bi_mbar_base #elif defined(CONFIG_MPC83xx) #define bi_bar bi_immrbar #endif diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h index e354edf..0454872 100644 --- a/arch/arc/include/asm/u-boot.h +++ b/arch/arc/include/asm/u-boot.h @@ -8,6 +8,7 @@ #define __ASM_ARC_U_BOOT_H__ #include +#include /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_ARC diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index deb7b24..46183ae 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -19,6 +19,15 @@ config HAS_VBAR config HAS_THUMB2 bool +# Used for compatibility with asm files copied from the kernel +config ARM_ASM_UNIFIED + bool + default y + +# Used for compatibility with asm files copied from the kernel +config THUMB2_KERNEL + bool + # If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -128,6 +137,7 @@ config CPU_V7 config CPU_V7M bool select HAS_THUMB2 + select THUMB2_KERNEL select SYS_CACHE_SHIFT_5 config CPU_PXA @@ -656,8 +666,8 @@ config ARCH_SUNXI select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE - select SPL_STACK_R if SUPPORT_SPL - select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL + select SPL_STACK_R if SPL + select SPL_SYS_MALLOC_SIMPLE if SPL select SYS_NS16550 select SPL_SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a5eebb9..1a77779 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -142,9 +142,11 @@ OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \ -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn endif -ifdef CONFIG_OF_EMBED +# if a dtb section exists we always have to include it +# there are only two cases where it is generated +# 1) OF_EMBEDED is turned on +# 2) unit tests include device tree blobs OBJCOPYFLAGS += -j .dtb.init.rodata -endif ifdef CONFIG_EFI_LOADER OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 0bb3441..365d8f0 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -38,7 +38,8 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif @@ -62,7 +63,8 @@ c_runtime_cpu_setup: ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) cpu_init_crit: mov ip, lr diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 8faf34b..948b764 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -11,7 +11,6 @@ obj-y += cpu.o obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ -obj-$(CONFIG_S3C24X0) += s3c24x0/ # some files can only build in ARM mode diff --git a/arch/arm/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c index 9dc60b6..f0ab7d4 100644 --- a/arch/arm/cpu/arm920t/ep93xx/speed.c +++ b/arch/arm/cpu/arm920t/ep93xx/speed.c @@ -39,7 +39,7 @@ static ulong get_PLLCLK(uint32_t *pllreg) } /* return FCLK frequency */ -ulong get_FCLK() +ulong get_FCLK(void) { const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile deleted file mode 100644 index e78f8a0..0000000 --- a/arch/arm/cpu/arm920t/s3c24x0/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o -obj-y += speed.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c deleted file mode 100644 index fede51a..0000000 --- a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2010 - * David Mueller - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -typedef ulong (*getfreq)(void); - -static const getfreq freq_f[] = { - get_FCLK, - get_HCLK, - get_PCLK, -}; - -static const char freq_c[] = { 'F', 'H', 'P' }; - -int print_cpuinfo(void) -{ - int i; - char buf[32]; -/* the S3C2400 seems to be lacking a CHIP ID register */ -#ifndef CONFIG_S3C2400 - ulong cpuid; - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - cpuid = readl(&gpio->gstatus1); - printf("CPUID: %8lX\n", cpuid); -#endif - for (i = 0; i < ARRAY_SIZE(freq_f); i++) - printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]())); - - return 0; -} diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c deleted file mode 100644 index 3701c5d..0000000 --- a/arch/arm/cpu/arm920t/s3c24x0/speed.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* This code should work for both the S3C2400 and the S3C2410 - * as they seem to have the same PLL and clock machinery inside. - * The different address mapping is handled by the s3c24xx.h files below. - */ - -#include -#ifdef CONFIG_S3C24X0 - -#include -#include - -#define MPLL 0 -#define UPLL 1 - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * - * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -static ulong get_PLLCLK(int pllreg) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - ulong r, m, p, s; - - if (pllreg == MPLL) - r = readl(&clk_power->mpllcon); - else if (pllreg == UPLL) - r = readl(&clk_power->upllcon); - else - hang(); - - m = ((r & 0xFF000) >> 12) + 8; - p = ((r & 0x003F0) >> 4) + 2; - s = r & 0x3; - -#if defined(CONFIG_S3C2440) - if (pllreg == MPLL) - return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s)); -#endif - return (CONFIG_SYS_CLK_FREQ * m) / (p << s); - -} - -/* return FCLK frequency */ -ulong get_FCLK(void) -{ - return get_PLLCLK(MPLL); -} - -/* return HCLK frequency */ -ulong get_HCLK(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); -#ifdef CONFIG_S3C2440 - switch (readl(&clk_power->clkdivn) & 0x6) { - default: - case 0: - return get_FCLK(); - case 2: - return get_FCLK() / 2; - case 4: - return (readl(&clk_power->camdivn) & (1 << 9)) ? - get_FCLK() / 8 : get_FCLK() / 4; - case 6: - return (readl(&clk_power->camdivn) & (1 << 8)) ? - get_FCLK() / 6 : get_FCLK() / 3; - } -#else - return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); -#endif -} - -/* return PCLK frequency */ -ulong get_PCLK(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - - return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); -} - -/* return UCLK frequency */ -ulong get_UCLK(void) -{ - return get_PLLCLK(UPLL); -} - -#endif /* CONFIG_S3C24X0 */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c deleted file mode 100644 index ba1e616..0000000 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#ifdef CONFIG_S3C24X0 - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int timer_init(void) -{ - struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - ulong tmr; - - /* use PWM Timer 4 because it has no output */ - /* prescaler for Timer 4 is 16 */ - writel(0x0f00, &timers->tcfg0); - if (gd->arch.tbu == 0) { - /* - * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 - * (default) and prescaler = 16. Should be 10390 - * @33.25MHz and 15625 @ 50 MHz - */ - gd->arch.tbu = get_PCLK() / (2 * 16 * 100); - gd->arch.timer_rate_hz = get_PCLK() / (2 * 16); - } - /* load value for 10 ms timeout */ - writel(gd->arch.tbu, &timers->tcntb4); - /* auto load, manual update of timer 4 */ - tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; - writel(tmr, &timers->tcon); - /* auto load, start timer 4 */ - tmr = (tmr & ~0x0700000) | 0x0500000; - writel(tmr, &timers->tcon); - gd->arch.lastinc = 0; - gd->arch.tbl = 0; - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay (unsigned long usec) -{ - ulong tmo; - ulong start = get_ticks(); - - tmo = usec / 1000; - tmo *= (gd->arch.tbu * 100); - tmo /= 1000; - - while ((ulong) (get_ticks() - start) < tmo) - /*NOP*/; -} - -ulong get_timer_masked(void) -{ - ulong tmr = get_ticks(); - - return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ); -} - -void udelay_masked(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= (gd->arch.tbu * 100); - tmo /= 1000; - } else { - tmo = usec * (gd->arch.tbu * 100); - tmo /= (1000 * 1000); - } - - endtime = get_ticks() + tmo; - - do { - ulong now = get_ticks(); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - ulong now = readl(&timers->tcnto4) & 0xffff; - - if (gd->arch.lastinc >= now) { - /* normal mode */ - gd->arch.tbl += gd->arch.lastinc - now; - } else { - /* we have an overflow ... */ - gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now; - } - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -/* - * reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu(ulong ignored) -{ - struct s3c24x0_watchdog *watchdog; - - watchdog = s3c24x0_get_base_watchdog(); - - /* Disable watchdog */ - writel(0x0000, &watchdog->wtcon); - - /* Initialize watchdog timer count register */ - writel(0x0001, &watchdog->wtcnt); - - /* Enable watchdog timer; assert reset at timer timeout */ - writel(0x0021, &watchdog->wtcon); - - while (1) - /* loop forever and wait for reset to happen */; - - /*NOTREACHED*/ -} - -#endif /* CONFIG_S3C24X0 */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 3ada6d0..3880a40 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -50,43 +50,6 @@ copyex: bne copyex #endif -#ifdef CONFIG_S3C24X0 - /* turn off the watchdog */ - -# if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ -# define CLKDIVN 0x14800014 /* clock divisor register */ -#else -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define CLKDIVN 0x4C000014 /* clock divisor register */ -# endif - - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =INTMSK - str r1, [r0] -# if defined(CONFIG_S3C2410) - ldr r1, =0x3ff - ldr r0, =INTSUBMSK - str r1, [r0] -# endif - - /* FCLK:HCLK:PCLK = 1:2:4 */ - /* default FCLK is 120 MHz ! */ - ldr r0, =CLKDIVN - mov r1, #3 - str r1, [r0] -#endif /* CONFIG_S3C24X0 */ - /* * we do sys-critical inits only at reboot, * not when booting from ram! diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 5fac252..45dd3ca 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,11 +12,9 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif -endif obj-$(CONFIG_ARM_SMCCC) += smccc-call.o obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 658934d..64f1058 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -15,7 +15,14 @@ #include #include -ENTRY(lowlevel_init) +.pushsection .text.s_init, "ax" +WEAK(s_init) + bx lr +ENDPROC(s_init) +.popsection + +.pushsection .text.lowlevel_init, "ax" +WEAK(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ @@ -61,3 +68,4 @@ ENTRY(lowlevel_init) bl s_init pop {ip, pc} ENDPROC(lowlevel_init) +.popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index b3a34de..18da9cb 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -118,6 +118,23 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, } } +#ifdef CONFIG_MACH_SUN8I_R40 +/* secondary core entry address is programmed differently on R40 */ +static void __secure sunxi_set_entry_address(void *entry) +{ + writel((u32)entry, + SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); +} +#else +static void __secure sunxi_set_entry_address(void *entry) +{ + struct sunxi_cpucfg_reg *cpucfg = + (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; + + writel((u32)entry, &cpucfg->priv0); +} +#endif + #ifdef CONFIG_MACH_SUN7I /* sun7i (A20) is different from other single cluster SoCs */ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on) @@ -236,13 +253,7 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc) psci_save_target_pc(cpu, pc); /* Set secondary core power on PC */ -#ifdef CONFIG_MACH_SUN8I_R40 - /* secondary core entry address is programmed differently */ - writel((u32)&psci_cpu_entry, - SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0); -#else - writel((u32)&psci_cpu_entry, &cpucfg->priv0); -#endif + sunxi_set_entry_address(&psci_cpu_entry); /* Assert reset on target CPU */ writel(0, &cpucfg->cpu[cpu].rst); diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S index 49f2720..890c773 100644 --- a/arch/arm/cpu/armv7m/start.S +++ b/arch/arm/cpu/armv7m/start.S @@ -5,10 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include + .globl reset .type reset, %function reset: - b _main + W(b) _main .globl c_runtime_cpu_setup c_runtime_cpu_setup: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cb3a52c..c6fede3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -27,6 +27,7 @@ #ifdef CONFIG_SYS_FSL_DDR #include #endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 7dfd270..c220267 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -1,5 +1,6 @@ /** * (C) Copyright 2014, Cavium Inc. + * (C) Copyright 2017, Xilinx Inc. * * SPDX-License-Identifier: GPL-2.0+ **/ @@ -114,6 +115,22 @@ void __noreturn __efi_runtime psci_system_off(void) ; } +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + puts("poweroff ...\n"); + + udelay(50000); /* wait 50 ms */ + + disable_interrupts(); + + psci_system_off(); + + /*NOTREACHED*/ + return 0; +} +#endif + #ifdef CONFIG_PSCI_RESET void reset_misc(void) { diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index cc427c3..0d1b0c4 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -56,17 +56,17 @@ SECTIONS _image_binary_end = .; - .bss_start : { + .bss_start (NOLOAD) : { . = ALIGN(8); KEEP(*(.__bss_start)); } >.sdram - .bss : { + .bss (NOLOAD) : { *(.bss*) . = ALIGN(8); } >.sdram - .bss_end : { + .bss_end (NOLOAD) : { KEEP(*(.__bss_end)); } >.sdram diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index b0f1295..94ecf90 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -38,12 +38,6 @@ static struct mm_region zynqmp_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0xffe00000UL, - .phys = 0xffe00000UL, - .size = 0x00200000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { .virt = 0x400000000UL, .phys = 0x400000000UL, .size = 0x200000000UL, @@ -104,3 +98,111 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_SILICON; } + +#define ZYNQMP_MMIO_READ 0xC2000014 +#define ZYNQMP_MMIO_WRITE 0xC2000013 + +#ifndef CONFIG_SPL_BUILD +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, + u32 *ret_payload) +{ + /* + * Added SIP service call Function Identifier + * Make sure to stay in x0 register + */ + struct pt_regs regs; + + regs.regs[0] = pm_api_id; + regs.regs[1] = ((u64)arg1 << 32) | arg0; + regs.regs[2] = ((u64)arg3 << 32) | arg2; + + smc_call(®s); + + if (ret_payload != NULL) { + ret_payload[0] = (u32)regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + } + + return regs.regs[0]; +} + +#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 + +#define ZYNQMP_PM_VERSION_MAJOR 0 +#define ZYNQMP_PM_VERSION_MINOR 3 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF + +#define ZYNQMP_PM_VERSION \ + ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ + ZYNQMP_PM_VERSION_MINOR) + +#if defined(CONFIG_CLK_ZYNQMP) +void zynqmp_pmufw_version(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 pm_api_version; + + ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0, + ret_payload); + pm_api_version = ret_payload[1]; + + if (ret) + panic("PMUFW is not found - Please load it!\n"); + + printf("PMUFW:\tv%d.%d\n", + pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, + pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK); + + if (pm_api_version != ZYNQMP_PM_VERSION) + panic("PMUFW version error. Expected: v%d.%d\n", + ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR); +} +#endif + +int zynqmp_mmio_write(const u32 address, + const u32 mask, + const u32 value) +{ + return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL); +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 ret; + + if (!value) + return -EINVAL; + + ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload); + *value = ret_payload[1]; + + return ret; +} +#else +int zynqmp_mmio_write(const u32 address, + const u32 mask, + const u32 value) +{ + u32 data; + u32 value_local = value; + + zynqmp_mmio_read(address, &data); + data &= ~mask; + value_local &= mask; + value_local |= data; + writel(value_local, (ulong)address); + return 0; +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + *value = readl((ulong)address); + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 0a5f430..26bf80e 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -83,9 +83,15 @@ u32 spl_boot_device(void) case JTAG_MODE: return BOOT_DEVICE_RAM; #ifdef CONFIG_SPL_MMC_SUPPORT - case EMMC_MODE: - case SD_MODE: case SD_MODE1: + case SD1_LSHFT_MODE: /* not working on silicon v1 */ +/* if both controllers enabled, then these two are the second controller */ +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + return BOOT_DEVICE_MMC2; +/* else, fall through, the one SDHCI controller that is enabled is number 1 */ +#endif + case SD_MODE: + case EMMC_MODE: return BOOT_DEVICE_MMC1; #endif #ifdef CONFIG_SPL_DFU_SUPPORT @@ -106,10 +112,11 @@ u32 spl_boot_device(void) u32 spl_boot_mode(const u32 boot_device) { - switch (spl_boot_device()) { + switch (boot_device) { case BOOT_DEVICE_RAM: return 0; case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; default: puts("spl: error: unsupported device\n"); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b95920a..a01c9b6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,9 +41,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3328-evb.dtb \ + rk3368-sheep.dtb \ + rk3368-geekbox.dtb \ + rk3368-px5-evb.dtb \ rk3399-evb.dtb \ rk3399-firefly.dtb \ - rk3399-puma.dtb + rk3399-puma-ddr1333.dtb \ + rk3399-puma-ddr1600.dtb \ + rk3399-puma-ddr1866.dtb \ + rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ @@ -54,7 +60,6 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-tec.dtb \ tegra20-trimslice.dtb \ tegra20-ventana.dtb \ - tegra20-whistler.dtb \ tegra20-colibri.dtb \ tegra30-apalis.dtb \ tegra30-beaver.dtb \ @@ -122,6 +127,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ zynq-topic-miami.dtb \ + zynq-topic-miamilite.dtb \ zynq-topic-miamiplus.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ @@ -146,6 +152,7 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb +dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ @@ -310,6 +317,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb dtb-$(CONFIG_MACH_SUN8I_R40) += \ @@ -317,10 +325,13 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-orangepi-pc2.dtb \ - sun50i-h5-orangepi-prime.dtb + sun50i-h5-orangepi-prime.dtb \ + sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-bananapi-m64.dtb \ + sun50i-a64-orangepi-win.dtb \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb dtb-$(CONFIG_MACH_SUN9I) += \ @@ -383,7 +394,7 @@ dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ logicpd-torpedo-37xx-devkit.dtb \ - logicpd-som-lv-37xx-devkit.dts + logicpd-som-lv-37xx-devkit.dtb dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts new file mode 100644 index 0000000..0bf55fa --- /dev/null +++ b/arch/arm/dts/dm8168-evm.dts @@ -0,0 +1,175 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dm816x.dtsi" +#include + +/ { + model = "DM8168 EVM"; + compatible = "ti,dm8168-evm", "ti,dm8168"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000 /* 1 GB */ + 0xc0000000 0x40000000>; /* 1 GB */ + }; + + /* FDC6331L controlled by SD_POW pin */ + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dm816x_pinmux { + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ + DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ + DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ + DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ + >; + }; + + mmc_pins: pinmux_mmc_pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ + DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ + DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ + DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ + DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ + DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ + DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ + DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ + DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ + >; + }; + + usb0_pins: pinmux_usb0_pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ + >; + }; +}; + +&i2c1 { + extgpio0: pcf8575@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + extgpio1: pcf8575@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&gpmc { + ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + compatible = "ti,omap2-nand"; + linux,mtd-name= "micron,mt29f2g16aadwp"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "bch8"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@0x80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@0x1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@0x280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@0x780000 { + label = "Filesystem"; + reg = <0x780000 0xf880000>; + }; + }; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + m25p80@0 { + compatible = "w25x32"; + spi-max-frequency = <48000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +/* At least dm8168-evm rev c won't support multipoint, later may */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + mentor,multipoint = <0>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; + mentor,multipoint = <0>; +}; diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi new file mode 100644 index 0000000..51865eb --- /dev/null +++ b/arch/arm/dts/dm816x-clocks.dtsi @@ -0,0 +1,250 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&scrm { + main_fapll: main_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x400 0x40>; + clocks = <&sys_clkin_ck &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>, <4>, <5>, + <6>, <7>; + clock-output-names = "main_pll_clk1", + "main_pll_clk2", + "main_pll_clk3", + "main_pll_clk4", + "main_pll_clk5", + "main_pll_clk6", + "main_pll_clk7"; + }; + + ddr_fapll: ddr_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x440 0x30>; + clocks = <&sys_clkin_ck &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>, <4>; + clock-output-names = "ddr_pll_clk1", + "ddr_pll_clk2", + "ddr_pll_clk3", + "ddr_pll_clk4"; + }; + + video_fapll: video_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x470 0x30>; + clocks = <&sys_clkin_ck &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>; + clock-output-names = "video_pll_clk1", + "video_pll_clk2", + "video_pll_clk3"; + }; + + audio_fapll: audio_fapll { + #clock-cells = <1>; + compatible = "ti,dm816-fapll-clock"; + reg = <0x4a0 0x30>; + clocks = <&main_fapll 7>, < &sys_clkin_ck>; + clock-indices = <1>, <2>, <3>, <4>, <5>; + clock-output-names = "audio_pll_clk1", + "audio_pll_clk2", + "audio_pll_clk3", + "audio_pll_clk4", + "audio_pll_clk5"; + }; +}; + +&scrm_clocks { + secure_32k_ck: secure_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sys_clkin_ck: sys_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; +}; + +/* 0x48180000 */ +&prcm_clocks { + clkout_pre_ck: clkout_pre_ck@100 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 + &audio_fapll 1>; + reg = <0x100>; + }; + + clkout_div_ck: clkout_div_ck@100 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + reg = <0x100>; + }; + + clkout_ck: clkout_ck@100 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout_div_ck>; + ti,bit-shift = <7>; + reg = <0x100>; + }; + + /* CM_DPLL clocks p1795 */ + sysclk1_ck: sysclk1_ck@300 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 1>; + ti,max-div = <7>; + reg = <0x0300>; + }; + + sysclk2_ck: sysclk2_ck@304 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 2>; + ti,max-div = <7>; + reg = <0x0304>; + }; + + sysclk3_ck: sysclk3_ck@308 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 3>; + ti,max-div = <7>; + reg = <0x0308>; + }; + + sysclk4_ck: sysclk4_ck@30c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 4>; + ti,max-div = <1>; + reg = <0x030c>; + }; + + sysclk5_ck: sysclk5_ck@310 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sysclk4_ck>; + ti,max-div = <1>; + reg = <0x0310>; + }; + + sysclk6_ck: sysclk6_ck@314 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 4>; + ti,dividers = <2>, <4>; + reg = <0x0314>; + }; + + sysclk10_ck: sysclk10_ck@324 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&ddr_fapll 2>; + ti,max-div = <7>; + reg = <0x0324>; + }; + + sysclk24_ck: sysclk24_ck@3b4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&main_fapll 5>; + ti,max-div = <7>; + reg = <0x03b4>; + }; + + mpu_ck: mpu_ck@15dc { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sysclk2_ck>; + ti,bit-shift = <1>; + reg = <0x15dc>; + }; + + audio_pll_a_ck: audio_pll_a_ck@35c { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&audio_fapll 1>; + ti,max-div = <7>; + reg = <0x035c>; + }; + + sysclk18_ck: sysclk18_ck@378 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; + reg = <0x0378>; + }; + + timer1_fck: timer1_fck@390 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x0390>; + }; + + timer2_fck: timer2_fck@394 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x0394>; + }; + + timer3_fck: timer3_fck@398 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x0398>; + }; + + timer4_fck: timer4_fck@39c { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x039c>; + }; + + timer5_fck: timer5_fck@3a0 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x03a0>; + }; + + timer6_fck: timer6_fck@3a4 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x03a4>; + }; + + timer7_fck: timer7_fck@3a8 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; + reg = <0x03a8>; + }; +}; diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi new file mode 100644 index 0000000..276211e --- /dev/null +++ b/arch/arm/dts/dm816x.dtsi @@ -0,0 +1,518 @@ +/* + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include + +/ { + compatible = "ti,dm816"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the dm816x interconnect. + * The real dm816x interconnect network is quite complex. Since + * it will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + reg = <0x44000000 0x10000>; + interrupts = <9 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + prcm: prcm@48180000 { + compatible = "ti,dm816-prcm"; + reg = <0x48180000 0x4000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@48140000 { + compatible = "ti,dm816-scrm", "simple-bus"; + reg = <0x48140000 0x21000>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + ranges = <0 0x48140000 0x21000>; + + dm816x_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x50a>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xf>; + }; + + /* Device Configuration Registers */ + scm_conf: syscon@600 { + compatible = "syscon", "simple-bus"; + reg = <0x600 0x110>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x110>; + + usb_phy0: usb-phy@20 { + compatible = "ti,dm8168-usb-phy"; + reg = <0x20 0x8>; + reg-names = "phy"; + clocks = <&main_fapll 6>; + clock-names = "refclk"; + #phy-cells = <0>; + syscon = <&scm_conf>; + }; + + usb_phy1: usb-phy@28 { + compatible = "ti,dm8168-usb-phy"; + reg = <0x28 0x8>; + reg-names = "phy"; + clocks = <&main_fapll 6>; + clock-names = "refclk"; + #phy-cells = <0>; + syscon = <&scm_conf>; + }; + }; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + + edma: edma@49000000 { + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x40>; + interrupts = <12 13 14>; + #dma-cells = <1>; + }; + + elm: elm@48080000 { + compatible = "ti,816-elm"; + ti,hwmods = "elm"; + reg = <0x48080000 0x2000>; + interrupts = <4>; + }; + + gpio1: gpio@48032000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + reg = <0x48032000 0x1000>; + interrupts = <96>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@4804c000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + ti,gpio-always-on; + reg = <0x4804c000 0x1000>; + interrupts = <98>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = <100>; + dmas = <&edma 52>; + dma-names = "rxtx"; + gpmc,num-cs = <6>; + gpmc,num-waitpins = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c1: i2c@48028000 { + compatible = "ti,omap4-i2c"; + ti,hwmods = "i2c1"; + reg = <0x48028000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <70>; + dmas = <&edma 58 &edma 59>; + dma-names = "tx", "rx"; + }; + + i2c2: i2c@4802a000 { + compatible = "ti,omap4-i2c"; + ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <71>; + dmas = <&edma 60 &edma 61>; + dma-names = "tx", "rx"; + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,dm816-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + rtc: rtc@480c0000 { + compatible = "ti,am3352-rtc", "ti,da830-rtc"; + reg = <0x480c0000 0x1000>; + interrupts = <75 76>; + ti,hwmods = "rtc"; + }; + + mailbox: mailbox@480c8000 { + compatible = "ti,omap4-mailbox"; + reg = <0x480c8000 0x2000>; + interrupts = <77>; + ti,hwmods = "mailbox"; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <0 0 0>; + }; + }; + + spinbox: spinbox@480ca000 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x480ca000 0x2000>; + ti,hwmods = "spinbox"; + #hwlock-cells = <1>; + }; + + mdio: mdio@4a100800 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4a100800 0x100>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + phy0: ethernet-phy@0 { + reg = <1>; + }; + phy1: ethernet-phy@1 { + reg = <2>; + }; + }; + + eth0: ethernet@4a100000 { + compatible = "ti,dm816-emac"; + ti,hwmods = "emac0"; + reg = <0x4a100000 0x800 + 0x4a100900 0x3700>; + clocks = <&sysclk24_ck>; + syscon = <&scm_conf>; + ti,davinci-ctrl-reg-offset = <0>; + ti,davinci-ctrl-mod-reg-offset = <0x900>; + ti,davinci-ctrl-ram-offset = <0x2000>; + ti,davinci-ctrl-ram-size = <0x2000>; + interrupts = <40 41 42 43>; + phy-handle = <&phy0>; + }; + + eth1: ethernet@4a120000 { + compatible = "ti,dm816-emac"; + ti,hwmods = "emac1"; + reg = <0x4a120000 0x4000>; + clocks = <&sysclk24_ck>; + syscon = <&scm_conf>; + ti,davinci-ctrl-reg-offset = <0>; + ti,davinci-ctrl-mod-reg-offset = <0x900>; + ti,davinci-ctrl-ram-offset = <0x2000>; + ti,davinci-ctrl-ram-size = <0x2000>; + interrupts = <44 45 46 47>; + phy-handle = <&phy1>; + }; + + mcspi1: spi@48030000 { + compatible = "ti,omap4-mcspi"; + reg = <0x48030000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <65>; + ti,spi-num-cs = <4>; + ti,hwmods = "mcspi1"; + dmas = <&edma 16 &edma 17 + &edma 18 &edma 19 + &edma 20 &edma 21 + &edma 22 &edma 23>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mmc1: mmc@48060000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x48060000 0x11000>; + ti,hwmods = "mmc1"; + interrupts = <64>; + dmas = <&edma 24 &edma 25>; + dma-names = "tx", "rx"; + }; + + timer1: timer@4802e000 { + compatible = "ti,dm816-timer"; + reg = <0x4802e000 0x2000>; + interrupts = <67>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@48040000 { + compatible = "ti,dm816-timer"; + reg = <0x48040000 0x2000>; + interrupts = <68>; + ti,hwmods = "timer2"; + }; + + timer3: timer@48042000 { + compatible = "ti,dm816-timer"; + reg = <0x48042000 0x2000>; + interrupts = <69>; + ti,hwmods = "timer3"; + }; + + timer4: timer@48044000 { + compatible = "ti,dm816-timer"; + reg = <0x48044000 0x2000>; + interrupts = <92>; + ti,hwmods = "timer4"; + ti,timer-pwm; + }; + + timer5: timer@48046000 { + compatible = "ti,dm816-timer"; + reg = <0x48046000 0x2000>; + interrupts = <93>; + ti,hwmods = "timer5"; + ti,timer-pwm; + }; + + timer6: timer@48048000 { + compatible = "ti,dm816-timer"; + reg = <0x48048000 0x2000>; + interrupts = <94>; + ti,hwmods = "timer6"; + ti,timer-pwm; + }; + + timer7: timer@4804a000 { + compatible = "ti,dm816-timer"; + reg = <0x4804a000 0x2000>; + interrupts = <95>; + ti,hwmods = "timer7"; + ti,timer-pwm; + }; + + uart1: uart@48020000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart1"; + reg = <0x48020000 0x2000>; + clock-frequency = <48000000>; + interrupts = <72>; + dmas = <&edma 26 &edma 27>; + dma-names = "tx", "rx"; + }; + + uart2: uart@48022000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart2"; + reg = <0x48022000 0x2000>; + clock-frequency = <48000000>; + interrupts = <73>; + dmas = <&edma 28 &edma 29>; + dma-names = "tx", "rx"; + }; + + uart3: uart@48024000 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + ti,hwmods = "uart3"; + reg = <0x48024000 0x2000>; + clock-frequency = <48000000>; + interrupts = <74>; + dmas = <&edma 30 &edma 31>; + dma-names = "tx", "rx"; + }; + + /* NOTE: USB needs a transceiver driver for phys to work */ + usb: usb_otg_hs@47401000 { + compatible = "ti,am33xx-usb"; + reg = <0x47401000 0x400000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + ti,hwmods = "usb_otg_hs"; + + usb0: usb@47401000 { + compatible = "ti,musb-dm816"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; + reg-names = "mc", "control"; + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "host"; + interface-type = <0>; + phys = <&usb_phy0>; + phy-names = "usb2-phy"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1: usb@47401800 { + compatible = "ti,musb-dm816"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "host"; + interface-type = <0>; + phys = <&usb_phy1>; + phy-names = "usb2-phy"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@47402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + #dma-channels = <30>; + #dma-requests = <256>; + }; + }; + + wd_timer2: wd_timer@480c2000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer"; + reg = <0x480c2000 0x1000>; + interrupts = <0>; + }; + }; +}; + +#include "dm816x-clocks.dtsi" diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi new file mode 100644 index 0000000..072a758 --- /dev/null +++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/{ + soc { + u-boot,dm-pre-reloc; + }; +}; + +&i2c1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index 8aab607..2e6272b 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -21,7 +21,7 @@ stdout-path = &uart2; }; - panel_regulator: panel-regualtor { + panel_regulator: panel-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 01794ed..b807bc5 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -43,3 +43,16 @@ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + rockchip,vbus-gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 8a98ee3..f18cfc2 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -446,6 +446,20 @@ status = "disabled"; }; + usb_host0_ehci: usb@ff5c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xff5c0000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff5d0000 { + compatible = "generic-ohci"; + reg = <0x0 0xff5d0000 0x0 0x10000>; + interrupts = ; + status = "disabled"; + }; + sdmmc_ext: rksdmmc@ff5f0000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff5f0000 0x0 0x4000>; @@ -457,6 +471,17 @@ status = "disabled"; }; + usb_host0_xhci: usb@ff600000 { + compatible = "rockchip,rk3328-xhci"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = ; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + status = "disabled"; + }; + gic: interrupt-controller@ffb70000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm/dts/rk3368-geekbox.dts b/arch/arm/dts/rk3368-geekbox.dts new file mode 100644 index 0000000..46cdddf --- /dev/null +++ b/arch/arm/dts/rk3368-geekbox.dts @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "GeekBox"; + compatible = "geekbuying,geekbox", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + blue { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "geekbox:blue:led"; + default-state = "on"; + }; + + red { + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + label = "geekbox:red:led"; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcc33_lcd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_lcd"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcca_18: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_18"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + }; + }; + }; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts new file mode 100644 index 0000000..c7478f7 --- /dev/null +++ b/arch/arm/dts/rk3368-px5-evb.dts @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "PX5 EVB"; + compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + blue { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "geekbox:blue:led"; + default-state = "on"; + }; + + red { + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + label = "geekbox:red:led"; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcc33_lcd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_lcd"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcca_18: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_18"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + }; + }; + }; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts new file mode 100644 index 0000000..7c190f7 --- /dev/null +++ b/arch/arm/dts/rk3368-sheep.dts @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "Rockchip sheep board"; + compatible = "rockchip,sheep", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + blue { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "geekbox:blue:led"; + default-state = "on"; + }; + + red { + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + label = "geekbox:red:led"; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcc33_lcd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_lcd"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcca_18: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_18"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + }; + }; + }; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi new file mode 100644 index 0000000..025dc32 --- /dev/null +++ b/arch/arm/dts/rk3368.dtsi @@ -0,0 +1,1090 @@ +/* + * Copyright (c) 2015 Heiko Stuebner + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3368"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + core2 { + cpu = <&cpu_b2>; + }; + core3 { + cpu = <&cpu_b3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <0x3fffffff>; + exit-latency-us = <0x40000000>; + min-residency-us = <0xffffffff>; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_l1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_l3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x100>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x101>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x102>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + + cpu_b3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x103>; + cpu-idle-states = <&cpu_sleep>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, + <&cpu_b2>, <&cpu_b3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + sdmmc: dwmmc@ff0c0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0c0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + status = "disabled"; + }; + + sdio0: dwmmc@ff0d0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0d0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, + <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = ; + status = "disabled"; + }; + + emmc: dwmmc@ff0f0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + status = "disabled"; + }; + + saradc: saradc@ff100000 { + compatible = "rockchip,saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi@ff110000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff110000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff120000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff130000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ff140000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff150000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + i2c4: i2c@ff160000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + status = "disabled"; + }; + + i2c5: i2c@ff170000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + status = "disabled"; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-1 = <&uart0_xfer>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + uart4: serial@ff1c0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1c0000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "disabled"; + }; + + thermal-zones { + cpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <115000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3368-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + gmac: ethernet@ff290000 { + compatible = "rockchip,rk3368-gmac"; + reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, + <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + status = "disabled"; + }; + + usb_host0_ehci: usb@ff500000 { + compatible = "generic-ehci"; + reg = <0x0 0xff500000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_HOST0>; + clock-names = "usbhost"; + status = "disabled"; + }; + + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + status = "disabled"; + }; + + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + clocks = <&cru PCLK_I2C0>; + clock-names = "i2c"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff660000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff660000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + uart2: serial@ff690000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + mbox: mbox@ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0x0 0xff6b0000 0x0 0x1000>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + }; + + pmugrf: syscon@ff738000 { + compatible = "rockchip,rk3368-pmugrf", "syscon"; + reg = <0x0 0xff738000 0x0 0x1000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3368-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x1000>; + }; + + wdt: watchdog@ff800000 { + compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; + reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + timer@ff810000 { + compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; + }; + + gic: interrupt-controller@ffb71000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffb71000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x1000>, + <0x0 0xffb74000 0x0 0x2000>, + <0x0 0xffb76000 0x0 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3368-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + gpio0: gpio0@ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff750000 0x0 0x100>; + clocks = <&cru PCLK_GPIO0>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO1>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7a0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, + <1 19 RK_FUNC_2 &pcfg_pull_up>, + <1 20 RK_FUNC_2 &pcfg_pull_up>, + <1 21 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, + <1 19 RK_FUNC_2 &pcfg_pull_up>, + <1 20 RK_FUNC_2 &pcfg_pull_up>, + <1 21 RK_FUNC_2 &pcfg_pull_up>, + <1 22 RK_FUNC_2 &pcfg_pull_up>, + <1 23 RK_FUNC_2 &pcfg_pull_up>, + <1 24 RK_FUNC_2 &pcfg_pull_up>, + <1 25 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 19 RK_FUNC_1 &pcfg_pull_none>, + <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 15 RK_FUNC_1 &pcfg_pull_none>, + <3 16 RK_FUNC_1 &pcfg_pull_none>, + <3 17 RK_FUNC_1 &pcfg_pull_none>, + <3 18 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 20 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 19 RK_FUNC_1 &pcfg_pull_none>, + <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, + <3 15 RK_FUNC_1 &pcfg_pull_none>, + <3 16 RK_FUNC_1 &pcfg_pull_none>, + <3 20 RK_FUNC_1 &pcfg_pull_none>, + <3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, + <2 22 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, + <3 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, + <1 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, + <3 25 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, + <3 27 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, + <2 29 RK_FUNC_1 &pcfg_pull_up>, + <2 30 RK_FUNC_1 &pcfg_pull_up>, + <2 31 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, + <2 6 RK_FUNC_1 &pcfg_pull_up>, + <2 7 RK_FUNC_1 &pcfg_pull_up>, + <2 8 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, + <2 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, + <0 21 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, + <2 5 RK_FUNC_2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, + <3 30 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, + <0 26 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-puma-ddr1333.dts b/arch/arm/dts/rk3399-puma-ddr1333.dts new file mode 100644 index 0000000..564de91 --- /dev/null +++ b/arch/arm/dts/rk3399-puma-ddr1333.dts @@ -0,0 +1,11 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +#include "rk3399-puma.dtsi" +#include "rk3399-sdram-ddr3-1333.dtsi" + diff --git a/arch/arm/dts/rk3399-puma-ddr1600.dts b/arch/arm/dts/rk3399-puma-ddr1600.dts new file mode 100644 index 0000000..31aaf70 --- /dev/null +++ b/arch/arm/dts/rk3399-puma-ddr1600.dts @@ -0,0 +1,11 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +#include "rk3399-puma.dtsi" +#include "rk3399-sdram-ddr3-1600.dtsi" + diff --git a/arch/arm/dts/rk3399-puma-ddr1866.dts b/arch/arm/dts/rk3399-puma-ddr1866.dts new file mode 100644 index 0000000..4eec8e7 --- /dev/null +++ b/arch/arm/dts/rk3399-puma-ddr1866.dts @@ -0,0 +1,11 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +#include "rk3399-puma.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" + diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts deleted file mode 100644 index a234db8..0000000 --- a/arch/arm/dts/rk3399-puma.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" -#include "rk3399-sdram-ddr3-1600.dtsi" - -/ { - model = "Theobroma Systems RK3399-Q7 SoM"; - compatible = "tsd,puma", "rockchip,rk3399"; - - config { - u-boot,spl-payload-offset = <204800>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc; - }; - - aliases { - spi0 = &spi1; - spi1 = &spi5; - }; - - vdd_center: vdd-center { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 25000 0>; - regulator-name = "vdd_center"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_host: vcc5v0-host-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdmmc { - u-boot,dm-pre-reloc; - bus-width = <4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&dwc3_typec0 { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&dwc3_typec1 { - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_dvs2: pmic-dvs2 { - rockchip,pins = - <1 18 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; - status = "okay"; -}; - -&spi1 { - u-boot,dm-pre-reloc; - - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - spiflash: w25q32dw@0 { - u-boot,dm-pre-reloc; - - compatible = "spi-flash"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpol; - spi-cpha; - }; -}; - -&spi5 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi new file mode 100644 index 0000000..1aad6c5 --- /dev/null +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -0,0 +1,642 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +#include +#include "rk3399.dtsi" + +/ { + model = "Theobroma Systems RK3399-Q7 SoM"; + compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399"; + + config { + u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */ + u-boot,boot-led = "module_led"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc; + }; + + aliases { + spi0 = &spi1; + spi1 = &spi5; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_puma>; + + module_led { + label = "module_led"; + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + sd_card_led { + label = "sd_card_led"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dw_hdmi_audio: dw-hdmi-audio { + status = "enabled"; + compatible = "rockchip,dw-hdmi-audio"; + #sound-dai-cells = <0>; + }; + + hdmi_codec: hdmi-codec { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "HDMI-CODEC"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + /* for rockchip boot on */ + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <1000000>; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <2 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x10>; + rx_delay = <0x10>; + status = "okay"; +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_gpu: fan535555@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1230000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt? + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_ldo1: LDO_REG1 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_ldo1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_hdmi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_ldo5: LDO_REG5 { + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_ldo5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo6: LDO_REG6 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_ldo6"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcc0v9_hdmi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_efuse: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_efuse"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + clock-frequency = <400000>; + + vdd_cpu_b: fan53555@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1230000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */ +}; + +&pcie0 { + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + ep-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + supports-emmc; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + clock-frequency = <150000000>; + clock-freq-min-max = <100000 150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&dwc3_typec0 { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&dwc3_typec1 { + rockchip,vbus-gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&pinctrl { + /* Pins that are not explicitely used by any devices */ + pinctrl-names = "default"; + pinctrl-0 = <&puma_pin_hog>; + hog { + puma_pin_hog: puma_pin_hog { + rockchip,pins = + /* We need pull-ups on Q7 buttons */ + <0 4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */ + <0 10 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */ + <0 11 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */ + <0 9 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */ + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 22 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds_pins_puma: led_pins@0 { + rockchip,pins = + <2 25 RK_FUNC_GPIO &pcfg_pull_none>, + <1 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb2 { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c8 { + i2c8_xfer_a: i2c8-xfer { + rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>, + <1 20 RK_FUNC_1 &pcfg_pull_up>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; +&i2c2 { + status = "okay"; + clock-frequency = <400000>; +}; +&i2c4 { + status = "okay"; + clock-frequency = <400000>; +}; +&i2c6 { + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c6_xfer { + /* Enable pull-ups, the pins would float otherwise. */ + rockchip,pins = + <2 10 RK_FUNC_2 &pcfg_pull_up>, + <2 9 RK_FUNC_2 &pcfg_pull_up>; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <400000>; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + cooling-min-state = <0>; + cooling-max-state = <9>; + #cooling-cells = <2>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + + +&spi1 { + u-boot,dm-pre-reloc; + + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + spiflash: w25q32dw@0 { + u-boot,dm-pre-reloc; + + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <49500000>; + spi-cpol; + spi-cpha; + }; +}; + +&spi5 { + status = "okay"; +}; + diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi new file mode 100644 index 0000000..80e946e --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi @@ -0,0 +1,1537 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80181219 + 0x17050a03 + 0x00000002 + 0x00006456 + 0x0000004c + 0x00000000 + 0x1 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80181219 + 0x17050a03 + 0x00000002 + 0x00006456 + 0x0000004c + 0x00000000 + 933 + 3 + 2 + 9 + 1 + 0x00000600 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000a + 0x00000000 + 0x00000000 + 0x01000000 + 0x00000000 + 0x00000101 + 0x00020100 + 0x0002d976 + 0x00071fa6 + 0x02000200 + 0x091a0200 + 0x00091a00 + 0x0400091a + 0x2c060004 + 0x210c0820 + 0x202c0600 + 0x00210c08 + 0x08202c06 + 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a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index f3d3f53..7f1fc50 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1419,6 +1419,11 @@ reg = <3>; remote-endpoint = <&mipi_in_vopl>; }; + + vopl_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_vopl>; + }; }; }; @@ -1440,6 +1445,40 @@ reg = <3>; remote-endpoint = <&mipi_in_vopb>; }; + + vopb_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_vopb>; + }; + }; + }; + + hdmi: hdmi@ff940000 { + compatible = "rockchip,rk3399-dw-hdmi"; + reg = <0x0 0xff940000 0x0 0x20000>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; + power-domains = <&power RK3399_PD_HDCP>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; + clock-names = "iahb", "isfr", "vpll", "grf"; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; }; }; diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts new file mode 100644 index 0000000..0128dd8 --- /dev/null +++ b/arch/arm/dts/rv1108-evb.dts @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Rockchip RV1108 Evaluation board"; + compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + status = "okay"; + clock_in_out = <0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; +}; + +&sfc { + status = "okay"; + flash@0 { + compatible = "gd25q256","spi-flash"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <96000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi new file mode 100644 index 0000000..77ca24e --- /dev/null +++ b/arch/arm/dts/rv1108.dtsi @@ -0,0 +1,479 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1108"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + spi0 = &sfc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + + uart2: serial@10210000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10210000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart1: serial@10220000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10220000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart0: serial@10230000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + grf: syscon@10300000 { + compatible = "rockchip,rv1108-grf", "syscon"; + reg = <0x10300000 0x1000>; + }; + + pmugrf: syscon@20060000 { + compatible = "rockchip,rv1108-pmugrf", "syscon"; + reg = <0x20060000 0x1000>; + }; + + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + emmc: dwmmc@30110000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30110000 0x4000>; + status = "disabled"; + }; + + sdio: dwmmc@30120000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30120000 0x4000>; + status = "disabled"; + }; + + sdmmc: dwmmc@30130000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 100000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30130000 0x4000>; + status = "disabled"; + }; + + sfc: sfc@301c0000 { + compatible = "rockchip,sfc"; + reg = <0x301c0000 0x200>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + gmac: ethernet@30200000 { + compatible = "rockchip,rv1108-gmac"; + reg = <0x30200000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, + <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + max-speed = <100>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1108-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20030000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20030000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@10310000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10310000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@10320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10320000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@10330000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10330000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { + drive-strength = <4>; + }; + + pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + gmac { + rmii_pins: rmii-pins { + rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; + }; + + i2c2m1_gpio: i2c2m1-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c2m05v { + i2c2m05v_xfer: i2c2m05v-xfer { + rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; + }; + + i2c2m05v_gpio: i2c2m05v-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sfc { + sfc_pins: sfc-pins { + rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart01rts: uart1-rts { + rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2_5v { + uart2_5v_cts: uart2_5v-cts { + rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_5v_rts: uart2_5v-rts { + rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index ac24d98..54f5bc7 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -90,7 +90,7 @@ status = "disabled"; }; usart1: serial@40011000 { - compatible = "st,stm32-usart", "st,stm32-uart"; + compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 0 164>; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts new file mode 100644 index 0000000..cf76c35 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include + +/ { + model = "OrangePi Win/Win Plus"; + compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts new file mode 100644 index 0000000..c08af78 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include + +/ { + model = "FriendlyARM NanoPi NEO 2"; + compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts new file mode 100644 index 0000000..3f4baba --- /dev/null +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include + + +/ { + model = "OrangePi Zero Plus2"; + compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts new file mode 100644 index 0000000..8ddd1b2 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1 Plus"; + compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index fff1d78..65c3851 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -12,4 +12,13 @@ u-boot,dm-pre-reloc; }; }; + + spi@7000d400 { + spi-deactivate-delay = <200>; + spi-max-frequency = <3000000>; + + cros_ec: cros-ec@0 { + ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts deleted file mode 100644 index 4478746..0000000 --- a/arch/arm/dts/tegra20-whistler.dts +++ /dev/null @@ -1,77 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "NVIDIA Tegra20 Whistler evaluation board"; - compatible = "nvidia,whistler", "nvidia,tegra20"; - - chosen { - stdout-path = &uarta; - }; - - aliases { - i2c0 = "/i2c@7000d000"; - usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000400"; - }; - - memory { - device_type = "memory"; - reg = < 0x00000000 0x20000000 >; - }; - - serial@70006000 { - clock-frequency = < 216000000 >; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - pmic@3c { - compatible = "maxim,max8907b"; - reg = <0x3c>; - - clk_32k: clock { - compatible = "fixed-clock"; - /* - * leave out for now due to CPP: - * #clock-cells = <0>; - */ - clock-frequency = <32768>; - }; - }; - }; - - usb@c5008000 { - status = "okay"; - }; - - sdhci@c8000400 { - status = "okay"; - wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - -}; diff --git a/arch/arm/dts/zynq-topic-miamilite.dts b/arch/arm/dts/zynq-topic-miamilite.dts new file mode 100644 index 0000000..f88cb4b --- /dev/null +++ b/arch/arm/dts/zynq-topic-miamilite.dts @@ -0,0 +1,17 @@ +/* + * Topic Miami Lite board DTS + * + * Copyright (C) 2017 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include "zynq-topic-miami.dts" + +/ { + model = "Topic Miami Lite Zynq Board"; + compatible = "topic,miamilite", "xlnx,zynq-7000"; +}; + +&qspi { + is-dual = <1>; +}; diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 19ccf5c..5399bb8 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -14,7 +14,7 @@ #include #include -#ifdef CONFIG_TI81XX +#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 653ec1b..bc1dab5 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -29,6 +29,7 @@ #define NUM_OPPS 6 extern void enable_dmm_clocks(void); +extern void enable_emif_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 8cae291..e8d7d54 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -36,12 +36,6 @@ #define TCFG_RESET BIT(0) /* software reset */ #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ #define TCFG_IDLEMOD_SHIFT (2) /* power management */ -/* device type */ -#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 /* cpu-id for AM43XX AM33XX and TI81XX family */ #define AM437X 0xB98C diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 43e122e..a97ebb5 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -354,9 +354,15 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; +#ifdef CONFIG_TI816X +void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, + const struct dmm_lisa_map_regs *lisa_regs, int nrs); +#else void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +#endif void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 3293caa..d2c5df8 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -21,7 +21,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI81XX) +#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define NON_SECURE_SRAM_IMG_END 0x4031B800 @@ -41,6 +41,9 @@ struct omap_boot_parameters { unsigned char boot_device; unsigned char reset_reason; }; + +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #endif #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index 6935913..bf32782 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -20,5 +20,7 @@ enum mxc_clock { }; unsigned int mxc_get_clock(enum mxc_clock clk); +ulong get_ddr_freq(ulong); +uint get_svr(void); #endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index d6a273a..c4e5ecc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -353,4 +353,5 @@ static struct mm_region final_map[] = { int fsl_qoriq_core_to_cluster(unsigned int core); u32 cpu_mask(void); + #endif /* _FSL_LAYERSCAPE_CPU_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index cc3b079..497afe7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -8,6 +8,16 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ +#ifndef __ASSEMBLY__ +#include +#ifdef CONFIG_FSL_LSCH2 +#include +#endif +#ifdef CONFIG_FSL_LSCH3 +#include +#endif +#endif + #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) #define gur_out32(a, v) out_le32(a, v) @@ -120,4 +130,5 @@ void erratum_a010315(void); bool soc_has_dp_ddr(void); bool soc_has_aiop(void); #endif + #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index b052406..ec5b419 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -50,3 +50,10 @@ #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 u32 get_imx_reset_cause(void); +ulong get_systemPLLCLK(void); +ulong get_FCLK(void); +ulong get_HCLK(void); +ulong get_BCLK(void); +ulong get_PERCLK1(void); +ulong get_PERCLK2(void); +ulong get_PERCLK3(void); diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h index fd36bb0..a1d6afe 100644 --- a/arch/arm/include/asm/arch-ls102xa/clock.h +++ b/arch/arm/include/asm/arch-ls102xa/clock.h @@ -19,5 +19,7 @@ enum mxc_clock { }; unsigned int mxc_get_clock(enum mxc_clock clk); +ulong get_ddr_freq(ulong); +uint get_svr(void); #endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/soc.h b/arch/arm/include/asm/arch-ls102xa/soc.h new file mode 100644 index 0000000..e69de29 diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h index db763e4..8933f54 100644 --- a/arch/arm/include/asm/arch-omap3/omap.h +++ b/arch/arm/include/asm/arch-omap3/omap.h @@ -91,6 +91,9 @@ struct s32ktimer { unsigned int s32k_cr; /* 0x10 */ }; +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + #endif /* __ASSEMBLY__ */ #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index b86a776..1a3ff7d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -100,7 +100,6 @@ struct s32ktimer { #define DEVICE_TYPE_SHIFT (0x8) #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#define DEVICE_GP 0x3 #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 8f31da1..2f005dd 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -127,7 +127,6 @@ struct s32ktimer { #define DEVICE_TYPE_SHIFT 0x6 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#define DEVICE_GP 0x3 /* Output impedance control */ #define ds_120_ohm 0x0 diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h index aaef4b9..22278e1 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -16,9 +16,9 @@ #define CORE_PERI_HZ 150000000 #define CORE_ACLK_HZ 300000000 -#define CPU_ACLK_HZ 150000000 -#define CPU_HCLK_HZ 300000000 -#define CPU_PCLK_HZ 300000000 +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 #define PERI_ACLK_HZ 148500000 #define PERI_HCLK_HZ 148500000 @@ -68,102 +68,102 @@ struct pll_div { enum { /* PLLCON0*/ - PLL_POSTDIV1_MASK = 7, PLL_POSTDIV1_SHIFT = 12, - PLL_FBDIV_MASK = 0xfff, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, /* PLLCON1 */ - PLL_DSMPD_MASK = 1, + PLL_RST_SHIFT = 14, PLL_DSMPD_SHIFT = 12, - PLL_LOCK_STATUS_MASK = 1, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, PLL_LOCK_STATUS_SHIFT = 10, - PLL_POSTDIV2_MASK = 7, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, PLL_POSTDIV2_SHIFT = 6, - PLL_REFDIV_MASK = 0x3f, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, PLL_REFDIV_SHIFT = 0, - PLL_RST_SHIFT = 14, + PLL_REFDIV_MASK = 0x3f, /* CRU_MODE */ - GPLL_MODE_MASK = 3, GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORM, GPLL_MODE_DEEP, - DPLL_MODE_MASK = 1, DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORM, - APLL_MODE_MASK = 1, APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORM, /* CRU_CLK_SEL0_CON */ - CPU_CLK_PLL_SEL_MASK = 3, - CPU_CLK_PLL_SEL_SHIFT = 14, - CPU_CLK_PLL_SEL_APLL = 0, - CPU_CLK_PLL_SEL_DPLL, - CPU_CLK_PLL_SEL_GPLL, - ACLK_CPU_DIV_MASK = 0x1f, - ACLK_CPU_DIV_SHIFT = 8, - CORE_CLK_PLL_SEL_MASK = 1, + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_DPLL, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, CORE_CLK_PLL_SEL_APLL = 0, CORE_CLK_PLL_SEL_GPLL, - CORE_DIV_CON_MASK = 0x1f, CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, /* CRU_CLK_SEL1_CON */ - CPU_PCLK_DIV_MASK = 7, - CPU_PCLK_DIV_SHIFT = 12, - CPU_HCLK_DIV_MASK = 3, - CPU_HCLK_DIV_SHIFT = 8, - CORE_ACLK_DIV_MASK = 7, + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, CORE_ACLK_DIV_SHIFT = 4, - CORE_PERI_DIV_MASK = 0xf, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, /* CRU_CLKSEL10_CON */ - PERI_PLL_SEL_MASK = 3, PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, PERI_PLL_APLL = 0, PERI_PLL_DPLL, PERI_PLL_GPLL, - PERI_PCLK_DIV_MASK = 3, PERI_PCLK_DIV_SHIFT = 12, - PERI_HCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, PERI_HCLK_DIV_SHIFT = 8, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, /* CRU_CLKSEL11_CON */ - SDIO_DIV_MASK = 0x7f, SDIO_DIV_SHIFT = 8, - MMC0_DIV_MASK = 0x7f, + SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, /* CRU_CLKSEL12_CON */ - EMMC_PLL_MASK = 3, EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_SEL_APLL = 0, EMMC_SEL_DPLL, EMMC_SEL_GPLL, EMMC_SEL_24M, - SDIO_PLL_MASK = 3, SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, SDIO_SEL_APLL = 0, SDIO_SEL_DPLL, SDIO_SEL_GPLL, SDIO_SEL_24M, - MMC0_PLL_MASK = 3, MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_SEL_APLL = 0, MMC0_SEL_DPLL, MMC0_SEL_GPLL, MMC0_SEL_24M, - EMMC_DIV_MASK = 0x7f, EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, /* CRU_SOFTRST5_CON */ DDRCTRL_PSRST_SHIFT = 11, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d575f4a..cb0a935 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c); /* CRU_CLKSEL11_CON */ enum { HSICPHY_DIV_SHIFT = 8, - HSICPHY_DIV_MASK = 0x3f, + HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT, MMC0_PLL_SHIFT = 6, - MMC0_PLL_MASK = 3, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_PLL_SELECT_CODEC = 0, MMC0_PLL_SELECT_GENERAL, MMC0_PLL_SELECT_24MHZ, MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, }; /* CRU_CLKSEL12_CON */ enum { EMMC_PLL_SHIFT = 0xe, - EMMC_PLL_MASK = 3, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_PLL_SELECT_CODEC = 0, EMMC_PLL_SELECT_GENERAL, EMMC_PLL_SELECT_24MHZ, EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f, + EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT, SDIO0_PLL_SHIFT = 6, - SDIO0_PLL_MASK = 3, + SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, SDIO0_PLL_SELECT_CODEC = 0, SDIO0_PLL_SELECT_GENERAL, SDIO0_PLL_SELECT_24MHZ, SDIO0_DIV_SHIFT = 0, - SDIO0_DIV_MASK = 0x3f, + SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, }; /* CRU_CLKSEL21_CON */ enum { - MAC_DIV_CON_SHIFT = 0xf, - MAC_DIV_CON_MASK = 0x1f, + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT, - RMII_EXTCLK_SHIFT = 4, - RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, RMII_EXTCLK_SELECT_EXT_CLK = 1, - EMAC_PLL_SHIFT = 0, - EMAC_PLL_MASK = 0x3, - EMAC_PLL_SELECT_NEW = 0x0, - EMAC_PLL_SELECT_CODEC = 0x1, - EMAC_PLL_SELECT_GENERAL = 0x2, + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, }; /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, - SPI1_PLL_MASK = 1, + SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, SPI1_PLL_SELECT_CODEC = 0, SPI1_PLL_SELECT_GENERAL, SPI1_DIV_SHIFT = 8, - SPI1_DIV_MASK = 0x7f, + SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, SPI0_PLL_SHIFT = 7, - SPI0_PLL_MASK = 1, + SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, SPI0_PLL_SELECT_CODEC = 0, SPI0_PLL_SELECT_GENERAL, SPI0_DIV_SHIFT = 0, - SPI0_DIV_MASK = 0x7f, + SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, }; /* CRU_CLKSEL37_CON */ enum { PCLK_CORE_DBG_DIV_SHIFT = 9, - PCLK_CORE_DBG_DIV_MASK = 0x1f, + PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT, ATCLK_CORE_DIV_CON_SHIFT = 4, - ATCLK_CORE_DIV_CON_MASK = 0x1f, + ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT, CLK_L2RAM_DIV_SHIFT = 0, - CLK_L2RAM_DIV_MASK = 7, + CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, }; /* CRU_CLKSEL39_CON */ enum { ACLK_HEVC_PLL_SHIFT = 0xe, - ACLK_HEVC_PLL_MASK = 3, + ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, ACLK_HEVC_PLL_SELECT_CODEC = 0, ACLK_HEVC_PLL_SELECT_GENERAL, ACLK_HEVC_PLL_SELECT_NEW, ACLK_HEVC_DIV_SHIFT = 8, - ACLK_HEVC_DIV_MASK = 0x1f, + ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT, SPI2_PLL_SHIFT = 7, - SPI2_PLL_MASK = 1, + SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, SPI2_PLL_SELECT_CODEC = 0, SPI2_PLL_SELECT_GENERAL, SPI2_DIV_SHIFT = 0, - SPI2_DIV_MASK = 0x7f, + SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, }; /* CRU_MODE_CON */ enum { + CRU_MODE_MASK = 3, + NPLL_MODE_SHIFT = 0xe, - NPLL_MODE_MASK = 3, + NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, NPLL_MODE_SLOW = 0, NPLL_MODE_NORMAL, NPLL_MODE_DEEP, GPLL_MODE_SHIFT = 0xc, - GPLL_MODE_MASK = 3, + GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORMAL, GPLL_MODE_DEEP, CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 3, + CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, CPLL_MODE_SLOW = 0, CPLL_MODE_NORMAL, CPLL_MODE_DEEP, DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 3, + DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORMAL, DPLL_MODE_DEEP, APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 3, + APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORMAL, APLL_MODE_DEEP, @@ -201,21 +203,21 @@ enum { /* CRU_APLL_CON0 */ enum { CLKR_SHIFT = 8, - CLKR_MASK = 0x3f, + CLKR_MASK = 0x3f << CLKR_SHIFT, CLKOD_SHIFT = 0, - CLKOD_MASK = 0xf, + CLKOD_MASK = 0xf << CLKOD_SHIFT, }; /* CRU_APLL_CON1 */ enum { LOCK_SHIFT = 0x1f, - LOCK_MASK = 1, + LOCK_MASK = 1 << LOCK_SHIFT, LOCK_UNLOCK = 0, LOCK_LOCK, CLKF_SHIFT = 0, - CLKF_MASK = 0x1fff, + CLKF_MASK = 0x1fff << CLKF_SHIFT, }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h new file mode 100644 index 0000000..4910ee7 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3368_H +#define _ASM_ARCH_CRU_RK3368_H + +#include + + +/* RK3368 clock numbers */ +enum rk3368_pll_id { + APLLB, + APLLL, + DPLL, + CPLL, + GPLL, + NPLL, + PLL_COUNT, +}; + +struct rk3368_cru { + struct rk3368_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[6]; + unsigned int reserved[0x28]; + unsigned int clksel_con[56]; + unsigned int reserved1[8]; + unsigned int clkgate_con[25]; + unsigned int reserved2[7]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int reserved3[0x1e]; + unsigned int softrst_con[15]; + unsigned int reserved4[0x11]; + unsigned int misc_con; + unsigned int glb_cnt_th; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int reserved5[0x1c]; + unsigned int sdmmc_con[2]; + unsigned int sdio0_con[2]; + unsigned int sdio1_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rk3368_cru, emmc_con[1], 0x41c); + +struct rk3368_clk_priv { + struct rk3368_cru *cru; + ulong rate; + bool has_bwadj; +}; + +enum { + /* PLL CON0 */ + PLL_NR_SHIFT = 8, + PLL_NR_MASK = GENMASK(13, 8), + PLL_OD_SHIFT = 0, + PLL_OD_MASK = GENMASK(3, 0), + + /* PLL CON1 */ + PLL_LOCK_STA = BIT(31), + PLL_NF_SHIFT = 0, + PLL_NF_MASK = GENMASK(12, 0), + + /* PLL CON2 */ + PLL_BWADJ_SHIFT = 0, + PLL_BWADJ_MASK = GENMASK(11, 0), + + /* PLL CON3 */ + PLL_MODE_SHIFT = 8, + PLL_MODE_MASK = GENMASK(9, 8), + PLL_MODE_SLOW = 0, + PLL_MODE_NORMAL = 1, + PLL_MODE_DEEP_SLOW = 3, + PLL_RESET_SHIFT = 5, + PLL_RESET = 1, + PLL_RESET_MASK = GENMASK(5, 5), + + /* CLKSEL12_CON */ + MCU_STCLK_DIV_SHIFT = 8, + MCU_STCLK_DIV_MASK = GENMASK(10, 8), + MCU_PLL_SEL_SHIFT = 7, + MCU_PLL_SEL_MASK = BIT(7), + MCU_PLL_SEL_CPLL = 0, + MCU_PLL_SEL_GPLL = 1, + MCU_CLK_DIV_SHIFT = 0, + MCU_CLK_DIV_MASK = GENMASK(4, 0), + + /* CLKSEL51_CON */ + MMC_PLL_SEL_SHIFT = 8, + MMC_PLL_SEL_MASK = GENMASK(9, 8), + MMC_PLL_SEL_CPLL = 0, + MMC_PLL_SEL_GPLL, + MMC_PLL_SEL_USBPHY_480M, + MMC_PLL_SEL_24M, + MMC_CLK_DIV_SHIFT = 0, + MMC_CLK_DIV_MASK = GENMASK(6, 0), + + /* SOFTRST1_CON */ + MCU_PO_SRST_MASK = BIT(13), + MCU_SYS_SRST_MASK = BIT(12), + + /* GLB_RST_CON */ + PMU_GLB_SRST_CTRL_SHIFT = 2, + PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), + PMU_RST_BY_FST_GLB_SRST = 0, + PMU_RST_BY_SND_GLB_SRST = 1, + PMU_RST_DISABLE = 2, + WDT_GLB_SRST_CTRL_SHIFT = 1, + WDT_GLB_SRST_CTRL_MASK = BIT(1), + WDT_TRIGGER_SND_GLB_SRST = 0, + WDT_TRIGGER_FST_GLB_SRST = 1, + TSADC_GLB_SRST_CTRL_SHIFT = 0, + TSADC_GLB_SRST_CTRL_MASK = BIT(0), + TSADC_TRIGGER_SND_GLB_SRST = 0, + TSADC_TRIGGER_FST_GLB_SRST = 1, + +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h new file mode 100644 index 0000000..2a1ae69 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RV1108_H +#define _ASM_ARCH_CRU_RV1108_H + +#include + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +struct rv1108_clk_priv { + struct rv1108_cru *cru; + ulong rate; +}; + +struct rv1108_cru { + struct rv1108_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int con5; + unsigned int reserved[2]; + } pll[3]; + unsigned int clksel_con[46]; + unsigned int reserved1[2]; + unsigned int clkgate_con[20]; + unsigned int reserved2[4]; + unsigned int softrst_con[13]; + unsigned int reserved3[3]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int glb_cnt_th; + unsigned int misc_con; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rv1108_cru, emmc_con[1], 0x01ec); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLL CON0 */ + FBDIV_MASK = 0xfff, + FBDIV_SHIFT = 0, + + /* PLL CON1 */ + POSTDIV2_SHIFT = 12, + POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, + POSTDIV1_SHIFT = 8, + POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, + REFDIV_MASK = 0x3f, + REFDIV_SHIFT = 0, + + /* PLL CON2 */ + LOCK_STA_SHIFT = 31, + LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, + FRACDIV_MASK = 0xffffff, + FRACDIV_SHIFT = 0, + + /* PLL CON3 */ + WORK_MODE_SHIFT = 8, + WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, + WORK_MODE_SLOW = 0, + WORK_MODE_NORMAL = 1, + DSMPD_SHIFT = 3, + DSMPD_MASK = 1 << DSMPD_SHIFT, + + /* CLKSEL0_CON */ + CORE_PLL_SEL_SHIFT = 8, + CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, + CORE_PLL_SEL_APLL = 0, + CORE_PLL_SEL_GPLL = 1, + CORE_PLL_SEL_DPLL = 2, + CORE_CLK_DIV_SHIFT = 0, + CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + + /* CLKSEL24_CON */ + MAC_PLL_SEL_SHIFT = 12, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + MAC_PLL_SEL_APLL = 0, + MAC_PLL_SEL_GPLL = 1, + RMII_EXTCLK_SEL_SHIFT = 8, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, + MAC_CLK_DIV_MASK = 0x1f, + MAC_CLK_DIV_SHIFT = 0, + + /* CLKSEL27_CON */ + SFC_PLL_SEL_SHIFT = 7, + SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, + SFC_PLL_SEL_DPLL = 0, + SFC_PLL_SEL_GPLL = 1, + SFC_CLK_DIV_SHIFT = 0, + SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h index 72d133c..7625f24 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -83,57 +83,56 @@ check_member(rk3036_grf, sdmmc_det_cnt, 0x304); /* GRF_GPIO0A_IOMUX */ enum { GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 1, + GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, GPIO0A3_GPIO = 0, GPIO0A3_I2C1_SDA, GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 1, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, GPIO0A2_GPIO = 0, GPIO0A2_I2C1_SCL, GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, GPIO0A1_GPIO = 0, GPIO0A1_I2C0_SDA, GPIO0A1_PWM2, GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, GPIO0A0_GPIO = 0, GPIO0A0_I2C0_SCL, GPIO0A0_PWM1, - }; /* GRF_GPIO0B_IOMUX */ enum { GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, GPIO0B6_GPIO = 0, GPIO0B6_MMC1_D3, GPIO0B6_I2S1_SCLK, GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, GPIO0B5_GPIO = 0, GPIO0B5_MMC1_D2, GPIO0B5_I2S1_SDI, GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = 3, + GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, GPIO0B4_GPIO = 0, GPIO0B4_MMC1_D1, GPIO0B4_I2S1_LRCKTX, GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, GPIO0B3_GPIO = 0, GPIO0B3_MMC1_D0, GPIO0B3_I2S1_LRCKRX, GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, GPIO0B1_GPIO = 0, GPIO0B1_MMC1_CLKOUT, GPIO0B1_I2S1_MCLK, @@ -148,28 +147,28 @@ enum { /* GRF_GPIO0C_IOMUX */ enum { GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 1, + GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, GPIO0C4_GPIO = 0, GPIO0C4_DRIVE_VBUS, GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 1, + GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, GPIO0C3_GPIO = 0, GPIO0C3_UART0_CTSN, GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 1, + GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, GPIO0C2_GPIO = 0, GPIO0C2_UART0_RTSN, GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 1, + GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, GPIO0C1_GPIO = 0, GPIO0C1_UART0_SIN, GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 1, + GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, GPIO0C0_GPIO = 0, GPIO0C0_UART0_SOUT, }; @@ -177,17 +176,17 @@ enum { /* GRF_GPIO0D_IOMUX */ enum { GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, GPIO0D4_GPIO = 0, GPIO0D4_SPDIF, GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 1, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, GPIO0D3_GPIO = 0, GPIO0D3_PWM3, GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 1, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, GPIO0D2_GPIO = 0, GPIO0D2_PWM0, }; @@ -195,33 +194,33 @@ enum { /* GRF_GPIO1A_IOMUX */ enum { GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 1, + GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, GPIO1A5_GPIO = 0, GPIO1A5_I2S_SDI, GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 1, + GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, GPIO1A4_GPIO = 0, GPIO1A4_I2S_SD0, GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, GPIO1A3_GPIO = 0, GPIO1A3_I2S_LRCKTX, GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 6, + GPIO1A2_MASK = 6 << GPIO1A2_SHIFT, GPIO1A2_GPIO = 0, GPIO1A2_I2S_LRCKRX, GPIO1A2_I2S_PWM1_0, GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1, + GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, GPIO1A1_GPIO = 0, GPIO1A1_I2S_SCLK, GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1, + GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, GPIO1A0_GPIO = 0, GPIO1A0_I2S_MCLK, @@ -230,27 +229,27 @@ enum { /* GRF_GPIO1B_IOMUX */ enum { GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, GPIO1B7_GPIO = 0, GPIO1B7_MMC0_CMD, GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 1, + GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, GPIO1B3_GPIO = 0, GPIO1B3_HDMI_HPD, GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 1, + GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, GPIO1B2_GPIO = 0, GPIO1B2_HDMI_SCL, GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 1, + GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, GPIO1B1_GPIO = 0, GPIO1B1_HDMI_SDA, GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 1, + GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, GPIO1B0_GPIO = 0, GPIO1B0_HDMI_CEC, }; @@ -258,36 +257,36 @@ enum { /* GRF_GPIO1C_IOMUX */ enum { GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, GPIO1C5_GPIO = 0, GPIO1C5_MMC0_D3, GPIO1C5_JTAG_TMS, GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, GPIO1C4_GPIO = 0, GPIO1C4_MMC0_D2, GPIO1C4_JTAG_TCK, GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, GPIO1C3_GPIO = 0, GPIO1C3_MMC0_D1, GPIO1C3_UART2_SOUT, GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , GPIO1C2_GPIO = 0, GPIO1C2_MMC0_D0, GPIO1C2_UART2_SIN, GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 1, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, GPIO1C1_GPIO = 0, GPIO1C1_MMC0_DETN, GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 1, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, GPIO1C0_GPIO = 0, GPIO1C0_MMC0_CLKOUT, }; @@ -295,56 +294,56 @@ enum { /* GRF_GPIO1D_IOMUX */ enum { GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, GPIO1D7_GPIO = 0, GPIO1D7_NAND_D7, GPIO1D7_EMMC_D7, GPIO1D7_SPI_CSN1, GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, GPIO1D6_GPIO = 0, GPIO1D6_NAND_D6, GPIO1D6_EMMC_D6, GPIO1D6_SPI_CSN0, GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, GPIO1D5_GPIO = 0, GPIO1D5_NAND_D5, GPIO1D5_EMMC_D5, GPIO1D5_SPI_TXD, GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, GPIO1D4_GPIO = 0, GPIO1D4_NAND_D4, GPIO1D4_EMMC_D4, GPIO1D4_SPI_RXD, GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, GPIO1D3_GPIO = 0, GPIO1D3_NAND_D3, GPIO1D3_EMMC_D3, GPIO1D3_SFC_SIO3, GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, GPIO1D2_GPIO = 0, GPIO1D2_NAND_D2, GPIO1D2_EMMC_D2, GPIO1D2_SFC_SIO2, GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, GPIO1D1_GPIO = 0, GPIO1D1_NAND_D1, GPIO1D1_EMMC_D1, GPIO1D1_SFC_SIO1, GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, GPIO1D0_GPIO = 0, GPIO1D0_NAND_D0, GPIO1D0_EMMC_D0, @@ -354,42 +353,42 @@ enum { /* GRF_GPIO2A_IOMUX */ enum { GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 1, + GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, GPIO2A7_GPIO = 0, GPIO2A7_TESTCLK_OUT, GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 1, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, GPIO2A6_GPIO = 0, GPIO2A6_NAND_CS0, GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, GPIO2A4_GPIO = 0, GPIO2A4_NAND_RDY, GPIO2A4_EMMC_CMD, GPIO2A3_SFC_CLK, GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, GPIO2A3_GPIO = 0, GPIO2A3_NAND_RDN, GPIO2A4_SFC_CSN1, GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, GPIO2A2_GPIO = 0, GPIO2A2_NAND_WRN, GPIO2A4_SFC_CSN0, GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, GPIO2A1_GPIO = 0, GPIO2A1_NAND_CLE, GPIO2A1_EMMC_CLKOUT, GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, GPIO2A0_GPIO = 0, GPIO2A0_NAND_ALE, GPIO2A0_SPI_CLK, @@ -398,28 +397,28 @@ enum { /* GRF_GPIO2B_IOMUX */ enum { GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 1, + GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, GPIO2B7_GPIO = 0, GPIO2B7_MAC_RXER, GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, GPIO2B6_GPIO = 0, GPIO2B6_MAC_CLKOUT, GPIO2B6_MAC_CLKIN, GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, GPIO2B5_GPIO = 0, GPIO2B5_MAC_TXEN, GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 1, + GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, GPIO2B4_GPIO = 0, GPIO2B4_MAC_MDIO, GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, GPIO2B2_GPIO = 0, GPIO2B2_MAC_CRS, }; @@ -427,43 +426,43 @@ enum { /* GRF_GPIO2C_IOMUX */ enum { GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, GPIO2C7_GPIO = 0, GPIO2C7_UART1_SOUT, GPIO2C7_TESTCLK_OUT1, GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 1, + GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, GPIO2C6_GPIO = 0, GPIO2C6_UART1_SIN, GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 1, + GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, GPIO2C5_GPIO = 0, GPIO2C5_I2C2_SCL, GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 1, + GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, GPIO2C4_GPIO = 0, GPIO2C4_I2C2_SDA, GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 1, + GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, GPIO2C3_GPIO = 0, GPIO2C3_MAC_TXD0, GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 1, + GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, GPIO2C2_GPIO = 0, GPIO2C2_MAC_TXD1, GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 1, + GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, GPIO2C1_GPIO = 0, GPIO2C1_MAC_RXD0, GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 1, + GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, GPIO2C0_GPIO = 0, GPIO2C0_MAC_RXD1, }; @@ -471,22 +470,22 @@ enum { /* GRF_GPIO2D_IOMUX */ enum { GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, GPIO2D6_GPIO = 0, GPIO2D6_I2S_SDO1, GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, GPIO2D5_GPIO = 0, GPIO2D5_I2S_SDO2, GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, GPIO2D4_GPIO = 0, GPIO2D4_I2S_SDO3, GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 1, + GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, GPIO2D1_GPIO = 0, GPIO2D1_MAC_MDC, }; diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 7d56b8c..fbc4a0d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -813,7 +813,7 @@ enum { (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, RK3288_CLK_RX_DL_CFG_GMAC_MASK = diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h index 2776cef..f0a0781 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -131,4 +131,118 @@ struct rk3328_sgrf_regs { }; check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); +enum { + /* GPIO0A_IOMUX */ + GPIO0A5_SEL_SHIFT = 10, + GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, + GPIO0A5_I2C3_SCL = 2, + + GPIO0A6_SEL_SHIFT = 12, + GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, + GPIO0A6_I2C3_SDA = 2, + + GPIO0A7_SEL_SHIFT = 14, + GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, + GPIO0A7_EMMC_DATA0 = 2, + + /* GPIO0D_IOMUX*/ + GPIO0D6_SEL_SHIFT = 12, + GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDMMC0_PWRENM1 = 3, + + /* GPIO1A_IOMUX */ + GPIO1A0_SEL_SHIFT = 0, + GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, + GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, + + /* GPIO2A_IOMUX */ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, + + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + + GPIO2A2_SEL_SHIFT = 4, + GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, + GPIO2A2_PWM_IR = 1, + + GPIO2A4_SEL_SHIFT = 8, + GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, + GPIO2A4_PWM_0 = 1, + GPIO2A4_I2C1_SDA, + + GPIO2A5_SEL_SHIFT = 10, + GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, + GPIO2A5_PWM_1 = 1, + GPIO2A5_I2C1_SCL, + + GPIO2A6_SEL_SHIFT = 12, + GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, + GPIO2A6_PWM_2 = 1, + + GPIO2A7_SEL_SHIFT = 14, + GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_PWRENM0, + + /* GPIO2BL_IOMUX */ + GPIO2BL0_SEL_SHIFT = 0, + GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, + GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, + + GPIO2BL3_SEL_SHIFT = 6, + GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, + GPIO2BL3_SPI_CSN0_M0 = 1, + + GPIO2BL4_SEL_SHIFT = 8, + GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, + GPIO2BL4_SPI_CSN1_M0 = 1, + + GPIO2BL5_SEL_SHIFT = 10, + GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, + GPIO2BL5_I2C2_SDA = 1, + + GPIO2BL6_SEL_SHIFT = 12, + GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, + GPIO2BL6_I2C2_SCL = 1, + + /* GPIO2D_IOMUX */ + GPIO2D0_SEL_SHIFT = 0, + GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, + GPIO2D0_I2C0_SCL = 1, + + GPIO2D1_SEL_SHIFT = 2, + GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, + GPIO2D1_I2C0_SDA = 1, + + GPIO2D4_SEL_SHIFT = 8, + GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, + GPIO2D4_EMMC_DATA1234 = 0xaa, + + /* GPIO3C_IOMUX */ + GPIO3C0_SEL_SHIFT = 0, + GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, + GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, + + /* COM_IOMUX */ + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + + IOMUX_SEL_SPI_SHIFT = 4, + IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, + IOMUX_SEL_SPI_M0 = 0, + IOMUX_SEL_SPI_M1, + IOMUX_SEL_SPI_M2, + + IOMUX_SEL_SDMMC_SHIFT = 7, + IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, + IOMUX_SEL_SDMMC_M0 = 0, + IOMUX_SEL_SDMMC_M1, +}; + #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h new file mode 100644 index 0000000..3233dc3 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -0,0 +1,440 @@ +/* (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3368_H +#define _ASM_ARCH_GRF_RK3368_H + +#include + +struct rk3368_grf { + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 reserved[0x34]; + u32 gpio1a_pull; + u32 gpio1b_pull; + u32 gpio1c_pull; + u32 gpio1d_pull; + u32 gpio2a_pull; + u32 gpio2b_pull; + u32 gpio2c_pull; + u32 gpio2d_pull; + u32 gpio3a_pull; + u32 gpio3b_pull; + u32 gpio3c_pull; + u32 gpio3d_pull; + u32 reserved1[0x34]; + u32 gpio1a_drv; + u32 gpio1b_drv; + u32 gpio1c_drv; + u32 gpio1d_drv; + u32 gpio2a_drv; + u32 gpio2b_drv; + u32 gpio2c_drv; + u32 gpio2d_drv; + u32 gpio3a_drv; + u32 gpio3b_drv; + u32 gpio3c_drv; + u32 gpio3d_drv; + u32 reserved2[0x34]; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved3[0x1a]; + u32 gpio_smt; + u32 reserved4[0x1f]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; +}; +check_member(rk3368_grf, soc_con17, 0x444); + +struct rk3368_pmu_grf { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + u32 gpio0a_pull; + u32 gpio0b_pull; + u32 gpio0c_pull; + u32 gpio0d_pull; + u32 gpio0a_drv; + u32 gpio0b_drv; + u32 gpio0c_drv; + u32 gpio0d_drv; + u32 gpio0l_sr; + u32 gpio0h_sr; +}; +check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); + +/*GRF_GPIO0C_IOMUX*/ +enum { + GPIO0C7_SHIFT = 14, + GPIO0C7_MASK = 3 << GPIO0C7_SHIFT, + GPIO0C7_GPIO = 0, + GPIO0C7_LCDC_D19, + GPIO0C7_TRACE_D9, + GPIO0C7_UART1_RTSN, + + GPIO0C6_SHIFT = 12, + GPIO0C6_MASK = 3 << GPIO0C6_SHIFT, + GPIO0C6_GPIO = 0, + GPIO0C6_LCDC_D18, + GPIO0C6_TRACE_D8, + GPIO0C6_UART1_CTSN, + + GPIO0C5_SHIFT = 10, + GPIO0C5_MASK = 3 << GPIO0C5_SHIFT, + GPIO0C5_GPIO = 0, + GPIO0C5_LCDC_D17, + GPIO0C5_TRACE_D7, + GPIO0C5_UART1_SOUT, + + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_LCDC_D16, + GPIO0C4_TRACE_D6, + GPIO0C4_UART1_SIN, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 3 << GPIO0C3_SHIFT, + GPIO0C3_GPIO = 0, + GPIO0C3_LCDC_D15, + GPIO0C3_TRACE_D5, + GPIO0C3_MCU_JTAG_TDO, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 3 << GPIO0C2_SHIFT, + GPIO0C2_GPIO = 0, + GPIO0C2_LCDC_D14, + GPIO0C2_TRACE_D4, + GPIO0C2_MCU_JTAG_TDI, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_LCDC_D13, + GPIO0C1_TRACE_D3, + GPIO0C1_MCU_JTAG_TRTSN, + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 3 << GPIO0C0_SHIFT, + GPIO0C0_GPIO = 0, + GPIO0C0_LCDC_D12, + GPIO0C0_TRACE_D2, + GPIO0C0_MCU_JTAG_TDO, +}; + +/*GRF_GPIO0D_IOMUX*/ +enum { + GPIO0D7_SHIFT = 14, + GPIO0D7_MASK = 3 << GPIO0D7_SHIFT, + GPIO0D7_GPIO = 0, + GPIO0D7_LCDC_DCLK, + GPIO0D7_TRACE_CTL, + GPIO0D7_PMU_DEBUG5, + + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_LCDC_DEN, + GPIO0D6_TRACE_CLK, + GPIO0D6_PMU_DEBUG4, + + GPIO0D5_SHIFT = 10, + GPIO0D5_MASK = 3 << GPIO0D5_SHIFT, + GPIO0D5_GPIO = 0, + GPIO0D5_LCDC_VSYNC, + GPIO0D5_TRACE_D15, + GPIO0D5_PMU_DEBUG3, + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_LCDC_HSYNC, + GPIO0D4_TRACE_D14, + GPIO0D4_PMU_DEBUG2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_LCDC_D23, + GPIO0D3_TRACE_D13, + GPIO0D3_UART4_SIN, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_LCDC_D22, + GPIO0D2_TRACE_D12, + GPIO0D2_UART4_SOUT, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 3 << GPIO0D1_SHIFT, + GPIO0D1_GPIO = 0, + GPIO0D1_LCDC_D21, + GPIO0D1_TRACE_D11, + GPIO0D1_UART4_RTSN, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, + GPIO0D0_GPIO = 0, + GPIO0D0_LCDC_D20, + GPIO0D0_TRACE_D10, + GPIO0D0_UART4_CTSN, +}; + +/*GRF_GPIO2A_IOMUX*/ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_D2, + GPIO2A7_JTAG_TCK, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_SDMMC0_D1, + GPIO2A6_UART2_SIN, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_SDMMC0_D0, + GPIO2A5_UART2_SOUT, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_FLASH_DQS, + GPIO2A4_EMMC_CLKO, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_FLASH_CSN3, + GPIO2A3_EMMC_RSTNO, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_FLASH_CSN2, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_FLASH_CSN1, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_FLASH_CSN0, +}; + +/*GRF_GPIO2D_IOMUX*/ +enum { + GPIO2D7_SHIFT = 14, + GPIO2D7_MASK = 3 << GPIO2D7_SHIFT, + GPIO2D7_GPIO = 0, + GPIO2D7_SDIO0_D3, + + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_SDIO0_D2, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 3 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_SDIO0_D1, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 3 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_SDIO0_D0, + + GPIO2D3_SHIFT = 6, + GPIO2D3_MASK = 3 << GPIO2D3_SHIFT, + GPIO2D3_GPIO = 0, + GPIO2D3_UART0_RTS0, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_GPIO = 0, + GPIO2D2_UART0_CTS0, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3 << GPIO2D0_SHIFT, + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN, +}; + +/*GRF_GPIO3C_IOMUX*/ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 3 << GPIO3C7_SHIFT, + GPIO3C7_GPIO = 0, + GPIO3C7_EDPHDMI_CECINOUT, + GPIO3C7_ISP_FLASHTRIGIN, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_MAC_CLK, + GPIO3C6_ISP_SHUTTERTRIG, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_MAC_RXER, + GPIO3C5_ISP_PRELIGHTTRIG, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 3 << GPIO3C4_SHIFT, + GPIO3C4_GPIO = 0, + GPIO3C4_MAC_RXDV, + GPIO3C4_ISP_FLASHTRIGOUT, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + GPIO3C3_GPIO = 0, + GPIO3C3_MAC_RXDV, + GPIO3C3_EMMC_RSTNO, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + GPIO3C2_MAC_MDC = 0, + GPIO3C2_ISP_SHUTTEREN, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_MAC_RXD2, + GPIO3C1_UART3_RTSN, + + GPIO3C0_SHIFT = 0, + GPIO3C0_MASK = 3 << GPIO3C0_SHIFT, + GPIO3C0_GPIO = 0, + GPIO3C0_MAC_RXD1, + GPIO3C0_UART3_CTSN, + GPIO3C0_GPS_RFCLK, +}; + +/*GRF_GPIO3D_IOMUX*/ +enum { + GPIO3D7_SHIFT = 14, + GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, + GPIO3D7_GPIO = 0, + GPIO3D7_SC_VCC18V, + GPIO3D7_I2C2_SDA, + GPIO3D7_GPUJTAG_TCK, + + GPIO3D6_SHIFT = 12, + GPIO3D6_MASK = 3 << GPIO3D6_SHIFT, + GPIO3D6_GPIO = 0, + GPIO3D6_IR_TX, + GPIO3D6_UART3_SOUT, + GPIO3D6_PWM3, + + GPIO3D5_SHIFT = 10, + GPIO3D5_MASK = 3 << GPIO3D5_SHIFT, + GPIO3D5_GPIO = 0, + GPIO3D5_IR_RX, + GPIO3D5_UART3_SIN, + + GPIO3D4_SHIFT = 8, + GPIO3D4_MASK = 3 << GPIO3D4_SHIFT, + GPIO3D4_GPIO = 0, + GPIO3D4_MAC_TXCLKOUT, + GPIO3D4_SPI1_CSN1, + + GPIO3D3_SHIFT = 6, + GPIO3D3_MASK = 3 << GPIO3D3_SHIFT, + GPIO3D3_GPIO = 0, + GPIO3D3_HDMII2C_SCL, + GPIO3D3_I2C5_SCL, + + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_HDMII2C_SDA, + GPIO3D2_I2C5_SDA, + + GPIO3D1_SHIFT = 2, + GPIO3D1_MASK = 3 << GPIO3D1_SHIFT, + GPIO3D1_GPIO = 0, + GPIO3D1_MAC_RXCLKIN, + GPIO3D1_I2C4_SCL, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 3 << GPIO3D0_SHIFT, + GPIO3D0_GPIO = 0, + GPIO3D0_MAC_MDIO, + GPIO3D0_I2C4_SDA, +}; + +/*GRF_SOC_CON11/12/13*/ +enum { + MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, + MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON12*/ +enum { + MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0, + MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON13*/ +enum { + MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0, + MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON14*/ +enum { + MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12, + MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12), + MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8, + MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8), + MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4, + MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4), + MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, + MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index eda9956..8d21eb7 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -534,6 +534,9 @@ enum { GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, GRF_DSI0_VOP_SEL_B = 0, GRF_DSI0_VOP_SEL_L = 1, + GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6, + GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6, + GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6, /* GRF_SOC_CON22 */ GRF_DPHY_TX0_RXMODE_SHIFT = 0, diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h new file mode 100644 index 0000000..c816a5b --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RV1108_H +#define _ASM_ARCH_GRF_RV1108_H + +#include + +struct rv1108_grf { + u32 reserved[4]; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 reserved1[52]; + u32 gpio1a_pull; + u32 gpio1b_pull; + u32 gpio1c_pull; + u32 gpio1d_pull; + u32 gpio2a_pull; + u32 gpio2b_pull; + u32 gpio2c_pull; + u32 gpio2d_pull; + u32 gpio3a_pull; + u32 gpio3b_pull; + u32 gpio3c_pull; + u32 gpio3d_pull; + u32 reserved2[52]; + u32 gpio1a_drv; + u32 gpio1b_drv; + u32 gpio1c_drv; + u32 gpio1d_drv; + u32 gpio2a_drv; + u32 gpio2b_drv; + u32 gpio2c_drv; + u32 gpio2d_drv; + u32 gpio3a_drv; + u32 gpio3b_drv; + u32 gpio3c_drv; + u32 gpio3d_drv; + u32 reserved3[50]; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved4[26]; + u32 gpio1l_smt; + u32 gpio1h_smt; + u32 gpio2l_smt; + u32 gpio2h_smt; + u32 gpio3l_smt; + u32 gpio3h_smt; + u32 reserved5[24]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 reserved6[20]; + u32 soc_status0; + u32 soc_status1; + u32 reserved7[30]; + u32 cpu_con0; + u32 cpu_con1; + u32 reserved8[30]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; + u32 reserved9[29]; + u32 ddr_status; + u32 reserved10[30]; + u32 sig_det_con; + u32 reserved11[3]; + u32 sig_det_status; + u32 reserved12[3]; + u32 sig_det_clr; + u32 reserved13[23]; + u32 host_con0; + u32 host_con1; + u32 reserved14[2]; + u32 dma_con0; + u32 dma_con1; + u32 reserved15[539]; + u32 uoc_status; + u32 host_status; + u32 gmac_con0; + u32 chip_id; +}; +check_member(rv1108_grf, chip_id, 0xf90); + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_LCDC_D12, + GPIO1B7_I2S_SDIO2_M0, + GPIO1B7_GMAC_RXDV, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_LCDC_D13, + GPIO1B6_I2S_LRCLKTX_M0, + GPIO1B6_GMAC_RXD1, + + GPIO1B5_SHIFT = 10, + GPIO1B5_MASK = 3 << GPIO1B5_SHIFT, + GPIO1B5_GPIO = 0, + GPIO1B5_LCDC_D14, + GPIO1B5_I2S_SDIO1_M0, + GPIO1B5_GMAC_RXD0, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_LCDC_D15, + GPIO1B4_I2S_MCLK_M0, + GPIO1B4_GMAC_TXEN, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_LCDC_D16, + GPIO1B3_I2S_SCLK_M0, + GPIO1B3_GMAC_TXD1, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_LCDC_D17, + GPIO1B2_I2S_SDIO_M0, + GPIO1B2_GMAC_TXD0, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_LCDC_D9, + GPIO1B1_PWM7, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_LCDC_D8, + GPIO1B0_PWM6, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_CIF_D5, + GPIO1C7_I2S_SDIO2_M1, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_CIF_D4, + GPIO1C6_I2S_LRCLKTX_M1, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_LCDC_CLK, + GPIO1C5_GMAC_CLK, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_LCDC_HSYNC, + GPIO1C4_GMAC_MDC, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_LCDC_VSYNC, + GPIO1C3_GMAC_MDIO, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_LCDC_EN, + GPIO1C2_I2S_SDIO3_M0, + GPIO1C2_GMAC_RXER, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_LCDC_D10, + GPIO1C1_I2S_SDI_M0, + GPIO1C1_PWM4, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3, + GPIO1C0_GPIO = 0, + GPIO1C0_LCDC_D11, + GPIO1C0_I2S_LRCLKRX_M0, +}; + +/* GRF_GPIO1D_OIMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_HDMI_CEC, + GPIO1D7_DSP_RTCK, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 1 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_HDMI_HPD_M0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_UART2_RTSN, + GPIO1D5_HDMI_SDA_M0, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_UART2_CTSN, + GPIO1D4_HDMI_SCL_M0, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_UART0_SOUT, + GPIO1D3_SPI_TXD_M0, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_UART0_SIN, + GPIO1D2_SPI_RXD_M0, + GPIO1D2_DSP_TDI, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_UART0_RTSN, + GPIO1D1_SPI_CSN0_M0, + GPIO1D1_DSP_TMS, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_UART0_CTSN, + GPIO1D0_SPI_CLK_M0, + GPIO1D0_DSP_TCK, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_FLASH_D7, + GPIO2A7_EMMC_D7, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_FLASH_D6, + GPIO2A6_EMMC_D6, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_FLASH_D5, + GPIO2A5_EMMC_D5, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_FLASH_D4, + GPIO2A4_EMMC_D4, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_FLASH_D3, + GPIO2A3_EMMC_D3, + GPIO2A3_SFC_HOLD_IO3, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_FLASH_D2, + GPIO2A2_EMMC_D2, + GPIO2A2_SFC_WP_IO2, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_FLASH_D1, + GPIO2A1_EMMC_D1, + GPIO2A1_SFC_SO_IO1, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_FLASH_D0, + GPIO2A0_EMMC_D0, + GPIO2A0_SFC_SI_IO0, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_FLASH_CS1, + GPIO2B7_SFC_CLK, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 1 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_EMMC_CLKO, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_FLASH_CS0, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_FLASH_RDY, + GPIO2B4_EMMC_CMD, + GPIO2B4_SFC_CSN0, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 1 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_FLASH_RDN, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_FLASH_WRN, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 1 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_FLASH_CLE, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 1 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_FLASH_ALE, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D7_SHIFT = 14, + GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, + GPIO2D7_GPIO = 0, + GPIO2D7_SDIO_D0, + + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_SDIO_CMD, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_SDIO_CLKO, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_I2C1_SCL, + + GPIO2D3_SHIFT = 6, + GPIO2D3_MASK = 1 << GPIO2D3_SHIFT, + GPIO2D3_GPIO = 0, + GPIO2D3_I2C1_SDA, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_GPIO = 0, + GPIO2D2_UART2_SOUT_M0, + GPIO2D2_JTAG_TCK, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_UART2_SIN_M0, + GPIO2D1_JTAG_TMS, + GPIO2D1_DSP_TMS, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_CTSN, + GPIO2D0_SPI_CLK_M0, + GPIO2D0_DSP_TCK, +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, + GPIO3A7_GPIO = 0, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, + GPIO3A6_GPIO = 0, + GPIO3A6_UART1_SOUT, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, + GPIO3A5_GPIO = 0, + GPIO3A5_UART1_SIN, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, + GPIO3A4_GPIO = 0, + GPIO3A4_UART1_CTSN, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, + GPIO3A3_GPIO = 0, + GPIO3A3_UART1_RTSN, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, + GPIO3A2_GPIO = 0, + GPIO3A2_SDIO_D3, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, + GPIO3A1_GPIO = 0, + GPIO3A1_SDIO_D2, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 1, + GPIO3A0_GPIO = 0, + GPIO3A0_SDIO_D1, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, + GPIO3C7_GPIO = 0, + GPIO3C7_CIF_CLKI, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_CIF_VSYNC, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_SDMMC_CMD, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, + GPIO3C4_GPIO = 0, + GPIO3C4_SDMMC_CLKO, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + GPIO3C3_GPIO = 0, + GPIO3C3_SDMMC_D0, + GPIO3C3_UART2_SOUT_M1, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + GPIO3C2_GPIO = 0, + GPIO3C2_SDMMC_D1, + GPIO3C2_UART2_SIN_M1, + + GPIOC1_SHIFT = 2, + GPIOC1_MASK = 1 << GPIOC1_SHIFT, + GPIOC1_GPIO = 0, + GPIOC1_SDMMC_D2, + + GPIOC0_SHIFT = 0, + GPIOC0_MASK = 1, + GPIO3C0_GPIO = 0, + GPIO3C0_SDMMC_D3, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index 8018d47..9f4bc2e 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -42,6 +42,7 @@ enum periph_id { PERIPH_ID_SDMMC2, PERIPH_ID_HDMI, PERIPH_ID_GMAC, + PERIPH_ID_SFC, PERIPH_ID_COUNT, diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index d5599ec..21e59be 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -197,9 +197,20 @@ enum vop_modes { #define V_DSP_DEN_POL(x) (((x) & 1) << 6) #define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) #define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) +#define V_DSP_PIN_POL(x) (((x) & 0xf) << 4) #define V_DSP_OUT_MODE(x) ((x) & 0xf) /* VOP_DSP_CTRL1 */ +#define V_RK3399_DSP_MIPI_POL(x) ((x) << 28) +#define V_RK3399_DSP_EDP_POL(x) ((x) << 24) +#define V_RK3399_DSP_HDMI_POL(x) ((x) << 20) +#define V_RK3399_DSP_LVDS_POL(x) ((x) << 16) + +#define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf)) +#define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf)) +#define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf)) +#define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf)) + #define M_DSP_LAYER3_SEL (3 << 14) #define M_DSP_LAYER2_SEL (3 << 12) #define M_DSP_LAYER1_SEL (3 << 10) diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h deleted file mode 100644 index a749b64..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/gpio.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2012. - * - * Gabriel Huau - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S3C24X0_GPIO_H_ -#define _S3C24X0_GPIO_H_ - -enum s3c2440_gpio { - GPA0, - GPA1, - GPA2, - GPA3, - GPA4, - GPA5, - GPA6, - GPA7, - GPA8, - GPA9, - GPA10, - GPA11, - GPA12, - GPA13, - GPA14, - GPA15, - GPA16, - GPA17, - GPA18, - GPA19, - GPA20, - GPA21, - GPA22, - GPA23, - GPA24, - - GPB0 = 32, - GPB1, - GPB2, - GPB3, - GPB4, - GPB5, - GPB6, - GPB7, - GPB8, - GPB9, - GPB10, - - GPC0 = 64, - GPC1, - GPC2, - GPC3, - GPC4, - GPC5, - GPC6, - GPC7, - GPC8, - GPC9, - GPC10, - GPC11, - GPC12, - GPC13, - GPC14, - GPC15, - - GPD0 = 96, - GPD1, - GPD2, - GPD3, - GPD4, - GPD5, - GPD6, - GPD7, - GPD8, - GPD9, - GPD10, - GPD11, - GPD12, - GPD13, - GPD14, - GPD15, - - GPE0 = 128, - GPE1, - GPE2, - GPE3, - GPE4, - GPE5, - GPE6, - GPE7, - GPE8, - GPE9, - GPE10, - GPE11, - GPE12, - GPE13, - GPE14, - GPE15, - - GPF0 = 160, - GPF1, - GPF2, - GPF3, - GPF4, - GPF5, - GPF6, - GPF7, - - GPG0 = 192, - GPG1, - GPG2, - GPG3, - GPG4, - GPG5, - GPG6, - GPG7, - GPG8, - GPG9, - GPG10, - GPG11, - GPG12, - GPG13, - GPG14, - GPG15, - - GPH0 = 224, - GPH1, - GPH2, - GPH3, - GPH4, - GPH5, - GPH6, - GPH7, - GPH8, - GPH9, - GPH10, - - GPJ0 = 256, - GPJ1, - GPJ2, - GPJ3, - GPJ4, - GPJ5, - GPJ6, - GPJ7, - GPJ8, - GPJ9, - GPJ10, - GPJ11, - GPJ12, -}; - -#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h deleted file mode 100644 index 9811644..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/iomux.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2012 - * - * Gabriel Huau - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S3C24X0_IOMUX_H_ -#define _S3C24X0_IOMUX_H_ - -enum s3c2440_iomux_func { - /* PORT A */ - IOMUXA_ADDR0 = 1, - IOMUXA_ADDR16 = (1 << 1), - IOMUXA_ADDR17 = (1 << 2), - IOMUXA_ADDR18 = (1 << 3), - IOMUXA_ADDR19 = (1 << 4), - IOMUXA_ADDR20 = (1 << 5), - IOMUXA_ADDR21 = (1 << 6), - IOMUXA_ADDR22 = (1 << 7), - IOMUXA_ADDR23 = (1 << 8), - IOMUXA_ADDR24 = (1 << 9), - IOMUXA_ADDR25 = (1 << 10), - IOMUXA_ADDR26 = (1 << 11), - IOMUXA_nGCS1 = (1 << 12), - IOMUXA_nGCS2 = (1 << 13), - IOMUXA_nGCS3 = (1 << 14), - IOMUXA_nGCS4 = (1 << 15), - IOMUXA_nGCS5 = (1 << 16), - IOMUXA_CLE = (1 << 17), - IOMUXA_ALE = (1 << 18), - IOMUXA_nFWE = (1 << 19), - IOMUXA_nFRE = (1 << 20), - IOMUXA_nRSTOUT = (1 << 21), - IOMUXA_nFCE = (1 << 22), - - /* PORT B */ - IOMUXB_nXDREQ0 = (2 << 20), - IOMUXB_nXDACK0 = (2 << 18), - IOMUXB_nXDREQ1 = (2 << 16), - IOMUXB_nXDACK1 = (2 << 14), - IOMUXB_nXBREQ = (2 << 12), - IOMUXB_nXBACK = (2 << 10), - IOMUXB_TCLK0 = (2 << 8), - IOMUXB_TOUT3 = (2 << 6), - IOMUXB_TOUT2 = (2 << 4), - IOMUXB_TOUT1 = (2 << 2), - IOMUXB_TOUT0 = 2, - - /* PORT C */ - IOMUXC_VS7 = (2 << 30), - IOMUXC_VS6 = (2 << 28), - IOMUXC_VS5 = (2 << 26), - IOMUXC_VS4 = (2 << 24), - IOMUXC_VS3 = (2 << 22), - IOMUXC_VS2 = (2 << 20), - IOMUXC_VS1 = (2 << 18), - IOMUXC_VS0 = (2 << 16), - IOMUXC_LCD_LPCREVB = (2 << 14), - IOMUXC_LCD_LPCREV = (2 << 12), - IOMUXC_LCD_LPCOE = (2 << 10), - IOMUXC_VM = (2 << 8), - IOMUXC_VFRAME = (2 << 6), - IOMUXC_VLINE = (2 << 4), - IOMUXC_VCLK = (2 << 2), - IOMUXC_LEND = 2, - IOMUXC_I2SSDI = (3 << 8), - - /* PORT D */ - IOMUXD_VS23 = (2 << 30), - IOMUXD_VS22 = (2 << 28), - IOMUXD_VS21 = (2 << 26), - IOMUXD_VS20 = (2 << 24), - IOMUXD_VS19 = (2 << 22), - IOMUXD_VS18 = (2 << 20), - IOMUXD_VS17 = (2 << 18), - IOMUXD_VS16 = (2 << 16), - IOMUXD_VS15 = (2 << 14), - IOMUXD_VS14 = (2 << 12), - IOMUXD_VS13 = (2 << 10), - IOMUXD_VS12 = (2 << 8), - IOMUXD_VS11 = (2 << 6), - IOMUXD_VS10 = (2 << 4), - IOMUXD_VS9 = (2 << 2), - IOMUXD_VS8 = 2, - IOMUXD_nSS0 = (3 << 30), - IOMUXD_nSS1 = (3 << 28), - IOMUXD_SPICLK1 = (3 << 20), - IOMUXD_SPIMOSI1 = (3 << 18), - IOMUXD_SPIMISO1 = (3 << 16), - - /* PORT E */ - IOMUXE_IICSDA = (2 << 30), - IOMUXE_IICSCL = (2 << 28), - IOMUXE_SPICLK0 = (2 << 26), - IOMUXE_SPIMOSI0 = (2 << 24), - IOMUXE_SPIMISO0 = (2 << 22), - IOMUXE_SDDAT3 = (2 << 20), - IOMUXE_SDDAT2 = (2 << 18), - IOMUXE_SDDAT1 = (2 << 16), - IOMUXE_SDDAT0 = (2 << 14), - IOMUXE_SDCMD = (2 << 12), - IOMUXE_SDCLK = (2 << 10), - IOMUXE_I2SDO = (2 << 8), - IOMUXE_I2SDI = (2 << 6), - IOMUXE_CDCLK = (2 << 4), - IOMUXE_I2SSCLK = (2 << 2), - IOMUXE_I2SLRCK = 2, - IOMUXE_AC_SDATA_OUT = (3 << 8), - IOMUXE_AC_SDATA_IN = (3 << 6), - IOMUXE_AC_nRESET = (3 << 4), - IOMUXE_AC_BIT_CLK = (3 << 2), - IOMUXE_AC_SYNC = 3, - - /* PORT F */ - IOMUXF_EINT7 = (2 << 14), - IOMUXF_EINT6 = (2 << 12), - IOMUXF_EINT5 = (2 << 10), - IOMUXF_EINT4 = (2 << 8), - IOMUXF_EINT3 = (2 << 6), - IOMUXF_EINT2 = (2 << 4), - IOMUXF_EINT1 = (2 << 2), - IOMUXF_EINT0 = 2, - - /* PORT G */ - IOMUXG_EINT23 = (2 << 30), - IOMUXG_EINT22 = (2 << 28), - IOMUXG_EINT21 = (2 << 26), - IOMUXG_EINT20 = (2 << 24), - IOMUXG_EINT19 = (2 << 22), - IOMUXG_EINT18 = (2 << 20), - IOMUXG_EINT17 = (2 << 18), - IOMUXG_EINT16 = (2 << 16), - IOMUXG_EINT15 = (2 << 14), - IOMUXG_EINT14 = (2 << 12), - IOMUXG_EINT13 = (2 << 10), - IOMUXG_EINT12 = (2 << 8), - IOMUXG_EINT11 = (2 << 6), - IOMUXG_EINT10 = (2 << 4), - IOMUXG_EINT9 = (2 << 2), - IOMUXG_EINT8 = 2, - IOMUXG_TCLK1 = (3 << 22), - IOMUXG_nCTS1 = (3 << 20), - IOMUXG_nRTS1 = (3 << 18), - IOMUXG_SPICLK1 = (3 << 14), - IOMUXG_SPIMOSI1 = (3 << 12), - IOMUXG_SPIMISO1 = (3 << 10), - IOMUXG_LCD_PWRDN = (3 << 8), - IOMUXG_nSS1 = (3 << 6), - IOMUXG_nSS0 = (3 << 4), - - /* PORT H */ - IOMUXH_CLKOUT1 = (2 << 20), - IOMUXH_CLKOUT0 = (2 << 18), - IOMUXH_UEXTCLK = (2 << 16), - IOMUXH_RXD2 = (2 << 14), - IOMUXH_TXD2 = (2 << 12), - IOMUXH_RXD1 = (2 << 10), - IOMUXH_TXD1 = (2 << 8), - IOMUXH_RXD0 = (2 << 6), - IOMUXH_TXD0 = (2 << 4), - IOMUXH_nRTS0 = (2 << 2), - IOMUXH_nCTS0 = 2, - IOMUXH_nCTS1 = (3 << 14), - IOMUXH_nRTS1 = (3 << 12), - - /* PORT J */ - IOMUXJ_CAMRESET = (2 << 24), - IOMUXJ_CAMCLKOUT = (2 << 22), - IOMUXJ_CAMHREF = (2 << 20), - IOMUXJ_CAMVSYNC = (2 << 18), - IOMUXJ_CAMPCLK = (2 << 16), - IOMUXJ_CAMDATA7 = (2 << 14), - IOMUXJ_CAMDATA6 = (2 << 12), - IOMUXJ_CAMDATA5 = (2 << 10), - IOMUXJ_CAMDATA4 = (2 << 8), - IOMUXJ_CAMDATA3 = (2 << 6), - IOMUXJ_CAMDATA2 = (2 << 4), - IOMUXJ_CAMDATA1 = (2 << 2), - IOMUXJ_CAMDATA0 = 2 -}; - -#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/memory.h b/arch/arm/include/asm/arch-s3c24x0/memory.h deleted file mode 100644 index d6a787b..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/memory.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de - * based on - * linux/include/asm-arm/arch-sa1100/memory.h - * - * Copyright (c) 1999 Nicolas Pitre - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - - -/* - * Task size: 3GB - */ -#define TASK_SIZE (0xc0000000UL) -#define TASK_SIZE_26 (0x04000000UL) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -/* - * Page offset: 3GB - */ -#define PAGE_OFFSET (0xc0000000UL) - -/* - * Physical DRAM offset is 0x0c000000 on the S3C2400 - */ -#define PHYS_OFFSET (0x0c000000UL) - -/* Modified for S3C2400, by chc, 20010509 */ -#define RAM_IN_BANK_0 32*1024*1024 -#define RAM_IN_BANK_1 0 -#define RAM_IN_BANK_2 0 -#define RAM_IN_BANK_3 0 - -#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3) - - -/* translation macros */ -#define __virt_to_phys__is_a_macro -#define __phys_to_virt__is_a_macro - -#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 ) -#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET ) - -#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \ - (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -/* Two identical banks */ -#define __virt_to_phys(x) \ - ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \ - ((x) - PAGE_OFFSET + _DRAMBnk0) : \ - ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) ) -#define __phys_to_virt(x) \ - ( ((x)&0x07ffffff) + \ - (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) ) -#else - -/* It's more efficient for all other cases to use the function call */ -#undef __virt_to_phys__is_a_macro -#undef __phys_to_virt__is_a_macro -extern unsigned long __virt_to_phys(unsigned long vpage); -extern unsigned long __phys_to_virt(unsigned long ppage); - -#endif - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * On the SA1100, bus addresses are equivalent to physical addresses. - */ -#define __virt_to_bus__is_a_macro -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt__is_a_macro -#define __bus_to_virt(x) __phys_to_virt(x) - - -#ifdef CONFIG_DISCONTIGMEM -#error "CONFIG_DISCONTIGMEM will not work on S3C2400" -/* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much more convenient to use Linux's NUMA support to implement - * our memory map representation. Assuming all memory nodes have equal access - * characteristics, we then have generic discontiguous memory support. - * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. - * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff - */ - -#define NR_NODES 4 - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - 0xc0000000) >> 27) - -/* - * Given a physical address, convert it to a node id. - */ -#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(kvaddr) \ - (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) - -/* - * Given a kaddr, virt_to_page returns a pointer to the corresponding - * mem_map entry. - */ -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -/* - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they refer to. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ( (node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ -}) - -#else - -#define PHYS_TO_NID(addr) (0) - -#endif -#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2400.h b/arch/arm/include/asm/arch-s3c24x0/s3c2400.h deleted file mode 100644 index 2389118..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2400.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2400.h - * Version : 31.3.2003 - * - * Based on S3C2400X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2400_H__ -#define __S3C2400_H__ - -#define S3C24X0_UART_CHANNELS 2 -#define S3C24X0_SPI_CHANNELS 1 -#define PALETTE (0x14A00400) /* SJS */ - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, -}; - -/*S3C2400 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x14000000 -#define S3C24X0_USB_HOST_BASE 0x14200000 -#define S3C24X0_INTERRUPT_BASE 0x14400000 -#define S3C24X0_DMA_BASE 0x14600000 -#define S3C24X0_CLOCK_POWER_BASE 0x14800000 -#define S3C24X0_LCD_BASE 0x14A00000 -#define S3C24X0_UART_BASE 0x15000000 -#define S3C24X0_TIMER_BASE 0x15100000 -#define S3C24X0_USB_DEVICE_BASE 0x15200140 -#define S3C24X0_WATCHDOG_BASE 0x15300000 -#define S3C24X0_I2C_BASE 0x15400000 -#define S3C24X0_I2S_BASE 0x15508000 -#define S3C24X0_GPIO_BASE 0x15600000 -#define S3C24X0_RTC_BASE 0x15700000 -#define S3C24X0_ADC_BASE 0x15800000 -#define S3C24X0_SPI_BASE 0x15900000 -#define S3C2400_MMC_BASE 0x15A00000 - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2400_adc *s3c2400_get_base_adc(void) -{ - return (struct s3c2400_adc *)S3C24X0_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) -{ - return (struct s3c2400_mmc *)S3C2400_MMC_BASE; -} - -#endif /*__S3C2400_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h deleted file mode 100644 index 8773ce3..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2410.h - * Version : 31.3.2003 - * - * Based on S3C2410X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2410_H__ -#define __S3C2410_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2410 only supports 512 Byte HW ECC */ -#define S3C2410_ECCSIZE 512 -#define S3C2410_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2410 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2410_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) -{ - return (struct s3c24x0_nand *)S3C2410_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2410_adc *s3c2410_get_base_adc(void) -{ - return (struct s3c2410_adc *)S3C2410_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) -{ - return (struct s3c24x0_sdi *)S3C2410_SDI_BASE; -} - -#endif /*__S3C2410_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h deleted file mode 100644 index 7a525f2..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2003 - * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2440.h - * Version : 31.3.2003 - * - * Based on S3C2440 User's manual Rev x.x - ************************************************/ - -#ifndef __S3C2440_H__ -#define __S3C2440_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2440 only supports 512 Byte HW ECC */ -#define S3C2440_ECCSIZE 512 -#define S3C2440_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2440 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2440_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2440_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2440_SDI_BASE 0x5A000000 - -/* include common stuff */ -#include - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) -{ - return (struct s3c24x0_nand *)S3C2440_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2440_adc *s3c2440_get_base_adc(void) -{ - return (struct s3c2440_adc *)S3C2440_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) -{ - return (struct s3c24x0_sdi *)S3C2440_SDI_BASE; -} - -#endif /*__S3C2440_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h deleted file mode 100644 index 2dae9fc..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ /dev/null @@ -1,708 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c24x0.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C24X0 SoC - ************************************************/ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -/* Memory controller (see manual chapter 5) */ -struct s3c24x0_memctl { - u32 bwscon; - u32 bankcon[8]; - u32 refresh; - u32 banksize; - u32 mrsrb6; - u32 mrsrb7; -}; - - -/* USB HOST (see manual chapter 12) */ -struct s3c24x0_usb_host { - u32 HcRevision; - u32 HcControl; - u32 HcCommonStatus; - u32 HcInterruptStatus; - u32 HcInterruptEnable; - u32 HcInterruptDisable; - u32 HcHCCA; - u32 HcPeriodCuttendED; - u32 HcControlHeadED; - u32 HcControlCurrentED; - u32 HcBulkHeadED; - u32 HcBuldCurrentED; - u32 HcDoneHead; - u32 HcRmInterval; - u32 HcFmRemaining; - u32 HcFmNumber; - u32 HcPeriodicStart; - u32 HcLSThreshold; - u32 HcRhDescriptorA; - u32 HcRhDescriptorB; - u32 HcRhStatus; - u32 HcRhPortStatus1; - u32 HcRhPortStatus2; -}; - - -/* INTERRUPT (see manual chapter 14) */ -struct s3c24x0_interrupt { - u32 srcpnd; - u32 intmod; - u32 intmsk; - u32 priority; - u32 intpnd; - u32 intoffset; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 subsrcpnd; - u32 intsubmsk; -#endif -}; - - -/* DMAS (see manual chapter 8) */ -struct s3c24x0_dma { - u32 disrc; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 disrcc; -#endif - u32 didst; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 didstc; -#endif - u32 dcon; - u32 dstat; - u32 dcsrc; - u32 dcdst; - u32 dmasktrig; -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \ - || defined(CONFIG_S3C2440) - u32 res[1]; -#endif -}; - -struct s3c24x0_dmas { - struct s3c24x0_dma dma[4]; -}; - - -/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ -/* (see S3C2410 manual chapter 7) */ -struct s3c24x0_clock_power { - u32 locktime; - u32 mpllcon; - u32 upllcon; - u32 clkcon; - u32 clkslow; - u32 clkdivn; -#if defined(CONFIG_S3C2440) - u32 camdivn; -#endif -}; - - -/* LCD CONTROLLER (see manual chapter 15) */ -struct s3c24x0_lcd { - u32 lcdcon1; - u32 lcdcon2; - u32 lcdcon3; - u32 lcdcon4; - u32 lcdcon5; - u32 lcdsaddr1; - u32 lcdsaddr2; - u32 lcdsaddr3; - u32 redlut; - u32 greenlut; - u32 bluelut; - u32 res[8]; - u32 dithmode; - u32 tpal; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 lcdintpnd; - u32 lcdsrcpnd; - u32 lcdintmsk; - u32 lpcsel; -#endif -}; - - -/* NAND FLASH (see manual chapter 6) */ -struct s3c24x0_nand { - u32 nfconf; -#ifndef CONFIG_S3C2410 - u32 nfcont; -#endif - u32 nfcmd; - u32 nfaddr; - u32 nfdata; -#ifndef CONFIG_S3C2410 - u32 nfeccd0; - u32 nfeccd1; - u32 nfeccd; -#endif - u32 nfstat; -#ifdef CONFIG_S3C2410 - u32 nfecc; -#else - u32 nfstat0; - u32 nfstat1; - u32 nfmecc0; - u32 nfmecc1; - u32 nfsecc; - u32 nfsblk; - u32 nfeblk; -#endif -}; - -/* UART (see manual chapter 11) */ -struct s3c24x0_uart { - u32 ulcon; - u32 ucon; - u32 ufcon; - u32 umcon; - u32 utrstat; - u32 uerstat; - u32 ufstat; - u32 umstat; -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 utxh; - u8 res2[3]; - u8 urxh; -#else /* Little Endian */ - u8 utxh; - u8 res1[3]; - u8 urxh; - u8 res2[3]; -#endif - u32 ubrdiv; -}; - - -/* PWM TIMER (see manual chapter 10) */ -struct s3c24x0_timer { - u32 tcntb; - u32 tcmpb; - u32 tcnto; -}; - -struct s3c24x0_timers { - u32 tcfg0; - u32 tcfg1; - u32 tcon; - struct s3c24x0_timer ch[4]; - u32 tcntb4; - u32 tcnto4; -}; - - -/* USB DEVICE (see manual chapter 13) */ -struct s3c24x0_usb_dev_fifos { -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 ep_fifo_reg; -#else /* little endian */ - u8 ep_fifo_reg; - u8 res[3]; -#endif -}; - -struct s3c24x0_usb_dev_dmas { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 ep_dma_con; - u8 res2[3]; - u8 ep_dma_unit; - u8 res3[3]; - u8 ep_dma_fifo; - u8 res4[3]; - u8 ep_dma_ttc_l; - u8 res5[3]; - u8 ep_dma_ttc_m; - u8 res6[3]; - u8 ep_dma_ttc_h; -#else /* little endian */ - u8 ep_dma_con; - u8 res1[3]; - u8 ep_dma_unit; - u8 res2[3]; - u8 ep_dma_fifo; - u8 res3[3]; - u8 ep_dma_ttc_l; - u8 res4[3]; - u8 ep_dma_ttc_m; - u8 res5[3]; - u8 ep_dma_ttc_h; - u8 res6[3]; -#endif -}; - -struct s3c24x0_usb_device { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 func_addr_reg; - u8 res2[3]; - u8 pwr_reg; - u8 res3[3]; - u8 ep_int_reg; - u8 res4[15]; - u8 usb_int_reg; - u8 res5[3]; - u8 ep_int_en_reg; - u8 res6[15]; - u8 usb_int_en_reg; - u8 res7[3]; - u8 frame_num1_reg; - u8 res8[3]; - u8 frame_num2_reg; - u8 res9[3]; - u8 index_reg; - u8 res10[7]; - u8 maxp_reg; - u8 res11[3]; - u8 ep0_csr_in_csr1_reg; - u8 res12[3]; - u8 in_csr2_reg; - u8 res13[7]; - u8 out_csr1_reg; - u8 res14[3]; - u8 out_csr2_reg; - u8 res15[3]; - u8 out_fifo_cnt1_reg; - u8 res16[3]; - u8 out_fifo_cnt2_reg; -#else /* little endian */ - u8 func_addr_reg; - u8 res1[3]; - u8 pwr_reg; - u8 res2[3]; - u8 ep_int_reg; - u8 res3[15]; - u8 usb_int_reg; - u8 res4[3]; - u8 ep_int_en_reg; - u8 res5[15]; - u8 usb_int_en_reg; - u8 res6[3]; - u8 frame_num1_reg; - u8 res7[3]; - u8 frame_num2_reg; - u8 res8[3]; - u8 index_reg; - u8 res9[7]; - u8 maxp_reg; - u8 res10[7]; - u8 ep0_csr_in_csr1_reg; - u8 res11[3]; - u8 in_csr2_reg; - u8 res12[3]; - u8 out_csr1_reg; - u8 res13[7]; - u8 out_csr2_reg; - u8 res14[3]; - u8 out_fifo_cnt1_reg; - u8 res15[3]; - u8 out_fifo_cnt2_reg; - u8 res16[3]; -#endif /* __BIG_ENDIAN */ - struct s3c24x0_usb_dev_fifos fifo[5]; - struct s3c24x0_usb_dev_dmas dma[5]; -}; - - -/* WATCH DOG TIMER (see manual chapter 18) */ -struct s3c24x0_watchdog { - u32 wtcon; - u32 wtdat; - u32 wtcnt; -}; - -/* IIS (see manual chapter 21) */ -struct s3c24x0_i2s { -#ifdef __BIG_ENDIAN - u16 res1; - u16 iiscon; - u16 res2; - u16 iismod; - u16 res3; - u16 iispsr; - u16 res4; - u16 iisfcon; - u16 res5; - u16 iisfifo; -#else /* little endian */ - u16 iiscon; - u16 res1; - u16 iismod; - u16 res2; - u16 iispsr; - u16 res3; - u16 iisfcon; - u16 res4; - u16 iisfifo; - u16 res5; -#endif -}; - - -/* I/O PORT (see manual chapter 9) */ -struct s3c24x0_gpio { -#ifdef CONFIG_S3C2400 - u32 pacon; - u32 padat; - - u32 pbcon; - u32 pbdat; - u32 pbup; - - u32 pccon; - u32 pcdat; - u32 pcup; - - u32 pdcon; - u32 pddat; - u32 pdup; - - u32 pecon; - u32 pedat; - u32 peup; - - u32 pfcon; - u32 pfdat; - u32 pfup; - - u32 pgcon; - u32 pgdat; - u32 pgup; - - u32 opencr; - - u32 misccr; - u32 extint; -#endif -#ifdef CONFIG_S3C2410 - u32 gpacon; - u32 gpadat; - u32 res1[2]; - u32 gpbcon; - u32 gpbdat; - u32 gpbup; - u32 res2; - u32 gpccon; - u32 gpcdat; - u32 gpcup; - u32 res3; - u32 gpdcon; - u32 gpddat; - u32 gpdup; - u32 res4; - u32 gpecon; - u32 gpedat; - u32 gpeup; - u32 res5; - u32 gpfcon; - u32 gpfdat; - u32 gpfup; - u32 res6; - u32 gpgcon; - u32 gpgdat; - u32 gpgup; - u32 res7; - u32 gphcon; - u32 gphdat; - u32 gphup; - u32 res8; - - u32 misccr; - u32 dclkcon; - u32 extint0; - u32 extint1; - u32 extint2; - u32 eintflt0; - u32 eintflt1; - u32 eintflt2; - u32 eintflt3; - u32 eintmask; - u32 eintpend; - u32 gstatus0; - u32 gstatus1; - u32 gstatus2; - u32 gstatus3; - u32 gstatus4; -#endif -#if defined(CONFIG_S3C2440) - u32 gpacon; - u32 gpadat; - u32 res1[2]; - u32 gpbcon; - u32 gpbdat; - u32 gpbup; - u32 res2; - u32 gpccon; - u32 gpcdat; - u32 gpcup; - u32 res3; - u32 gpdcon; - u32 gpddat; - u32 gpdup; - u32 res4; - u32 gpecon; - u32 gpedat; - u32 gpeup; - u32 res5; - u32 gpfcon; - u32 gpfdat; - u32 gpfup; - u32 res6; - u32 gpgcon; - u32 gpgdat; - u32 gpgup; - u32 res7; - u32 gphcon; - u32 gphdat; - u32 gphup; - u32 res8; - - u32 misccr; - u32 dclkcon; - u32 extint0; - u32 extint1; - u32 extint2; - u32 eintflt0; - u32 eintflt1; - u32 eintflt2; - u32 eintflt3; - u32 eintmask; - u32 eintpend; - u32 gstatus0; - u32 gstatus1; - u32 gstatus2; - u32 gstatus3; - u32 gstatus4; - - u32 res9; - u32 dsc0; - u32 dsc1; - u32 mslcon; - u32 gpjcon; - u32 gpjdat; - u32 gpjup; - u32 res10; -#endif -}; - - -/* RTC (see manual chapter 17) */ -struct s3c24x0_rtc { -#ifdef __BIG_ENDIAN - u8 res1[67]; - u8 rtccon; - u8 res2[3]; - u8 ticnt; - u8 res3[11]; - u8 rtcalm; - u8 res4[3]; - u8 almsec; - u8 res5[3]; - u8 almmin; - u8 res6[3]; - u8 almhour; - u8 res7[3]; - u8 almdate; - u8 res8[3]; - u8 almmon; - u8 res9[3]; - u8 almyear; - u8 res10[3]; - u8 rtcrst; - u8 res11[3]; - u8 bcdsec; - u8 res12[3]; - u8 bcdmin; - u8 res13[3]; - u8 bcdhour; - u8 res14[3]; - u8 bcddate; - u8 res15[3]; - u8 bcdday; - u8 res16[3]; - u8 bcdmon; - u8 res17[3]; - u8 bcdyear; -#else /* little endian */ - u8 res0[64]; - u8 rtccon; - u8 res1[3]; - u8 ticnt; - u8 res2[11]; - u8 rtcalm; - u8 res3[3]; - u8 almsec; - u8 res4[3]; - u8 almmin; - u8 res5[3]; - u8 almhour; - u8 res6[3]; - u8 almdate; - u8 res7[3]; - u8 almmon; - u8 res8[3]; - u8 almyear; - u8 res9[3]; - u8 rtcrst; - u8 res10[3]; - u8 bcdsec; - u8 res11[3]; - u8 bcdmin; - u8 res12[3]; - u8 bcdhour; - u8 res13[3]; - u8 bcddate; - u8 res14[3]; - u8 bcdday; - u8 res15[3]; - u8 bcdmon; - u8 res16[3]; - u8 bcdyear; - u8 res17[3]; -#endif -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2400_adc { - u32 adccon; - u32 adcdat; -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2410_adc { - u32 adccon; - u32 adctsc; - u32 adcdly; - u32 adcdat0; - u32 adcdat1; -}; - - -/* SPI (see manual chapter 22) */ -struct s3c24x0_spi_channel { - u8 spcon; - u8 res1[3]; - u8 spsta; - u8 res2[3]; - u8 sppin; - u8 res3[3]; - u8 sppre; - u8 res4[3]; - u8 sptdat; - u8 res5[3]; - u8 sprdat; - u8 res6[3]; - u8 res7[16]; -}; - -struct s3c24x0_spi { - struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; -}; - - -/* MMC INTERFACE (see S3C2400 manual chapter 19) */ -struct s3c2400_mmc { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 mmcon; - u8 res2[3]; - u8 mmcrr; - u8 res3[3]; - u8 mmfcon; - u8 res4[3]; - u8 mmsta; - u16 res5; - u16 mmfsta; - u8 res6[3]; - u8 mmpre; - u16 res7; - u16 mmlen; - u8 res8[3]; - u8 mmcr7; - u32 mmrsp[4]; - u8 res9[3]; - u8 mmcmd0; - u32 mmcmd1; - u16 res10; - u16 mmcr16; - u8 res11[3]; - u8 mmdat; -#else - u8 mmcon; - u8 res1[3]; - u8 mmcrr; - u8 res2[3]; - u8 mmfcon; - u8 res3[3]; - u8 mmsta; - u8 res4[3]; - u16 mmfsta; - u16 res5; - u8 mmpre; - u8 res6[3]; - u16 mmlen; - u16 res7; - u8 mmcr7; - u8 res8[3]; - u32 mmrsp[4]; - u8 mmcmd0; - u8 res9[3]; - u32 mmcmd1; - u16 mmcr16; - u16 res10; - u8 mmdat; - u8 res11[3]; -#endif -}; - - -/* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c24x0_sdi { - u32 sdicon; - u32 sdipre; - u32 sdicarg; - u32 sdiccon; - u32 sdicsta; - u32 sdirsp0; - u32 sdirsp1; - u32 sdirsp2; - u32 sdirsp3; - u32 sdidtimer; - u32 sdibsize; - u32 sdidcon; - u32 sdidcnt; - u32 sdidsta; - u32 sdifsta; -#ifdef CONFIG_S3C2410 - u32 sdidat; - u32 sdiimsk; -#else - u32 sdiimsk; - u32 sdidat; -#endif -}; - -#ifdef CONFIG_CMD_MMC -#include -int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *), - int (*getwp)(struct mmc *)); -#endif - -#endif /*__S3C24X0_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h deleted file mode 100644 index 393cc9d..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2009 - * Kevin Morfitt, Fearnside Systems Ltd, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef CONFIG_S3C2400 - #include -#elif defined CONFIG_S3C2410 - #include -#elif defined CONFIG_S3C2440 - #include -#else - #error Please define the s3c24x0 cpu type -#endif diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 6aa5e91..2419062 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -34,7 +34,9 @@ #define SUNXI_MS_BASE 0x01c07000 #define SUNXI_TVD_BASE 0x01c08000 #define SUNXI_CSI0_BASE 0x01c09000 +#ifndef CONFIG_MACH_SUNXI_H3_H5 #define SUNXI_TVE0_BASE 0x01c0a000 +#endif #define SUNXI_EMAC_BASE 0x01c0b000 #define SUNXI_LCD0_BASE 0x01c0C000 #define SUNXI_LCD1_BASE 0x01c0d000 @@ -161,10 +163,18 @@ defined(CONFIG_MACH_SUN50I) /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 +#ifndef CONFIG_MACH_SUN8I_H3 #define SUNXI_DE_FE0_BASE 0x01e00000 +#else +#define SUNXI_TVE0_BASE 0x01e00000 +#endif #define SUNXI_DE_FE1_BASE 0x01e20000 #define SUNXI_DE_BE0_BASE 0x01e60000 +#ifndef CONFIG_MACH_SUN50I_H5 #define SUNXI_DE_BE1_BASE 0x01e40000 +#else +#define SUNXI_TVE0_BASE 0x01e40000 +#endif #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h index b5875f9..359cacd 100644 --- a/arch/arm/include/asm/arch-sunxi/display2.h +++ b/arch/arm/include/asm/arch-sunxi/display2.h @@ -90,6 +90,23 @@ struct de_ui { u32 ovl_size; }; +struct de_csc { + u32 csc_ctl; + u8 res[0xc]; + u32 coef11; + u32 coef12; + u32 coef13; + u32 coef14; + u32 coef21; + u32 coef22; + u32 coef23; + u32 coef24; + u32 coef31; + u32 coef32; + u32 coef33; + u32 coef34; +}; + /* * DE register constants. */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index f452f88..80abac9 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,10 +24,8 @@ #include #elif defined(CONFIG_MACH_SUN8I_A83T) #include -#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \ - defined(CONFIG_MACH_SUN8I_R40) || \ - defined(CONFIG_MACH_SUN50I) -#include +#elif defined(CONFIG_SUNXI_DRAM_DW) +#include #elif defined(CONFIG_MACH_SUN9I) #include #else diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h similarity index 86% rename from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h rename to arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index 2770986..03fd46b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -53,9 +53,9 @@ struct sunxi_mctl_com_reg { #define MCTL_CR_SEQUENTIAL (0x1 << 15) #define MCTL_CR_INTERLEAVED (0x0 << 15) -#define MCTL_CR_32BIT (0x1 << 12) -#define MCTL_CR_16BIT (0x0 << 12) -#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) +#define MCTL_CR_FULL_WIDTH (0x1 << 12) +#define MCTL_CR_HALF_WIDTH (0x0 << 12) +#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) #define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) @@ -205,4 +205,34 @@ struct sunxi_mctl_ctl_reg { #define DXBDLR_WRITE_DELAY(x) ((x) << 8) #define DXBDLR_READ_DELAY(x) ((x) << 0) +/* + * The delay parameters below allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define BITS_PER_BYTE 8 +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) +struct dram_para { + u16 page_size; + u8 bus_full_width; + u8 dual_rank; + u8 row_bits; + u8 bank_bits; + const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 ac_delays[31]; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 388afcb..f62b2a4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -288,6 +288,9 @@ void clock_init(void); /* Initialize the PLLs */ void clock_early_init(void); +/* @return true if hardware indicates that clock_early_init() was called */ +bool clock_early_init_done(void); + /* Returns a pointer to the clock source register for a peripheral */ u32 *get_periph_source_reg(enum periph_id periph_id); diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 7b11895..d91d98a 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,6 +8,8 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#define PAYLOAD_ARG_CNT 5 + int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); @@ -16,4 +18,10 @@ void psu_init(void); void handoff_setup(void); +void zynqmp_pmufw_version(void); +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); +int zynqmp_mmio_read(const u32 address, u32 *value); +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, + u32 *ret_payload); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index 436c35a..4c9bb86 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -41,6 +41,7 @@ extern void udc_disconnect(void); #define BOOTM_ENABLE_INITRD_TAG 0 #endif +struct tag_serialnr; #ifdef CONFIG_SERIAL_TAG #define BOOTM_ENABLE_SERIAL_TAG 1 void get_board_serial(struct tag_serialnr *serialnr); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index c1a70b1..d2ca277 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -484,6 +484,7 @@ struct omap_sys_ctrl_regs { u32 ctrl_core_sma_sw_1; }; +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) struct dpll_params { u32 m; u32 n; @@ -516,6 +517,7 @@ struct dpll_regs { u32 cm_div_h23_dpll; u32 cm_div_h24_dpll; }; +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ struct dplls { const struct dpll_params *mpu; @@ -539,6 +541,7 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) enum { OPP_LOW, OPP_NOM, @@ -584,6 +587,7 @@ struct vcores_data { struct volts eve; struct volts iva; }; +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; @@ -595,6 +599,8 @@ extern struct dplls dra7xx_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const am33xx_ctrl; +extern struct omap_sys_ctrl_regs const omap3_ctrl; extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl; @@ -611,6 +617,7 @@ const struct dpll_params *get_iva_dpll_params(struct dplls const *); const struct dpll_params *get_usb_dpll_params(struct dplls const *); const struct dpll_params *get_abe_dpll_params(struct dplls const *); +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void do_enable_clocks(u32 const *clk_domains, u32 const *clk_modules_hw_auto, u32 const *clk_modules_explicit_en, @@ -619,6 +626,7 @@ void do_enable_clocks(u32 const *clk_domains, void do_disable_clocks(u32 const *clk_domains, u32 const *clk_modules_disable, u8 wait_for_disable); +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ void setup_post_dividers(u32 const base, const struct dpll_params *params); @@ -630,7 +638,9 @@ void enable_basic_uboot_clocks(void); void enable_usb_clocks(int index); void disable_usb_clocks(int index); +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void scale_vcores(struct vcores_data const *); +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ int get_voltrail_opp(int rail_offset); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); @@ -638,11 +648,19 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, u32 txdone, u32 txdone_mask, u32 opp); s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); +struct tag_serialnr; + void omap_die_id_serial(void); void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); void omap_die_id_usbethaddr(void); void omap_die_id_display(void); +#ifdef CONFIG_FASTBOOT_FLASH +void omap_set_fastboot_vars(void); +#else +static inline void omap_set_fastboot_vars(void) { } +#endif + void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); @@ -748,7 +766,6 @@ static inline u8 is_dra72x(void) * silicon device type * Moving to common from cpu.h, since it is shared by various omap devices */ -#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) #define TST_DEVICE 0x0 #define EMU_DEVICE 0x1 #define HS_DEVICE 0x2 diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 5d7f7e6..0e67470 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -29,6 +29,7 @@ enum { BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, + BOOT_DEVICE_XIP, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index b931c22..ef4fca6 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -13,6 +13,8 @@ #ifndef _U_BOOT_ARM_H_ #define _U_BOOT_ARM_H_ 1 +#ifndef __ASSEMBLY__ + /* for the following variables, see start.S */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ @@ -45,6 +47,8 @@ ulong get_timer_masked (void); void udelay_masked (unsigned long usec); /* calls to c from vectors.S */ +struct pt_regs; + void bad_mode(void); void do_undefined_instruction(struct pt_regs *pt_regs); void do_software_interrupt(struct pt_regs *pt_regs); @@ -59,4 +63,6 @@ void do_fiq(struct pt_regs *pt_regs); void do_irq(struct pt_regs *pt_regswq); #endif +#endif /* __ASSEMBLY__ */ + #endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index ca3abd7..ef9196f 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -22,6 +22,7 @@ /* Use the generic board which requires a unified bd_info */ #include +#include /* For image.h:image_check_target_arch() */ #ifndef CONFIG_ARM64 diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index f162c14..6e1c436 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -72,8 +72,6 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o endif -asflags-y += -DCONFIG_ARM_ASM_UNIFIED - # some files can only build in ARM or THUMB2, not THUMB1 ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index eb24222..b3e5d24 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -31,6 +31,7 @@ #ifdef CONFIG_ARMV7_NONSEC #include #endif +#include DECLARE_GLOBAL_DATA_PTR; @@ -359,6 +360,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) #ifdef CONFIG_CPU_V7M ulong addr = (ulong)kernel_entry | 1; kernel_entry = (void *)addr; + dcache_disable(); #endif s = getenv("machid"); if (s) { diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e9bbcf5..f0c1b03 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -22,16 +22,6 @@ __weak void arm_init_domains(void) { } -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - void set_section_dcache(int section, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE @@ -129,7 +119,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } -#ifdef CONFIG_ARMV7_LPAE +#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 /* Set up 4 PTE entries pointing to our 4 1GB page tables */ for (i = 0; i < 4; i++) { u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); @@ -147,7 +137,7 @@ static inline void mmu_setup(void) #endif if (is_hyp()) { - /* Set HCTR to enable LPAE */ + /* Set HTCR to enable LPAE */ asm volatile("mcr p15, 4, %0, c2, c0, 2" : : "r" (reg) : "memory"); /* Set HTTBR0 */ @@ -172,6 +162,15 @@ static inline void mmu_setup(void) : : "r" (MEMORY_ATTRIBUTES) : "memory"); } #elif defined(CONFIG_CPU_V7) + if (is_hyp()) { + /* Set HTCR to disable LPAE */ + asm volatile("mcr p15, 4, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } else { + /* Set TTBCR to disable LPAE */ + asm volatile("mcr p15, 0, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } /* Set TTBR0 */ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) @@ -196,7 +195,6 @@ static inline void mmu_setup(void) /* and enable the mmu */ reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | CR_M); } @@ -214,7 +212,6 @@ static void cache_enable(uint32_t cache_bit) if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | cache_bit); } @@ -224,7 +221,6 @@ static void cache_disable(uint32_t cache_bit) uint32_t reg; reg = get_cr(); - cp_delay(); if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ @@ -234,7 +230,7 @@ static void cache_disable(uint32_t cache_bit) cache_bit |= CR_M; } reg = get_cr(); - cp_delay(); + if (cache_bit == (CR_C | CR_M)) flush_dcache_all(); set_cr(reg & ~cache_bit); diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 066c172..80869ad 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -93,10 +93,18 @@ void show_regs (struct pt_regs *regs) thumb_mode (regs) ? " (T)" : ""); } +/* fixup PC to point to the instruction leading to the exception */ +static inline void fixup_pc(struct pt_regs *regs, int offset) +{ + uint32_t pc = instruction_pointer(regs) + offset; + regs->ARM_pc = pc | (regs->ARM_pc & PCMASK); +} + void do_undefined_instruction (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("undefined instruction\n"); + fixup_pc(pt_regs, -4); show_regs (pt_regs); bad_mode (); } @@ -105,6 +113,7 @@ void do_software_interrupt (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("software interrupt\n"); + fixup_pc(pt_regs, -4); show_regs (pt_regs); bad_mode (); } @@ -113,6 +122,7 @@ void do_prefetch_abort (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("prefetch abort\n"); + fixup_pc(pt_regs, -8); show_regs (pt_regs); bad_mode (); } @@ -121,6 +131,7 @@ void do_data_abort (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("data abort\n"); + fixup_pc(pt_regs, -8); show_regs (pt_regs); bad_mode (); } @@ -129,6 +140,7 @@ void do_not_used (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("not used\n"); + fixup_pc(pt_regs, -8); show_regs (pt_regs); bad_mode (); } @@ -137,6 +149,7 @@ void do_fiq (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("fast interrupt request\n"); + fixup_pc(pt_regs, -8); show_regs (pt_regs); bad_mode (); } @@ -145,6 +158,7 @@ void do_irq (struct pt_regs *pt_regs) { efi_restore_gd(); printf ("interrupt request\n"); + fixup_pc(pt_regs, -8); show_regs (pt_regs); bad_mode (); } diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 8ff2c50..27d6682 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -12,6 +12,7 @@ #include #include #include +#include #ifndef CONFIG_SPL_DM /* Pointer to as well as the global data structure for SPL */ diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index f53b1e9..1019091 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -117,7 +117,6 @@ data_abort: not_used: irq: fiq: - 1: bl 1b /* hang and never return */ @@ -126,7 +125,11 @@ fiq: /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: +#ifdef IRAM_BASE_ADDR + .word IRAM_BASE_ADDR + 0x20 +#else .word 0x0badc0de +#endif @ @ IRQ stack frame. diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 03be388..79090e0 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -7,6 +7,8 @@ #ifndef __MISC_H #define __MISC_H +#include + /* pin muxer definitions */ #define PIN_MUX_NUM_FIELDS 8 /* Per register */ #define PIN_MUX_FIELD_SIZE 4 /* n in bits */ diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index c31f38c..e11099c 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -14,14 +14,15 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include #include #define REG(addr) (*(volatile unsigned int *)(addr)) #define REG_P(addr) ((volatile unsigned int *)(addr)) +#ifndef __ASSEMBLY__ typedef volatile unsigned int dv_reg; typedef volatile unsigned int * dv_reg_p; +#endif /* * Base register addresses @@ -285,6 +286,7 @@ typedef volatile unsigned int * dv_reg_p; #endif /* CONFIG_SOC_DA8XX */ +#ifndef __ASSEMBLY__ void lpsc_on(unsigned int id); void lpsc_syncreset(unsigned int id); void lpsc_disable(unsigned int id); @@ -625,5 +627,6 @@ static inline enum davinci_clk_ids get_async3_src(void) #define FLAG_FLGOFF 0x00000010 #endif +#endif /* !__ASSEMBLY__ */ #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 408b62c..683cdb9 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -2,63 +2,7 @@ if ARCH_OMAP2PLUS choice prompt "OMAP2+ platform select" - default TARGET_BRXRE1 - -config TARGET_BRXRE1 - bool "Support BRXRE1" - select BOARD_LATE_INIT - -config TARGET_BRPPT1 - bool "Support BRPPT1" - select BOARD_LATE_INIT - -config TARGET_DRACO - bool "Support draco" - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_THUBAN - bool "Support thuban" - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_RASTABAN - bool "Support rastaban" - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_ETAMIN - bool "Support etamin" - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_PXM2 - bool "Support pxm2" - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_RUT - bool "Support rut" - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_TI814X_EVM - bool "Support ti814x_evm" - -config TARGET_TI816X_EVM - bool "Support ti816x_evm" + default OMAP34XX config OMAP34XX bool "OMAP34XX SoC" @@ -116,6 +60,20 @@ config OMAP54XX imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT +config TI814X + bool "TI814X SoC" + help + Support for AM335x SOC from Texas Instruments. + The AM335x high performance SOC features a Cortex-A8 + ARM core and more. + +config TI816X + bool "TI816X SoC" + help + Support for AM335x SOC from Texas Instruments. + The AM335x high performance SOC features a Cortex-A8 + ARM core and more. + config AM43XX bool "AM43XX SoC" imply SPL_DM @@ -143,9 +101,6 @@ config AM33XX protocols, optional 3D graphics and an optional customer programmable secure boot. -config TARGET_CM_T43 - bool "Support cm_t43" - endchoice config SYS_MPUCLK diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index aa3986d..d43085c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -20,6 +20,7 @@ endif endif obj-y += utils.o +obj-y += sysinfo-common.o ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) obj-y += hwinit-common.o obj-y += clocks-common.o diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 5c4168f..d8abba9 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -1,3 +1,23 @@ +if TI816X + +config TARGET_TI816X_EVM + bool "Support ti816x_evm" + help + This option specifies support for the TI8168 EVM development platform + with PG2.0 silicon and DDR3 DRAM. + +endif + +if TI814X + +config TARGET_TI814X_EVM + bool "Support ti814x_evm" + help + This option specifies support for the TI8148 + EVM development platform. + +endif + if AM33XX config AM33XX_CHILISOM @@ -6,7 +26,6 @@ config AM33XX_CHILISOM choice prompt "AM33xx board select" - optional config TARGET_AM335X_EVM bool "Support am335x_evm" @@ -84,6 +103,14 @@ config TARGET_BAV335X For more information, visit: http://birdland.com/oem +config TARGET_BRXRE1 + bool "Support BRXRE1" + select BOARD_LATE_INIT + +config TARGET_BRPPT1 + bool "Support BRPPT1" + select BOARD_LATE_INIT + config TARGET_CHILIBOARD bool "Grinn chiliBoard" select AM33XX_CHILISOM @@ -97,6 +124,20 @@ config TARGET_CM_T335 select DM_SERIAL select DM_GPIO +config TARGET_DRACO + bool "Support draco" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_ETAMIN + bool "Support etamin" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + config TARGET_PCM051 bool "Support pcm051" select DM @@ -115,12 +156,43 @@ config TARGET_PEPPER select DM_SERIAL select DM_GPIO +config TARGET_PXM2 + bool "Support pxm2" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_RASTABAN + bool "Support rastaban" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_RUT + bool "Support rut" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_THUBAN + bool "Support thuban" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + endchoice endif if AM43XX +choice + prompt "AM43xx board select" + config TARGET_AM43XX_EVM bool "Support am43xx_evm" select BOARD_LATE_INIT @@ -151,6 +223,12 @@ config TARGET_AM43XX_EVM evaluation module system that enables developers to write software and develop hardware around an AM43xx processor subsystem. + +config TARGET_CM_T43 + bool "Support cm_t43" + +endchoice + endif if AM43XX || AM33XX diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 05cc8a1..b2f8158 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -15,9 +15,14 @@ endif obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o obj-y += ddr.o +ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),) obj-y += emif4.o +endif +obj-$(CONFIG_TI816X) += ti816x_emif4.o obj-y += board.o obj-y += mux.o +obj-y += prcm-regs.o +obj-y += hw_data.o obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index a8b5d13..5f1bf9c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,27 @@ DECLARE_GLOBAL_DATA_PTR; +int dram_init(void) +{ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + sdram_init(); +#endif + + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_platdata am33xx_serial[] = { { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, @@ -326,6 +348,7 @@ void early_system_init(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { + hw_data_init(); early_system_init(); board_early_init_f(); sdram_init(); @@ -340,6 +363,7 @@ void board_init_f(ulong dummy) int arch_cpu_init_dm(void) { + hw_data_init(); #ifndef CONFIG_SKIP_LOWLEVEL_INIT early_system_init(); #endif diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c index 079ddd7..967623d 100644 --- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c +++ b/arch/arm/mach-omap2/am33xx/clock_ti816x.c @@ -54,55 +54,6 @@ #define MAIN_MDIV7 0x4 /* DDR PLL */ -#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x4 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x3 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ -#define DDR_N 50 -#define DDR_P 0x1 -#define DDR_MDIV1 0x2 -#define DDR_INTFREQ2 0x9 -#define DDR_FRACFREQ2 0x0 -#define DDR_MDIV2 0x19 -#define DDR_INTFREQ3 0x13 -#define DDR_FRACFREQ3 0x800000 -#define DDR_MDIV3 0x2 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 -#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ #define DDR_N 59 #define DDR_P 0x1 #define DDR_MDIV1 0x2 @@ -118,12 +69,10 @@ #define DDR_INTFREQ5 0xE /* Expansion DDR clk */ #define DDR_FRACFREQ5 0x0 #define DDR_MDIV5 0x4 -#endif #define CONTROL_STATUS (CTRL_BASE + 0x40) #define DDR_RCD (CTRL_BASE + 0x070C) #define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) -#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) #define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) #define INTCPS_SYSCONFIG 0x48200010 @@ -187,6 +136,15 @@ const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; void enable_dmm_clocks(void) { + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + /* Wait for dmm to be fully functional, including OCP */ + while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) + ; +} + +void enable_emif_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->fwclkctrl); writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); @@ -200,14 +158,6 @@ void enable_dmm_clocks(void) /* Wait for emif1 to be fully functional, including OCP */ while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) ; - - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - /* Wait for dmm to be fully functional, including OCP */ - while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) - ; - - /* Enable Tiled Access */ - writel(0x80000000, DMM_PAT_BASE_ADDR); } /* assume delay is aprox at least 1us */ diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 690487e..7bf19ed 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -163,6 +163,14 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) */ void config_sdram(const struct emif_regs *regs, int nr) { +#ifdef CONFIG_TI816X + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); + writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */ + writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */ + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); +#else if (regs->zq_config) { writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); @@ -184,6 +192,7 @@ void config_sdram(const struct emif_regs *regs, int nr) /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */ if (regs->ocp_config) writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); +#endif } /** diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index 3a110f2..68c7705 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -17,40 +17,9 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - sdram_init(); -#endif - - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_TI81XX -static struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; -#endif -#ifndef CONFIG_TI816X static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; -#endif #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif @@ -60,9 +29,12 @@ static struct cm_device_inst *cm_device = (struct cm_device_inst *)CM_DEVICE_INST; #endif -#ifdef CONFIG_TI81XX +#ifdef CONFIG_TI814X void config_dmm(const struct dmm_lisa_map_regs *regs) { + struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)DMM_BASE; + enable_dmm_clocks(); writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); @@ -77,7 +49,6 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) } #endif -#ifndef CONFIG_TI816X static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -92,7 +63,6 @@ static void config_vtp(int nr) VTP_CTRL_READY) ; } -#endif void __weak ddr_pll_config(unsigned int ddrpll_m) { @@ -103,9 +73,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct emif_regs *regs, int nr) { ddr_pll_config(pll); -#ifndef CONFIG_TI816X config_vtp(nr); -#endif config_cmd_ctrl(ctrl, nr); config_ddr_data(data, nr); @@ -139,4 +107,3 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, else config_sdram(regs, nr); } -#endif diff --git a/arch/arm/mach-omap2/am33xx/hw_data.c b/arch/arm/mach-omap2/am33xx/hw_data.c new file mode 100644 index 0000000..63e55cf --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/hw_data.c @@ -0,0 +1,19 @@ +/* + * HW data initialization for AM33xx. + * + * (C) Copyright 2017 Linaro Ltd. + * Sam Protsenko + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; + +void hw_data_init(void) +{ + *ctrl = &am33xx_ctrl; +} diff --git a/arch/arm/mach-omap2/am33xx/prcm-regs.c b/arch/arm/mach-omap2/am33xx/prcm-regs.c new file mode 100644 index 0000000..c9a3af6 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/prcm-regs.c @@ -0,0 +1,15 @@ +/* + * HW regs data for AM33xx. + * + * (C) Copyright 2017 Linaro Ltd. + * Sam Protsenko + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct omap_sys_ctrl_regs const am33xx_ctrl = { + .control_status = CTRL_BASE + 0x40, +}; diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 564bae6..ea434aa 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -51,16 +51,6 @@ u32 get_cpu_type(void) } /** - * get_device_type(): tell if GP/HS/EMU/TST - */ -u32 get_device_type(void) -{ - int mode; - mode = readl(&cstat->statusreg) & (DEVICE_MASK); - return mode >>= 8; -} - -/** * get_sysboot_value(void) - return SYS_BOOT[4:0] */ u32 get_sysboot_value(void) diff --git a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c new file mode 100644 index 0000000..2e7ea90 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c @@ -0,0 +1,165 @@ +/* + * ti816x_emif4.c + * + * TI816x emif4 configuration file + * + * Copyright (C) 2017, Konsulko Group + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/********************************************************************* + * Init DDR3 on TI816X EVM + *********************************************************************/ +static void ddr_init_settings(const struct cmd_control *ctrl, int emif) +{ + /* + * setup use_rank_delays to 1. This is only necessary when + * multiple ranks are in use. Though the EVM does not have + * multiple ranks, this is a good value to set. + */ + writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS + writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS + writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS + writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS + + config_cmd_ctrl(ctrl, emif); + + /* for ddr3 this needs to be set to 1 */ + writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ + writel(0x1, DDRPHY_CONFIG_BASE + 0x104); + writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); + writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); + writel(0x1, DDRPHY_CONFIG_BASE + 0x240); + writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); + writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4); + writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0); + + /* + * This represents the initial value for the leveling process. The + * value is a ratio - so 0x100 represents one cycle. The real delay + * is determined through the leveling process. + * + * During the leveling process, 0x20 is subtracted from the value, so + * we have added that to the value we want to set. We also set the + * values such that byte3 completes leveling after byte2 and byte1 + * after byte0. + */ + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */ + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */ + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */ + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */ + + + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x100); + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4); + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x248); + writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */ + writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC); + + writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */ +} + +static void ddr3_sw_levelling(const struct ddr_data *data, int emif) +{ + /* Set the correct value to DDR_VTP_CTRL_0 */ + writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); + + writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108)); + writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC)); + writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250)); + writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4)); + + writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC)); + writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180)); + writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224)); + writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8)); + + writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120)); + writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4)); + writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268)); + writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C)); + + writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8)); + writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C)); + writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210)); + writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4)); +} + +static struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)DMM_BASE; + +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) +void config_dmm(const struct dmm_lisa_map_regs *regs) +{ + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); + + writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); +} + +void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, + const struct dmm_lisa_map_regs *lisa_regs, int nrs) +{ + int i; + + enable_emif_clocks(); + + for (i = 0; i < nrs; i++) + ddr_init_settings(ctrl, i); + + enable_dmm_clocks(); + + /* Program the DMM to for non-interleaved configuration */ + config_dmm(lisa_regs); + + /* Program EMIF CFG Registers */ + for (i = 0; i < nrs; i++) { + set_sdram_timings(regs, i); + config_sdram(regs, i); + } + + udelay(1000); + for (i = 0; i < nrs; i++) + ddr3_sw_levelling(data, i); + + udelay(50000); /* Some delay needed */ +} diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index 0346cb9..c12fbc6 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -67,9 +67,14 @@ u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin FORCE u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkomapsecimg) -# Standard ISSW target (certain devices, various boot modes) +# Standard ISSW target (certain devices, various boot modes), when copied to +# an SD card FAT partition this file must be called "MLO", we make a copy with +# this name to make this clear u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkomapsecimg) + @if [ -f $@ ]; then \ + cp -f $@ MLO; \ + fi # For SPI flash on AM335x and AM43xx, these require special byte swap handling # so we use the SPI_X-LOADER target instead of X-LOADER and let the @@ -79,9 +84,13 @@ u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin FORCE # For supporting single stage boot on keystone, the image is a full u-boot # file, not an SPL. This will work for all boot devices, other than SPI -# flash +# flash. On Keystone devices when booting from an SD card FAT partition this +# file must be called "MLO" u-boot_HS_MLO: $(obj)/u-boot.bin $(call if_changed,mkomapsecimg) + @if [ -f $@ ]; then \ + cp -f $@ MLO; \ + fi # For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot # file, not an SPL. In this case the mkomapsecimg command looks for a diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index c090442..7f6db3c 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -278,15 +278,6 @@ int checkboard(void) return 0; } -/* - * get_device_type(): tell if GP/HS/EMU/TST - */ -u32 get_device_type(void) -{ - return (readl((*ctrl)->control_status) & - (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; -} - #if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile index 06cc9f2..61a76b6 100644 --- a/arch/arm/mach-omap2/omap3/Makefile +++ b/arch/arm/mach-omap2/omap3/Makefile @@ -14,6 +14,8 @@ obj-y += board.o obj-y += boot.o obj-y += clock.o obj-y += sys_info.o +obj-y += prcm-regs.o +obj-y += hw_data.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o endif diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 01df579..cd8e302 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -173,6 +173,11 @@ void try_unlock_memory(void) return; } +void early_system_init(void) +{ + hw_data_init(); +} + /****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. @@ -181,6 +186,7 @@ void try_unlock_memory(void) void s_init(void) { watchdog_init(); + early_system_init(); try_unlock_memory(); @@ -204,6 +210,7 @@ void s_init(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { + early_system_init(); mem_init(); } #endif diff --git a/arch/arm/mach-omap2/omap3/hw_data.c b/arch/arm/mach-omap2/omap3/hw_data.c new file mode 100644 index 0000000..53b220a --- /dev/null +++ b/arch/arm/mach-omap2/omap3/hw_data.c @@ -0,0 +1,19 @@ +/* + * HW data initialization for OMAP3. + * + * (C) Copyright 2017 Linaro Ltd. + * Sam Protsenko + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; + +void hw_data_init(void) +{ + *ctrl = &omap3_ctrl; +} diff --git a/arch/arm/mach-omap2/omap3/prcm-regs.c b/arch/arm/mach-omap2/omap3/prcm-regs.c new file mode 100644 index 0000000..ca29ce9 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/prcm-regs.c @@ -0,0 +1,15 @@ +/* + * HW regs data for OMAP3. + * + * (C) Copyright 2017 Linaro Ltd. + * Sam Protsenko + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct omap_sys_ctrl_regs const omap3_ctrl = { + .control_status = OMAP34XX_CTRL_BASE + 0x2F0, +}; diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c index 7e6c263..155f5b2 100644 --- a/arch/arm/mach-omap2/omap3/sys_info.c +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -17,6 +17,7 @@ #include /* get mem tables */ #include #include +#include #include #include @@ -236,14 +237,6 @@ u32 get_boot_type(void) return (readl(&ctrl_base->status) & SYSBOOT_MASK); } -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8); -} - #ifdef CONFIG_DISPLAY_CPUINFO /** * Print CPU information diff --git a/arch/arm/mach-omap2/sysinfo-common.c b/arch/arm/mach-omap2/sysinfo-common.c new file mode 100644 index 0000000..1dc7051 --- /dev/null +++ b/arch/arm/mach-omap2/sysinfo-common.c @@ -0,0 +1,21 @@ +/* + * System information routines for all OMAP based boards. + * + * (C) Copyright 2017 Linaro Ltd. + * Sam Protsenko + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * Tell if device is GP/HS/EMU/TST. + */ +u32 get_device_type(void) +{ + return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >> + DEVICE_TYPE_SHIFT; +} diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 2d03ebf..1946641 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include static void do_cancel_out(u32 *num, u32 *den, u32 factor) { @@ -18,6 +19,121 @@ static void do_cancel_out(u32 *num, u32 *den, u32 factor) } } +#ifdef CONFIG_FASTBOOT_FLASH +static void omap_set_fastboot_cpu(void) +{ + char *cpu; + u32 cpu_rev = omap_revision(); + + switch (cpu_rev) { + case DRA752_ES1_0: + case DRA752_ES1_1: + case DRA752_ES2_0: + cpu = "DRA752"; + break; + case DRA722_ES1_0: + case DRA722_ES2_0: + cpu = "DRA722"; + break; + default: + cpu = NULL; + printf("Warning: fastboot.cpu: unknown CPU rev: %u\n", cpu_rev); + } + + setenv("fastboot.cpu", cpu); +} + +static void omap_set_fastboot_secure(void) +{ + const char *secure; + u32 dev = get_device_type(); + + switch (dev) { + case EMU_DEVICE: + secure = "EMU"; + break; + case HS_DEVICE: + secure = "HS"; + break; + case GP_DEVICE: + secure = "GP"; + break; + default: + secure = NULL; + printf("Warning: fastboot.secure: unknown CPU sec: %u\n", dev); + } + + setenv("fastboot.secure", secure); +} + +static void omap_set_fastboot_board_rev(void) +{ + const char *board_rev; + + board_rev = getenv("board_rev"); + if (board_rev == NULL) + printf("Warning: fastboot.board_rev: unknown board revision\n"); + + setenv("fastboot.board_rev", board_rev); +} + +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV +static u32 omap_mmc_get_part_size(const char *part) +{ + int res; + struct blk_desc *dev_desc; + disk_partition_t info; + u64 sz = 0; + + dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + error("invalid mmc device\n"); + return 0; + } + + res = part_get_info_by_name(dev_desc, part, &info); + if (res < 0) { + error("cannot find partition: '%s'\n", part); + return 0; + } + + /* Calculate size in bytes */ + sz = (info.size * (u64)info.blksz); + /* to KiB */ + sz >>= 10; + + return (u32)sz; +} + +static void omap_set_fastboot_userdata_size(void) +{ + char buf[16]; + u32 sz_kb; + + sz_kb = omap_mmc_get_part_size("userdata"); + if (sz_kb == 0) { + buf[0] = '\0'; + printf("Warning: fastboot.userdata_size: unable to calc\n"); + } else { + sprintf(buf, "%u", sz_kb); + } + + setenv("fastboot.userdata_size", buf); +} +#else +static inline void omap_set_fastboot_userdata_size(void) +{ +} +#endif /* CONFIG_FASTBOOT_FLASH_MMC_DEV */ +void omap_set_fastboot_vars(void) +{ + omap_set_fastboot_cpu(); + omap_set_fastboot_secure(); + omap_set_fastboot_board_rev(); + omap_set_fastboot_userdata_size(); +} +#endif /* CONFIG_FASTBOOT_FLASH */ + /* * Cancel out the denominator and numerator of a fraction * to get smaller numerator and denominator. diff --git a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h index 057bf3f..1fb0648 100644 --- a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h +++ b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h @@ -1,9 +1,9 @@ /* * drivers/mmc/sh-sdhi.h * - * SD/MMC driver for Reneas rmobile ARM SoCs + * SD/MMC driver for Renesas rmobile ARM SoCs * - * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2013-2017 Renesas Electronics Corporation * Copyright (C) 2008-2009 Renesas Solutions Corp. * * SPDX-License-Identifier: GPL-2.0 @@ -50,8 +50,10 @@ /* SDHI CMD VALUE */ #define CMD_MASK 0x0000ffff #define SDHI_APP 0x0040 +#define SDHI_MMC_SEND_OP_COND 0x0701 #define SDHI_SD_APP_SEND_SCR 0x0073 #define SDHI_SD_SWITCH 0x1C06 +#define SDHI_MMC_SEND_EXT_CSD 0x1C08 /* SDHI_PORTSEL */ #define USE_1PORT (1 << 8) /* 1 port */ @@ -120,7 +122,10 @@ #define CLK_ENABLE (1 << 8) /* SDHI_OPTION */ -#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */ +#define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */ +#define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */ +#define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */ +#define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */ /* SDHI_ERR_STS1 */ #define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \ @@ -162,7 +167,9 @@ #define CLKDEV_INIT 400000 /* 100 - 400 KHz */ /* For quirk */ -#define SH_SDHI_QUIRK_16BIT_BUF (1) +#define SH_SDHI_QUIRK_16BIT_BUF BIT(0) +#define SH_SDHI_QUIRK_64BIT_BUF BIT(1) + int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks); #endif /* _SH_SDHI_H */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6be2ab5..9b2ef29 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -51,6 +51,18 @@ config ROCKCHIP_RK3328 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3368 + bool "Support Rockchip RK3368" + select ARM64 + select SYS_NS16550 + help + The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53. + including NEON and GPU, 512KB L2 cache for big cluster and 256 KB + L2 cache for little cluser, PowerVR G6110 based graphics, one video + output processor supporting LVDS、HDMI、eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 @@ -67,6 +79,13 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RV1108 + bool "Support Rockchip RV1108" + select CPU_V7 + help + The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 + and a DSP. + config ROCKCHIP_SPL_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 @@ -94,5 +113,7 @@ source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" +source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rv1108/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 327b267..87d2019 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -31,4 +31,6 @@ endif obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ +obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9894a25..a354d99 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -86,8 +86,10 @@ static int veyron_init(void) int ret; ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) + if (ret) { + debug("Cannot set regulator name\n"); return ret; + } /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); @@ -307,3 +309,38 @@ U_BOOT_CMD( "display information about clocks", "" ); + +#define GRF_SOC_CON2 0xff77024c + +int board_early_init_f(void) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + return ret; + } + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig new file mode 100644 index 0000000..6d32068 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -0,0 +1,32 @@ +if ROCKCHIP_RK3368 + +choice + prompt "RK3368 board" + +config TARGET_SHEEP + bool "Sheep board" + help + Sheep board is designed by Rockchip as a EVB board + for rk3368. + +config TARGET_GEEKBOX + bool "GeekBox" + +config TARGET_EVB_PX5 + bool "Evb-PX5" + help + PX5 EVB is designed by Rockchip for automotive field + with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS + HDMI video input/output interface, audio codec ES8396, + WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity + sensor STK3410. +endchoice + +config SYS_SOC + default "rockchip" + +source "board/rockchip/sheep_rk3368/Kconfig" +source "board/geekbuying/geekbox/Kconfig" +source "board/rockchip/evb_px5/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile new file mode 100644 index 0000000..46798c2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2016 Andreas Färber +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += clk_rk3368.o +obj-y += rk3368.o +obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c new file mode 100644 index 0000000..2f98165 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3368_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3368_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c new file mode 100644 index 0000000..fb829a4 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IMEM_BASE 0xFF8C0000 + +/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ +#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4) +#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28) +#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12) +/* exsram may using by mcu to accessing dram(0x0-0x20000000) */ +#define MCU_EXSRAM_BASE (0) +#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28) +#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12) +/* experi no used, reserved value = 0 */ +#define MCU_EXPERI_BASE (0) +#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28) +#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12) + +static struct mm_region rk3368_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3368_mem_map; + +#ifdef CONFIG_ARCH_EARLY_INIT_R +static int mcu_init(void) +{ + struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3368_cru *cru = rockchip_get_cru(); + + rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, + MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, + MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT); + rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, + MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, + MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT); + rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, + MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT); + rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, + MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT); + + rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, + (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) | + (5 << MCU_CLK_DIV_SHIFT)); + + /* mcu dereset, for start running */ + rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); + + return 0; +} + +int arch_early_init_r(void) +{ + return mcu_init(); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c new file mode 100644 index 0000000..03e97eb --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id rk3368_syscon_ids[] = { + { .compatible = "rockchip,rk3368-grf", + .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3368-pmugrf", + .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3368) = { + .name = "rk3368_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 050f5e1..e050aff 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -156,8 +156,6 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -#define SGRF_DDR_RGN_CON16 0xff330040 - void board_debug_uart_init(void) { #include @@ -188,6 +186,8 @@ void board_debug_uart_init(void) } #define GRF_EMMCCORE_CON11 0xff77f02c +#define SGRF_DDR_RGN_CON16 0xff330040 +#define SGRF_SLV_SECURE_CON4 0xff33e3d0 void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -207,6 +207,7 @@ void board_init_f(ulong dummy) debug_uart_init(); printascii("U-Boot SPL board init"); #endif + /* Emmc clock generator: disable the clock multipilier */ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); @@ -217,7 +218,7 @@ void board_init_f(ulong dummy) } /* - * Disable DDR security regions. + * Disable DDR and SRAM security regions. * * As we are entered from the BootROM, the region from * 0x0 through 0xfffff (i.e. the first MB of memory) will @@ -226,6 +227,7 @@ void board_init_f(ulong dummy) * located in this range. */ rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0); + rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000); secure_timer_init(); diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index a3ae8bd..1b91bb1 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -5,6 +5,7 @@ * * Adapted from coreboot. */ + #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; struct chan_info { @@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret; + const ulong timeout_ms = 200; /* * work around controller bug: @@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); /* Wating for PHY and DRAM init complete */ - tmp = 0; - while (!(readl(&denali_ctl[203]) & (1 << 3))) { - mdelay(10); - tmp++; - if (tmp > 10) + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("DRAM (%s): phy failed to lock within %ld ms\n", + __func__, timeout_ms); return -ETIME; - } + } + } while (!(readl(&denali_ctl[203]) & (1 << 3))); + debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit); @@ -1082,7 +1087,7 @@ static int sdram_init(struct dram_info *dram, debug("Starting SDRAM initialization...\n"); - if ((dramtype == DDR3 && ddr_freq > 800) || + if ((dramtype == DDR3 && ddr_freq > 933) || (dramtype == LPDDR3 && ddr_freq > 933) || (dramtype == LPDDR4 && ddr_freq > 800)) { debug("SDRAM frequency is to high!"); diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig new file mode 100644 index 0000000..e6cba66 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -0,0 +1,28 @@ +if ROCKCHIP_RV1108 + +config TARGET_EVB_RV1108 + bool "EVB_RV1108" + help + RV1108 EVB is a evaluation board for Rockchp RV1108. + + Key features of the board include: + * one macro USB OTG port + * one USB HOST port + * one RS232 to USB port route to UART2 as debug port + * MIPI screen with resolution 720 x 1280 + * 128M DDR3 + * 64M SPI Nor Flash + * macro SD card interface + * HDMI output + * 10/100 Mbps Ethernet + * camera interface compatible with imx323 / ov2710 / ov4689 + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +source board/rockchip/evb_rv1108/Kconfig + +endif diff --git a/arch/arm/mach-rockchip/rv1108/Makefile b/arch/arm/mach-rockchip/rv1108/Makefile new file mode 100644 index 0000000..9035a1a --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y += syscon_rv1108.o +endif +obj-y += rv1108.o +obj-y += clk_rv1108.o diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c new file mode 100644 index 0000000..968c356 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(clk_rv1108), devp); +} + +void *rockchip_get_cru(void) +{ + struct rv1108_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c new file mode 100644 index 0000000..868cdd5 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c new file mode 100644 index 0000000..8bb0ab8 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id rv1108_syscon_ids[] = { + { .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rv1108) = { + .name = "rv1108_syscon", + .id = UCLASS_SYSCON, + .of_match = rv1108_syscon_ids, +}; diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index ec6b3ff..8f43714 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -8,6 +8,25 @@ config STM32F1 config STM32F7 bool "stm32f7 family" + select SUPPORT_SPL + select SPL + select SPL_CLK + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_DRIVERS_MISC_SUPPORT + select SPL_GPIO_SUPPORT + select SPL_LIBCOMMON_SUPPORT + select SPL_LIBGENERIC_SUPPORT + select SPL_MTD_SUPPORT + select SPL_OF_CONTROL + select SPL_OF_LIBFDT + select SPL_OF_TRANSLATE + select SPL_OS_BOOT + select SPL_PINCTRL + select SPL_RAM + select SPL_SERIAL_SUPPORT + select SPL_SYS_MALLOC_SIMPLE + select SPL_XIP_SUPPORT source "arch/arm/mach-stm32/stm32f4/Kconfig" source "arch/arm/mach-stm32/stm32f1/Kconfig" diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 7ced838..bd3e7d3 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -29,11 +29,34 @@ config SUNXI_GEN_SUN6I separate ahb reset control registers, custom pmic bus, new style watchdog, etc. +config SUNXI_DRAM_DW + bool + ---help--- + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code, but can + use modified H3 DRAM initialization code. + +if SUNXI_DRAM_DW +config SUNXI_DRAM_DW_16BIT + bool + ---help--- + Select this for sunxi SoCs with DesignWare DRAM controller and + have only 16-bit memory buswidth. + +config SUNXI_DRAM_DW_32BIT + bool + ---help--- + Select this for sunxi SoCs with DesignWare DRAM controller with + 32-bit memory buswidth. +endif config MACH_SUNXI_H3_H5 bool select DM_I2C select SUNXI_DE2 + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -118,6 +141,8 @@ config MACH_SUN8I_R40 select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT config MACH_SUN8I_V3S bool "sun8i (Allwinner V3s)" @@ -126,6 +151,9 @@ config MACH_SUN8I_V3S select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_16BIT + select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN9I @@ -143,6 +171,8 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUNXI_HIGH_SRAM select SUPPORT_SPL + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT select FIT select SPL_LOAD_FIT @@ -189,6 +219,47 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed. +if SUNXI_DRAM_DW +config SUNXI_DRAM_DDR3 + bool + +config SUNXI_DRAM_DDR2 + bool + +config SUNXI_DRAM_LPDDR3 + bool + +choice + prompt "DRAM Type and Timing" + default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S + default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S + +config SUNXI_DRAM_DDR3_1333 + bool "DDR3 1333" + select SUNXI_DRAM_DDR3 + depends on !MACH_SUN8I_V3S + ---help--- + This option is the original only supported memory type, which suits + many H3/H5/A64 boards available now. + +config SUNXI_DRAM_LPDDR3_STOCK + bool "LPDDR3 with Allwinner stock configuration" + select SUNXI_DRAM_LPDDR3 + ---help--- + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. + +config SUNXI_DRAM_DDR2_V3S + bool "DDR2 found in V3s chip" + select SUNXI_DRAM_DDR2 + depends on MACH_SUN8I_V3S + ---help--- + This option is only for the DDR2 memory chip which is co-packaged in + Allwinner V3s SoC. + +endchoice +endif + config DRAM_TYPE int "sunxi dram type" depends on MACH_SUN8I_A83T @@ -201,7 +272,8 @@ config DRAM_CLK default 792 if MACH_SUN9I default 648 if MACH_SUN8I_R40 default 312 if MACH_SUN6I || MACH_SUN8I - default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ + MACH_SUN8I_V3S default 672 if MACH_SUN50I ---help--- Set the dram clock speed, valid range 240 - 480 (prior to sun9i), @@ -221,6 +293,7 @@ config DRAM_ZQ int "sunxi dram zq value" default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I default 127 if MACH_SUN7I + default 14779 if MACH_SUN8I_V3S default 3881979 if MACH_SUN8I_R40 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 5510aa5..2a3c379 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,8 +48,7 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o -obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o -obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c similarity index 84% rename from arch/arm/mach-sunxi/dram_sun8i_h3.c rename to arch/arm/mach-sunxi/dram_sunxi_dw.c index 2d12661..78b4ffb 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -16,33 +16,6 @@ #include #include -/* - * The delay parameters below allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define BITS_PER_BYTE 8 -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para { - u16 page_size; - u8 bus_width; - u8 dual_rank; - u8 row_bits; - const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 ac_delays[31]; -}; - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - static void mctl_phy_init(u32 val) { struct sunxi_mctl_ctl_reg * const mctl_ctl = @@ -268,90 +241,6 @@ static void mctl_set_master_priority(uint16_t socid) } } -static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - u8 tccd = 2; - u8 tfaw = ns_to_t(50); - u8 trrd = max(ns_to_t(10), 4); - u8 trcd = ns_to_t(15); - u8 trc = ns_to_t(53); - u8 txp = max(ns_to_t(8), 3); - u8 twtr = max(ns_to_t(8), 4); - u8 trtp = max(ns_to_t(8), 4); - u8 twr = max(ns_to_t(15), 3); - u8 trp = ns_to_t(15); - u8 tras = ns_to_t(38); - u16 trefi = ns_to_t(7800) / 32; - u16 trfc = ns_to_t(350); - - u8 tmrw = 0; - u8 tmrd = 4; - u8 tmod = 12; - u8 tcke = 3; - u8 tcksrx = 5; - u8 tcksre = 5; - u8 tckesr = 4; - u8 trasmax = 24; - - u8 tcl = 6; /* CL 12 */ - u8 tcwl = 4; /* CWL 8 */ - u8 t_rdata_en = 4; - u8 wr_latency = 2; - - u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ - u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ - u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - - u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ - - /* set mode register */ - writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ - writel(0x40, &mctl_ctl->mr[1]); - writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ - writel(0x0, &mctl_ctl->mr[3]); - - if (socid == SOCID_R40) - writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */ - - /* set DRAM timing */ - writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | - DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), - &mctl_ctl->dramtmg[0]); - writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), - &mctl_ctl->dramtmg[1]); - writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | - DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), - &mctl_ctl->dramtmg[2]); - writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), - &mctl_ctl->dramtmg[3]); - writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | - DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); - writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | - DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), - &mctl_ctl->dramtmg[5]); - - /* set two rank timing */ - clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), - ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0)); - - /* set PHY interface timing, write latency and read latency configure */ - writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | - (wr_latency << 0), &mctl_ctl->pitmg[0]); - - /* set PHY timing, PTR0-2 use default */ - writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); - writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); - - /* set refresh timing */ - writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); -} - static u32 bin_to_mgray(int val) { static const u8 lookup_table[32] = { @@ -380,6 +269,13 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + int zq_count; + +#if defined CONFIG_SUNXI_DRAM_DW_16BIT + zq_count = 4; +#else + zq_count = 6; +#endif if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { @@ -408,7 +304,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); - for (i = 0; i < 6; i++) { + for (i = 0; i < zq_count; i++) { u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; writel((zq << 20) | (zq << 16) | (zq << 12) | @@ -430,7 +326,9 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); - writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + if (zq_count > 4) + writel((zq_val[5] << 16) | zq_val[4], + &mctl_ctl->zqdr[2]); } } @@ -439,8 +337,18 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | + writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED | +#if defined CONFIG_SUNXI_DRAM_DDR3 + MCTL_CR_DDR3 | MCTL_CR_2T | +#elif defined CONFIG_SUNXI_DRAM_DDR2 + MCTL_CR_DDR2 | MCTL_CR_2T | +#elif defined CONFIG_SUNXI_DRAM_LPDDR3 + MCTL_CR_LPDDR3 | MCTL_CR_1T | +#else +#error Unsupported DRAM type! +#endif + (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | + MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); @@ -578,9 +486,15 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) } /* set half DQ */ - if (para->bus_width != 32) { + if (!para->bus_full_width) { +#if defined CONFIG_SUNXI_DRAM_DW_32BIT writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); +#elif defined CONFIG_SUNXI_DRAM_DW_16BIT + writel(0x0, &mctl_ctl->dx[1].gcr); +#else +#error Unsupported DRAM bus width! +#endif } /* data training configuration */ @@ -611,19 +525,29 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* detect ranks and bus width */ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { /* only one rank */ - if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) || - ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) { + if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) +#if defined CONFIG_SUNXI_DRAM_DW_32BIT + || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2) +#endif + ) { clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); para->dual_rank = 0; } /* only half DQ width */ +#if defined CONFIG_SUNXI_DRAM_DW_32BIT if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) || ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); - para->bus_width = 16; + para->bus_full_width = 0; + } +#elif defined CONFIG_SUNXI_DRAM_DW_16BIT + if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) { + writel(0x0, &mctl_ctl->dx[1].gcr); + para->bus_full_width = 0; } +#endif mctl_set_cr(socid, para); udelay(20); @@ -663,10 +587,19 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) /* detect row address bits */ para->page_size = 512; para->row_bits = 16; + para->bank_bits = 2; mctl_set_cr(socid, para); for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) - if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) + break; + + /* detect bank address bits */ + para->bank_bits = 3; + mctl_set_cr(socid, para); + + for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) + if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) break; /* detect page size */ @@ -757,9 +690,10 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct dram_para para = { - .dual_rank = 0, - .bus_width = 32, + .dual_rank = 1, + .bus_full_width = 1, .row_bits = 15, + .bank_bits = 3, .page_size = 4096, #if defined(CONFIG_MACH_SUN8I_H3) @@ -789,6 +723,11 @@ unsigned long sunxi_dram_init(void) uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN8I_R40) uint16_t socid = SOCID_R40; + /* Currently we cannot support R40 with dual rank memory */ + para.dual_rank = 0; +#elif defined(CONFIG_MACH_SUN8I_V3S) + /* TODO: set delays and mbus priority for V3s */ + uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN50I) uint16_t socid = SOCID_A64; #elif defined(CONFIG_MACH_SUN50I_H5) @@ -824,6 +763,6 @@ unsigned long sunxi_dram_init(void) mctl_auto_detect_dram_size(socid, ¶); mctl_set_cr(socid, ¶); - return (1UL << (para.row_bits + 3)) * para.page_size * - (para.dual_rank ? 2 : 1); + return (1UL << (para.row_bits + para.bank_bits)) * para.page_size * + (para.dual_rank ? 2 : 1); } diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile new file mode 100644 index 0000000..278a8a1 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o +obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o diff --git a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c new file mode 100644 index 0000000..9077f86 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c @@ -0,0 +1,84 @@ +#include +#include +#include + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 1; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = ns_to_t(20); + u8 trc = ns_to_t(65); + u8 txp = 2; + u8 twtr = max(ns_to_t(8), 2); + u8 trtp = max(ns_to_t(8), 2); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(45); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(328); + + u8 tmrw = 0; + u8 tmrd = 2; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 27; + + u8 tcl = 3; /* CL 6 */ + u8 tcwl = 3; /* CWL 6 */ + u8 t_rdata_en = 1; + u8 wr_latency = 1; + + u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */ + u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x263, &mctl_ctl->mr[0]); + writel(0x4, &mctl_ctl->mr[1]); + writel(0x0, &mctl_ctl->mr[2]); + writel(0x0, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c new file mode 100644 index 0000000..0471e8a --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -0,0 +1,87 @@ +#include +#include +#include + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ + writel(0x40, &mctl_ctl->mr[1]); + writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ + writel(0x0, &mctl_ctl->mr[3]); + + if (socid == SOCID_R40) + writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */ + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c new file mode 100644 index 0000000..bd57e2f --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -0,0 +1,83 @@ +#include +#include +#include + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = max(ns_to_t(50), 4); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = max(ns_to_t(24), 2); + u8 trc = ns_to_t(70); + u8 txp = max(ns_to_t(8), 2); + u8 twtr = max(ns_to_t(8), 2); + u8 trtp = max(ns_to_t(8), 2); + u8 twr = max(ns_to_t(15), 3); + u8 trp = max(ns_to_t(27), 2); + u8 tras = ns_to_t(42); + u16 trefi = ns_to_t(3900) / 32; + u16 trfc = ns_to_t(210); + + u8 tmrw = 5; + u8 tmrd = 5; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 5; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 3; /* CWL 6 */ + u8 t_rdata_en = 5; + u8 wr_latency = 2; + + u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ + u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 4 + twr + 1; + u8 twr2rd = tcwl + 4 + 1 + twtr; + u8 trd2wr = tcl + 4 + 5 - tcwl + 1; + + /* set mode register */ + writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */ + writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */ + writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */ + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 84f1ee5..1e627ba 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -191,6 +191,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { + if (!clock_early_init_done()) + clock_early_init(); + #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) #define USBCMD_FS2 (1 << 15) { diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 3bb7233..bac4211 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * return value doesn't help. In summary this clock driver is * quite broken but I'm afraid I have no idea how to fix it * without completely replacing it. + * + * Be careful to avoid a divide by zero error. */ - div -= 2; + if (div >= 1) + div -= 2; break; #endif default: @@ -825,3 +828,8 @@ int clock_external_output(int clk_id) return 0; } + +__weak bool clock_early_init_done(void) +{ + return true; +} diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 5e44061..5ae718b 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -891,6 +891,24 @@ void clock_early_init(void) udelay(2); } +/* + * clock_early_init_done - Check if clock_early_init() has been called + * + * Check a register that we set up to see if clock_early_init() has already + * been called. + * + * @return true if clock_early_init() was called, false if not + */ +bool clock_early_init_done(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = readl(&clkrst->crc_sclk_brst_pol); + + return val == 0x20002222; +} + void arch_timer_init(void) { struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 99445a4..5c4d35b 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -36,10 +36,6 @@ config TARGET_VENTANA bool "NVIDIA Tegra20 Ventana evaluation board" select BOARD_LATE_INIT -config TARGET_WHISTLER - bool "NVIDIA Tegra20 Whistler evaluation board" - select BOARD_LATE_INIT - config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" select BOARD_LATE_INIT @@ -57,7 +53,6 @@ source "board/nvidia/seaboard/Kconfig" source "board/avionic-design/tec/Kconfig" source "board/compulab/trimslice/Kconfig" source "board/nvidia/ventana/Kconfig" -source "board/nvidia/whistler/Kconfig" source "board/toradex/colibri_t20/Kconfig" endif diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 2529c9f..c428ce5 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -24,6 +24,14 @@ config SPL_SPI_FLASH_SUPPORT config SPL_SPI_SUPPORT default y if ZYNQ_QSPI +config ZYNQ_DDRC_INIT + bool "Zynq DDRC initialization" + default y + help + This option used to perform DDR specific initialization + if required. There might be cases like ddr less where we + want to skip ddr init and this option is useful for it. + config SYS_BOARD default "zynq" diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index d74f8db..bde52d6 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -12,6 +12,9 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_ZYNQ_DDRC_INIT +void zynq_ddrc_init(void) {} +#else /* Control regsiter bitfield definitions */ #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2 @@ -46,3 +49,4 @@ void zynq_ddrc_init(void) puts("ECC disabled "); } } +#endif diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 5e70d9e..f80d8fd 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-y += microblaze-generic.dtb +dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb targets += $(dtb-y) diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index af03e8d..68985af 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -17,6 +17,7 @@ /* Use the generic board which requires a unified bd_info */ #include +#include /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_MIPS diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h index 2efdeb1..4378ebf 100644 --- a/arch/nds32/include/asm/u-boot.h +++ b/arch/nds32/include/asm/u-boot.h @@ -20,6 +20,8 @@ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 +#include + #include typedef struct bd_info { diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 4c95a41..21aadf2 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index f37a9cb..d030610 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -8,18 +8,6 @@ choice prompt "CPU select" optional -config MPC512X - bool "MPC512X" - -config 5xx - bool "MPC5xx" - -config MPC5xxx - bool "MPC5xxx" - -config MPC8260 - bool "MPC8260" - config MPC83xx bool "MPC83xx" select CREATE_ARCH_SYMLINK @@ -41,9 +29,6 @@ config MPC86xx select SYS_FSL_DDR select SYS_FSL_DDR_BE -config 8xx - bool "MPC8xx" - config 4xx bool "PPC4xx" select CREATE_ARCH_SYMLINK @@ -51,16 +36,9 @@ config 4xx endchoice -source "arch/powerpc/lib/Kconfig" - -source "arch/powerpc/cpu/mpc512x/Kconfig" -source "arch/powerpc/cpu/mpc5xx/Kconfig" -source "arch/powerpc/cpu/mpc5xxx/Kconfig" -source "arch/powerpc/cpu/mpc8260/Kconfig" source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc86xx/Kconfig" -source "arch/powerpc/cpu/mpc8xx/Kconfig" source "arch/powerpc/cpu/ppc4xx/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc512x/Kconfig b/arch/powerpc/cpu/mpc512x/Kconfig deleted file mode 100644 index 53450ae..0000000 --- a/arch/powerpc/cpu/mpc512x/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -menu "mpc512x CPU" - depends on MPC512X - -config SYS_CPU - default "mpc512x" - -choice - prompt "Target select" - optional - -config TARGET_PDM360NG - bool "Support pdm360ng" - -config TARGET_ARIA - bool "Support aria" - -config TARGET_MECP5123 - bool "Support mecp5123" - -config TARGET_MPC5121ADS - bool "Support mpc5121ads" - -config TARGET_AC14XX - bool "Support ac14xx" - -endchoice - -source "board/davedenx/aria/Kconfig" -source "board/esd/mecp5123/Kconfig" -source "board/freescale/mpc5121ads/Kconfig" -source "board/ifm/ac14xx/Kconfig" -source "board/pdm360ng/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile deleted file mode 100644 index 933deeb..0000000 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2007-2009 DENX Software Engineering -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y := cpu.o -obj-y += traps.o -obj-y += cpu_init.o -obj-y += fixed_sdram.o -obj-y += interrupts.o -obj-y += iopin.o -obj-y += serial.o -obj-y += speed.o -obj-$(CONFIG_FSL_DIU_FB) += diu.o -obj-$(CONFIG_CMD_IDE) += ide.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc512x/asm-offsets.h b/arch/powerpc/cpu/mpc512x/asm-offsets.h deleted file mode 100644 index 957d4be2..0000000 --- a/arch/powerpc/cpu/mpc512x/asm-offsets.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * needed for arch/powerpc/cpu/mpc512x/start.S - * - * These should be auto-generated - */ -#define LPCS0AW 0x0024 -#define SRAMBAR 0x00C4 -#define SWCRR 0x0904 -#define LPC_OFFSET 0x10000 -#define CS0_CONFIG 0x00000 -#define CS_CTRL 0x00020 -#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ - -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk deleted file mode 100644 index 5bf1b2a..0000000 --- a/arch/powerpc/cpu/mpc512x/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2007-2010 DENX Software Engineering -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c deleted file mode 100644 index ce524fc..0000000 --- a/arch/powerpc/cpu/mpc512x/cpu.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2007-2010 DENX Software Engineering - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for the MPC512x family. - * - * Derived from the MPC83xx code. - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int checkcpu (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong clock = gd->cpu_clk; - u32 pvr = get_pvr (); - u32 spridr = in_be32(&immr->sysconf.spridr); - char buf1[32], buf2[32]; - - puts ("CPU: "); - - switch (spridr & 0xffff0000) { - case SPR_5121E: - puts ("MPC5121e "); - break; - default: - printf ("Unknown part ID %08x ", spridr & 0xffff0000); - } - printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr)); - - switch (pvr & 0xffff0000) { - case PVR_E300C4: - puts ("e300c4 "); - break; - default: - puts ("unknown "); - } - printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n", - strmhz(buf1, clock), - strmhz(buf2, gd->arch.csb_clk), - gd->arch.reset_status & 0xffff); - return 0; -} - - -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~( MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Enable Reset Control Reg - "RSTE" is the magic word that let us go - */ - out_be32(&immap->reset.rpr, 0x52535445); - - /* Verify Reset Control Reg is enabled */ - while (!(in_be32(&immap->reset.rcer) & RCER_CRE)) - ; - - printf ("Resetting the board.\n"); - udelay(200); - - /* Perform reset */ - out_be32(&immap->reset.rcr, RCR_SWHR); - - /* Unreached... */ - return 1; -} - - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - */ -unsigned long get_tbclk (void) -{ - return (gd->bus_clk + 3L) / 4L; -} - - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - /* Reset watchdog */ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - out_be32(&immr->wdt.swsrr, 0x556c); - out_be32(&immr->wdt.swsrr, 0xaa39); - - if (re_enable) - enable_interrupts (); -} -#endif - -#ifdef CONFIG_OF_LIBFDT - -#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES -/* - * fdt setup for old device trees - * fix up - * cpu clocks - * soc clocks - * ethernet addresses - */ -static void old_ft_cpu_setup(void *blob, bd_t *bd) -{ - /* - * avoid fixing up by path because that - * produces scary error messages - */ - uchar enetaddr[6]; - - /* - * old device trees have ethernet nodes with - * device_type = "network" - */ - eth_getenv_enetaddr("ethaddr", enetaddr); - do_fixup_by_prop(blob, "device_type", "network", 8, - "local-mac-address", enetaddr, 6, 0); - do_fixup_by_prop(blob, "device_type", "network", 8, - "address", enetaddr, 6, 0); - /* - * old device trees have soc nodes with - * device_type = "soc" - */ - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, - "bus-frequency", bd->bi_ipsfreq, 0); -} -#endif - -static void ft_clock_setup(void *blob, bd_t *bd) -{ - char *cpu_path = "/cpus/" OF_CPU; - - /* - * fixup cpu clocks using path - */ - do_fixup_by_path_u32(blob, cpu_path, - "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, - "clock-frequency", bd->bi_intfreq, 1); - /* - * fixup soc clocks using compatible - */ - do_fixup_by_compat_u32(blob, OF_SOC_COMPAT, - "bus-frequency", bd->bi_ipsfreq, 1); -} - -void ft_cpu_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES - old_ft_cpu_setup(blob, bd); -#endif - ft_clock_setup(blob, bd); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#endif - -#ifdef CONFIG_MPC512x_FEC -/* Default initializations for FEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -int cpu_eth_init(bd_t *bis) -{ - return mpc512x_fec_initialize(bis); -} -#endif diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c deleted file mode 100644 index 48a5e4f..0000000 --- a/arch/powerpc/cpu/mpc512x/cpu_init.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. - * Copyright (C) 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Derived from the MPC83xx code. - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Set up the memory map, initialize registers, - */ -void cpu_init_f (volatile immap_t * im) -{ - u32 ips_div; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* Local Window and chip select configuration */ -#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) - out_be32(&im->sysconf.lpcs0aw, - CSAW_START(CONFIG_SYS_CS0_START) | - CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE)); - sync_law(&im->sysconf.lpcs0aw); -#endif -#if defined(CONFIG_SYS_CS0_CFG) - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); -#endif - -#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(CONFIG_SYS_CS1_START) | - CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE)); - sync_law(&im->sysconf.lpcs1aw); -#endif -#if defined(CONFIG_SYS_CS1_CFG) - out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); -#endif - -#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE) - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_CS2_START) | - CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE)); - sync_law(&im->sysconf.lpcs2aw); -#endif -#if defined(CONFIG_SYS_CS2_CFG) - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); -#endif - -#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) - out_be32(&im->sysconf.lpcs3aw, - CSAW_START(CONFIG_SYS_CS3_START) | - CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE)); - sync_law(&im->sysconf.lpcs3aw); -#endif -#if defined(CONFIG_SYS_CS3_CFG) - out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG); -#endif - -#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) - out_be32(&im->sysconf.lpcs4aw, - CSAW_START(CONFIG_SYS_CS4_START) | - CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE)); - sync_law(&im->sysconf.lpcs4aw); -#endif -#if defined(CONFIG_SYS_CS4_CFG) - out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG); -#endif - -#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) - out_be32(&im->sysconf.lpcs5aw, - CSAW_START(CONFIG_SYS_CS5_START) | - CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE)); - sync_law(&im->sysconf.lpcs5aw); -#endif -#if defined(CONFIG_SYS_CS5_CFG) - out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG); -#endif - -#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) - out_be32(&im->sysconf.lpcs6aw, - CSAW_START(CONFIG_SYS_CS6_START) | - CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE)); - sync_law(&im->sysconf.lpcs6aw); -#endif -#if defined(CONFIG_SYS_CS6_CFG) - out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG); -#endif - -#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) - out_be32(&im->sysconf.lpcs7aw, - CSAW_START(CONFIG_SYS_CS7_START) | - CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE)); - sync_law(&im->sysconf.lpcs7aw); -#endif -#if defined(CONFIG_SYS_CS7_CFG) - out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG); -#endif - -#if defined CONFIG_SYS_CS_ALETIMING - if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2) - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); -#endif -#if defined CONFIG_SYS_CS_BURST - out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST); -#endif -#if defined CONFIG_SYS_CS_DEADCYCLE - out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE); -#endif -#if defined CONFIG_SYS_CS_HOLDCYCLE - out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE); -#endif - - /* system performance tweaking */ - -#ifdef CONFIG_SYS_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - out_be32(&im->arbiter.acr, - (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) - ); -#endif - -#ifdef CONFIG_SYS_ACR_RPTCNT - /* Arbiter repeat count */ - out_be32(im->arbiter.acr, - (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) - ); -#endif - - /* RSR - Reset Status Register - clear all status */ - gd->arch.reset_status = im->reset.rsr; - out_be32(&im->reset.rsr, ~RSR_RES); - - /* - * RMR - Reset Mode Register - enable checkstop reset - */ - out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT)); - - /* Set IPS-CSB divider: IPS = 1/2 CSB */ - ips_div = in_be32(&im->clk.scfr[0]); - ips_div &= ~(SCFR1_IPS_DIV_MASK); - ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; - out_be32(&im->clk.scfr[0], ips_div); - -#ifdef SCFR1_LPC_DIV - clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK, - SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT); -#endif - -#ifdef SCFR1_NFC_DIV - clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK, - SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT); -#endif - -#ifdef SCFR1_DIU_DIV - clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK, - SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT); -#endif - - /* - * Enable Time Base/Decrementer - * - * NOTICE: TB needs to be enabled as early as possible in order to - * have udelay() working; if not enabled, usually leads to a hang, like - * during FLASH chip identification etc. - */ - setbits_be32(&im->sysconf.spcr, SPCR_TBEN); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif -} - -int cpu_init_r (void) -{ - return 0; -} diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c deleted file mode 100644 index 36e1f9c..0000000 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * York Sun - * - * FSL DIU Framebuffer driver - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -void diu_set_pixel_clock(unsigned int pixclock) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile clk512x_t *clk = &immap->clk; - volatile unsigned int *clkdvdr = &clk->scfr[0]; - unsigned long speed_ccb, temp, pixval; - - speed_ccb = get_bus_freq(0) * 4; - temp = 1000000000/pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - debug("DIU pixval = %lu\n", pixval); - - /* Modify PXCLK in GUTS CLKDVDR */ - debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); - temp = in_be32(clkdvdr) & 0xFFFFFF00; - out_be32(clkdvdr, temp | (pixval & 0xFF)); - debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - unsigned int pixel_format = 0x88883316; - - debug("mpc5121_diu_init\n"); - return fsl_diu_init(xres, yres, pixel_format, 0); -} diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c deleted file mode 100644 index 68c5f8a..0000000 --- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * MDDRC Config Runtime Settings - */ -ddr512x_config_t default_mddrc_config = { - .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG, - .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, - .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1, - .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2, -}; - -u32 default_init_seq[] = { - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_EM3, - CONFIG_SYS_DDRCMD_EN_DLL, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_OCD_DEFAULT, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP -}; - -/* - * fixed sdram init: - * The board doesn't use memory modules that have serial presence - * detect or similar mechanism for discovery of the DRAM settings - */ -long int fixed_sdram(ddr512x_config_t *mddrc_config, - u32 *dram_init_seq, int seq_sz) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_MAX_RAM_SIZE; - u32 msize_log2 = __ilog2(msize); - u32 i; - - /* take default settings and init sequence if necessary */ - if (mddrc_config == NULL) - mddrc_config = &default_mddrc_config; - if (dram_init_seq == NULL) { - dram_init_seq = default_init_seq; - seq_sz = ARRAY_SIZE(default_init_seq); - } - - /* Initialize IO Control */ - out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR); - - /* Initialize DDR Local Window */ - out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); - out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); - sync_law(&im->sysconf.ddrlaw.ar); - - /* DDR Enable */ - /* - * the "enable" combination: DRAM controller out of reset, - * clock enabled, command mode -- BUT leave CKE low for now - */ - i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK; - out_be32(&im->mddrc.ddr_sys_config, i); - /* maintain 200 microseconds of stable power and clock */ - udelay(200); - /* apply a NOP, it shouldn't harm */ - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP); - /* now assert CKE (high) */ - i |= MDDRC_SYS_CFG_CKE_MASK; - out_be32(&im->mddrc.ddr_sys_config, i); - - /* Initialize DDR Priority Manager */ - out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); - out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); - out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); - out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); - out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); - out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); - out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); - out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); - out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); - out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); - out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); - out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); - out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); - out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); - out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); - out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); - out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); - out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); - out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); - out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); - out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); - out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); - out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); - - /* - * Initialize MDDRC - * put MDDRC in CMD mode and - * set the max time between refreshes to 0 during init process - */ - out_be32(&im->mddrc.ddr_sys_config, - mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, - mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, - mddrc_config->ddr_time_config1); - out_be32(&im->mddrc.ddr_time_config2, - mddrc_config->ddr_time_config2); - - /* Initialize DDR with either default or supplied init sequence */ - for (i = 0; i < seq_sz; i++) - out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); - - /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config); - - /* Allow for the DLL to startup before accessing data */ - udelay(10); - - msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE); - /* Fix DDR Local Window for new size */ - out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1); - sync_law(&im->sysconf.ddrlaw.ar); - - return msize; -} diff --git a/arch/powerpc/cpu/mpc512x/ide.c b/arch/powerpc/cpu/mpc512x/ide.c deleted file mode 100644 index dd11306..0000000 --- a/arch/powerpc/cpu/mpc512x/ide.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_IDE_RESET) - -void ide_set_reset (int idereset) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - debug ("ide_set_reset(%d)\n", idereset); - - if (idereset) { - out_be32(&im->pata.pata_ata_control, 0); - } else { - out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B); - } - udelay(100); -} - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* - * Clear the reset bit to reset the interface - * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus - */ - ide_set_reset(1); - - /* Assert the reset bit to enable the interface */ - ide_set_reset(0); - -} - -#define CALC_TIMING(t) (t + period - 1) / period - -int ide_preinit (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - long t; - const struct { - short t0; - short t1; - short t2_8; - short t2_16; - short t2i; - short t4; - short t9; - short tA; - } pio_specs = { - .t0 = 600, - .t1 = 70, - .t2_8 = 290, - .t2_16 = 165, - .t2i = 0, - .t4 = 30, - .t9 = 20, - .tA = 50, - }; - union { - u32 config; - struct { - u8 field1; - u8 field2; - u8 field3; - u8 field4; - }bytes; - } cfg; - - debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n", - (u32)&im->pata); - - /* Set the reset bit to 1 to enable the interface */ - ide_set_reset(0); - - /* Init timings : we use PIO mode 0 timings */ - t = 1000000000 / gd->arch.ips_clk; /* period in ns */ - cfg.bytes.field1 = 3; - cfg.bytes.field2 = 3; - cfg.bytes.field3 = (pio_specs.t1 + t) / t; - cfg.bytes.field4 = (pio_specs.t2_8 + t) / t; - - out_be32(&im->pata.pata_time1, cfg.config); - - cfg.bytes.field1 = (pio_specs.t2_8 + t) / t; - cfg.bytes.field2 = (pio_specs.tA + t) / t + 2; - cfg.bytes.field3 = 1; - cfg.bytes.field4 = (pio_specs.t4 + t) / t; - - out_be32(&im->pata.pata_time2, cfg.config); - - cfg.config = in_be32(&im->pata.pata_time3); - cfg.bytes.field1 = (pio_specs.t9 + t) / t; - - out_be32(&im->pata.pata_time3, cfg.config); - - debug ("PATA preinit complete.\n"); - - return 0; -} - -#endif /* defined(CONFIG_IDE_RESET) */ diff --git a/arch/powerpc/cpu/mpc512x/interrupts.c b/arch/powerpc/cpu/mpc512x/interrupts.c deleted file mode 100644 index 3385aed..0000000 --- a/arch/powerpc/cpu/mpc512x/interrupts.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2000-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2004 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Derived from the MPC83xx code. - */ - -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; - - return 0; -} - -/* - * Install and free an interrupt handler. - */ -void -irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) -{ -} - -void irq_free_handler (int irq) -{ -} - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} diff --git a/arch/powerpc/cpu/mpc512x/iopin.c b/arch/powerpc/cpu/mpc512x/iopin.c deleted file mode 100644 index 0b53c7b..0000000 --- a/arch/powerpc/cpu/mpc512x/iopin.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2008 - * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com - * mpc512x I/O pin/pad initialization for the ADS5121 board - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void iopin_initialize(iopin_t *ioregs_init, int len) -{ - short i, j, p; - u32 *reg; - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - reg = (u32 *)&(im->io_ctrl); - - if (sizeof(ioregs_init) == 0) - return; - - for (i = 0; i < len; i++) { - for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); - p < ioregs_init[i].nr_pins; p++, j++) { - if (ioregs_init[i].bit_or) - setbits_be32(reg + j, ioregs_init[i].val); - else - out_be32 (reg + j, ioregs_init[i].val); - } - } - return; -} - -void iopin_initialize_bits(iopin_t *ioregs_init, int len) -{ - short i, j, p; - u32 *reg, mask; - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - reg = (u32 *)&(im->io_ctrl); - - /* iterate over table entries */ - for (i = 0; i < len; i++) { - /* iterate over pins within a table entry */ - for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); - p < ioregs_init[i].nr_pins; p++, j++) { - if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) { - /* replace all settings at once */ - out_be32(reg + j, ioregs_init[i].val); - } else { - /* - * only replace individual parts, but - * REPLACE them instead of just ORing - * them in and "inheriting" previously - * set bits which we don't want - */ - mask = 0; - if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX) - mask |= IO_PIN_FMUX(3); - - if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD) - mask |= IO_PIN_HOLD(3); - - if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL) - mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1); - - if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG) - mask |= IO_PIN_ST(1); - - if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR) - mask |= IO_PIN_DS(3); - /* - * DON'T do the "mask, then insert" - * in place on the register, it may - * break access to external hardware - * (like boot ROMs) when configuring - * LPB related pins, while the code to - * configure the pin is read from this - * very address region - */ - clrsetbits_be32(reg + j, mask, - ioregs_init[i].val & mask); - } - } - } -} diff --git a/arch/powerpc/cpu/mpc512x/pci.c b/arch/powerpc/cpu/mpc512x/pci.c deleted file mode 100644 index 7ea5df2..0000000 --- a/arch/powerpc/cpu/mpc512x/pci.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2009-2010 DENX Software Engineering - * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE - -static struct pci_controller pci_hose; - - -/************************************************************************** - * pci_init_board() - * - */ -void -pci_init_board(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile law512x_t *pci_law; - volatile pot512x_t *pci_pot; - volatile pcictrl512x_t *pci_ctrl; - u16 reg16; - u32 reg32; - u32 dev; - int i; - struct pci_controller *hose; - - /* Set PCI divider for 33MHz */ - reg32 = in_be32(&im->clk.scfr[0]); - reg32 &= ~(SCFR1_PCI_DIV_MASK); - reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT; - out_be32(&im->clk.scfr[0], reg32); - - clrsetbits_be32(&im->clk.scfr[0], - SCFR1_PCI_DIV_MASK, - SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT - ); - - pci_law = im->sysconf.pcilaw; - pci_pot = im->ios.pot; - pci_ctrl = &im->pci_ctrl; - - hose = &pci_hose; - - /* - * Release PCI RST Output signal - */ - out_be32(&pci_ctrl->gcr, 0); - udelay(2000); - out_be32(&pci_ctrl->gcr, 1); - - /* We need to wait at least a 1sec based on PCI specs */ - for (i = 0; i < 1000; i++) - udelay(1000); - - /* - * Configure PCI Local Access Windows - */ - out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR); - out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M); - - out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR); - out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M); - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - out_be32(&pci_pot[0].potar, - (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK); - out_be32(&pci_pot[0].pobar, - (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK); - out_be32(&pci_pot[0].pocmr, - POCMR_EN | POCMR_PRE | POCMR_CM_256M); - - /* PCI IO space */ - out_be32(&pci_pot[1].potar, - (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK); - out_be32(&pci_pot[1].pobar, - (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK); - out_be32(&pci_pot[1].pocmr, - POCMR_EN | POCMR_IO | POCMR_CM_16M); - - /* PCI mmio - non-prefetch mem space */ - out_be32(&pci_pot[2].potar, - (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK); - out_be32(&pci_pot[2].pobar, - (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK); - out_be32(&pci_pot[2].pocmr, - POCMR_EN | POCMR_CM_256M); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - out_be32(&pci_ctrl[0].pitar1, 0x0); - out_be32(&pci_ctrl[0].pibar1, 0x0); - out_be32(&pci_ctrl[0].piebar1, 0x0); - out_be32(&pci_ctrl[0].piwar1, - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1)); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI_MEM_BASE, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI_MMIO_BASE, - CONFIG_SYS_PCI_MMIO_PHYS, - CONFIG_SYS_PCI_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI_IO_BASE, - CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR + 0x8300), - (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose.first_busno); - tmp[1] = cpu_to_be32(pci_hose.last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } - } -} -#endif /* CONFIG_OF_LIBFDT */ diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c deleted file mode 100644 index ac77ddc..0000000 --- a/arch/powerpc/cpu/mpc512x/serial.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2000 - 2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Based ont the MPC5200 PSC driver. - * Adapted for MPC512x by Jan Wrobel - */ - -/* - * Minimal serial functions needed to use one of the PSC ports - * as serial console interface. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_PSC_CONSOLE) - -static void fifo_init (volatile psc512x_t *psc) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 tfsize, rfsize; - - /* reset Rx & Tx fifo slice */ - out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE); - out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE); - - /* disable Tx & Rx FIFO interrupts */ - out_be32(&psc->rfintmask, 0); - out_be32(&psc->tfintmask, 0); - - switch (((u32)psc & 0xf00) >> 8) { - case 0: - tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16); - rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16); - break; - case 1: - tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16); - rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16); - break; - case 2: - tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16); - rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16); - break; - case 3: - tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16); - rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16); - break; - case 4: - tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16); - rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16); - break; - case 5: - tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16); - rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16); - break; - case 6: - tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16); - rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16); - break; - case 7: - tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16); - rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16); - break; - case 8: - tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16); - rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16); - break; - case 9: - tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16); - rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16); - break; - case 10: - tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16); - rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16); - break; - case 11: - tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16); - rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16); - break; - default: - return; - } - - out_be32(&psc->tfsize, tfsize); - out_be32(&psc->rfsize, rfsize); - - /* enable Tx & Rx FIFO slice */ - out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE); - out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE); - - out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE); - __asm__ volatile ("sync"); -} - -void serial_setbrg_dev(unsigned int idx) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - unsigned long baseclk, div; - unsigned long baudrate; - char buf[16]; - char *br_env; - - baudrate = gd->baudrate; - if (idx != CONFIG_PSC_CONSOLE) { - /* Allows setting baudrate for other serial devices - * on PSCx using environment. If not specified, use - * the same baudrate as for console. - */ - sprintf(buf, "psc%d_baudrate", idx); - br_env = getenv(buf); - if (br_env) - baudrate = simple_strtoul(br_env, NULL, 10); - - debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate); - } - - /* calculate divisor for setting PSC CTUR and CTLR registers */ - baseclk = (gd->arch.ips_clk + 8) / 16; - div = (baseclk + (baudrate / 2)) / baudrate; - - out_8(&psc->ctur, (div >> 8) & 0xff); - out_8(&psc->ctlr, div & 0xff); /* set baudrate */ -} - -int serial_init_dev(unsigned int idx) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - u32 reg; - - reg = in_be32(&im->clk.sccr[0]); - out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx)); - - fifo_init (psc); - - /* set MR register to point to MR1 */ - out_8(&psc->command, PSC_SEL_MODE_REG_1); - - /* disable Tx/Rx */ - out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE); - - /* choose the prescaler by 16 for the Tx/Rx clock generation */ - out_be16(&psc->psc_clock_select, 0xdd00); - - /* switch to UART mode */ - out_be32(&psc->sicr, 0); - - /* mode register points to mr1 */ - /* configure parity, bit length and so on in mode register 1*/ - out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); - /* now, mode register points to mr2 */ - out_8(&psc->mode, PSC_MODE_1_STOPBIT); - - /* set baudrate */ - serial_setbrg_dev(idx); - - /* disable all interrupts */ - out_be16(&psc->psc_imr, 0); - - /* reset and enable Rx/Tx */ - out_8(&psc->command, PSC_RST_RX); - out_8(&psc->command, PSC_RST_TX); - out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE); - - return 0; -} - -int serial_uninit_dev(unsigned int idx) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - u32 reg; - - out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE); - reg = in_be32(&im->clk.sccr[0]); - reg &= ~CLOCK_SCCR1_PSC_EN(idx); - out_be32(&im->clk.sccr[0], reg); - - return 0; -} - -void serial_putc_dev(unsigned int idx, const char c) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - - if (c == '\n') - serial_putc_dev(idx, '\r'); - - /* Wait for last character to go. */ - while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP)) - ; - - out_8(&psc->tfdata_8, c); -} - -void serial_puts_dev(unsigned int idx, const char *s) -{ - while (*s) - serial_putc_dev(idx, *s++); -} - -int serial_getc_dev(unsigned int idx) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - - /* Wait for a character to arrive. */ - while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY) - ; - - return in_8(&psc->rfdata_8); -} - -int serial_tstc_dev(unsigned int idx) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - - return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY); -} - -void serial_setrts_dev(unsigned int idx, int s) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - - if (s) { - /* Assert RTS (become LOW) */ - out_8(&psc->op1, 0x1); - } - else { - /* Negate RTS (become HIGH) */ - out_8(&psc->op0, 0x1); - } -} - -int serial_getcts_dev(unsigned int idx) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; - - return (in_8(&psc->ip) & 0x1) ? 0 : 1; -} -#endif /* CONFIG_PSC_CONSOLE */ - -#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \ - int serial##port##_init(void) \ - { \ - return serial_init_dev(port); \ - } \ - int serial##port##_uninit(void) \ - { \ - return serial_uninit_dev(port); \ - } \ - void serial##port##_setbrg(void) \ - { \ - serial_setbrg_dev(port); \ - } \ - int serial##port##_getc(void) \ - { \ - return serial_getc_dev(port); \ - } \ - int serial##port##_tstc(void) \ - { \ - return serial_tstc_dev(port); \ - } \ - void serial##port##_putc(const char c) \ - { \ - serial_putc_dev(port, c); \ - } \ - void serial##port##_puts(const char *s) \ - { \ - serial_puts_dev(port, s); \ - } - -#define INIT_PSC_SERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = serial##port##_init, \ - .stop = serial##port##_uninit, \ - .setbrg = serial##port##_setbrg, \ - .getc = serial##port##_getc, \ - .tstc = serial##port##_tstc, \ - .putc = serial##port##_putc, \ - .puts = serial##port##_puts, \ -} - -#if defined(CONFIG_SYS_PSC1) -DECLARE_PSC_SERIAL_FUNCTIONS(1); -struct serial_device serial1_device = -INIT_PSC_SERIAL_STRUCTURE(1, "psc1"); -#endif - -#if defined(CONFIG_SYS_PSC3) -DECLARE_PSC_SERIAL_FUNCTIONS(3); -struct serial_device serial3_device = -INIT_PSC_SERIAL_STRUCTURE(3, "psc3"); -#endif - -#if defined(CONFIG_SYS_PSC4) -DECLARE_PSC_SERIAL_FUNCTIONS(4); -struct serial_device serial4_device = -INIT_PSC_SERIAL_STRUCTURE(4, "psc4"); -#endif - -#if defined(CONFIG_SYS_PSC6) -DECLARE_PSC_SERIAL_FUNCTIONS(6); -struct serial_device serial6_device = -INIT_PSC_SERIAL_STRUCTURE(6, "psc6"); -#endif - -__weak struct serial_device *default_serial_console(void) -{ -#if (CONFIG_PSC_CONSOLE == 3) - return &serial3_device; -#elif (CONFIG_PSC_CONSOLE == 6) - return &serial6_device; -#else -#error "invalid CONFIG_PSC_CONSOLE" -#endif -} - -void mpc512x_serial_initialize(void) -{ -#if defined(CONFIG_SYS_PSC1) - serial_register(&serial1_device); -#endif -#if defined(CONFIG_SYS_PSC3) - serial_register(&serial3_device); -#endif -#if defined(CONFIG_SYS_PSC4) - serial_register(&serial4_device); -#endif -#if defined(CONFIG_SYS_PSC6) - serial_register(&serial6_device); -#endif -} - -#include -/* - * Routines for communication with serial devices over PSC - */ -/* Bitfield for initialized PSCs */ -static unsigned int initialized; - -struct stdio_dev *open_port(int num, int baudrate) -{ - struct stdio_dev *port; - char env_var[16]; - char env_val[10]; - char name[7]; - - if (num < 0 || num > 11) - return NULL; - - sprintf(name, "psc%d", num); - port = stdio_get_by_name(name); - if (!port) - return NULL; - - if (!test_bit(num, &initialized)) { - sprintf(env_var, "psc%d_baudrate", num); - sprintf(env_val, "%d", baudrate); - setenv(env_var, env_val); - - if (port->start(port)) - return NULL; - - set_bit(num, &initialized); - } - - return port; -} - -int close_port(int num) -{ - struct stdio_dev *port; - int ret; - char name[7]; - - if (num < 0 || num > 11) - return -1; - - sprintf(name, "psc%d", num); - port = stdio_get_by_name(name); - if (!port) - return -1; - - ret = port->stop(port); - clear_bit(num, &initialized); - - return ret; -} - -int write_port(struct stdio_dev *port, char *buf) -{ - if (!port || !buf) - return -1; - - port->puts(port, buf); - - return 0; -} - -int read_port(struct stdio_dev *port, char *buf, int size) -{ - int cnt = 0; - - if (!port || !buf) - return -1; - - if (!size) - return 0; - - while (port->tstc(port)) { - buf[cnt++] = port->getc(port); - if (cnt > size) - break; - } - - return cnt; -} diff --git a/arch/powerpc/cpu/mpc512x/speed.c b/arch/powerpc/cpu/mpc512x/speed.c deleted file mode 100644 index 95069ca..0000000 --- a/arch/powerpc/cpu/mpc512x/speed.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Based on the MPC83xx code. - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static int spmf_mult[] = { - 68, 1, 12, 16, - 20, 24, 28, 32, - 36, 40, 44, 48, - 52, 56, 60, 64 -}; - -static int cpmf_mult[][2] = { - {0, 1}, {0, 1}, /* 0 and 1 are not valid */ - {1, 1}, {3, 2}, - {2, 1}, {5, 2}, - {3, 1}, {7, 2}, - {0, 1}, {0, 1}, /* and all above 7 are not valid too */ - {0, 1}, {0, 1}, - {0, 1}, {0, 1}, - {0, 1}, {0, 1} -}; - -static int sys_dividors[][2] = { - {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1}, - {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1}, - {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1}, - {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1}, - {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1}, - {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1}, - {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1} -}; - -int get_clocks (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u8 spmf; - u8 cpmf; - u8 sys_div; - u8 ips_div; - u8 pci_div; - u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN; - u32 spll; - u32 sys_clk; - u32 core_clk; - u32 csb_clk; - u32 ips_clk; - u32 pci_clk; - u32 reg; - - reg = in_be32(&im->sysconf.immrbar); - if ((reg & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - reg = in_be32(&im->clk.spmr); - spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT; - spll = ref_clk * spmf_mult[spmf]; - - reg = in_be32(&im->clk.scfr[1]); - sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; - sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; - - csb_clk = sys_clk / 2; - - reg = in_be32(&im->clk.spmr); - cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT; - core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; - - reg = in_be32(&im->clk.scfr[0]); - ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; - if (ips_div != 0) { - ips_clk = csb_clk / ips_div; - } else { - /* in case we cannot get a sane IPS divisor, fail gracefully */ - ips_clk = 0; - } - - reg = in_be32(&im->clk.scfr[0]); - pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT; - if (pci_div != 0) { - pci_clk = csb_clk / pci_div; - } else { - /* in case we cannot get a sane IPS divisor, fail gracefully */ - pci_clk = 333333; - } - - gd->arch.ips_clk = ips_clk; - gd->pci_clk = pci_clk; - gd->arch.csb_clk = csb_clk; - gd->cpu_clk = core_clk; - gd->bus_clk = csb_clk; - return 0; - -} - -/******************************************** - * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) -{ - return gd->arch.csb_clk; -} - -int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - char buf[32]; - - printf("Clock configuration:\n"); - printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk)); - printf(" Coherent System Bus: %-4s MHz\n", - strmhz(buf, gd->arch.csb_clk)); - printf(" IPS Bus: %-4s MHz\n", - strmhz(buf, gd->arch.ips_clk)); - printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk)); - printf(" DDR: %-4s MHz\n", - strmhz(buf, 2 * gd->arch.csb_clk)); - return 0; -} - -U_BOOT_CMD(clocks, 1, 0, do_clocks, - "print clock configuration", - " clocks" -); diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S deleted file mode 100644 index dd3066e..0000000 --- a/arch/powerpc/cpu/mpc512x/start.S +++ /dev/null @@ -1,694 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000-2009 Wolfgang Denk - * Copyright Freescale Semiconductor, Inc. 2004, 2006. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Based on the MPC83xx code. - */ - -/* - * U-Boot - Startup Code for MPC512x based Embedded Boards - */ - -#include -#include -#include - -#define CONFIG_521X 1 /* needed for Linux kernel header files*/ - -#include -#include "asm-offsets.h" - -#include -#include - -#include -#include -#include - -/* - * Floating Point enable, Machine Check and Recoverable Interr. - */ -#undef MSR_KERNEL -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* Macros for manipulating CSx_START/STOP */ -#define START_REG(start) ((start) >> 16) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Magic number and version string - */ - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - -/* - * Vector Table - */ - .text - . = EXC_OFF_SYS_RESET - - .globl _start - /* Start from here after reset/power on */ -_start: - b boot_cold - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, UnknownException) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - -/* Floating Point Unit unavailable exception */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - -/* Decrementer */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - -/* Critical interrupt */ - STD_EXCEPTION(0xa00, Critical, UnknownException) - -/* System Call */ - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - -/* Trace interrupt */ - STD_EXCEPTION(0xd00, Trace, UnknownException) - -/* Performance Monitor interrupt */ - STD_EXCEPTION(0xf00, PerfMon, UnknownException) - -/* Intruction Translation Miss */ - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - -/* Data Load Translation Miss */ - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - -/* Data Store Translation Miss */ - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) - -/* Instruction Address Breakpoint */ - STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException) - -/* System Management interrupt */ - STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 -boot_cold: - /* Save msr contents */ - mfmsr r5 - - /* Set IMMR area to our preferred location */ - lis r4, CONFIG_DEFAULT_IMMR@h - lis r3, CONFIG_SYS_IMMR@h - ori r3, r3, CONFIG_SYS_IMMR@l - stw r3, IMMRBAR(r4) - mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ - - /* Initialise the machine */ - bl cpu_early_init - - /* - * Set up Local Access Windows: - * - * 1) Boot/CS0 (boot FLASH) - * 2) On-chip SRAM (initial stack purposes) - */ - - /* Boot CS/CS0 window range */ - lis r3, CONFIG_SYS_IMMR@h - ori r3, r3, CONFIG_SYS_IMMR@l - - lis r4, START_REG(CONFIG_SYS_FLASH_BASE) - ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE) - stw r4, LPCS0AW(r3) - - /* - * The SRAM window has a fixed size (256K), so only the start address - * is necessary - */ - lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00 - stw r4, SRAMBAR(r3) - - /* - * According to MPC5121e RM, configuring local access windows should - * be followed by a dummy read of the config register that was - * modified last and an isync - */ - lwz r4, SRAMBAR(r3) - isync - - /* - * Set configuration of the Boot/CS0, the SRAM window does not have a - * config register so no params can be set for it - */ - lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h - ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l - - lis r4, CONFIG_SYS_CS0_CFG@h - ori r4, r4, CONFIG_SYS_CS0_CFG@l - stw r4, CS0_CONFIG(r3) - - /* Master enable all CS's */ - lis r4, CS_CTRL_ME@h - ori r4, r4, CS_CTRL_ME@l - stw r4, CS_CTRL(r3) - - lis r4, (CONFIG_SYS_MONITOR_BASE)@h - ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l - addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r5 - blr - -in_flash: - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable & stack humble */ - /*------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - lis r3, CONFIG_SYS_IMMR@h - /* run low-level CPU init code (in Flash) */ - bl cpu_init_f - - /* run 1st part of board init code (in Flash) */ - bl board_init_f - - /* NOTREACHED - board_init_f() does not return */ - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the machine, it expects original MSR contents to be in r5. - */ -cpu_early_init: - /* Initialize machine status; enable machine check interrupt */ - /*-----------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ -#endif - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ - - lis r3, CONFIG_SYS_IMMR@h - -#if defined(CONFIG_WATCHDOG) - /* Initialise the watchdog and reset it */ - /*--------------------------------------*/ - lis r4, CONFIG_SYS_WATCHDOG_VALUE - ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) - stw r4, SWCRR(r3) - - /* reset */ - li r4, 0x556C - sth r4, SWSRR@l(r3) - li r4, 0x0 - ori r4, r4, 0xAA39 - sth r4, SWSRR@l(r3) -#else - /* Disable the watchdog */ - /*----------------------*/ - lwz r4, SWCRR(r3) - /* - * Check to see if it's enabled for disabling: once disabled by s/w - * it's not possible to re-enable it - */ - andi. r4, r4, 0x4 - beq 1f - xor r4, r4, r4 - stw r4, SWCRR(r3) -1: -#endif /* CONFIG_WATCHDOG */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*------------------------------------------------------*/ - lis r3, CONFIG_SYS_HID0_INIT@h - ori r3, r3, CONFIG_SYS_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID0_FINAL@h - ori r3, r3, CONFIG_SYS_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID2@h - ori r3, r3, CONFIG_SYS_HID2@l - SYNC - mtspr HID2, r3 - sync - blr - - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - .globl get_svr -get_svr: - mfspr r3, SVR - blr - -/*-------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) - * + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - la r8,-4(r4) - la r7,-4(r3) - - /* copy */ -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - - addi r0,r5,3 - srwi. r0,r0,2 - mtctr r0 - la r8,-4(r4) - la r7,-4(r3) - - /* and compare */ -20: lwzu r20,4(r8) - lwzu r21,4(r7) - xor. r22, r20, r21 - bne 30f - bdnz 20b - b 4f - - /* compare failed */ -30: li r3, 0 - blr - -2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_Trace - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c deleted file mode 100644 index 9f5bcd7..0000000 --- a/arch/powerpc/cpu/mpc512x/traps.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * (C) Copyright 2000 - 2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Derived from the MPC83xx code. - */ - -/* - * This file handles the architecture-dependent parts of hardware - * exceptions - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern unsigned long search_exception_table(unsigned long); - -/* - * End of addressable memory. This may be less than the actual - * amount of memory on the system if we're unable to keep all - * the memory mapped in. - */ -#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - puts("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - putc('\n'); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *) *sp; - } - putc('\n'); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0, - regs->msr & MSR_IR ? 1 : 0, - regs->msr & MSR_DR ? 1 : 0); - - putc('\n'); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - putc('\n'); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception at pc %lx signal %d", regs->nip, signr); -} - - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup = search_exception_table(regs->nip); - - if (fixup) { - regs->nip = fixup; - return; - } - -#ifdef CONFIG_CMD_KGDB - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - puts("Machine check.\nCaused by (from msr): "); - printf("regs %p ", regs); - switch (regs->msr & 0x00FF0000) { - case (0x80000000 >> 10): - puts("Instruction cache parity signal\n"); - break; - case (0x80000000 >> 11): - puts("Data cache parity signal\n"); - break; - case (0x80000000 >> 12): - puts("Machine check signal\n"); - break; - case (0x80000000 >> 13): - puts("Transfer error ack signal\n"); - break; - case (0x80000000 >> 14): - puts("Data parity signal\n"); - break; - case (0x80000000 >> 15): - puts("Address parity signal\n"); - break; - default: - puts("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#ifdef CONFIG_CMD_KGDB - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ -#ifdef CONFIG_CMD_KGDB - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#ifdef CONFIG_CMD_KGDB - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ -#ifdef CONFIG_CMD_KGDB - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#ifdef CONFIG_CMD_BEDBUG -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip); - show_regs(regs); -#ifdef CONFIG_CMD_BEDBUG - do_bedbug_breakpoint(regs); -#endif -} diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds deleted file mode 100644 index b32f74e..0000000 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2007-2010 DENX Software Engineering. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - .text : - { - arch/powerpc/cpu/mpc512x/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - *(.fixup) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig deleted file mode 100644 index d81bfd2..0000000 --- a/arch/powerpc/cpu/mpc5xx/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -menu "mpc5xx CPU" - depends on 5xx - -config SYS_CPU - default "mpc5xx" - -choice - prompt "Target select" - optional - -config TARGET_PATI - bool "Support PATI" - -endchoice - -source "board/mpl/pati/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc5xx/Makefile b/arch/powerpc/cpu/mpc5xx/Makefile deleted file mode 100644 index 7b8826a..0000000 --- a/arch/powerpc/cpu/mpc5xx/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# File: arch/powerpc/cpu/mpc5xx/Makefile -# -# Discription: Makefile to build mpc5xx cpu configuration. -# Will include top config.mk which itselfs -# uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk -# - -extra-y = start.o -obj-y = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk deleted file mode 100644 index dd2ec37..0000000 --- a/arch/powerpc/cpu/mpc5xx/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mpowerpc -msoft-float diff --git a/arch/powerpc/cpu/mpc5xx/cpu.c b/arch/powerpc/cpu/mpc5xx/cpu.c deleted file mode 100644 index cfcf633..0000000 --- a/arch/powerpc/cpu/mpc5xx/cpu.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cpu.c - * - * Discription: Some cpu specific function for watchdog, - * cpu version test, clock setting ... - * - */ - - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if (defined(CONFIG_MPC555)) -# define ID_STR "MPC555/556" - -/* - * Check version of cpu with Processor Version Register (PVR) - */ -static int check_cpu_version (long clock, uint pvr, uint immr) -{ - char buf[32]; - /* The highest 16 bits should be 0x0002 for a MPC555/556 */ - if ((pvr >> 16) == 0x0002) { - printf (" " ID_STR " Version %x", (pvr >> 16)); - printf (" at %s MHz:", strmhz (buf, clock)); - } else { - printf ("Not supported cpu version"); - return -1; - } - return 0; -} -#endif /* CONFIG_MPC555 */ - - -/* - * Check version of mpc5xx - */ -int checkcpu (void) -{ - ulong clock = gd->cpu_clk; - uint immr = get_immr (0); /* Return full IMMR contents */ - uint pvr = get_pvr (); /* Retrieve PVR register */ - - puts ("CPU: "); - - return check_cpu_version (clock, pvr, immr); -} - -/* - * Called by macro WATCHDOG_RESET - */ -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); - if (re_enable) - enable_interrupts (); -} - -/* - * Will clear software reset - */ -void reset_5xx_watchdog (volatile immap_t * immr) -{ - /* Use the MPC5xx Internal Watchdog */ - immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */ - immr->im_siu_conf.sc_swsr = 0xaa39; -} - -#endif /* CONFIG_WATCHDOG */ - - -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk (void) -{ - volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR; - ulong oscclk, factor; - - if (immr->im_clkrst.car_sccr & SCCR_TBS) { - return (gd->cpu_clk / 16); - } - - factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; - - oscclk = gd->cpu_clk / factor; - - if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { - return (oscclk / 4); - } - return (oscclk / 16); -} - -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - -/* - * Reset board - */ -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ -#if defined(CONFIG_PATI) - volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS; - *addr = 1; -#else - ulong addr; - - /* Interrupts off, enable reset */ - __asm__ volatile (" mtspr 81, %r0 \n\t" - " mfmsr %r3 \n\t" - " rlwinm %r31,%r3,0,25,23\n\t" - " mtmsr %r31 \n\t"); - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*) (void)) addr) (); -#endif /* #if defined(CONFIG_PATI) */ - return 1; -} diff --git a/arch/powerpc/cpu/mpc5xx/cpu_init.c b/arch/powerpc/cpu/mpc5xx/cpu_init.c deleted file mode 100644 index 5bae39f..0000000 --- a/arch/powerpc/cpu/mpc5xx/cpu_init.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cpu_init.c - * - * Discription: Contains initialisation functions to setup - * the cpu properly - * - */ - -#include -#include -#include - -/* - * Setup essential cpu registers to run - */ -void cpu_init_f (volatile immap_t * immr) -{ - volatile memctl5xx_t *memctl = &immr->im_memctl; - ulong reg; - - /* SYPCR - contains watchdog control. This will enable watchdog */ - /* if CONFIG_WATCHDOG is set */ - immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - - /* SIUMCR - contains debug pin configuration */ - immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; - - /* Initialize timebase. Unlock TBSCRK */ - immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; - - /* Full IMB bus speed */ - immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR; - - /* Time base and decrementer will be enables (TBE) */ - /* in timer_init() in time.c called from board_init_f(). */ - - /* Initialize the PIT. Unlock PISCRK */ - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - -#if !defined(CONFIG_PATI) - /* PATI sest PLL in start.S */ - /* PLL (CPU clock) settings */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, - * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF - * field value. - */ -#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) - reg = CONFIG_SYS_PLPRCR; /* reset control bits */ -#else - reg = immr->im_clkrst.car_plprcr; - reg &= PLPRCR_MF_MSK; /* isolate MF field */ - reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ -#endif - immr->im_clkrst.car_plprcr = reg; - -#endif /* !defined(CONFIG_PATI) */ - - /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; - reg |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = reg; - - /* Memory Controller */ - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; - -#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -} - -/* - * Initialize higher level parts of cpu - */ -int cpu_init_r (void) -{ - /* Nothing to do at the moment */ - return (0); -} diff --git a/arch/powerpc/cpu/mpc5xx/interrupts.c b/arch/powerpc/cpu/mpc5xx/interrupts.c deleted file mode 100644 index 35dddf5..0000000 --- a/arch/powerpc/cpu/mpc5xx/interrupts.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2000-2002 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: interrupt.c - * - * Discription: Contains interrupt routines needed by U-Boot - * - */ - -#include -#include -#include -#include - -#if defined(CONFIG_PATI) -/* PATI uses IRQs for PCI doorbell */ -#undef NR_IRQS -#define NR_IRQS 16 -#endif - -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct interrupt_action irq_vecs[NR_IRQS]; - -/* - * Initialise interrupts - */ - -int interrupt_init_cpu (ulong *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int vec; - - /* Decrementer used here for status led */ - *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; - - /* Disable all interrupts */ - immr->im_siu_conf.sc_simask = 0; - for (vec=0; vecim_siu_conf.sc_sivec; - irq = vec >> 26; - v_bit = 0x80000000UL >> irq; - - /* - * Read Interrupt Mask Register and Mask Interrupts - */ - simask = immr->im_siu_conf.sc_simask; - newmask = simask & (~(0xFFFF0000 >> irq)); - immr->im_siu_conf.sc_simask = newmask; - - if (!(irq & 0x1)) { /* External Interrupt ? */ - ulong siel; - - /* - * Read Interrupt Edge/Level Register - */ - siel = immr->im_siu_conf.sc_siel; - - if (siel & v_bit) { /* edge triggered interrupt ? */ - /* - * Rewrite SIPEND Register to clear interrupt - */ - immr->im_siu_conf.sc_sipend = v_bit; - } - } - - if (irq_vecs[irq].handler != NULL) { - irq_vecs[irq].handler (irq_vecs[irq].arg); - } else { - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", - irq, vec); - /* turn off the bogus interrupt to avoid it from now */ - simask &= ~v_bit; - } - /* - * Re-Enable old Interrupt Mask - */ - immr->im_siu_conf.sc_simask = simask; -} - -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, - void *arg) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - /* SIU interrupt */ - if (irq_vecs[vec].handler != NULL) { - printf ("SIU interrupt %d 0x%x\n", - vec, - (uint) handler); - } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; - immr->im_siu_conf.sc_simask |= 1 << (31 - vec); -#if 0 - printf ("Install SIU interrupt for vector %d ==> %p\n", - vec, handler); -#endif -} - -void irq_free_handler (int vec) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - /* SIU interrupt */ -#if 0 - printf ("Free CPM interrupt for vector %d\n", - vec); -#endif - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; -} - -/* - * Timer interrupt - gets called when bit 0 of DEC changes from - * 0. Decrementer is enabled with bit TBE in TBSCR. - */ -void timer_interrupt_cpu (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if 0 - printf ("*** Timer Interrupt *** "); -#endif - /* Reset Timer Status Bit and Timers Interrupt Status */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - __asm__ ("nop"); - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST; - - return; -} - -#if defined(CONFIG_CMD_IRQ) -/******************************************************************************* - * - * irqinfo - print information about IRQs - * - */ -int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int vec; - - printf ("\nInterrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Local functions - */ - -static int ready_to_send(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile short status; - - do { -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - } while ((status & SCI_TDRE) == 0); - return 1; - -} - -/* - * Minimal global serial functions needed to use one of the SCI modules. - */ - -static int mpc5xx_serial_init(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - serial_setbrg(); - -#if defined(CONFIG_5xx_CONS_SCI1) - /* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */ - immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10; - immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE; -#else - immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10; - immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE; -#endif - return 0; -} - -static void mpc5xx_serial_putc(const char c) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* Test for completition */ - if(ready_to_send()) { -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_sc1dr = (short)c; -#else - immr->im_qsmcm.qsmcm_sc2dr = (short)c; -#endif - if(c == '\n') { - if(ready_to_send()); -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_sc1dr = (short)'\r'; -#else - immr->im_qsmcm.qsmcm_sc2dr = (short)'\r'; -#endif - } - } -} - -static int mpc5xx_serial_getc(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile short status; - unsigned char tmp; - - /* New data ? */ - do { -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - } while ((status & SCI_RDRF) == 0); - - /* Read data */ -#if defined(CONFIG_5xx_CONS_SCI1) - tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK); -#else - tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK); -#endif - return tmp; -} - -static int mpc5xx_serial_tstc(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - short status; - - /* New data character ? */ -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - return (status & SCI_RDRF); -} - -static void mpc5xx_serial_setbrg(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - short scxbr; - - /* Set baudrate */ - scxbr = (gd->cpu_clk / (32 * gd->baudrate)); -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK); -#else - immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK); -#endif -} - -static struct serial_device mpc5xx_serial_drv = { - .name = "mpc5xx_serial", - .start = mpc5xx_serial_init, - .stop = NULL, - .setbrg = mpc5xx_serial_setbrg, - .putc = mpc5xx_serial_putc, - .puts = default_serial_puts, - .getc = mpc5xx_serial_getc, - .tstc = mpc5xx_serial_tstc, -}; - -void mpc5xx_serial_initialize(void) -{ - serial_register(&mpc5xx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc5xx_serial_drv; -} diff --git a/arch/powerpc/cpu/mpc5xx/speed.c b/arch/powerpc/cpu/mpc5xx/speed.c deleted file mode 100644 index 24b9026..0000000 --- a/arch/powerpc/cpu/mpc5xx/speed.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: speed.c - * - * Discription: Provides cpu speed calculation - * - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Get cpu and bus clock - */ -int get_clocks (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#ifndef CONFIG_5xx_GCLK_FREQ - uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK); - uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT); - ulong vcoout; - - vcoout = (CONFIG_SYS_OSC_CLK / (divf + 1)) * (mf + 1) * 2; - if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { - gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); - } else { - gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); - } - -#else /* CONFIG_5xx_GCLK_FREQ */ - gd->bus_clk = CONFIG_5xx_GCLK_FREQ; -#endif /* CONFIG_5xx_GCLK_FREQ */ - - if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) { - /* No Bus Divider active */ - gd->bus_clk = gd->cpu_clk; - } else { - /* CLKOUT is GCLK / 2 */ - gd->bus_clk = gd->cpu_clk / 2; - } - return (0); -} diff --git a/arch/powerpc/cpu/mpc5xx/spi.c b/arch/powerpc/cpu/mpc5xx/spi.c deleted file mode 100644 index ef8b55f..0000000 --- a/arch/powerpc/cpu/mpc5xx/spi.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * , - * - * Copyright (c) 2001 Gerd Mennchen - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC5xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - * Ported to MPC5xx - * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch. - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI) - -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ - -void spi_init_f (void) -{ - int i; - - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - - qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */ - qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PQSPAR[00] = 0 reserved - * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3) - * PQSPAR[02] = 0 [0x0000] -> GPIO - * PQSPAR[03] = 0 [0x0000] -> GPIO - * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0) - * PQSPAR[05] = 0 reseved - * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI) - * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO) - * -------------------------------------------- */ - qsmcm->qsmcm_pqspar = 0x3 | (CONFIG_SYS_SPI_CS_USED << 3); - - /* -------------------------------------------- - * DDRQS[00] = 0 reserved - * DDRQS[01] = 1 [0x0040] -> SPICS3 Output - * DDRQS[02] = 0 [0x0000] -> GPIO Output - * DDRQS[03] = 0 [0x0000] -> GPIO Output - * DDRQS[04] = 1 [0x0008] -> SPICS0 Output - * DDRQS[05] = 1 [0x0004] -> SPICLK Output - * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output - * DDRQS[07] = 0 [0x0001] -> SPIMISO Input - * -------------------------------------------- */ - qsmcm->qsmcm_ddrqs = 0x7E; - /* -------------------------------------------- - * Base state for used SPI CS pins, if base = 0 active must be 1 - * PORTQS[00] = 0 reserved - * PORTQS[01] = 0 reserved - * PORTQS[02] = 0 reserved - * PORTQS[03] = 0 reserved - * PORTQS[04] = 0 [0x0000] RxD2 - * PORTQS[05] = 1 [0x0400] TxD2 - * PORTQS[06] = 0 [0x0000] RxD1 - * PORTQS[07] = 1 [0x0100] TxD1 - * PORTQS[08] = 0 reserved - * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output - * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output - * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output - * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output - * PORTQS[13] = 0 [0x0004] -> SPICLK Output - * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output - * PORTQS[15] = 0 [0x0001] -> SPIMISO Input - * -------------------------------------------- */ - qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3); - /* -------------------------------------------- - * Controll Register 0 - * SPCR0[00] = 1 (0x8000) Master - * SPCR0[01] = 0 (0x0000) Wired-Or - * SPCR0[2..5] = (0x2000) Bits per transfer (default 8) - * SPCR0[06] = 0 (0x0000) Normal polarity - * SPCR0[07] = 0 (0x0000) Normal Clock Phase - * SPCR0[08..15] = 14 1.4MHz - */ - qsmcm->qsmcm_spcr0=0xA00E; - /* -------------------------------------------- - * Controll Register 1 - * SPCR1[00] = 0 (0x0000) QSPI enabled - * SPCR1[1..7] = (0x7F00) Delay before Transfer - * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz) - */ - qsmcm->qsmcm_spcr1=0x7F00; - /* -------------------------------------------- - * Controll Register 2 - * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld - * SPCR2[01] = 0 (0x0000) No Wrap around - * SPCR2[02] = 0 (0x0000) Wrap to 0 - * SPCR2[3..7] = (0x0000) End Queue pointer = 0 - * SPCR2[8..10] = 0 (0x0000) reserved - * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0 - */ - qsmcm->qsmcm_spcr2=0x0000; - /* -------------------------------------------- - * Controll Register 3 - * SPCR3[00..04] = 0 (0x0000) reserved - * SPCR3[05] = 0 (0x0000) Feedback disabled - * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled - * SPCR3[07] = 0 (0x0000) Not halted - */ - qsmcm->qsmcm_spcr3=0x00; - /* -------------------------------------------- - * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10 - * SPCR3[08] = 1 (0x80) QSPI finished - * SPCR3[09] = 1 (0x40) Mode Fault Flag - * SPCR3[10] = 1 (0x20) HALTA - * SPCR3[11..15] = 0 (0x0000) Last executed command - */ - qsmcm->qsmcm_spsr=0xE0; - /*------------------------------------------- - * Setup RAM - */ - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * Dummy, all initializations have been done in spi_init_r - * *********************************************************************** */ -void spi_init_r (void) -{ - return; - -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i,dlen; - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - i=0; - qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */ - qsmcm->qsmcm_tranram[i++] = addr[0]; - qsmcm->qsmcm_tranram[i++] = addr[1]; - - for(dlen=0;dlenqsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */ - } - /* transmit it */ - spi_xfer(i+dlen); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */ - qsmcm->qsmcm_tranram[1] = 0; - spi_xfer(2); - if (!(qsmcm->qsmcm_recram[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - return len; -} - -#define TRANSFER_LEN 16 - -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int index,i,newlen; - uchar newaddr[2]; - int curraddr; - - curraddr=(addr[alen-2]<<8)+addr[alen-1]; - i=len; - index=0; - do { - newaddr[1]=(curraddr & 0xff); - newaddr[0]=((curraddr>>8) & 0xff); - if(i>TRANSFER_LEN) { - newlen=TRANSFER_LEN; - i-=TRANSFER_LEN; - } - else { - newlen=i; - i=0; - } - short_spi_write (newaddr, 2, &buffer[index], newlen); - index+=newlen; - curraddr+=newlen; - }while(i); - return (len); -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - i=0; - qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ - qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff; - qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff; - spi_xfer(3 + len); - for(i=0;iqsmcm_recram[i+3]; - } - return len; -} - -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int index,i,newlen; - uchar newaddr[2]; - int curraddr; - - curraddr=(addr[alen-2]<<8)+addr[alen-1]; - i=len; - index=0; - do { - newaddr[1]=(curraddr & 0xff); - newaddr[0]=((curraddr>>8) & 0xff); - if(i>TRANSFER_LEN) { - newlen=TRANSFER_LEN; - i-=TRANSFER_LEN; - } - else { - newlen=i; - i=0; - } - short_spi_read (newaddr, 2, &buffer[index], newlen); - index+=newlen; - curraddr+=newlen; - }while(i); - return (len); -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - int i; - int tm; - ushort status; - immr = (immap_t *) CONFIG_SYS_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - DPRINT (("*** spi_xfer entered count %d***\n",count)); - - /* Set CS for device */ - for(i=0;i<(count-1);i++) - qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - - qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count)); - - qsmcm->qsmcm_spsr=0xE0; /* clear all flags */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - status=qsmcm->qsmcm_spcr1; - if((status & 0x8000)==0) - break; - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */ - printf ("\nspi_xfer: commbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */ - printf ("\n"); -#endif - - return count; -} - -#endif /* CONFIG_SPI */ diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S deleted file mode 100644 index 6b196de..0000000 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ /dev/null @@ -1,541 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000, 2001, 2002 Wolfgang Denk - * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: start.S - * - * Discription: startup code - * - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include - -/* We don't have a MMU. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - mfspr r3, 638 - li r4, CONFIG_SYS_ISB /* Set ISB bit */ - or r3, r3, r4 - mtspr 638, r3 - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize debug port registers */ - /*----------------------------------------------------------------------*/ - xor r0, r0, r0 /* Clear R0 */ - mtspr LCTRL1, r0 /* Initialize debug port regs */ - mtspr LCTRL2, r0 - mtspr COUNTA, r0 - mtspr COUNTB, r0 - -#if defined(CONFIG_PATI) - /* the external flash access on PATI fails if programming the PLL to 40MHz. - * Copy the PLL programming code to the internal RAM and execute it - *----------------------------------------------------------------------*/ - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET - - lis r4, CONFIG_SYS_INIT_RAM_ADDR@h - ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l - mtlr r4 - addis r5,0,0x0 - ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2) - mtctr r5 - addi r3, r3, -4 - addi r4, r4, -4 -0: - lwzu r0,4(r3) - stwu r0,4(r4) - bdnz 0b /* copy loop */ - blrl -#endif - - /* - * Calculate absolute address in FLASH and jump there - *----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - - /* Initialize some SPRs that are hard to access from C */ - /*----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */ - lis r2, CONFIG_SYS_INIT_SP_ADDR@h - ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ - /* Note: R0 is still 0 here */ - stwu r0, -4(r1) /* Clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* - * Disable serialized ifetch and show cycles - * (i.e. set processor to normal mode) for maximum - * performance. - */ - - li r2, 0x0007 - mtspr ICTRL, r2 - - /* Set up debug mode entry */ - - lis r2, CONFIG_SYS_DER@h - ori r2, r2, CONFIG_SYS_DER@l - mtspr DER, r2 - - /* Let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - bl board_init_f /* run 1st part of board init code (from Flash) */ - - /* NOTREACHED - board_init_f() does not return */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* FPU on MPC5xx available. We will use it later. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - - -/* - * unsigned int get_immr (unsigned int mask) - * - * return (mask ? (IMMR & mask) : IMMR); - */ - .globl get_immr -get_immr: - mr r4,r3 /* save mask */ - mfspr r3, IMMR /* IMMR */ - cmpwi 0,r4,0 /* mask != 0 ? */ - beq 4f - and r3,r3,r4 /* IMMR & mask */ -4: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer in SRAM */ - mr r9, r4 /* Save copy of global data pointer in SRAM */ - mr r10, r5 /* Save copy of monitor destination Address in SRAM */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 4f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -4: sync - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - -#if defined(CONFIG_PATI) -/* Program the PLL */ -pll_prog_code_start: - lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h - ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l - lis r3, (0x55ccaa33)@h - ori r3, r3, (0x55ccaa33)@l - stw r3, 0(r4) - lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h - ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l - lis r3, CONFIG_SYS_PLPRCR@h - ori r3, r3, CONFIG_SYS_PLPRCR@l - stw r3, 0(r4) - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - blr -pll_prog_code_end: - nop - blr -#endif diff --git a/arch/powerpc/cpu/mpc5xx/traps.c b/arch/powerpc/cpu/mpc5xx/traps.c deleted file mode 100644 index 6f31d81..0000000 --- a/arch/powerpc/cpu/mpc5xx/traps.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x0001000 - - -/* - * Print stack backtrace - */ -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -/* - * Print current registers - */ -void show_regs(struct pt_regs *regs) -{ - int i; - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -/* - * General exception handler routine - */ -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -/* - * Machine check exception handler routine - */ -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -/* - * Alignment exception handler routine - */ -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -/* - * Program check exception handler routine - */ -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -/* - * Software emulation exception handler routine - */ -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -/* - * Unknown exception handler routine - */ -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -/* - * Debug exception handler routine - */ -void DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds deleted file mode 100644 index 6a53571..0000000 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2001-2010 Wolfgang Denk, DENX Software Engineering, wd@denx.de - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc5xx/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); - . = env_start; - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } -} diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig deleted file mode 100644 index 6ba0dd4..0000000 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ /dev/null @@ -1,90 +0,0 @@ -menu "mpc5xxx CPU" - depends on MPC5xxx - -config SYS_CPU - default "mpc5xxx" - -choice - prompt "Target select" - optional - -config TARGET_A3M071 - bool "Support a3m071" - select SUPPORT_SPL - -config TARGET_A4M072 - bool "Support a4m072" - -config TARGET_CANMB - bool "Support canmb" - -config TARGET_CM5200 - bool "Support cm5200" - -config TARGET_INKA4X0 - bool "Support inka4x0" - -config TARGET_IPEK01 - bool "Support ipek01" - -config TARGET_JUPITER - bool "Support jupiter" - -config TARGET_MOTIONPRO - bool "Support motionpro" - -config TARGET_MUNICES - bool "Support munices" - -config TARGET_V38B - bool "Support v38b" - -config TARGET_O2D - bool "Support O2D" - -config TARGET_O2D300 - bool "Support O2D300" - -config TARGET_O2DNT2 - bool "Support O2DNT2" - -config TARGET_O2I - bool "Support O2I" - -config TARGET_O2MNT - bool "Support O2MNT" - -config TARGET_O3DNT - bool "Support O3DNT" - -config TARGET_DIGSY_MTC - bool "Support digsy_mtc" - imply CMD_IRQ - -config TARGET_PCM030 - bool "Support pcm030" - -config TARGET_CHARON - bool "Support charon" - -config TARGET_TQM5200 - bool "Support TQM5200" - -endchoice - -source "board/a3m071/Kconfig" -source "board/a4m072/Kconfig" -source "board/canmb/Kconfig" -source "board/cm5200/Kconfig" -source "board/ifm/o2dnt2/Kconfig" -source "board/inka4x0/Kconfig" -source "board/intercontrol/digsy_mtc/Kconfig" -source "board/ipek01/Kconfig" -source "board/jupiter/Kconfig" -source "board/motionpro/Kconfig" -source "board/munices/Kconfig" -source "board/phytec/pcm030/Kconfig" -source "board/tqc/tqm5200/Kconfig" -source "board/v38b/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile deleted file mode 100644 index 88e3b2e..0000000 --- a/arch/powerpc/cpu/mpc5xxx/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -extra-y += traps.o -obj-y += io.o -obj-y += firmware_sc_task_bestcomm.impl.o -obj-y += cpu.o -obj-y += cpu_init.o -obj-y += ide.o -obj-y += interrupts.o -obj-y += loadtask.o -obj-y += pci_mpc5200.o -obj-y += serial.o -obj-y += speed.o -obj-$(CONFIG_CMD_USB) += usb_ohci.o -obj-$(CONFIG_CMD_USB) += usb.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl_boot.o -endif diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk deleted file mode 100644 index bcff214..0000000 --- a/arch/powerpc/cpu/mpc5xxx/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c deleted file mode 100644 index 84fabbd..0000000 --- a/arch/powerpc/cpu/mpc5xxx/cpu.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for the MPC5xxx CPUs - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - -#if defined(CONFIG_OF_IDE_FIXUP) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int checkcpu (void) -{ - ulong clock = gd->cpu_clk; - char buf[32]; - uint svr, pvr; - - puts ("CPU: "); - - svr = get_svr(); - pvr = get_pvr(); - - switch (pvr) { - case PVR_5200: - printf("MPC5200"); - break; - case PVR_5200B: - printf("MPC5200B"); - break; - default: - printf("Unknown MPC5xxx"); - break; - } - - printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), - PVR_MAJ(pvr), PVR_MIN(pvr)); - printf (" at %s MHz\n", strmhz (buf, clock)); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr; - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* Charge the watchdog timer */ - *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f; - *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */ - while(1); - - return 1; - -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_OF_BOARD_SETUP -void ft_cpu_setup(void *blob, bd_t *bd) -{ - int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4; - char * cpu_path = "/cpus/" OF_CPU; -#ifdef CONFIG_MPC5xxx_FEC - uchar enetaddr[6]; - char * eth_path = "/" OF_SOC "/ethernet@3000"; -#endif - - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", - bd->bi_busfreq*div, 1); -#ifdef CONFIG_MPC5xxx_FEC - eth_getenv_enetaddr("ethaddr", enetaddr); - do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); - do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); -#endif -#ifdef CONFIG_OF_IDE_FIXUP - if (!ide_device_present(0)) { - /* NO CF card detected -> delete ata node in DTS */ - int nodeoffset = 0; - char nodename[] = "/soc5200@f0000000/ata@3a00"; - - nodeoffset = fdt_path_offset(blob, nodename); - if (nodeoffset >= 0) { - fdt_del_node(blob, nodeoffset); - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror(nodeoffset)); - } - } - -#endif /* CONFIG_OF_IDE_FIXUP */ - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#ifdef CONFIG_MPC5xxx_FEC -/* Default initializations for FEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -int cpu_eth_init(bd_t *bis) -{ - return mpc5xxx_fec_initialize(bis); -} -#endif - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - reset_5xxx_watchdog(); - if (re_enable) enable_interrupts(); -} - -void reset_5xxx_watchdog(void) -{ - volatile struct mpc5xxx_gpt *gpt0 = - (struct mpc5xxx_gpt *) MPC5XXX_GPT; - - /* Trigger TIMER_0 by writing A5 to OCPW */ - clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000); -} -#endif /* CONFIG_WATCHDOG */ diff --git a/arch/powerpc/cpu/mpc5xxx/cpu_init.c b/arch/powerpc/cpu/mpc5xxx/cpu_init.c deleted file mode 100644 index f9b57ba..0000000 --- a/arch/powerpc/cpu/mpc5xxx/cpu_init.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers. - */ -void cpu_init_f (void) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - volatile struct mpc5xxx_lpb *lpb = - (struct mpc5xxx_lpb *) MPC5XXX_LPB; - volatile struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - volatile struct mpc5xxx_xlb *xlb = - (struct mpc5xxx_xlb *) MPC5XXX_XLBARB; -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *) MPC5XXX_CDM; -#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ -#if defined(CONFIG_WATCHDOG) - volatile struct mpc5xxx_gpt *gpt0 = - (struct mpc5xxx_gpt *) MPC5XXX_GPT; -#endif /* CONFIG_WATCHDOG */ - unsigned long addecr = (1 << 25); /* Boot_CS */ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* - * Memory Controller: configure chip selects and enable them - */ -#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE) - out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START)); - out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START, - CONFIG_SYS_BOOTCS_SIZE)); -#endif -#if defined(CONFIG_SYS_BOOTCS_CFG) - out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG); -#endif - -#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) - out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START)); - out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START, - CONFIG_SYS_CS0_SIZE)); - /* CS0 and BOOT_CS cannot be enabled at once. */ - /* addecr |= (1 << 16); */ -#endif -#if defined(CONFIG_SYS_CS0_CFG) - out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG); -#endif - -#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) - out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START)); - out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START, - CONFIG_SYS_CS1_SIZE)); - addecr |= (1 << 17); -#endif -#if defined(CONFIG_SYS_CS1_CFG) - out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG); -#endif - -#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE) - out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START)); - out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START, - CONFIG_SYS_CS2_SIZE)); - addecr |= (1 << 18); -#endif -#if defined(CONFIG_SYS_CS2_CFG) - out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG); -#endif - -#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) - out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START)); - out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START, - CONFIG_SYS_CS3_SIZE)); - addecr |= (1 << 19); -#endif -#if defined(CONFIG_SYS_CS3_CFG) - out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG); -#endif - -#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) - out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START)); - out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START, - CONFIG_SYS_CS4_SIZE)); - addecr |= (1 << 20); -#endif -#if defined(CONFIG_SYS_CS4_CFG) - out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG); -#endif - -#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) - out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START)); - out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START, - CONFIG_SYS_CS5_SIZE)); - addecr |= (1 << 21); -#endif -#if defined(CONFIG_SYS_CS5_CFG) - out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG); -#endif - - addecr |= 1; -#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) - out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START)); - out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START, - CONFIG_SYS_CS6_SIZE)); - addecr |= (1 << 26); -#endif -#if defined(CONFIG_SYS_CS6_CFG) - out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG); -#endif - -#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) - out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START)); - out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START, - CONFIG_SYS_CS7_SIZE)); - addecr |= (1 << 27); -#endif -#if defined(CONFIG_SYS_CS7_CFG) - out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG); -#endif - -#if defined(CONFIG_SYS_CS_BURST) - out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST); -#endif -#if defined(CONFIG_SYS_CS_DEADCYCLE) - out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE); -#endif - - /* Enable chip selects */ - out_be32(&mm->ipbi_ws_ctrl, addecr); - out_be32(&lpb->cs_ctrl, (1 << 24)); - - /* Setup pin multiplexing */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); -#endif - - /* Setup gpios */ -#if defined(CONFIG_SYS_GPIO_DATADIR) - out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR); -#endif -#if defined(CONFIG_SYS_GPIO_OPENDRAIN) - out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN); -#endif -#if defined(CONFIG_SYS_GPIO_DATAVALUE) - out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE); -#endif -#if defined(CONFIG_SYS_GPIO_ENABLE) - out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE); -#endif - - /* enable timebase */ - setbits_be32(&xlb->config, (1 << 13)); - - /* Enable snooping for RAM */ - setbits_be32(&xlb->config, (1 << 15)); - out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d); - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) - /* Motorola reports IPB should better run at 133 MHz. */ - setbits_be32(&mm->ipbi_ws_ctrl, 1); - /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ - addecr = in_be32(&cdm->cfg); - addecr &= ~0x103; -# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) - /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ - addecr |= 0x01; -# else - /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ - addecr |= 0x02; -# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ - out_be32(&cdm->cfg, addecr); -#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ - /* Configure the XLB Arbiter */ - out_be32(&xlb->master_pri_enable, 0xff); - out_be32(&xlb->master_priority, 0x11111111); - -#if defined(CONFIG_SYS_XLB_PIPELINING) - /* Enable piplining */ - clrbits_be32(&xlb->config, (1 << 31)); -#endif - -#if defined(CONFIG_WATCHDOG) - /* Charge the watchdog timer - prescaler = 64k, count = 64k*/ - out_be32(&gpt0->cir, 0x0000ffff); - out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */ - - reset_5xxx_watchdog(); -#endif /* CONFIG_WATCHDOG */ -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - volatile struct mpc5xxx_intr *intr = - (struct mpc5xxx_intr *) MPC5XXX_ICTL; - - /* mask all interrupts */ - out_be32(&intr->per_mask, 0xffffff00); - setbits_be32(&intr->main_mask, 0x0001ffff); - clrbits_be32(&intr->ctrl, 0x00000f00); - /* route critical ints to normal ints */ - setbits_be32(&intr->ctrl, 0x00000001); - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) - /* load FEC microcode */ - loadtask(0, 2); -#endif - - return (0); -} diff --git a/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S deleted file mode 100644 index 00c2312..0000000 --- a/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MPC5200 CPU. - */ - -#include - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.align 9 -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long CONFIG_SYS_MBAR -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long CONFIG_SYS_MBAR - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010cf04c /* 0020: DRD2B1: var4 = EU3(); EU3(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf04e /* 0030: DRD2B1: var6 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020cf04f /* 0038: DRD2B1: var8 = EU3(); EU3(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04c /* 00A0: DRD2B1: idx0 = EU3(); EU3(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80024800 /* 0000: LCDEXT: idx0 = 0xf0008800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024cf04d /* 0020: DRD2B1: var9 = EU3(); EU3(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010cf04e /* 0034: DRD2B1: var4 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014cf04f /* 003C: DRD2B1: var5 = EU3(); EU3(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028cf050 /* 0044: DRD2B1: var10 = EU3(); EU3(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf051 /* 004C: DRD2B1: var6 = EU3(); EU3(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01ccf0a1 /* 0058: DRD2B1: var7 = EU3(); EU3(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000001 /* 0088: DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */ -.long 0x0c4cfc4d /* 008C: DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04d /* 00CC: DRD2B1: idx0 = EU3(); EU3(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 128, 0x0 - - -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 128, 0x0 diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c deleted file mode 100644 index d1f4349..0000000 --- a/arch/powerpc/cpu/mpc5xxx/ide.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2004 - * Pierre AUBERT, Staubli Faverges, - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Init is derived from Linux code. - */ -#include - -#if defined(CONFIG_IDE) -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define CALC_TIMING(t) (t + period - 1) / period - -#ifdef CONFIG_IDE_RESET -extern void init_ide_reset (void); -#endif - -int ide_preinit (void) -{ - long period, t0, t1, t2_8, t2_16, t4, ta; - vu_long reg; - struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA; - - reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG; -#if defined(CONFIG_SYS_ATA_CS_ON_I2C2) - /* ATA cs0/1 on i2c2 clk/io */ - reg = (reg & ~0x03000000ul) | 0x02000000ul; -#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01) - /* ATA cs0/1 on Timer 0/1 */ - reg = (reg & ~0x03000000ul) | 0x03000000ul; -#else - /* ATA cs0/1 on Local Plus cs4/5 */ - reg = (reg & ~0x03000000ul) | 0x01000000ul; -#endif /* CONFIG_TOTAL5200 */ - *(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg; - - /* All sample codes do that... */ - *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; - - /* Configure and reset host */ - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | - MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; - udelay (10); - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; - - /* Disable prefetch on Commbus */ - psdma->PtdCntrl |= 1; - - /* Init timings : we use PIO mode 0 timings */ - period = 1000000000 / gd->arch.ipb_clk; /* period in ns */ - - t0 = CALC_TIMING (600); - t2_8 = CALC_TIMING (290); - t2_16 = CALC_TIMING (165); - reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8); - *(vu_long *) MPC5XXX_ATA_PIO1 = reg; - - t4 = CALC_TIMING (30); - t1 = CALC_TIMING (70); - ta = CALC_TIMING (35); - reg = (t4 << 24) | (t1 << 16) | (ta << 8); - - *(vu_long *) MPC5XXX_ATA_PIO2 = reg; - -#ifdef CONFIG_IDE_RESET - init_ide_reset (); -#endif /* CONFIG_IDE_RESET */ - - return (0); -} -#endif diff --git a/arch/powerpc/cpu/mpc5xxx/interrupts.c b/arch/powerpc/cpu/mpc5xxx/interrupts.c deleted file mode 100644 index 9121fa0..0000000 --- a/arch/powerpc/cpu/mpc5xxx/interrupts.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * (C) Copyright 2006 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de - * - * (C) Copyright -2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the - * Linux 2.6 source with the following copyright. - * - * Based on (well, mostly copied from) the code from the 2.4 kernel by - * Dale Farnsworth and Kent Borg. - * - * Copyright (C) 2004 Sylvain Munaut - * Copyright (C) 2003 Montavista Software, Inc - */ - -#include -#include -#include -#include - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -static struct irq_action irq_handlers[NR_IRQS]; - -static struct mpc5xxx_intr *intr; -static struct mpc5xxx_sdma *sdma; - -static void mpc5xxx_ic_disable(unsigned int irq) -{ - u32 val; - - if (irq == MPC5XXX_IRQ0) { - val = in_be32(&intr->ctrl); - val &= ~(1 << 11); - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_IRQ1) { - BUG(); - } else if (irq <= MPC5XXX_IRQ3) { - val = in_be32(&intr->ctrl); - val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1))); - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { - val = in_be32(&intr->main_mask); - val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)); - out_be32(&intr->main_mask, val); - } else if (irq < MPC5XXX_PERP_IRQ_BASE) { - val = in_be32(&sdma->IntMask); - val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE); - out_be32(&sdma->IntMask, val); - } else { - val = in_be32(&intr->per_mask); - val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)); - out_be32(&intr->per_mask, val); - } -} - -static void mpc5xxx_ic_enable(unsigned int irq) -{ - u32 val; - - if (irq == MPC5XXX_IRQ0) { - val = in_be32(&intr->ctrl); - val |= 1 << 11; - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_IRQ1) { - BUG(); - } else if (irq <= MPC5XXX_IRQ3) { - val = in_be32(&intr->ctrl); - val |= 1 << (10 - (irq - MPC5XXX_IRQ1)); - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { - val = in_be32(&intr->main_mask); - val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE))); - out_be32(&intr->main_mask, val); - } else if (irq < MPC5XXX_PERP_IRQ_BASE) { - val = in_be32(&sdma->IntMask); - val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); - out_be32(&sdma->IntMask, val); - } else { - val = in_be32(&intr->per_mask); - val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE))); - out_be32(&intr->per_mask, val); - } -} - -static void mpc5xxx_ic_ack(unsigned int irq) -{ - u32 val; - - /* - * Only some irqs are reset here, others in interrupting hardware. - */ - - switch (irq) { - case MPC5XXX_IRQ0: - val = in_be32(&intr->ctrl); - val |= 0x08000000; - out_be32(&intr->ctrl, val); - break; - case MPC5XXX_CCS_IRQ: - val = in_be32(&intr->enc_status); - val |= 0x00000400; - out_be32(&intr->enc_status, val); - break; - case MPC5XXX_IRQ1: - val = in_be32(&intr->ctrl); - val |= 0x04000000; - out_be32(&intr->ctrl, val); - break; - case MPC5XXX_IRQ2: - val = in_be32(&intr->ctrl); - val |= 0x02000000; - out_be32(&intr->ctrl, val); - break; - case MPC5XXX_IRQ3: - val = in_be32(&intr->ctrl); - val |= 0x01000000; - out_be32(&intr->ctrl, val); - break; - default: - if (irq >= MPC5XXX_SDMA_IRQ_BASE - && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) { - out_be32(&sdma->IntPend, - 1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); - } - break; - } -} - -static void mpc5xxx_ic_disable_and_ack(unsigned int irq) -{ - mpc5xxx_ic_disable(irq); - mpc5xxx_ic_ack(irq); -} - -static void mpc5xxx_ic_end(unsigned int irq) -{ - mpc5xxx_ic_enable(irq); -} - -void mpc5xxx_init_irq(void) -{ - u32 intr_ctrl; - - /* Remap the necessary zones */ - intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL); - sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA); - - /* Disable all interrupt sources. */ - out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ - out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ - out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ - out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ - intr_ctrl = in_be32(&intr->ctrl); - intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ - 0x00ff0000 | /* IRQ 0-3 level sensitive low active */ - 0x00001000 | /* MEE master external enable */ - 0x00000000 | /* 0 means disable IRQ 0-3 */ - 0x00000001; /* CEb route critical normally */ - out_be32(&intr->ctrl, intr_ctrl); - - /* Zero a bunch of the priority settings. */ - out_be32(&intr->per_pri1, 0); - out_be32(&intr->per_pri2, 0); - out_be32(&intr->per_pri3, 0); - out_be32(&intr->main_pri1, 0); - out_be32(&intr->main_pri2, 0); -} - -int mpc5xxx_get_irq(struct pt_regs *regs) -{ - u32 status; - int irq = -1; - - status = in_be32(&intr->enc_status); - - if (status & 0x00000400) { /* critical */ - irq = (status >> 8) & 0x3; - if (irq == 2) /* high priority peripheral */ - goto peripheral; - irq += MPC5XXX_CRIT_IRQ_BASE; - } else if (status & 0x00200000) { /* main */ - irq = (status >> 16) & 0x1f; - if (irq == 4) /* low priority peripheral */ - goto peripheral; - irq += MPC5XXX_MAIN_IRQ_BASE; - } else if (status & 0x20000000) { /* peripheral */ - peripheral: - irq = (status >> 24) & 0x1f; - if (irq == 0) { /* bestcomm */ - status = in_be32(&sdma->IntPend); - irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1; - } else - irq += MPC5XXX_PERP_IRQ_BASE; - } - - return irq; -} - -/****************************************************************************/ - -int interrupt_init_cpu(ulong * decrementer_count) -{ - *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; - - mpc5xxx_init_irq(); - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt(struct pt_regs *regs) -{ - int irq, unmask = 1; - - irq = mpc5xxx_get_irq(regs); - - mpc5xxx_ic_disable_and_ack(irq); - - enable_interrupts(); - - if (irq_handlers[irq].handler != NULL) - (*irq_handlers[irq].handler) (irq_handlers[irq].arg); - else { - printf("\nBogus External Interrupt IRQ %d\n", irq); - /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ - unmask = 0; - } - - if (unmask) - mpc5xxx_ic_end(irq); -} - -void timer_interrupt_cpu(struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf("irq_install_handler: bad irq number %d\n", irq); - return; - } - - if (irq_handlers[irq].handler != NULL) - printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, (ulong) irq_handlers[irq].handler); - - irq_handlers[irq].handler = handler; - irq_handlers[irq].arg = arg; - - mpc5xxx_ic_enable(irq); -} - -void irq_free_handler(int irq) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf("irq_free_handler: bad irq number %d\n", irq); - return; - } - - mpc5xxx_ic_disable(irq); - - irq_handlers[irq].handler = NULL; - irq_handlers[irq].arg = NULL; -} - -/****************************************************************************/ - -#if defined(CONFIG_CMD_IRQ) -void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) -{ - int irq, re_enable; - u32 intr_ctrl; - char *irq_config[] = { "level sensitive, active high", - "edge sensitive, rising active edge", - "edge sensitive, falling active edge", - "level sensitive, active low" - }; - - re_enable = disable_interrupts(); - - intr_ctrl = in_be32(&intr->ctrl); - printf("Interrupt configuration:\n"); - - for (irq = 0; irq <= 3; irq++) { - printf("IRQ%d: %s\n", irq, - irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]); - } - - puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n"); - - for (irq = 0; irq < NR_IRQS; irq++) - if (irq_handlers[irq].handler != NULL) - printf("%02d %08lx %08lx %ld\n", irq, - (ulong) irq_handlers[irq].handler, - (ulong) irq_handlers[irq].arg, - irq_handlers[irq].count); - - if (re_enable) - enable_interrupts(); -} -#endif diff --git a/arch/powerpc/cpu/mpc5xxx/io.S b/arch/powerpc/cpu/mpc5xxx/io.S deleted file mode 100644 index 32641ed..0000000 --- a/arch/powerpc/cpu/mpc5xxx/io.S +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * Copyright (C) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/arch/powerpc/cpu/mpc5xxx/loadtask.c b/arch/powerpc/cpu/mpc5xxx/loadtask.c deleted file mode 100644 index 47e7b59..0000000 --- a/arch/powerpc/cpu/mpc5xxx/loadtask.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - */ - -#include -#include - -/* BestComm/SmartComm microcode */ -extern int taskTable; - -void loadtask(int basetask, int tasks) -{ - int *sram = (int *)MPC5XXX_SRAM; - int *task_org = &taskTable; - unsigned int start, offset, end; - int i; - -#ifdef DEBUG - printf("basetask = %d, tasks = %d\n", basetask, tasks); - printf("task_org = 0x%08x\n", (unsigned int)task_org); -#endif - - /* setup TaskBAR register */ - *(vu_long *)MPC5XXX_SDMA = MPC5XXX_SRAM; - - /* relocate task table entries */ - offset = (unsigned int)sram; - for (i = basetask; i < basetask + tasks; i++) { - sram[i * 8 + 0] = task_org[i * 8 + 0] + offset; - sram[i * 8 + 1] = task_org[i * 8 + 1] + offset; - sram[i * 8 + 2] = task_org[i * 8 + 2] + offset; - sram[i * 8 + 3] = task_org[i * 8 + 3] + offset; - sram[i * 8 + 4] = task_org[i * 8 + 4]; - sram[i * 8 + 5] = task_org[i * 8 + 5]; - sram[i * 8 + 6] = task_org[i * 8 + 6] + offset; - sram[i * 8 + 7] = task_org[i * 8 + 7]; - } - - /* relocate task descriptors */ - start = (sram[basetask * 8] - (unsigned int)sram); - end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int)sram); - -#ifdef DEBUG - printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end); -#endif - - start /= 4; - end /= 4; - for (i = start; i <= end; i++) { - sram[i] = task_org[i]; - } - - /* relocate variables */ - start = (sram[basetask * 8 + 2] - (unsigned int)sram); - end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - (unsigned int)sram); - start /= 4; - end /= 4; - for (i = start; i < end; i++) { - sram[i] = task_org[i]; - } - - /* relocate function decriptors */ - start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int)sram); - end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - (unsigned int)sram); - start /= 4; - end /= 4; - for (i = start; i < end; i++) { - sram[i] = task_org[i]; - } - - asm volatile ("sync"); -} diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c deleted file mode 100644 index 70b7e6e..0000000 --- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#if defined(CONFIG_PCI) - -#include -#include -#include -#include - -/* System RAM mapped over PCI */ -#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) - -/* PCIIWCR bit fields */ -#define IWCR_MEM (0 << 3) -#define IWCR_IO (1 << 3) -#define IWCR_READ (0 << 1) -#define IWCR_READLINE (1 << 1) -#define IWCR_READMULT (2 << 1) -#define IWCR_EN (1 << 0) - -static int mpc5200_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -static int mpc5200_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); - out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -void pci_mpc5xxx_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEMORY_BUS, - CONFIG_PCI_MEMORY_PHYS, - CONFIG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - /* GPIO Multiplexing - enable PCI */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); - - /* Set host bridge as pci master and enable memory decoding */ - *(vu_long *)MPC5XXX_PCI_CMD |= - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - - /* Set maximum latency timer */ - *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); - - /* Set cache line size */ - *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | - (CONFIG_SYS_CACHELINE_SIZE / 4); - - /* Map MBAR to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1; - - /* Map RAM to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); - *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; - - /* Park XLB on PCI */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); - *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); - - /* Disable interrupts from PCI controller */ - *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); - *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); - - /* Set PCI retry counter to 0 = infinite retry. */ - /* The default of 255 is too short for slow devices. */ - *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; - - /* Disable initiator windows */ - *(vu_long *)MPC5XXX_PCI_IWCR = 0; - - /* Map PCI memory to physical space */ - *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | - (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_MEM_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; - - /* Map PCI I/O to physical space */ - *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | - (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_IO_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; - - /* Reset the PCI bus */ - *(vu_long *)MPC5XXX_PCI_GSCR |= 1; - udelay(1000); - *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; - udelay(1000); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - mpc5200_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - mpc5200_write_config_dword); - - udelay(1000); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI */ diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c deleted file mode 100644 index bccdcf7..0000000 --- a/arch/powerpc/cpu/mpc5xxx/serial.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2000 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with - * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the - * Linux/PPC sources (m8260_tty.c had no copyright info in it). - * - * Martin Krause, 8 Jun 2006 - * Added SERIAL_MULTI support - */ - -/* - * Minimal serial functions needed to use one of the PSC ports - * as serial console interface. - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_PSC_CONSOLE) - -#if CONFIG_PSC_CONSOLE == 1 -#define PSC_BASE MPC5XXX_PSC1 -#elif CONFIG_PSC_CONSOLE == 2 -#define PSC_BASE MPC5XXX_PSC2 -#elif CONFIG_PSC_CONSOLE == 3 -#define PSC_BASE MPC5XXX_PSC3 -#elif CONFIG_PSC_CONSOLE == 4 -#define PSC_BASE MPC5XXX_PSC4 -#elif CONFIG_PSC_CONSOLE == 5 -#define PSC_BASE MPC5XXX_PSC5 -#elif CONFIG_PSC_CONSOLE == 6 -#define PSC_BASE MPC5XXX_PSC6 -#else -#error CONFIG_PSC_CONSOLE must be in 1 ... 6 -#endif - -#if defined(CONFIG_PSC_CONSOLE2) - -#if CONFIG_PSC_CONSOLE2 == 1 -#define PSC_BASE2 MPC5XXX_PSC1 -#elif CONFIG_PSC_CONSOLE2 == 2 -#define PSC_BASE2 MPC5XXX_PSC2 -#elif CONFIG_PSC_CONSOLE2 == 3 -#define PSC_BASE2 MPC5XXX_PSC3 -#elif CONFIG_PSC_CONSOLE2 == 4 -#define PSC_BASE2 MPC5XXX_PSC4 -#elif CONFIG_PSC_CONSOLE2 == 5 -#define PSC_BASE2 MPC5XXX_PSC5 -#elif CONFIG_PSC_CONSOLE2 == 6 -#define PSC_BASE2 MPC5XXX_PSC6 -#else -#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6 -#endif - -#endif - -int serial_init_dev (unsigned long dev_base) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - unsigned long baseclk; - int div; - - /* reset PSC */ - psc->command = PSC_SEL_MODE_REG_1; - - /* select clock sources */ - psc->psc_clock_select = 0; - baseclk = (gd->arch.ipb_clk + 16) / 32; - - /* switch to UART mode */ - psc->sicr = 0; - - /* configure parity, bit length and so on */ - psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; - psc->mode = PSC_MODE_ONE_STOP; - - /* set up UART divisor */ - div = (baseclk + (gd->baudrate/2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xff; - psc->ctlr = div & 0xff; - - /* disable all interrupts */ - psc->psc_imr = 0; - - /* reset and enable Rx/Tx */ - psc->command = PSC_RST_RX; - psc->command = PSC_RST_TX; - psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; - - return (0); -} - -void serial_putc_dev (unsigned long dev_base, const char c) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - - if (c == '\n') - serial_putc_dev (dev_base, '\r'); - - /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) - ; - - psc->psc_buffer_8 = c; -} - -void serial_puts_dev (unsigned long dev_base, const char *s) -{ - while (*s) { - serial_putc_dev (dev_base, *s++); - } -} - -int serial_getc_dev (unsigned long dev_base) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - - /* Wait for a character to arrive. */ - while (!(psc->psc_status & PSC_SR_RXRDY)) - ; - - return psc->psc_buffer_8; -} - -int serial_tstc_dev (unsigned long dev_base) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - - return (psc->psc_status & PSC_SR_RXRDY); -} - -void serial_setbrg_dev (unsigned long dev_base) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - unsigned long baseclk, div; - - baseclk = (gd->arch.ipb_clk + 16) / 32; - - /* set up UART divisor */ - div = (baseclk + (gd->baudrate/2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xFF; - psc->ctlr = div & 0xff; -} - -void serial_setrts_dev (unsigned long dev_base, int s) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - - if (s) { - /* Assert RTS (become LOW) */ - psc->op1 = 0x1; - } - else { - /* Negate RTS (become HIGH) */ - psc->op0 = 0x1; - } -} - -int serial_getcts_dev (unsigned long dev_base) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; - - return (psc->ip & 0x1) ? 0 : 1; -} - -int serial0_init(void) -{ - return (serial_init_dev(PSC_BASE)); -} - -void serial0_setbrg (void) -{ - serial_setbrg_dev(PSC_BASE); -} - -void serial0_putc(const char c) -{ - serial_putc_dev(PSC_BASE,c); -} - -void serial0_puts(const char *s) -{ - serial_puts_dev(PSC_BASE, s); -} - -int serial0_getc(void) -{ - return(serial_getc_dev(PSC_BASE)); -} - -int serial0_tstc(void) -{ - return (serial_tstc_dev(PSC_BASE)); -} - -struct serial_device serial0_device = -{ - .name = "serial0", - .start = serial0_init, - .stop = NULL, - .setbrg = serial0_setbrg, - .getc = serial0_getc, - .tstc = serial0_tstc, - .putc = serial0_putc, - .puts = serial0_puts, -}; - -__weak struct serial_device *default_serial_console(void) -{ - return &serial0_device; -} - -#ifdef CONFIG_PSC_CONSOLE2 -int serial1_init(void) -{ - return serial_init_dev(PSC_BASE2); -} - -void serial1_setbrg(void) -{ - serial_setbrg_dev(PSC_BASE2); -} - -void serial1_putc(const char c) -{ - serial_putc_dev(PSC_BASE2, c); -} - -void serial1_puts(const char *s) -{ - serial_puts_dev(PSC_BASE2, s); -} - -int serial1_getc(void) -{ - return serial_getc_dev(PSC_BASE2); -} - -int serial1_tstc(void) -{ - return serial_tstc_dev(PSC_BASE2); -} - -struct serial_device serial1_device = -{ - .name = "serial1", - .start = serial1_init, - .stop = NULL, - .setbrg = serial1_setbrg, - .getc = serial1_getc, - .tstc = serial1_tstc, - .putc = serial1_putc, - .puts = serial1_puts, -}; -#endif /* CONFIG_PSC_CONSOLE2 */ - -#endif /* CONFIG_PSC_CONSOLE */ diff --git a/arch/powerpc/cpu/mpc5xxx/speed.c b/arch/powerpc/cpu/mpc5xxx/speed.c deleted file mode 100644 index b37c4a5..0000000 --- a/arch/powerpc/cpu/mpc5xxx/speed.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* Bus-to-Core Multipliers */ - -static int bus2core[] = { - 3, 2, 2, 2, 4, 4, 5, 9, - 6, 11, 8, 10, 3, 12, 7, 0, - 6, 5, 13, 2, 14, 4, 15, 9, - 0, 11, 8, 10, 16, 12, 7, 0 -}; -/* ------------------------------------------------------------------------- */ - -/* - * - */ - -int get_clocks (void) -{ - ulong val, vco; - -#if !defined(CONFIG_SYS_MPC5XXX_CLKIN) -#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN -#endif - - val = *(vu_long *)MPC5XXX_CDM_PORCFG; - if (val & (1 << 6)) { - vco = CONFIG_SYS_MPC5XXX_CLKIN * 12; - } else { - vco = CONFIG_SYS_MPC5XXX_CLKIN * 16; - } - if (val & (1 << 5)) { - gd->bus_clk = vco / 8; - } else { - gd->bus_clk = vco / 4; - } - gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2; - - val = *(vu_long *)MPC5XXX_CDM_CFG; - if (val & (1 << 8)) { - gd->arch.ipb_clk = gd->bus_clk / 2; - } else { - gd->arch.ipb_clk = gd->bus_clk; - } - switch (val & 3) { - case 0: - gd->pci_clk = gd->arch.ipb_clk; - break; - case 1: - gd->pci_clk = gd->arch.ipb_clk / 2; - break; - default: - gd->pci_clk = gd->bus_clk / 4; - break; - } - - return (0); -} - -int print_cpuinfo(void) -{ - char buf1[32], buf2[32], buf3[32]; - - printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n", - strmhz(buf1, gd->bus_clk), - strmhz(buf2, gd->arch.ipb_clk), - strmhz(buf3, gd->pci_clk) - ); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c deleted file mode 100644 index 2d7f6c4..0000000 --- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2012 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Needed to align size SPL image to a 4-byte length - */ -u32 end_align __attribute__ ((section(".end_align"))); - -/* - * Return selected boot device. On MPC5200 its only NOR flash right now. - */ -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NOR; -} - -/* - * SPL version of board_init_f() - */ -void board_init_f(ulong bootflag) -{ - end_align = (u32)__spl_flash_end; - - /* - * On MPC5200, the initial RAM (and gd) is located in the internal - * SRAM. So we can actually call the preloader console init code - * before calling dram_init(). This makes serial output (printf) - * available very early, even before SDRAM init, which has been - * an U-Boot priciple from day 1. - */ - - /* - * Init global_data pointer. Has to be done before calling - * get_clocks(), as it stores some clock values into gd needed - * later on in the serial driver. - */ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* Clear initial global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - /* - * get_clocks() needs to be called so that the serial driver - * works correctly - */ - get_clocks(); - - /* - * Do rudimental console / serial setup - */ - preloader_console_init(); - - /* - * First we need to initialize the SDRAM, so that the real - * U-Boot or the OS (Linux) can be loaded - */ - dram_init(); - - /* Clear bss */ - memset(__bss_start, '\0', __bss_end - __bss_start); - - /* - * Call board_init_r() (SPL framework version) to load and boot - * real U-Boot or OS - */ - board_init_r(NULL, 0); - /* Does not return!!! */ -} diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S deleted file mode 100644 index b4c5543..0000000 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ /dev/null @@ -1,780 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 - 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * U-Boot - Startup Code for MPC5xxx CPUs - */ -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -#ifndef CONFIG_SPL_BUILD -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT -#endif - -/* - * Version string - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - -/* - * Exception vectors - */ - .text - . = EXC_OFF_SYS_RESET - .globl _start -_start: - -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - /* - * This is the entry of the real U-Boot from a board port - * that supports SPL booting on the MPC5200. We only need - * to call board_init_f() here. Everything else has already - * been done in the SPL u-boot version. - */ - GET_GOT /* initialize GOT access */ - - /* - * The GD (global data) struct needs to get cleared. Lets do - * this by calling memset(). - * This function is called when the platform is build with SPL - * support from the main (full-blown) U-Boot. And the GD needs - * to get cleared (again) so that the following generic - * board support code initializes all variables correctly. - */ - mr r3, r2 /* parameter 1: GD pointer */ - li r4,0 /* parameter 2: value to fill */ - li r5,GD_SIZE /* parameter 3: count */ - bl memset - - li r3, 0 /* parameter 1: bootflag */ - bl board_init_f /* run 1st part of board init code (in Flash)*/ - /* NOTREACHED - board_init_f() does not return */ -#else - mfmsr r5 /* save msr contents */ - - /* Move CSBoot and adjust instruction pointer */ - /*--------------------------------------------------------------*/ - -#if defined(CONFIG_SYS_LOWBOOT) -# if defined(CONFIG_SYS_RAMBOOT) -# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT -# endif /* CONFIG_SYS_RAMBOOT */ - lis r4, CONFIG_SYS_DEFAULT_MBAR@h - lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h - ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l - stw r3, 0x4(r4) /* CS0 start */ - lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l - stw r3, 0x8(r4) /* CS0 stop */ - lis r3, 0x02010000@h - ori r3, r3, 0x02010000@l - stw r3, 0x54(r4) /* CS0 and Boot enable */ - - lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ - ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ - mtlr r3 - blr - -lowboot_reentry: - lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h - ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l - stw r3, 0x4c(r4) /* Boot start */ - lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l - stw r3, 0x50(r4) /* Boot stop */ - lis r3, 0x02000001@h - ori r3, r3, 0x02000001@l - stw r3, 0x54(r4) /* Boot enable, CS0 disable */ -#endif /* CONFIG_SYS_LOWBOOT */ - -#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) - lis r3, CONFIG_SYS_MBAR@h - ori r3, r3, CONFIG_SYS_MBAR@l - /* MBAR is mirrored into the MBAR SPR */ - mtspr MBAR,r3 - rlwinm r3, r3, 16, 16, 31 - lis r4, CONFIG_SYS_DEFAULT_MBAR@h - stw r3, 0(r4) -#endif /* CONFIG_SYS_DEFAULT_MBAR */ - - /* Initialise the MPC5xxx processor core */ - /*--------------------------------------------------------------*/ - - bl init_5xxx_core - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - /* set up stack in on-chip SRAM */ - lis r3, CONFIG_SYS_INIT_RAM_ADDR@h - ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - -#ifndef CONFIG_SPL_BUILD - GET_GOT /* initialize GOT access */ -#endif - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - - li r3, 0 /* parameter 1: bootflag */ - bl board_init_f /* run 1st part of board init code (in Flash)*/ - - /* NOTREACHED - board_init_f() does not return */ -#endif - -#ifndef CONFIG_SPL_BUILD -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi -#endif /* CONFIG_SPL_BUILD */ - -/* - * This code initialises the MPC5xxx processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_5xx_core -init_5xxx_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_HID0_INIT@h - ori r3, r3, CONFIG_SYS_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID0_FINAL@h - ori r3, r3, CONFIG_SYS_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr DBAT4U, r0 - mtspr DBAT4L, r0 - mtspr DBAT5U, r0 - mtspr DBAT5L, r0 - mtspr DBAT6U, r0 - mtspr DBAT6L, r0 - mtspr DBAT7U, r0 - mtspr DBAT7L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - mtspr IBAT4U, r0 - mtspr IBAT4L, r0 - mtspr IBAT5U, r0 - mtspr IBAT5L, r0 - mtspr IBAT6U, r0 - mtspr IBAT6L, r0 - mtspr IBAT7U, r0 - mtspr IBAT7L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_DCE - lis r4, 0 - ori r4, r4, HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_svr -get_svr: - mfspr r3, SVR - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -#ifndef CONFIG_SPL_BUILD -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr - -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/powerpc/cpu/mpc5xxx/traps.c b/arch/powerpc/cpu/mpc5xxx/traps.c deleted file mode 100644 index 5498b7e..0000000 --- a/arch/powerpc/cpu/mpc5xxx/traps.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de) - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - /* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */ - switch( regs->msr & 0x000F0000) - { - case (0x80000000>>12) : - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13) : - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14) : - printf("Data parity signal\n"); - break; - case (0x80000000>>15) : - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds deleted file mode 100644 index 5354172..0000000 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc5xxx/start.o (.text*) - arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds deleted file mode 100644 index 1aa925e..0000000 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY -{ - sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, - LENGTH = CONFIG_SPL_BSS_MAX_SIZE - flash : ORIGIN = CONFIG_SPL_TEXT_BASE, - LENGTH = CONFIG_SYS_SPL_MAX_LEN -} - -OUTPUT_ARCH(powerpc) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - arch/powerpc/cpu/mpc5xxx/start.o (.text) - *(.text*) - } > flash - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash - - . = ALIGN(4); - .end_align : { *(.end_align*) } > flash - __spl_flash_end = .; - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } > sdram -} diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds deleted file mode 100644 index aa80d3d..0000000 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc5xxx/start.o (.text*) - arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(COMMON) - *(.bss*) - *(.sbss*) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/mpc5xxx/usb.c b/arch/powerpc/cpu/mpc5xxx/usb.c deleted file mode 100644 index bdf1484..0000000 --- a/arch/powerpc/cpu/mpc5xxx/usb.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2007 - * Markus Klotzbuecher, DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - -#include - -int usb_cpu_init(void) -{ - /* Set the USB Clock */ - *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; - -#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */ - /* remove all PSC3 USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00; -#else - /* remove all USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; -#endif - /* Activate USB port */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; - - return 0; -} - -int usb_cpu_stop(void) -{ - return 0; -} - -int usb_cpu_init_fail(void) -{ - return 0; -} - -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c deleted file mode 100644 index cf36954..0000000 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ /dev/null @@ -1,1529 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200. - * - * (C) Copyright 2003-2004 - * Gary Jennejohn, DENX Software Engineering - * - * (C) Copyright 2004 - * Pierre Aubert, Staubli Faverges - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include - -#ifdef CONFIG_USB_OHCI - -#include -#include -#include "usb_ohci.h" - -#include - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ -#undef DEBUG -#undef SHOW_INFO -#undef OHCI_FILL_TRACE - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((volatile u32 *)(a))) -#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) - -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -#define ohci_cpu_to_le16(x) (x) -#define ohci_cpu_to_le32(x) (x) - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return ohci_cpu_to_le16 (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | (usb_dev->speed == USB_SPEED_LOW) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = ohci_cpu_to_le32 (info); - td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); - if (data) - td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); - else - td->hwBE = 0; - td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the - USB-toggle bits for resetting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdBE = ohci_cpu_to_le32 (td->hwBE); - tdCBP = ohci_cpu_to_le32 (td->hwCBP); - - - if (!(usb_pipecontrol(lurb_priv->pipe) && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | - (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); - } - td_list->hwNextTD = 0; - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK)) - && (lurb_priv->state != URB_DEL)) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - urb_finished = 1; - } - } - - if (ed->state != ED_NEW) { - edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; - edTailP = ohci_cpu_to_le32 (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -#include - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#endif - if (usb_pipeint(pipe)) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipebulk(pipe)) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - mdelay(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - mdelay (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - ohci->hc_control = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { - ohci->disabled++; - err ("%s device removed!", ohci->slot_name); - return -1; - - } else if ((ints &= readl (®s->intrenable)) == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; - mdelay(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - - /* Set the USB Clock */ - *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; - -#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */ - /* remove all PSC3 USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00; -#else - /* remove all USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; -#endif - /* Activate USB port */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)MPC5XXX_USB; - - gohci.flags = 0; - gohci.slot_name = "mpc5200"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - return -1; - } - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#endif - ohci_inited = 1; - urb_finished = 1; - - return 0; -} - -int usb_lowlevel_stop(int index) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.h b/arch/powerpc/cpu/mpc5xxx/usb_ohci.h deleted file mode 100644 index 629b529..0000000 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute__((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute__((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u16 frame_no; /* current frame number */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute__((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute__((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig deleted file mode 100644 index 47bae55..0000000 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -menu "mpc8260 CPU" - depends on MPC8260 - -config SYS_CPU - default "mpc8260" - -choice - prompt "Target select" - optional - -config TARGET_KM82XX - bool "Support km82xx" - imply CMD_CRAMFS - imply FS_CRAMFS - -endchoice - -source "board/keymile/km82xx/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc8260/Makefile b/arch/powerpc/cpu/mpc8260/Makefile deleted file mode 100644 index 72dd8ab..0000000 --- a/arch/powerpc/cpu/mpc8260/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ - interrupts.o ether_fcc.o commproc.o \ - bedbug_603e.o pci.o spi.o kgdb.o - -obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o diff --git a/arch/powerpc/cpu/mpc8260/bedbug_603e.c b/arch/powerpc/cpu/mpc8260/bedbug_603e.c deleted file mode 100644 index 92f8957..0000000 --- a/arch/powerpc/cpu/mpc8260/bedbug_603e.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Bedbug Functions specific to the MPC603e core - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CMD_BEDBUG) \ - && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) - -#define MAX_BREAK_POINTS 1 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug603e_init __P((void)); -void bedbug603e_do_break __P((cmd_tbl_t*,int,int,char*const[])); -void bedbug603e_break_isr __P((struct pt_regs*)); -int bedbug603e_find_empty __P((void)); -int bedbug603e_set __P((int,unsigned long)); -int bedbug603e_clear __P((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the processor. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug603e_init( void ) -{ - int i; - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug603e_do_break; - bug_ctx.break_isr = bedbug603e_break_isr; - bug_ctx.find_empty = bedbug603e_find_empty; - bug_ctx.set = bedbug603e_set; - bug_ctx.clear = bedbug603e_clear; - - for( i = 1; i <= MAX_BREAK_POINTS; ++i ) - (*bug_ctx.clear)( i ); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show the hardware breakpoint for the 603e. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - long addr; /* Address to break at */ - int which_bp; /* Breakpoint number */ - /* -------------------------------------------------- */ - - if (argc < 2) { - cmd_usage(cmdtp); - return; - } - - /* Turn off a breakpoint */ - - if( strcmp( argv[ 1 ], "off" ) == 0 ) - { - if( bug_ctx.hw_debug_enabled == 0 ) - { - puts ( "No breakpoints enabled\n" ); - return; - } - - which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); - - if( bug_ctx.clear ) - (*bug_ctx.clear)( which_bp ); - - printf( "Breakpoint %d removed\n", which_bp ); - return; - } - - /* Show a list of breakpoints */ - - if( strcmp( argv[ 1 ], "show" ) == 0 ) - { - for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) - { - - addr = GET_IABR(); - - printf( "Breakpoint [%d]: ", which_bp ); - if( (addr & 0x00000002) == 0 ) - puts ( "NOT SET\n" ); - else - disppc( (unsigned char *)(addr & 0xFFFFFFFC), 0, 1, bedbug_puts, F_RADHEX ); - } - return; - } - - /* Set a breakpoint at the address */ - - if(!(( isdigit( argv[ 1 ][ 0 ] )) || - (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) || - (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) { - cmd_usage(cmdtp); - return; - } - - addr = simple_strtoul( argv[ 1 ], NULL, 16 ); - - if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) - { - printf( "Breakpoint [%d]: ", which_bp ); - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - - return; -} /* bedbug603e_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. Enter a mini main loop. Stay in the loop until - * the stopped flag in the debug context is cleared. - * ====================================================================== */ - -void bedbug603e_break_isr( struct pt_regs *regs ) -{ - unsigned long addr; /* Address stopped at */ - /* -------------------------------------------------- */ - - bug_ctx.current_bp = 1; - addr = GET_IABR() & 0xFFFFFFFC; - - bedbug_main_loop( addr, regs ); - return; -} /* bedbug603e_break_isr */ - - - -/* ====================================================================== - * See if the hardware breakpoint is available. - * ====================================================================== */ - -int bedbug603e_find_empty( void ) -{ - /* -------------------------------------------------- */ - - if( (GET_IABR() && 0x00000002) == 0 ) - return 1; - - return 0; -} /* bedbug603e_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the IABR register. - * ====================================================================== */ - -int bedbug603e_set( int which_bp, unsigned long addr ) -{ - /* -------------------------------------------------- */ - - if(( addr & 0x00000003 ) != 0 ) - { - puts ( "Breakpoints must be on a 32 bit boundary\n" ); - return 0; - } - - /* Only look if which_bp == 0, else use which_bp */ - if(( bug_ctx.find_empty ) && ( !which_bp ) && - ( which_bp = (*bug_ctx.find_empty)()) == 0 ) - { - puts ( "All breakpoints in use\n" ); - return 0; - } - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # %d\n", which_bp ); - return 0; - } - - if( ! bug_ctx.hw_debug_enabled ) - { - bug_ctx.hw_debug_enabled = 1; - } - - SET_IABR( addr | 0x00000002 ); - - return which_bp; -} /* bedbug603e_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the IABR register to zero. - * ====================================================================== */ - -int bedbug603e_clear( int which_bp ) -{ - /* -------------------------------------------------- */ - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # (%d)\n", which_bp ); - return -1; - } - - SET_IABR( 0 ); - - return 0; -} /* bedbug603e_clear */ - - -/* ====================================================================== */ -#endif diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c deleted file mode 100644 index ff69881..0000000 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void -m8260_cpm_reset(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile ulong count; - - /* Reclaim the DP memory for our use. - */ - gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; - gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; - - /* - * Reset CPM - */ - immr->im_cpm.cp_cpcr = CPM_CR_RST; - count = 0; - do { /* Spin until command processed */ - __asm__ __volatile__ ("eieio"); - } while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000); -} - -/* Allocate some memory from the dual ported ram. - * To help protocols with object alignment restrictions, we do that - * if they ask. - */ -uint -m8260_cpm_dpalloc(uint size, uint align) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - uint retloc; - uint align_mask, off; - uint savebase; - - align_mask = align - 1; - savebase = gd->arch.dp_alloc_base; - - off = gd->arch.dp_alloc_base & align_mask; - if (off != 0) - gd->arch.dp_alloc_base += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) { - gd->arch.dp_alloc_base = savebase; - panic("m8260_cpm_dpalloc: ran out of dual port ram!"); - } - - retloc = gd->arch.dp_alloc_base; - gd->arch.dp_alloc_base += size; - - memset((void *)&immr->im_dprambase[retloc], 0, size); - - return(retloc); -} - -/* We also own one page of host buffer space for the allocation of - * UART "fifos" and the like. - */ -uint -m8260_cpm_hostalloc(uint size, uint align) -{ - /* the host might not even have RAM yet - just use dual port RAM */ - return (m8260_cpm_dpalloc(size, align)); -} - -/* Set a baud rate generator. This needs lots of work. There are - * eight BRGs, which can be connected to the CPM channels or output - * as clocks. The BRGs are in two different block of internal - * memory mapped space. - * The baud rate clock is the system clock divided by something. - * It was set up long ago during the initial boot phase and is - * is given to us. - * Baud rate clocks are zero-based in the driver code (as that maps - * to port numbers). Documentation uses 1-based numbering. - */ -#define BRG_INT_CLK gd->arch.brg_clk -#define BRG_UART_CLK (BRG_INT_CLK / 16) - -/* This function is used by UARTs, or anything else that uses a 16x - * oversampled clock. - */ -void -m8260_cpm_setbrg(uint brg, uint rate) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *bp; - uint cd = BRG_UART_CLK / rate; - - if ((BRG_UART_CLK % rate) < (rate / 2)) - cd--; - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = (cd << 1) | CPM_BRG_EN; -} - -/* This function is used to set high speed synchronous baud rate - * clocks. - */ -void -m8260_cpm_fastbrg(uint brg, uint rate, int div16) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (div16) - *bp |= CPM_BRG_DIV16; -} - -/* This function is used to set baud rate generators using an external - * clock source and 16x oversampling. - */ - -void -m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile uint *bp; - - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (pinsel == 0) - *bp |= CPM_BRG_EXTC_CLK3_9; - else - *bp |= CPM_BRG_EXTC_CLK5_15; -} diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk deleted file mode 100644 index 6a1b6e3..0000000 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_CPM2 \ - -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c deleted file mode 100644 index 7302b37..0000000 --- a/arch/powerpc/cpu/mpc8260/cpu.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * modified by - * Wolfgang Denk - * - * modified for 8260 by - * Murray Jensen - * - * added 8260 masks by - * Marius Groeger - * - * added HiP7 (824x/827x/8280) processors support by - * Yuli Barcohen - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_GET_CPU_STR_F) -extern int get_cpu_str_f (char *buf); -#endif - -int checkcpu (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - ulong clock = gd->cpu_clk; - uint pvr = get_pvr (); - uint immr, rev, m, k; - char buf[32]; - int ret; - - ret = prt_8260_rsr(); - if (ret) - return ret; - ret = prt_8260_clks(); - if (ret) - return ret; - puts ("CPU: "); - - switch (pvr) { - case PVR_8260: - case PVR_8260_HIP3: - k = 3; - break; - case PVR_8260_HIP4: - k = 4; - break; - case PVR_8260_HIP7R1: - case PVR_8260_HIP7RA: - case PVR_8260_HIP7: - k = 7; - break; - default: - return -1; /* whoops! not an MPC8260 */ - } - rev = pvr & 0xff; - - immr = immap->im_memctl.memc_immr; - if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR) - return -1; /* whoops! someone moved the IMMR */ - -#if defined(CONFIG_GET_CPU_STR_F) - get_cpu_str_f (buf); - printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev); -#else - printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); -#endif - - /* - * the bottom 16 bits of the immr are the Part Number and Mask Number - * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the - * RISC Microcode Revision Number (13-10). - * For the 8260, Motorola doesn't include the Microcode Revision - * in the mask. - */ - m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK); - k = immap->im_dprambase16[PROFF_REVNUM / sizeof(u16)]; - - switch (m) { - case 0x0000: - puts ("0.2 2J24M"); - break; - case 0x0010: - puts ("A.0 K22A"); - break; - case 0x0011: - puts ("A.1 1K22A-XC"); - break; - case 0x0001: - puts ("B.1 1K23A"); - break; - case 0x0021: - puts ("B.2 2K23A-XC"); - break; - case 0x0023: - puts ("B.3 3K23A"); - break; - case 0x0024: - puts ("C.2 6K23A"); - break; - case 0x0060: - puts ("A.0(A) 2K25A"); - break; - case 0x0062: - puts ("B.1 4K25A"); - break; - case 0x0064: - puts ("C.0 5K25A"); - break; - case 0x0A00: - puts ("0.0 0K49M"); - break; - case 0x0A01: - puts ("0.1 1K49M"); - break; - case 0x0A10: - puts ("1.0 1K49M"); - break; - case 0x0C00: - puts ("0.0 0K50M"); - break; - case 0x0C10: - puts ("1.0 1K50M"); - break; - case 0x0D00: - puts ("0.0 0K50M"); - break; - case 0x0D10: - puts ("1.0 1K50M"); - break; - default: - printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); - break; - } - - printf (") at %s MHz\n", strmhz (buf, clock)); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -/* configures a UPM by writing into the UPM RAM array */ -/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */ -/* NOTE: the physical address chosen must not overlap into any other area */ -/* mapped by the memory controller because bank 11 has the lowest priority */ - -void upmconfig (uint upm, uint * table, uint size) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ - uint i; - - /* first set up bank 11 to reference the correct UPM at a dummy address */ - - memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */ - - switch (upm) { - - case UPMA: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA | - BRx_V; - memctl->memc_mamr = MxMR_OP_WARR; - break; - - case UPMB: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB | - BRx_V; - memctl->memc_mbmr = MxMR_OP_WARR; - break; - - case UPMC: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC | - BRx_V; - memctl->memc_mcmr = MxMR_OP_WARR; - break; - - default: - panic ("upmconfig passed invalid UPM number (%u)\n", upm); - break; - - } - - /* - * at this point, the dummy address is set up to access the selected UPM, - * the MAD pointer is zero, and the MxMR OP is set for writing to RAM - * - * now we simply load the mdr with each word and poke the dummy address. - * the MAD is incremented on each access. - */ - - for (i = 0; i < size; i++) { - memctl->memc_mdr = table[i]; - *dummy = 0; - } - - /* now kill bank 11 */ - memctl->memc_br11 = 0; -} - -/* ------------------------------------------------------------------------- */ - -#if !defined(CONFIG_HAVE_OWN_RESET) -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr, addr; - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; - -} -#endif /* CONFIG_HAVE_OWN_RESET */ - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR); - if (re_enable) - enable_interrupts (); -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_BOARD_SETUP -void ft_cpu_setup (void *blob, bd_t *bd) -{ - do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", - "clock-frequency", bd->bi_brgfreq, 1); - - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_ETHER_ON_FCC) - fec_initialize(bis); -#endif -#if defined(CONFIG_ETHER_ON_SCC) - mpc82xx_scc_enet_initialize(bis); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c deleted file mode 100644 index 55130f7..0000000 --- a/arch/powerpc/cpu/mpc8260/cpu_init.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -extern unsigned long board_get_cpu_clk_f (void); -#endif - -static void config_8260_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < 4; portnum++) { - uint pmsk = 0, - ppar = 0, - psor = 0, - pdir = 0, - podr = 0, - pdat = 0; - iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; - iop_conf_t *eiopc = iopc + 32; - uint msk = 1; - - /* - * NOTE: - * index 0 refers to pin 31, - * index 31 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - } - - msk <<= 1; - iopc++; - } - - if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); - uint tpmsk = ~pmsk; - - /* - * the (somewhat confused) paragraph at the - * bottom of page 35-5 warns that there might - * be "unknown behaviour" when programming - * PSORx and PDIRx, if PPARx = 1, so I - * decided this meant I had to disable the - * dedicated function first, and enable it - * last. - */ - iop->ppar &= tpmsk; - iop->psor = (iop->psor & tpmsk) | psor; - iop->podr = (iop->podr & tpmsk) | podr; - iop->pdat = (iop->pdat & tpmsk) | pdat; - iop->pdir = (iop->pdir & tpmsk) | pdir; - iop->ppar |= ppar; - } - } -} - -#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask)) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * immr) -{ - uint sccr; -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - unsigned long cpu_clk; -#endif - volatile memctl8260_t *memctl = &immr->im_memctl; - extern void m8260_cpm_reset (void); - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* RSR - Reset Status Register - clear all status (5-4) */ - gd->arch.reset_status = immr->im_clkrst.car_rsr; - immr->im_clkrst.car_rsr = RSR_ALLBITS; - - /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ - immr->im_clkrst.car_rmr = CONFIG_SYS_RMR; - - /* BCR - Bus Configuration Register (4-25) */ -#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE) - if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010); - } else { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010); - } -#else - immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR; -#endif - - /* SIUMCR - contains debug pin configuration (4-31) */ -#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH) - cpu_clk = board_get_cpu_clk_f (); - if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000); - } else { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000); - } -#else - immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; -#endif - - config_8260_ioports (immr); - - /* initialize time counter status and control register (4-40) */ - immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC; - - /* initialize the PIT (4-42) */ - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - - /* System clock control register (9-8) */ - sccr = immr->im_clkrst.car_sccr & - (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); - immr->im_clkrst.car_sccr = sccr | - (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); - - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ - /* the PS came from the HRCW, don't change it */ - memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK); - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; - memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; - memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM) - memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM; - memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM) - memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM; - memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM) - memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM; - memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM) - memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM; - memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM; -#endif - - m8260_cpm_reset (); -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; - - immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; - - return (0); -} - -/* - * print out the reason for the reset - */ -int prt_8260_rsr (void) -{ - static struct { - ulong mask; - char *desc; - } bits[] = { - { - RSR_JTRS, "JTAG"}, { - RSR_CSRS, "Check Stop"}, { - RSR_SWRS, "Software Watchdog"}, { - RSR_BMRS, "Bus Monitor"}, { - RSR_ESRS, "External Soft"}, { - RSR_EHRS, "External Hard"} - }; - static int n = ARRAY_SIZE(bits); - ulong rsr = gd->arch.reset_status; - int i; - char *sep; - - puts (CPU_ID_STR " Reset Status:"); - - sep = " "; - for (i = 0; i < n; i++) - if (rsr & bits[i].mask) { - printf ("%s%s", sep, bits[i].desc); - sep = ", "; - } - - puts ("\n\n"); - return (0); -} diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c deleted file mode 100644 index 072eb76..0000000 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ /dev/null @@ -1,1155 +0,0 @@ -/* - * MPC8260 FCC Fast Ethernet - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8260 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CONFIG_SYS_CMXFCR_MASK1, - CONFIG_SYS_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CONFIG_SYS_CMXFCR_MASK2, - CONFIG_SYS_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CONFIG_SYS_CMXFCR_MASK3, - CONFIG_SYS_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 -#ifdef __GNUC__ -static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8))); -#else -#error "txbuf must be 64-bit aligned" -#endif - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | - BD_ENET_TX_WRAP); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc); -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, bd_t *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8260_t *cp = &(immr->im_cpm); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ - immr->im_fcc[info->ether_index].fcc_gfmr = - FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ - immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - - /* 28.9 - (6): FDSR: Ethernet Syn */ - immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555; - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialise parameter ram */ - pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - - /* protocol-specific area */ - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_ethaddr() - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */ - pram_ptr->fen_rfthr = 1; - pram_ptr->fen_rfcnt = 1; -#if 0 - printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8): clear out events in FCCE */ - immr->im_fcc[info->ether_index].fcc_fcce = ~0x0; - - /* 28.9 - (9): FCCM: mask all events */ - immr->im_fcc[info->ether_index].fcc_fccm = 0; - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* write GFMR: disable tx/rx */ - immr->im_fcc[info->ether_index].fcc_gfmr &= - ~(FCC_GFMR_ENT | FCC_GFMR_ENR); -} - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d", - ether_fcc_info[i].ether_index + 1); - dev->priv = ðer_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - - return 1; -} - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - -#define ELBT_BUFSZ 1024 /* must be multiple of 32 */ - -#define ELBT_CRCSZ 4 - -#define ELBT_NRXBD 4 /* must be at least 2 */ -#define ELBT_NTXBD 4 - -#define ELBT_MAXRXERR 32 -#define ELBT_MAXTXERR 32 - -#define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */ - -typedef - struct { - uint off; - char *lab; - } -elbt_prdesc; - -typedef - struct { - uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl; - uint badsrc, badtyp, badlen, badbit; - } -elbt_rxeacc; - -static elbt_prdesc rxeacc_descs[] = { - { offsetof(elbt_rxeacc, _l), "Not Last in Frame" }, - { offsetof(elbt_rxeacc, _f), "Not First in Frame" }, - { offsetof(elbt_rxeacc, m), "Address Miss" }, - { offsetof(elbt_rxeacc, bc), "Broadcast Address" }, - { offsetof(elbt_rxeacc, mc), "Multicast Address" }, - { offsetof(elbt_rxeacc, lg), "Frame Length Violation"}, - { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" }, - { offsetof(elbt_rxeacc, sh), "Short Frame" }, - { offsetof(elbt_rxeacc, cr), "CRC Error" }, - { offsetof(elbt_rxeacc, ov), "Overrun" }, - { offsetof(elbt_rxeacc, cl), "Collision" }, - { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" }, - { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" }, - { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" }, - { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" }, -}; -static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs); - -typedef - struct { - uint def, hb, lc, rl, rc, un, csl; - } -elbt_txeacc; - -static elbt_prdesc txeacc_descs[] = { - { offsetof(elbt_txeacc, def), "Defer Indication" }, - { offsetof(elbt_txeacc, hb), "Heartbeat" }, - { offsetof(elbt_txeacc, lc), "Late Collision" }, - { offsetof(elbt_txeacc, rl), "Retransmission Limit" }, - { offsetof(elbt_txeacc, rc), "Retry Count" }, - { offsetof(elbt_txeacc, un), "Underrun" }, - { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" }, -}; -static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs); - -typedef - struct { - uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ]; - uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ]; - cbd_t rxbd[ELBT_NRXBD]; - cbd_t txbd[ELBT_NTXBD]; - enum { Idle, Running, Closing, Closed } state; - int proff, page, sblock; - uint clstime, nsent, ntxerr, nrcvd, nrxerr; - ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR]; - elbt_rxeacc rxeacc; - elbt_txeacc txeacc; - } __attribute__ ((aligned(8))) -elbt_chan; - -static uchar patbytes[ELBT_NTXBD] = { - 0xff, 0xaa, 0x55, 0x00 -}; -static uint patwords[ELBT_NTXBD] = { - 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000 -}; - -#ifdef __GNUC__ -static elbt_chan elbt_chans[3] __attribute__ ((aligned(8))); -#else -#error "elbt_chans must be 64-bit aligned" -#endif - -#define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005) - -static elbt_prdesc epram_descs[] = { - { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" }, - { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" }, - { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" }, - { offsetof(fcc_enet_t, fen_octc), "Octets" }, - { offsetof(fcc_enet_t, fen_colc), "Collisions" }, - { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" }, - { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" }, - { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" }, - { offsetof(fcc_enet_t, fen_frgc), "Fragments" }, - { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" }, - { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" }, - { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"}, -}; -static int epram_ndesc = ARRAY_SIZE(epram_descs); - -/* - * given an elbt_prdesc array and an array of base addresses, print - * each prdesc down the screen with the values fetched from each - * base address across the screen - */ -static void -print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase) -{ - elbt_prdesc *dp = descs, *edp = dp + ndesc; - int i; - - printf ("%32s", ""); - - for (i = 0; i < nbase; i++) - printf (" Channel %d", i); - - putc ('\n'); - - while (dp < edp) { - - printf ("%-32s", dp->lab); - - for (i = 0; i < nbase; i++) { - uint val = *(uint *)(bases[i] + dp->off); - - printf (" %10u", val); - } - - putc ('\n'); - - dp++; - } -} - -/* - * return number of bits that are set in a value; value contains - * nbits (right-justified) bits. - */ -static uint __inline__ -nbs (uint value, uint nbits) -{ - uint cnt = 0; -#if 1 - uint pos = sizeof (uint) * 8; - - __asm__ __volatile__ ("\ - mtctr %2\n\ -1: rlwnm. %2,%1,%4,31,31\n\ - beq 2f\n\ - addi %0,%0,1\n\ -2: subi %4,%4,1\n\ - bdnz 1b" - : "=r"(cnt) - : "r"(value), "r"(nbits), "r"(cnt), "r"(pos) - : "ctr", "cc" ); -#else - uint mask = 1; - - do { - if (value & mask) - cnt++; - mask <<= 1; - } while (--nbits); -#endif - - return (cnt); -} - -static ulong -badbits (uchar *bp, int n, ulong pat) -{ - ulong *lp, cnt = 0; - int nl; - - while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) { - uchar diff; - - diff = *bp++ ^ (uchar)pat; - - if (diff) - cnt += nbs ((ulong)diff, 8); - - n--; - } - - lp = (ulong *)bp; - nl = n / sizeof (ulong); - n -= nl * sizeof (ulong); - - while (nl > 0) { - ulong diff; - - diff = *lp++ ^ pat; - - if (diff) - cnt += nbs (diff, 32); - - nl--; - } - - bp = (uchar *)lp; - - while (n > 0) { - uchar diff; - - diff = *bp++ ^ (uchar)pat; - - if (diff) - cnt += nbs ((ulong)diff, 8); - - n--; - } - - return (cnt); -} - -static inline unsigned short -swap16 (unsigned short x) -{ - return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); -} - -/* broadcast is not an error - we send them like that */ -#define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC) - -void -eth_loopback_test (void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8260_t *cp = &(immr->im_cpm); - int c, nclosed; - ulong runtime, nmsec; - uchar *bases[3]; - - puts ("FCC Ethernet External loopback test\n"); - - eth_getenv_enetaddr("ethaddr", net_ethaddr); - - /* - * global initialisations for all FCC channels - */ - - /* 28.9 - (1-2): ioports have been set up already */ - -#if defined(CONFIG_SACSng) - /* - * Attention: this is board-specific - * 1, FCC2 - */ -# define FCC_START_LOOP 1 -# define FCC_END_LOOP 1 - - /* - * Attention: this is board-specific - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; -#else -#error "eth_loopback_test not supported on your board" -#endif - - puts ("Initialise FCC channels:"); - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - elbt_chan *ecp = &elbt_chans[c]; - volatile fcc_t *fcp = &immr->im_fcc[c]; - volatile fcc_enet_t *fpp; - int i; - ulong addr; - - /* - * initialise channel data - */ - - printf (" %d", c); - - memset ((void *)ecp, 0, sizeof (*ecp)); - - ecp->state = Idle; - - switch (c) { - - case 0: /* FCC1 */ - ecp->proff = PROFF_FCC1; - ecp->page = CPM_CR_FCC1_PAGE; - ecp->sblock = CPM_CR_FCC1_SBLOCK; - break; - - case 1: /* FCC2 */ - ecp->proff = PROFF_FCC2; - ecp->page = CPM_CR_FCC2_PAGE; - ecp->sblock = CPM_CR_FCC2_SBLOCK; - break; - - case 2: /* FCC3 */ - ecp->proff = PROFF_FCC3; - ecp->page = CPM_CR_FCC3_PAGE; - ecp->sblock = CPM_CR_FCC3_SBLOCK; - break; - } - - /* - * set up tx buffers and bds - */ - - for (i = 0; i < ELBT_NTXBD; i++) { - cbd_t *bdp = &ecp->txbd[i]; - uchar *bp = &ecp->txbufs[i][0]; - - bdp->cbd_bufaddr = (uint)bp; - /* room for crc */ - bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ; - bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \ - BD_ENET_TX_LAST | BD_ENET_TX_TC; - - memset((void *)bp, patbytes[i], ELBT_BUFSZ); - net_set_ether(bp, net_bcast_ethaddr, 0x8000); - } - ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * set up rx buffers and bds - */ - - for (i = 0; i < ELBT_NRXBD; i++) { - cbd_t *bdp = &ecp->rxbd[i]; - uchar *bp = &ecp->rxbufs[i][0]; - - bdp->cbd_bufaddr = (uint)bp; - bdp->cbd_datlen = 0; - bdp->cbd_sc = BD_ENET_RX_EMPTY; - - memset ((void *)bp, 0, ELBT_BUFSZ); - } - ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * set up the FCC channel hardware - */ - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ - fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - - /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */ - fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \ - FCC_PSMR_ENCRC | FCC_PSMR_PRO | \ - FCC_PSMR_MON | FCC_PSMR_RSH; - - /* 28.9 - (6): FDSR: Ethernet Syn */ - fcp->fcc_fdsr = 0xD555; - - /* 29.9 - (7): initialise parameter ram */ - fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]); - - /* clear whole struct to make sure all resv fields are zero */ - memset ((void *)fpp, 0, sizeof (fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - addr = CPM_FCC_SPECIAL_BASE + (c * 64); - fpp->fen_genfcc.fcc_riptr = addr; - fpp->fen_genfcc.fcc_tiptr = addr + 32; - - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - * buffers are in 60x bus memory. - */ - fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]); - fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]); - - /* protocol-specific area */ - fpp->fen_cmask = 0xdebb20e3; /* CRC mask */ - fpp->fen_cpres = 0xffffffff; /* CRC preset */ - fpp->fen_retlim = 15; /* Retry limit threshold */ - fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */ - - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We use - * the same address for all channels - */ - fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4]; - fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2]; - fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0]; - - fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */ - /* - * pad pointer. use tiptr since we don't need - * a specific padding char - */ - fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr; - fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */ - fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */ - fpp->fen_rfthr = 1; - fpp->fen_rfcnt = 1; - - /* 28.9 - (8): clear out events in FCCE */ - fcp->fcc_fcce = ~0x0; - - /* 28.9 - (9): FCCM: mask all events */ - fcp->fcc_fccm = 0; - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \ - 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - } - - puts (" done\nStarting test... (Ctrl-C to Finish)\n"); - - /* - * Note: don't want serial output from here until the end of the - * test - the delays would probably stuff things up. - */ - - clear_ctrlc (); - runtime = get_timer (0); - - do { - nclosed = 0; - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - volatile fcc_t *fcp = &immr->im_fcc[c]; - elbt_chan *ecp = &elbt_chans[c]; - int i; - - switch (ecp->state) { - - case Idle: - /* - * set the channel Running ... - */ - - /* 28.9 - (14): enable tx/rx in gfmr */ - fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - - ecp->state = Running; - break; - - case Running: - /* - * (while Running only) check for - * termination of the test - */ - - (void)ctrlc (); - - if (had_ctrlc ()) { - /* - * initiate a "graceful stop transmit" - * on the channel - */ - cp->cp_cpcr = mk_cr_cmd (ecp->page, \ - ecp->sblock, 0x0c, \ - CPM_CR_GRACEFUL_STOP_TX) | \ - CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - ecp->clstime = get_timer (0); - ecp->state = Closing; - } - /* fall through ... */ - - case Closing: - /* - * (while Running or Closing) poll the channel: - * - check for any non-READY tx buffers and - * make them ready - * - check for any non-EMPTY rx buffers and - * check that they were received correctly, - * adjust counters etc, then make empty - */ - - for (i = 0; i < ELBT_NTXBD; i++) { - cbd_t *bdp = &ecp->txbd[i]; - ushort sc = bdp->cbd_sc; - - if ((sc & BD_ENET_TX_READY) != 0) - continue; - - /* - * this frame has finished - * transmitting - */ - ecp->nsent++; - - if (sc & BD_ENET_TX_STATS) { - ulong n; - - /* - * we had an error on - * the transmission - */ - n = ecp->ntxerr++; - if (n < ELBT_MAXTXERR) - ecp->txerrs[n] = sc; - - if (sc & BD_ENET_TX_DEF) - ecp->txeacc.def++; - if (sc & BD_ENET_TX_HB) - ecp->txeacc.hb++; - if (sc & BD_ENET_TX_LC) - ecp->txeacc.lc++; - if (sc & BD_ENET_TX_RL) - ecp->txeacc.rl++; - if (sc & BD_ENET_TX_RCMASK) - ecp->txeacc.rc++; - if (sc & BD_ENET_TX_UN) - ecp->txeacc.un++; - if (sc & BD_ENET_TX_CSL) - ecp->txeacc.csl++; - - bdp->cbd_sc &= \ - ~BD_ENET_TX_STATS; - } - - if (ecp->state == Closing) - ecp->clstime = get_timer (0); - - /* make it ready again */ - bdp->cbd_sc |= BD_ENET_TX_READY; - } - - for (i = 0; i < ELBT_NRXBD; i++) { - cbd_t *bdp = &ecp->rxbd[i]; - ushort sc = bdp->cbd_sc, mask; - - if ((sc & BD_ENET_RX_EMPTY) != 0) - continue; - - /* we have a new frame in this buffer */ - ecp->nrcvd++; - - mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST; - if ((sc & mask) != mask) { - /* somethings wrong here ... */ - if (!(sc & BD_ENET_RX_LAST)) - ecp->rxeacc._l++; - if (!(sc & BD_ENET_RX_FIRST)) - ecp->rxeacc._f++; - } - - if (sc & BD_ENET_RX_ERRS) { - ulong n; - - /* - * we had some sort of error - * on the frame - */ - n = ecp->nrxerr++; - if (n < ELBT_MAXRXERR) - ecp->rxerrs[n] = sc; - - if (sc & BD_ENET_RX_MISS) - ecp->rxeacc.m++; - if (sc & BD_ENET_RX_BC) - ecp->rxeacc.bc++; - if (sc & BD_ENET_RX_MC) - ecp->rxeacc.mc++; - if (sc & BD_ENET_RX_LG) - ecp->rxeacc.lg++; - if (sc & BD_ENET_RX_NO) - ecp->rxeacc.no++; - if (sc & BD_ENET_RX_SH) - ecp->rxeacc.sh++; - if (sc & BD_ENET_RX_CR) - ecp->rxeacc.cr++; - if (sc & BD_ENET_RX_OV) - ecp->rxeacc.ov++; - if (sc & BD_ENET_RX_CL) - ecp->rxeacc.cl++; - - bdp->cbd_sc &= \ - ~BD_ENET_RX_ERRS; - } - else { - ushort datlen = bdp->cbd_datlen; - struct ethernet_hdr *ehp; - ushort prot; - int ours, tb, n, nbytes; - - ehp = (struct ethernet_hdr *) \ - &ecp->rxbufs[i][0]; - - ours = memcmp (ehp->et_src, \ - net_ethaddr, 6); - - prot = swap16 (ehp->et_protlen); - tb = prot & 0x8000; - n = prot & 0x7fff; - - nbytes = ELBT_BUFSZ - - ETHER_HDR_SIZE - - ELBT_CRCSZ; - - /* check the frame is correct */ - if (datlen != ELBT_BUFSZ) - ecp->rxeacc.badlen++; - else if (!ours) - ecp->rxeacc.badsrc++; - else if (!tb || n >= ELBT_NTXBD) - ecp->rxeacc.badtyp++; - else { - ulong patword = \ - patwords[n]; - uint nbb; - - nbb = badbits( - ((uchar *)&ehp) + - ETHER_HDR_SIZE, - nbytes, patword); - - ecp->rxeacc.badbit += \ - nbb; - } - } - - if (ecp->state == Closing) - ecp->clstime = get_timer (0); - - /* make it empty again */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - } - - if (ecp->state != Closing) - break; - - /* - * (while Closing) check to see if - * waited long enough - */ - - if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) { - /* write GFMR: disable tx/rx */ - fcp->fcc_gfmr &= \ - ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - ecp->state = Closed; - } - - break; - - case Closed: - nclosed++; - break; - } - } - - } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1)); - - runtime = get_timer (runtime); - if (runtime <= ELBT_CLSWAIT) { - printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n", - runtime, ELBT_CLSWAIT); - return; - } - nmsec = runtime - ELBT_CLSWAIT; - - printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n", - nmsec, ELBT_CLSWAIT); - - /* - * now print stats - */ - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - elbt_chan *ecp = &elbt_chans[c]; - uint rxpps, txpps, nerr; - - rxpps = (ecp->nrcvd * 1000) / nmsec; - txpps = (ecp->nsent * 1000) / nmsec; - - printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), " - "%d sent (%d pps, %d txerrs)\n\n", c, - ecp->nrcvd, rxpps, ecp->nrxerr, - ecp->nsent, txpps, ecp->ntxerr); - - if ((nerr = ecp->nrxerr) > 0) { - ulong i; - - printf ("\tFirst %d rx errs:", nerr); - for (i = 0; i < nerr; i++) - printf (" %04x", ecp->rxerrs[i]); - putc ('\n'); - } - - if ((nerr = ecp->ntxerr) > 0) { - ulong i; - - printf ("\tFirst %d tx errs:", nerr); - for (i = 0; i < nerr; i++) - printf (" %04x", ecp->txerrs[i]); - putc ('\n'); - } - } - - puts ("Receive Error Counts:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&elbt_chans[c].rxeacc; - print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3); - - puts ("\nTransmit Error Counts:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&elbt_chans[c].txeacc; - print_desc (txeacc_descs, txeacc_ndesc, bases, 3); - - puts ("\nRMON(-like) Counters:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff]; - print_desc (epram_descs, epram_ndesc, bases, 3); -} - -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#endif diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c deleted file mode 100644 index fff8f2b..0000000 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * MPC8260 SCC Ethernet - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright (c) 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * Modified so that it plays nicely when more than one ETHERNET interface - * is in use a la ether_fcc.c. - * (C) Copyright 2008 - * DENX Software Engineerin GmbH - * Gary Jennejohn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (CONFIG_ETHER_INDEX == 1) -# define PROFF_ENET PROFF_SCC1 -# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC1 |\ - CMXSCR_RS1CS_MSK |\ - CMXSCR_TS1CS_MSK) - -#elif (CONFIG_ETHER_INDEX == 2) -# define PROFF_ENET PROFF_SCC2 -# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC2 |\ - CMXSCR_RS2CS_MSK |\ - CMXSCR_TS2CS_MSK) - -#elif (CONFIG_ETHER_INDEX == 3) -# define PROFF_ENET PROFF_SCC3 -# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC3 |\ - CMXSCR_RS3CS_MSK |\ - CMXSCR_TS3CS_MSK) -#elif (CONFIG_ETHER_INDEX == 4) -# define PROFF_ENET PROFF_SCC4 -# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC4 |\ - CMXSCR_RS4CS_MSK |\ - CMXSCR_TS4CS_MSK) - -#endif - - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#if !defined(CONFIG_SYS_SCC_TOUT_LOOP) - #define CONFIG_SYS_SCC_TOUT_LOOP 1000000 -#endif - -static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - - -static int sec_send(struct eth_device *dev, void *packet, int length) -{ - int i; - int result = 0; - - if (length <= 0) { - printf("scc: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { - puts ("scc: tx buffer not ready\n"); - goto out; - } - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | - BD_ENET_TX_WRAP); - - for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { - puts ("scc: tx error\n"); - goto out; - } - } - - /* return only status bits */ - result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - - out: - return result; -} - - -static int sec_rx(struct eth_device *dev) -{ - int length; - - for (;;) - { - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) - { - printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); - } - else - { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | - BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ - -static int sec_init(struct eth_device *dev, bd_t *bis) -{ - int i; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - scc_enet_t *pram_ptr; - uint dpaddr; - uchar ea[6]; - - rxIdx = 0; - txIdx = 0; - - /* - * Assign static pointer to BD area. - * Avoid exhausting DPRAM, which would cause a panic. - */ - if (rtx == NULL) { - dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); - rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; - } - - /* 24.21 - (1-3): ioports have been set up already */ - - /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | - CONFIG_SYS_CMXSCR_VALUE); - - - /* 24.21 (6) write RBASE and TBASE to parameter RAM */ - pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); - pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); - pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - - - /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ - while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); - immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, - CPM_CR_ENET_SBLOCK, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - - /* 24.21 - (8-18): Set up parameter RAM */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - - eth_getenv_enetaddr("ethaddr", ea); - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* 24.21 - (19): Initialize RxBD */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* 24.21 - (20): Initialize TxBD */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | - BD_ENET_TX_LAST | - BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 24.21 - (21): Write 0xffff to SCCE */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); - - /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | - SCCE_ENET_RXF | - SCCE_ENET_TXB); - - /* 24.21 - (23): we don't use ethernet interrupts */ - - /* 24.21 - (24): Clear GSMR_H to enable normal operations */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; - - /* 24.21 - (25): Clear GSMR_L to enable normal operations */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_MODE_ENET); - - /* 24.21 - (26): Initialize DSR */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; - - /* 24.21 - (27): Initialize PSMR2 - * - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * FDE = Full Duplex Enable - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packets regardless of dest. MAC adress - */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | -#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) - SCC_PSMR_FDE | -#endif -#if defined(CONFIG_SCC_ENET_NO_BROADCAST) - SCC_PSMR_BRO | -#endif -#if defined(CONFIG_SCC_ENET_PROMISCOUS) - SCC_PSMR_PRO | -#endif - 0; - - /* 24.21 - (28): Write to GSMR_L to enable SCC */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | - SCC_GSMRL_ENT); - - return 0; -} - - -static void sec_halt(struct eth_device *dev) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | - SCC_GSMRL_ENT); -} - -#if 0 -static void sec_restart(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | - SCC_GSMRL_ENT); -} -#endif - -int mpc82xx_scc_enet_initialize(bd_t *bis) -{ - struct eth_device *dev; - - dev = (struct eth_device *) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - strcpy(dev->name, "SCC"); - dev->init = sec_init; - dev->halt = sec_halt; - dev->send = sec_send; - dev->recv = sec_rx; - - eth_register(dev); - - return 1; -} diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c deleted file mode 100644 index 41d2c04..0000000 --- a/arch/powerpc/cpu/mpc8260/interrupts.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/****************************************************************************/ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -static struct irq_action irq_handlers[NR_IRQS]; - -static ulong ppc_cached_irq_mask[NR_MASK_WORDS]; - -/****************************************************************************/ -/* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the */ -/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */ - -/* The 8260 internal interrupt controller. It is usually - * the only interrupt controller. - * There are two 32-bit registers (high/low) for up to 64 - * possible interrupts. - * - * Now, the fun starts.....Interrupt Numbers DO NOT MAP - * in a simple arithmetic fashion to mask or pending registers. - * That is, interrupt 4 does not map to bit position 4. - * We create two tables, indexed by vector number, to indicate - * which register to use and which bit in the register to use. - */ -static u_char irq_to_siureg[] = { - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u_char irq_to_siubit[] = { - 31, 16, 17, 18, 19, 20, 21, 22, - 23, 24, 25, 26, 27, 28, 29, 30, - 29, 30, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 27, 28, 31, - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 15, 14, 13, 12, 11, 10, 9, 8, - 7, 6, 5, 4, 3, 2, 1, 0 -}; - -static void m8260_mask_irq (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int bit, word; - volatile uint *simr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void m8260_unmask_irq (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int bit, word; - volatile uint *simr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] |= (1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void m8260_mask_and_ack (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int bit, word; - volatile uint *simr, *sipnr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - sipnr = &(immr->im_intctl.ic_sipnrh); - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; - sipnr[word] = 1 << (31 - bit); -} - -static int m8260_get_irq (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int irq; - unsigned long bits; - - /* For MPC8260, read the SIVEC register and shift the bits down - * to get the irq number. */ - bits = immr->im_intctl.ic_sivec; - irq = bits >> 26; - return irq; -} - -/* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c */ -/****************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ; - - /* Initialize the default interrupt mapping priorities */ - immr->im_intctl.ic_sicr = 0; - immr->im_intctl.ic_siprr = 0x05309770; - immr->im_intctl.ic_scprrh = 0x05309770; - immr->im_intctl.ic_scprrl = 0x05309770; - - /* disable all interrupts and clear all pending bits */ - immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0; - immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0; - immr->im_intctl.ic_sipnrh = 0xffffffff; - immr->im_intctl.ic_sipnrl = 0xffffffff; - - return 0; -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - int irq, unmask = 1; - - irq = m8260_get_irq (regs); - - m8260_mask_and_ack (irq); - - enable_interrupts (); - - if (irq_handlers[irq].handler != NULL) - (*irq_handlers[irq].handler) (irq_handlers[irq].arg); - else { - printf ("\nBogus External Interrupt IRQ %d\n", irq); - /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ - unmask = 0; - } - - if (unmask) - m8260_unmask_irq (irq); -} - -/****************************************************************************/ - -/* - * Install and free an interrupt handler. - */ - -void -irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf ("irq_install_handler: bad irq number %d\n", irq); - return; - } - - if (irq_handlers[irq].handler != NULL) - printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, (ulong) irq_handlers[irq].handler); - - irq_handlers[irq].handler = handler; - irq_handlers[irq].arg = arg; - - m8260_unmask_irq (irq); -} - -void irq_free_handler (int irq) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf ("irq_free_handler: bad irq number %d\n", irq); - return; - } - - m8260_mask_irq (irq); - - irq_handlers[irq].handler = NULL; - irq_handlers[irq].arg = NULL; -} - -/****************************************************************************/ - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -#if defined(CONFIG_CMD_IRQ) - -/* ripped this out of ppc4xx/interrupts.c */ - -/******************************************************************************* -* -* irqinfo - print information about PCI devices -* -*/ -void -do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[]) -{ - int irq, re_enable; - - re_enable = disable_interrupts (); - - puts ("\nInterrupt-Information:\n" - "Nr Routine Arg Count\n"); - - for (irq = 0; irq < 32; irq++) - if (irq_handlers[irq].handler != NULL) - printf ("%02d %08lx %08lx %ld\n", irq, - (ulong) irq_handlers[irq].handler, - (ulong) irq_handlers[irq].arg, - irq_handlers[irq].count); - - if (re_enable) - enable_interrupts (); -} - -#endif diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S deleted file mode 100644 index bc9c628..0000000 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include -#include - -#include -#include - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - mfspr r3, HID0 - ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */ - SYNC - mtspr HID0, r3 - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c deleted file mode 100644 index 56f290c..0000000 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug - * Added support for PCI bridge on MPC8272ADS - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include -#ifdef CONFIG_OF_LIBFDT -#include -#include -#endif - -/* - * Local->PCI map (from CPU) controlled by - * MPC826x master window - * - * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 - * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 - * - * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) - * PCI Mem with prefetch - * - * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) - * PCI Mem w/o prefetch - * - * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) - * 32-bit PCI IO - * - * PCI->Local map (from PCI) - * MPC826x slave window controlled by - * - * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) - * MPC826x local memory - */ - -/* - * Slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - -#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ -#else -#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS -#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#else -#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS -#endif - -#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB -#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) -#else -#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB -#endif - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* PCIBR0 */ -#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL -#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ -#else -#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL -#endif - -#ifndef CONFIG_SYS_PCIMSK0_MASK -#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ -#else -#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK -#endif - -/* PCIBR1 */ -#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL -#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ -#else -#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL -#endif - -#ifndef CONFIG_SYS_PCIMSK1_MASK -#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ -#else -#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK -#endif - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL -#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#else -#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS -#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#else -#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS -#endif - -#ifndef CONFIG_SYS_CPU_PCI_MEM_START -#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#else -#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE -#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ -#else -#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE -#endif - -#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB -#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) -#else -#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB -#endif - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL -#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ -#else -#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS -#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ -#else -#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS -#endif - -#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START -#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#else -#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE -#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ -#else -#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE -#endif - -#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB -#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) -#else -#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB -#endif - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the third set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL -#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ -#else -#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS -#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ -#else -#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS -#endif - -#ifndef CONFIG_SYS_CPU_PCI_IO_START -#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#else -#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START -#endif - -#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE -#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ -#else -#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE -#endif - -#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB -#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) -#else -#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB -#endif - -/* PCI bus configuration registers. - */ - -#define PCI_CLASS_BRIDGE_CTLR 0x06 - - -static inline void pci_outl (u32 addr, u32 data) -{ - *(volatile u32 *) addr = cpu_to_le32 (data); -} - -void pci_mpc8250_init (struct pci_controller *hose) -{ - u16 tempShort; - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - pci_dev_t host_devno = PCI_BDF (0, 0, 0); - - pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, - CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); - - /* - * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), - * and local bus for PCI (SIUMCR [LBPC]). - */ - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_LBPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_LBPC11) | - SIUMCR_LBPC01 | - SIUMCR_CS10PC01 | - SIUMCR_APPC10; - - /* Make PCI lowest priority */ - /* Each 4 bits is a device bus request and the MS 4bits - is highest priority */ - /* Bus 4bit value - --- ---------- - CPM high 0b0000 - CPM middle 0b0001 - CPM low 0b0010 - PCI reguest 0b0011 - Reserved 0b0100 - Reserved 0b0101 - Internal Core 0b0110 - External Master 1 0b0111 - External Master 2 0b1000 - External Master 3 0b1001 - The rest are reserved */ - immap->im_siu_conf.sc_ppc_alrh = 0x61207893; - - /* Park bus on core while modifying PCI Bus accesses */ - immap->im_siu_conf.sc_ppc_acr = 0x6; - - /* - * Set up master windows that allow the CPU to access PCI space. These - * windows are set up using the two SIU PCIBR registers. - */ - immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; - immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; - - /* Release PCI RST (by default the PCI RST signal is held low) */ - immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); - - /* give it some time */ - { - udelay (1000); - } - - /* - * Set up master window that allows the CPU to access PCI Memory (prefetch) - * space. This window is set up using the first set of Outbound ATU registers. - */ - immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI Memory (non-prefetch) - * space. This window is set up using the second set of Outbound ATU registers. - */ - immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI IO space. This window - * is set up using the third set of Outbound ATU registers. - */ - immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ - immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ - immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ - - /* See above for description - puts PCI request as highest priority */ - immap->im_siu_conf.sc_ppc_alrh = 0x03124567; - - /* Park the bus on the PCI */ - immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; - - /* Host mode - specify the bridge as a host-PCI bridge */ - - pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, - PCI_CLASS_BRIDGE_CTLR); - - /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ - pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); - pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, - tempShort | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); - - /* do some bridge init, should be done on all 8260 based bridges */ - pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, - 0x08); - pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, - 0xF8); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region (hose->regions + 0, - CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_BASE, - 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - PCI_MSTR_MEM_BUS, - PCI_MSTR_MEM_LOCAL, - PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_MSTR_IO_BUS, - PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - /* Mask off master abort machine checks */ - immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); - eieio (); - - hose->last_busno = pci_hose_scan (hose); - - - /* clear the error in the error status register */ - immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); - - /* unmask master abort machine checks */ - immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "pci", 4, - "clock-frequency", gd->pci_clk, 1); -} -#endif - -#endif /* CONFIG_PCI */ diff --git a/arch/powerpc/cpu/mpc8260/serial_scc.c b/arch/powerpc/cpu/mpc8260/serial_scc.c deleted file mode 100644 index 8bfb3de..0000000 --- a/arch/powerpc/cpu/mpc8260/serial_scc.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. - */ - -/* - * Minimal serial functions needed to use one of the SCC ports - * as serial console interface. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_ON_SCC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ - -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ - -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ - -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ - -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "console not correctly defined" - -#endif - -static int mpc8260_scc_serial_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(im->im_scc[SCC_INDEX]); - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ - serial_setbrg (); - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->scc_gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - return (0); -} - -static void mpc8260_scc_serial_setbrg(void) -{ -#if defined(CONFIG_CONS_USE_EXTC) - m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8260_cpm_setbrg(SCC_INDEX, gd->baudrate); -#endif -} - -static void mpc8260_scc_serial_putc(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - serial_putc ('\r'); - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -static int mpc8260_scc_serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -static int mpc8260_scc_serial_tstc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); -} - -static struct serial_device mpc8260_scc_serial_drv = { - .name = "mpc8260_scc_uart", - .start = mpc8260_scc_serial_init, - .stop = NULL, - .setbrg = mpc8260_scc_serial_setbrg, - .putc = mpc8260_scc_serial_putc, - .puts = default_serial_puts, - .getc = mpc8260_scc_serial_getc, - .tstc = mpc8260_scc_serial_tstc, -}; - -void mpc8260_scc_serial_initialize(void) -{ - serial_register(&mpc8260_scc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc8260_scc_serial_drv; -} -#endif /* CONFIG_CONS_ON_SCC */ - -#if defined(CONFIG_KGDB_ON_SCC) - -#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Whoops! serial console and kgdb are on the same scc serial port -#endif - -#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */ - -#define KGDB_SCC_INDEX 0 -#define KGDB_PROFF_SCC PROFF_SCC1 -#define KGDB_CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */ - -#define KGDB_SCC_INDEX 1 -#define KGDB_PROFF_SCC PROFF_SCC2 -#define KGDB_CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */ - -#define KGDB_SCC_INDEX 2 -#define KGDB_PROFF_SCC PROFF_SCC3 -#define KGDB_CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */ - -#define KGDB_SCC_INDEX 3 -#define KGDB_PROFF_SCC PROFF_SCC4 -#define KGDB_CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "kgdb serial port not correctly defined" - -#endif - -void -kgdb_serial_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; - char *s, *e; - - if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { - ulong rate = simple_strtoul(s, &e, 10); - if (e > s && *e == '\0') - speed = rate; - } - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]); - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpmux.cmx_scr = \ - (im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ -#if defined(CONFIG_KGDB_USE_EXTC) - m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed, - CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); -#else - m8260_cpm_setbrg(KGDB_SCC_INDEX, speed); -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->scc_gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed); -} - -void -putDebugChar(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - putDebugChar ('\r'); - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -putDebugStr (const char *s) -{ - while (*s) { - putDebugChar (*s++); - } -} - -int -getDebugChar(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CONFIG_SYS_IMMR; - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -void -kgdb_interruptible(int yes) -{ - return; -} - -#endif /* CONFIG_KGDB_ON_SCC */ diff --git a/arch/powerpc/cpu/mpc8260/serial_smc.c b/arch/powerpc/cpu/mpc8260/serial_smc.c deleted file mode 100644 index 594c5eb..0000000 --- a/arch/powerpc/cpu/mpc8260/serial_smc.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with - * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the - * Linux/PPC sources (m8260_tty.c had no copyright info in it). - */ - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_ON_SMC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */ - -#define SMC_INDEX 0 -#define PROFF_SMC_BASE PROFF_SMC1_BASE -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE -#define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK -#define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) -#define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 - -#elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */ - -#define SMC_INDEX 1 -#define PROFF_SMC_BASE PROFF_SMC2_BASE -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE -#define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK -#define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) -#define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 - -#else - -#error "console not correctly defined" - -#endif - -#if !defined(CONFIG_SYS_SMC_RXBUFLEN) -#define CONFIG_SYS_SMC_RXBUFLEN 1 -#define CONFIG_SYS_MAXIDLE 0 -#else -#if !defined(CONFIG_SYS_MAXIDLE) -#error "you must define CONFIG_SYS_MAXIDLE" -#endif -#endif - -typedef volatile struct serialbuffer { - cbd_t rxbd; /* Rx BD */ - cbd_t txbd; /* Tx BD */ - uint rxindex; /* index for next character to read */ - volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ - volatile uchar txbuf; /* tx buffers */ -} serialbuffer_t; - -/* map rs_table index to baud rate generator index */ -static unsigned char brg_map[] = { - 6, /* BRG7 for SMC1 */ - 7, /* BRG8 for SMC2 */ - 0, /* BRG1 for SCC1 */ - 1, /* BRG1 for SCC2 */ - 2, /* BRG1 for SCC3 */ - 3, /* BRG1 for SCC4 */ -}; - -static int mpc8260_smc_serial_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr; - volatile serialbuffer_t *rtx; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(im->im_smc[SMC_INDEX]); - im->im_dprambase16[PROFF_SMC_BASE / sizeof(u16)] = PROFF_SMC; - up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC]; - - /* Disable transmitter/receiver. */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - /* allocate size of struct serialbuffer with bd rx/tx, - * buffer rx/tx and rx index - */ - dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16); - - rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr]; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; - rtx->rxbd.cbd_sc = 0; - - rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; - rtx->txbd.cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* put the SMC channel into NMSI (non multiplexd serial interface) - * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). - */ - im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE; - - /* Set up the baud rate generator. */ - serial_setbrg (); - - /* Make the first buffer the only buffer. */ - rtx->txbd.cbd_sc |= BD_SC_WRAP; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* single/multi character receive. */ - up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; - up->smc_maxidl = CONFIG_SYS_MAXIDLE; - rtx->rxindex = 0; - - /* Initialize Tx/Rx parameters. */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -static void mpc8260_smc_serial_setbrg(void) -{ -#if defined(CONFIG_CONS_USE_EXTC) - m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate); -#endif -} - -static void mpc8260_smc_serial_putc(const char c) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile serialbuffer_t *rtx; - - if (c == '\n') - serial_putc ('\r'); - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for last character to go. */ - while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY) - ; - rtx->txbuf = c; - rtx->txbd.cbd_datlen = 1; - rtx->txbd.cbd_sc |= BD_SC_READY; -} - -static int mpc8260_smc_serial_getc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile serialbuffer_t *rtx; - unsigned char c; - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for character to show up. */ - while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) - ; - - /* the characters are read one by one, - * use the rxindex to know the next char to deliver - */ - c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex); - rtx->rxindex++; - - /* check if all char are readout, then make prepare for next receive */ - if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { - rtx->rxindex = 0; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY; - } - return(c); -} - -static int mpc8260_smc_serial_tstc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile serialbuffer_t *rtx; - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - - return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); -} - -static struct serial_device mpc8260_smc_serial_drv = { - .name = "mpc8260_smc_uart", - .start = mpc8260_smc_serial_init, - .stop = NULL, - .setbrg = mpc8260_smc_serial_setbrg, - .putc = mpc8260_smc_serial_putc, - .puts = default_serial_puts, - .getc = mpc8260_smc_serial_getc, - .tstc = mpc8260_smc_serial_tstc, -}; - -void mpc8260_smc_serial_initialize(void) -{ - serial_register(&mpc8260_smc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mpc8260_smc_serial_drv; -} -#endif /* CONFIG_CONS_ON_SMC */ - -#if defined(CONFIG_KGDB_ON_SMC) - -#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Whoops! serial console and kgdb are on the same smc serial port -#endif - -#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */ - -#define KGDB_SMC_INDEX 0 -#define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE -#define KGDB_PROFF_SMC PROFF_SMC1 -#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE -#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK -#define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) -#define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 - -#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */ - -#define KGDB_SMC_INDEX 1 -#define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE -#define KGDB_PROFF_SMC PROFF_SMC2 -#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE -#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK -#define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) -#define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 - -#else - -#error "console not correctly defined" - -#endif - -void -kgdb_serial_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; - char *s, *e; - - if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { - ulong rate = simple_strtoul(s, &e, 10); - if (e > s && *e == '\0') - speed = rate; - } - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]); - im->im_dprambase16[KGDB_PROFF_SMC_BASE / sizeof(u16)] = KGDB_PROFF_SMC; - up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC]; - - /* Disable transmitter/receiver. */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* put the SMC channel into NMSI (non multiplexd serial interface) - * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). - */ - im->im_cpmux.cmx_smr = - (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE; - - /* Set up the baud rate generator. */ -#if defined(CONFIG_KGDB_USE_EXTC) - m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed, - CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); -#else - m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed); -#endif - - /* Make the first buffer the only buffer. */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed); -} - -void -putDebugChar(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (c == '\n') - putDebugChar ('\r'); - - up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); - - tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; - - /* Wait for last character to go. */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY) - ; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -putDebugStr (const char *s) -{ - while (*s) { - putDebugChar (*s++); - } -} - -int -getDebugChar(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned char c; - - up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); - - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for character to show up. */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -void -kgdb_interruptible(int yes) -{ - return; -} - -#endif /* CONFIG_KGDB_ON_SMC */ diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c deleted file mode 100644 index 0a06c48..0000000 --- a/arch/powerpc/cpu/mpc8260/speed.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -extern unsigned long board_get_cpu_clk_f (void); -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* Bus-to-Core Multiplier */ -#define _1x 2 -#define _1_5x 3 -#define _2x 4 -#define _2_5x 5 -#define _3x 6 -#define _3_5x 7 -#define _4x 8 -#define _4_5x 9 -#define _5x 10 -#define _5_5x 11 -#define _6x 12 -#define _6_5x 13 -#define _7x 14 -#define _7_5x 15 -#define _8x 16 -#define _byp -1 -#define _off -2 -#define _unk -3 - -typedef struct { - int b2c_mult; - int vco_div; - char *freq_60x; - char *freq_core; -} corecnf_t; - -/* - * this table based on "Errata to MPC8260 PowerQUICC II User's Manual", - * Rev. 1, 8/2000, page 10. - */ -corecnf_t corecnf_tab[] = { - { _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */ - { _1x, 4, " 50-150", " 50-150" }, /* 0x01 */ - { _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */ - { _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */ - { _2x, 2, " 50-150", "100-300" }, /* 0x04 */ - { _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */ - { _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */ - { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */ - { _3x, 2, " 33-100", "100-300" }, /* 0x08 */ - { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */ - { _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */ - { _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */ - { _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */ - { _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */ - { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */ - { _off, -1, " ?-? ", " ?-? " }, /* 0x0F */ - { _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */ - { _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */ - { _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */ - { _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */ - { _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */ - { _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */ - { _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */ - { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */ - { _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */ - { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */ - { _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */ - { _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */ - { _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */ - { _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */ - { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */ - { _off, -1, " ?-? ", " ?-? " }, /* 0x1F */ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * - */ - -int get_clocks (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - ulong clkin; - ulong sccr, dfbrg; - ulong scmr, corecnf, plldf, pllmf; - corecnf_t *cp; - -#if !defined(CONFIG_8260_CLKIN) -#error clock measuring not implemented yet - define CONFIG_8260_CLKIN -#else -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - clkin = board_get_cpu_clk_f (); -#else - clkin = CONFIG_8260_CLKIN; -#endif -#endif - - sccr = immap->im_clkrst.car_sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; - - scmr = immap->im_clkrst.car_scmr; - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - cp = &corecnf_tab[corecnf]; - - /* HiP7, HiP7 Rev01, HiP7 RevA */ - if ((get_pvr () == PVR_8260_HIP7) || - (get_pvr () == PVR_8260_HIP7R1) || - (get_pvr () == PVR_8260_HIP7RA)) { - pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; - gd->arch.vco_out = clkin * (pllmf + 1); - } else { /* HiP3, HiP4 */ - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); - } - - gd->arch.cpm_clk = gd->arch.vco_out / 2; - gd->bus_clk = clkin; - gd->arch.scc_clk = gd->arch.vco_out / 4; - gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); - - if (cp->b2c_mult > 0) { - gd->cpu_clk = (clkin * cp->b2c_mult) / 2; - } else { - gd->cpu_clk = clkin; - } - -#ifdef CONFIG_PCI - gd->pci_clk = clkin; - - if (sccr & SCCR_PCI_MODE) { - uint pci_div; - uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; - - if (sccr & SCCR_PCI_MODCK) { - pci_div = 2; - if (pcidf == 9) { - pci_div *= 5; - } else if (pcidf == 0xB) { - pci_div *= 6; - } else { - pci_div *= (pcidf + 1); - } - } else { - pci_div = pcidf + 1; - } - - gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div; - } -#endif - - return (0); -} - -int prt_8260_clks (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - ulong sccr, dfbrg; - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf; - corecnf_t *cp; - - sccr = immap->im_clkrst.car_sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; - - scmr = immap->im_clkrst.car_scmr; - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; - - cp = &corecnf_tab[corecnf]; - - puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult "); - - switch (cp->b2c_mult) { - case _byp: - puts ("BYPASS"); - break; - - case _off: - puts ("OFF"); - break; - - case _unk: - puts ("UNKNOWN"); - break; - - default: - printf ("%d%sx", - cp->b2c_mult / 2, - (cp->b2c_mult % 2) ? ".5" : ""); - break; - } - - printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n", - cp->vco_div, cp->freq_60x, cp->freq_core); - - printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, " - "plldf %ld, pllmf %ld, pcidf %ld\n", - dfbrg, corecnf, busdf, cpmdf, - plldf, pllmf, pcidf); - - printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", - gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk); - - printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", - gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk); -#ifdef CONFIG_PCI - printf (" - pci_clk %10ld\n", gd->pci_clk); -#endif - putc ('\n'); - - return (0); -} diff --git a/arch/powerpc/cpu/mpc8260/spi.c b/arch/powerpc/cpu/mpc8260/spi.c deleted file mode 100644 index c7fb4e9..0000000 --- a/arch/powerpc/cpu/mpc8260/spi.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * , - * - * Copyright (c) 2001 Gerd Mennchen - * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, . - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8260 CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI) - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0x2000 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0x2000 -#endif - -#define CPM_SPI_BASE 0x100 - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f (void) -{ - unsigned int dpaddr; - - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpm8260_t *cp; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; - - immr->im_dprambase16[PROFF_SPI_BASE / sizeof(u16)] = PROFF_SPI; - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port D SPI pins - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PPARD[16] = 1 [0x00008000] (SPIMISO) - * PPARD[17] = 1 [0x00004000] (SPIMOSI) - * PPARD[18] = 1 [0x00002000] (SPICLK) - * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM) - * -------------------------------------------- */ - immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */ - immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO - * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI - * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK - * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM - * ---------------------------------------------- */ - immr->im_ioport.iop_pdird &= ~0x0000E000; - immr->im_ioport.iop_pdird |= 0x00080000; - - /* ---------------------------------------------- - * special option reg. - * PSORD[16] = 1 [0x00008000] -> SPIMISO - * PSORD[17] = 1 [0x00004000] -> SPIMOSI - * PSORD[18] = 1 [0x00002000] -> SPICLK - * ---------------------------------------------- */ - immr->im_ioport.iop_psord |= 0x0000E000; - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - spi->spi_rstate = 0; - spi->spi_rdp = 0; - spi->spi_rbptr = 0; - spi->spi_rbc = 0; - spi->spi_rxtmp = 0; - spi->spi_tstate = 0; - spi->spi_tdp = 0; - spi->spi_tbptr = 0; - spi->spi_tbc = 0; - spi->spi_txtmp = 0; - - dpaddr = CPM_SPI_BASE; - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - spi->spi_rbase = dpaddr; - spi->spi_tbase = dpaddr + sizeof (cbd_t); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - spi->spi_rbptr = spi->spi_rbase; - spi->spi_tbptr = spi->spi_tbase; - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (cp->cp_cpcr & CPM_CR_FLG) - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG) - ; - -/* 6 */ - /* Set to big endian. */ - spi->spi_tfcr = CPMFCR_EB; - spi->spi_rfcr = CPMFCR_EB; - -/* 7 */ - /* Set maximum receive size. */ - spi->spi_mrblr = MAX_BUFFER; - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - tbdf->cbd_sc &= ~BD_SC_READY; - rbdf->cbd_sc &= ~BD_SC_EMPTY; - - /* Set the bd's rx and tx buffer address pointers */ - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - -/* 10 + 11 */ - immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ - immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ - - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r (void) -{ - volatile spi_t *spi; - volatile immap_t *immr; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *) malloc (MAX_BUFFER); - txbuf = (uchar *) malloc (MAX_BUFFER); - - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile spi_t *spi; - cbd_t *tbdf, *rbdf; - int tm; - - DPRINT (("*** spi_xfer entered ***\n")); - - immr = (immap_t *) CONFIG_SYS_IMMR; - - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - /* Board-specific: Set CS for device (ATC EEPROM) */ - immr->im_ioport.iop_pdatd &= ~0x00080000; - - /* Setting tx bd status and data length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; - tbdf->cbd_datlen = count; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", - tbdf->cbd_datlen)); - - /* Setting rx bd status and data length */ - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - rbdf->cbd_datlen = 0; /* rx length has no significance */ - - immr->im_spi.spi_spmode = SPMODE_REV | - SPMODE_MSTR | - SPMODE_EN | - SPMODE_LEN(8) | /* 8 Bits per char */ - SPMODE_PM(0x8) ; /* medium speed */ - immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ - immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */ - DPRINT (("*** spi_xfer: Tx buffer empty\n")); - break; - } - if ((tbdf->cbd_sc & BD_SC_READY) == 0) { - DPRINT (("*** spi_xfer: Tx BD done\n")); - break; - } - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } - DPRINT (("*** spi_xfer: ... transfer ended\n")); - -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ - printf ("\n"); -#endif - - /* Clear CS for device */ - immr->im_ioport.iop_pdatd |= 0x00080000; - - return count; -} -#endif /* CONFIG_SPI */ diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S deleted file mode 100644 index d255bde..0000000 --- a/arch/powerpc/cpu/mpc8260/start.S +++ /dev/null @@ -1,901 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000, 2001,2002 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards - */ -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Version string - must be in data segment because MPC8260 uses the first - * 256 bytes for the Hard Reset Configuration Word table (see below). - * Similarly, can't have the U-Boot Magic Number as the first thing in - * the image - don't know how this will affect the image tools, but I guess - * I'll find out soon - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - -/* - * Hard Reset Configuration Word (HRCW) table - * - * The Hard Reset Configuration Word (HRCW) sets a number of useful things - * such as whether there is an external memory controller, whether the - * PowerPC core is disabled (i.e. only the communications processor is - * active, accessed by another CPU on the bus), whether using external - * arbitration, external bus mode, boot port size, core initial prefix, - * internal space base, boot memory space, etc. - * - * These things dictate where the processor begins execution, where the - * boot ROM appears in memory, the memory controller setup when access - * boot ROM, etc. The HRCW is *extremely* important. - * - * The HRCW is read from the bus during reset. One CPU on the bus will - * be a hard reset configuration master, any others will be hard reset - * configuration slaves. The master reads eight HRCWs from flash during - * reset - the first it uses for itself, the other 7 it communicates to - * up to 7 configuration slaves by some complicated mechanism, which is - * not really important here. - * - * The configuration master performs 32 successive reads starting at address - * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8 - * bits is read, and always from byte lane D[0-7] (so that port size of the - * boot device does not matter). The first four reads form the 32 bit HRCW - * for the master itself. The second four reads form the HRCW for the first - * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by - * concatenating the four bytes, with the first read placed in byte 0 (the - * most significant byte), and so on with the fourth read placed in byte 3 - * (the least significant byte). - */ -#define _HRCW_TABLE_ENTRY(w) \ - .fill 8,1,(((w)>>24)&0xff); \ - .fill 8,1,(((w)>>16)&0xff); \ - .fill 8,1,(((w)>> 8)&0xff); \ - .fill 8,1,(((w) )&0xff) - .text - .globl _hrcw_table -_hrcw_table: - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7) -/* - * After configuration, a system reset exception is executed using the - * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP] - * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address - * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value - * of MSR[IP] is determined by the CIP field in the HRCW. - * - * Other bits in the HRCW set up the Base Address and Port Size in BR0. - * This determines the location of the boot ROM (flash or EPROM) in the - * processor's address space at boot time. As long as the HRCW is set up - * so that we eventually end up executing the code below when the processor - * executes the reset exception, the actual values used should not matter. - * - * Once we have got here, the address mask in OR0 is cleared so that the - * bottom 32K of the boot ROM is effectively repeated all throughout the - * processor's address space, after which we can jump to the absolute - * address at which the boot ROM was linked at compile time, and proceed - * to initialise the memory controller without worrying if the rug will be - * pulled out from under us, so to speak (it will be fine as long as we - * configure BR0 with the same boot ROM link address). - */ - . = EXC_OFF_SYS_RESET - - .globl _start -_start: - mfmsr r5 /* save msr contents */ - -#if defined(CONFIG_SYS_DEFAULT_IMMR) - lis r3, CONFIG_SYS_IMMR@h - ori r3, r3, CONFIG_SYS_IMMR@l - lis r4, CONFIG_SYS_DEFAULT_IMMR@h - stw r3, 0x1A8(r4) -#endif /* CONFIG_SYS_DEFAULT_IMMR */ - - /* Initialise the MPC8260 processor core */ - /*--------------------------------------------------------------*/ - - bl init_8260_core - -#ifndef CONFIG_SYS_RAMBOOT - /* When booting from ROM (Flash or EPROM), clear the */ - /* Address Mask in OR0 so ROM appears everywhere */ - /*--------------------------------------------------------------*/ - - lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h - lwz r4, IM_OR0@l(r3) - li r5, 0x7fff - and r4, r4, r5 - stw r4, IM_OR0@l(r3) - - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: -#endif /* CONFIG_SYS_RAMBOOT */ - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */ - ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - -#ifdef DEBUG - bl init_debug /* set up debugging stuff */ -#endif - - bl board_init_f /* run 1st part of board init code (in Flash)*/ - - /* NOTREACHED - board_init_f() does not return */ - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the MPC8260 processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_8260_core -init_8260_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialise the SYPCR early, and reset the watchdog (if req) */ - /*--------------------------------------------------------------*/ - - lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h - lis r4, CONFIG_SYS_SYPCR@h - ori r4, r4, CONFIG_SYS_SYPCR@l - stw r4, IM_SYPCR@l(r3) -#if defined(CONFIG_WATCHDOG) - li r4, 21868 /* = 0x556c */ - sth r4, IM_SWSR@l(r3) - li r4, -21959 /* = 0xaa39 */ - sth r4, IM_SWSR@l(r3) -#endif /* CONFIG_WATCHDOG */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_HID0_INIT@h - ori r3, r3, CONFIG_SYS_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID0_FINAL@h - ori r3, r3, CONFIG_SYS_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - lis r3, CONFIG_SYS_HID2@h - ori r3, r3, CONFIG_SYS_HID2@l - mtspr HID2, r3 - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -#ifdef DEBUG - -/* - * initialise things related to debugging. - * - * must be called after the global offset table (GOT) is initialised - * (GET_GOT) and after cpu_init_f() has executed. - */ - - .globl init_debug -init_debug: - - lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h - - /* Quick and dirty hack to enable the RAM and copy the */ - /* vectors so that we can take exceptions. */ - /*--------------------------------------------------------------*/ - /* write Memory Refresh Prescaler */ - li r4, CONFIG_SYS_MPTPR - sth r4, IM_MPTPR@l(r3) - /* write 60x Refresh Timer */ - li r4, CONFIG_SYS_PSRT - stb r4, IM_PSRT@l(r3) - /* init the 60x SDRAM Mode Register */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l - stw r4, IM_PSDMR@l(r3) - /* write Precharge All Banks command */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* write eight CBR Refresh commands */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - /* write Mode Register Write command */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* write Normal Operation command and enable Refresh */ - lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h - ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* RAM should now be operational */ - -#define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4) - mflr r3 - GET_GOT - mtlr r3 - lwz r3, GOT(_end_of_vectors) - rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */ - lis r5, VEC_WRD_CNT@h - ori r5, r5, VEC_WRD_CNT@l - mtctr r5 -1: - lwzu r5, -4(r3) - stwu r5, -4(r4) - bdnz 1b - - /* Load the Instruction Address Breakpoint Register (IABR). */ - /* */ - /* The address to load is stored in the first word of dual port */ - /* ram and should be preserved while the power is on, so you */ - /* can plug addresses into that location then reset the cpu and */ - /* this code will load that address into the IABR after the */ - /* reset. */ - /* */ - /* When the program counter matches the contents of the IABR, */ - /* an exception is generated (before the instruction at that */ - /* location completes). The vector for this exception is 0x1300 */ - /*--------------------------------------------------------------*/ - lis r3, CONFIG_SYS_IMMR@h - lwz r3, 0(r3) - mtspr IABR, r3 - - /* Set the entire dual port RAM (where the initial stack */ - /* resides) to a known value - makes it easier to see where */ - /* the stack has been written */ - /*--------------------------------------------------------------*/ - lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h - ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l - li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4) - mtctr r4 - lis r4, 0xdeadbeaf@h - ori r4, r4, 0xdeadbeaf@l -1: - stwu r4, -4(r3) - bdnz 1b - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr -#endif - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_DCE - lis r4, 0 - ori r4, r4, HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr diff --git a/arch/powerpc/cpu/mpc8260/traps.c b/arch/powerpc/cpu/mpc8260/traps.c deleted file mode 100644 index cbcf533..0000000 --- a/arch/powerpc/cpu/mpc8260/traps.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - puts ("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - putc ('\n'); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - putc ('\n'); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - putc ('\n'); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - putc ('\n'); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -#ifdef CONFIG_PCI -void dump_pci (void) -{ - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - printf ("PCI: err status %x err mask %x err ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_esr), - le32_to_cpu (immap->im_pci.pci_emr), - le32_to_cpu (immap->im_pci.pci_ecr)); - printf (" error address %x error data %x ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_eacr), - le32_to_cpu (immap->im_pci.pci_edcr), - le32_to_cpu (immap->im_pci.pci_eccr)); - -} -#endif - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ -#ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; -#ifdef DEBUG - dump_pci(); -#endif - /* clear the error in the error status register */ - if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { - immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); - return; - } -#endif - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - puts ("Machine check in kernel mode.\n" - "Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - puts ("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - puts ("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - puts ("Data parity signal\n"); - break; - case (0x80000000>>15): - puts ("Address parity signal\n"); - break; - default: - puts ("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); -#ifdef CONFIG_PCI - dump_pci(); -#endif - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds deleted file mode 100644 index 469fc29..0000000 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc8260/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index ff31289..2fed4a1 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -140,7 +140,7 @@ ppcDWload: #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined -#endif /* CONFIG_SYS_DEFAULT_IMMR */ +#endif /* CONFIG_DEFAULT_IMMR */ #ifndef CONFIG_SYS_IMMR #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR #endif /* CONFIG_SYS_IMMR */ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 88d56a9..4db687c 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -88,10 +88,6 @@ config TARGET_MPC8536DS # Use DDR3 controller with DDR2 DIMMs on this board select SYS_FSL_DDRC_GEN3 -config TARGET_MPC8540ADS - bool "Support MPC8540ADS" - select ARCH_MPC8540 - config TARGET_MPC8541CDS bool "Support MPC8541CDS" select ARCH_MPC8541 @@ -108,10 +104,6 @@ config TARGET_MPC8555CDS bool "Support MPC8555CDS" select ARCH_MPC8555 -config TARGET_MPC8560ADS - bool "Support MPC8560ADS" - select ARCH_MPC8560 - config TARGET_MPC8568MDS bool "Support MPC8568MDS" select ARCH_MPC8568 @@ -1395,12 +1387,10 @@ source "board/freescale/bsc9132qds/Kconfig" source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8536ds/Kconfig" -source "board/freescale/mpc8540ads/Kconfig" source "board/freescale/mpc8541cds/Kconfig" source "board/freescale/mpc8544ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" source "board/freescale/mpc8555cds/Kconfig" -source "board/freescale/mpc8560ads/Kconfig" source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig deleted file mode 100644 index 79cee35..0000000 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -menu "mpc8xx CPU" - depends on 8xx - -config SYS_CPU - default "mpc8xx" - -choice - prompt "Target select" - optional - -config TARGET_TQM823L - bool "Support TQM823L" - -config TARGET_TQM823M - bool "Support TQM823M" - -config TARGET_TQM850L - bool "Support TQM850L" - -config TARGET_TQM850M - bool "Support TQM850M" - -config TARGET_TQM855L - bool "Support TQM855L" - -config TARGET_TQM855M - bool "Support TQM855M" - -config TARGET_TQM860L - bool "Support TQM860L" - -config TARGET_TQM860M - bool "Support TQM860M" - -config TARGET_TQM862L - bool "Support TQM862L" - -config TARGET_TQM862M - bool "Support TQM862M" - -config TARGET_TQM866M - bool "Support TQM866M" - -config TARGET_TQM885D - bool "Support TQM885D" - -endchoice - -source "board/tqc/tqm8xx/Kconfig" - -endmenu diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile deleted file mode 100644 index fc91a05..0000000 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# ccflags-y += -DET_DEBUG - -extra-y += start.o -extra-y += traps.o -obj-y += bedbug_860.o -obj-y += cpu.o -obj-y += cpu_init.o -obj-y += fec.o -obj-$(CONFIG_OF_LIBFDT) += fdt.o -obj-y += interrupts.o -obj-y += scc.o -obj-y += serial.o -obj-y += speed.o -obj-y += spi.o -obj-y += upatch.o -obj-y += video.o -obj-y += kgdb.o -obj-y += plprcr_write.o diff --git a/arch/powerpc/cpu/mpc8xx/bedbug_860.c b/arch/powerpc/cpu/mpc8xx/bedbug_860.c deleted file mode 100644 index c0016f7..0000000 --- a/arch/powerpc/cpu/mpc8xx/bedbug_860.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Bedbug Functions specific to the MPC860 chip - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_8xx) - -#define MAX_BREAK_POINTS 2 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug860_init __P((void)); -void bedbug860_do_break __P((cmd_tbl_t*,int,int,char*const[])); -void bedbug860_break_isr __P((struct pt_regs*)); -int bedbug860_find_empty __P((void)); -int bedbug860_set __P((int,unsigned long)); -int bedbug860_clear __P((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the MPC860. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug860_init( void ) -{ - int i; - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug860_do_break; - bug_ctx.break_isr = bedbug860_break_isr; - bug_ctx.find_empty = bedbug860_find_empty; - bug_ctx.set = bedbug860_set; - bug_ctx.clear = bedbug860_clear; - - for( i = 1; i <= MAX_BREAK_POINTS; ++i ) - (*bug_ctx.clear)( i ); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show one of the hardware breakpoints for the 860. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - long addr = 0; /* Address to break at */ - int which_bp; /* Breakpoint number */ - /* -------------------------------------------------- */ - - if (argc < 2) { - cmd_usage(cmdtp); - return; - } - - /* Turn off a breakpoint */ - - if( strcmp( argv[ 1 ], "off" ) == 0 ) - { - if( bug_ctx.hw_debug_enabled == 0 ) - { - printf( "No breakpoints enabled\n" ); - return; - } - - which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); - - if( bug_ctx.clear ) - (*bug_ctx.clear)( which_bp ); - - printf( "Breakpoint %d removed\n", which_bp ); - return; - } - - /* Show a list of breakpoints */ - - if( strcmp( argv[ 1 ], "show" ) == 0 ) - { - for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) - { - - switch( which_bp ) - { - case 1: addr = GET_CMPA(); break; - case 2: addr = GET_CMPB(); break; - case 3: addr = GET_CMPC(); break; - case 4: addr = GET_CMPD(); break; - } - - printf( "Breakpoint [%d]: ", which_bp ); - if( addr == 0 ) - printf( "NOT SET\n" ); - else - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - return; - } - - /* Set a breakpoint at the address */ - - if( !isdigit( argv[ 1 ][ 0 ])) { - cmd_usage(cmdtp); - return; - } - - addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc; - - if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) - { - printf( "Breakpoint [%d]: ", which_bp ); - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - - return; -} /* bedbug860_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. First determine which breakpoint was hit by - * looking at the DeBug Status Register (DBSR), clear the breakpoint - * and enter a mini main loop. Stay in the loop until the stopped flag - * in the debug context is cleared. - * ====================================================================== */ - -void bedbug860_break_isr( struct pt_regs *regs ) -{ - unsigned long addr; /* Address stopped at */ - unsigned long cause; /* Address stopped at */ - /* -------------------------------------------------- */ - - cause = GET_ICR(); - - if( !(cause & 0x00000004)) { - printf( "Not an instruction breakpoint (ICR 0x%08lx)\n", cause ); - return; - } - - addr = regs->nip; - - if( addr == GET_CMPA() ) - { - bug_ctx.current_bp = 1; - } - else if( addr == GET_CMPB() ) - { - bug_ctx.current_bp = 2; - } - else if( addr == GET_CMPC() ) - { - bug_ctx.current_bp = 3; - } - else if( addr == GET_CMPD() ) - { - bug_ctx.current_bp = 4; - } - - bedbug_main_loop( addr, regs ); - return; -} /* bedbug860_break_isr */ - - - -/* ====================================================================== - * Look through all of the hardware breakpoints available to see if one - * is unused. - * ====================================================================== */ - -int bedbug860_find_empty( void ) -{ - /* -------------------------------------------------- */ - - if( GET_CMPA() == 0 ) - return 1; - - if( GET_CMPB() == 0 ) - return 2; - - if( GET_CMPC() == 0 ) - return 3; - - if( GET_CMPD() == 0 ) - return 4; - - return 0; -} /* bedbug860_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the appropriate IACx register and enable proper address - * beakpoint in DBCR0. - * ====================================================================== */ - -int bedbug860_set( int which_bp, unsigned long addr ) -{ - /* -------------------------------------------------- */ - - /* Only look if which_bp == 0, else use which_bp */ - if(( bug_ctx.find_empty ) && ( !which_bp ) && - ( which_bp = (*bug_ctx.find_empty)()) == 0 ) - { - printf( "All breakpoints in use\n" ); - return 0; - } - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # %d\n", which_bp ); - return 0; - } - - if( ! bug_ctx.hw_debug_enabled ) - { - bug_ctx.hw_debug_enabled = 1; - SET_DER( GET_DER() | 0x00000004 ); - } - - switch( which_bp ) - { - case 1: - SET_CMPA( addr ); - SET_ICTRL( GET_ICTRL() | 0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ - break; - - case 2: - SET_CMPB( addr ); - SET_ICTRL( GET_ICTRL() | 0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ - break; - - case 3: - SET_CMPC( addr ); - SET_ICTRL( GET_ICTRL() | 0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ - break; - - case 4: - SET_CMPD( addr ); - SET_ICTRL( GET_ICTRL() | 0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ - break; - } - - return which_bp; -} /* bedbug860_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the appropriate IACx register - * to zero and claring the instruction address breakpoint in DBCR0. - * ====================================================================== */ - -int bedbug860_clear( int which_bp ) -{ - /* -------------------------------------------------- */ - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # (%d)\n", which_bp ); - return -1; - } - - switch( which_bp ) - { - case 1: - SET_CMPA( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ - break; - - case 2: - SET_CMPB( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ - break; - - case 3: - SET_CMPC( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ - break; - - case 4: - SET_CMPD( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ - break; - } - - return 0; -} /* bedbug860_clear */ - - -/* ====================================================================== */ -#endif diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk deleted file mode 100644 index 485e43d..0000000 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c deleted file mode 100644 index 105be9c..0000000 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ /dev/null @@ -1,580 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * m8xx.c - * - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * minor modifications by - * Wolfgang Denk - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static char *cpu_warning = "\n " \ - "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; - -#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ - !defined(CONFIG_MPC862)) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - char *id_str = -# if defined(CONFIG_MPC855) - "PC855"; -# elif defined(CONFIG_MPC860P) - "PC860P"; -# else - NULL; -# endif - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char pre = 'X'; - char *mid = "xx"; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 860 */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; - m = 0; - suf = ""; - - /* - * Some boards use sockets so different CPUs can be used. - * We have to check chip version in run time. - */ - switch (k) { - case 0x00020001: pre = 'P'; break; - case 0x00030001: break; - case 0x00120003: suf = "A"; break; - case 0x00130003: suf = "A3"; break; - - case 0x00200004: suf = "B"; break; - - case 0x00300004: suf = "C"; break; - case 0x00310004: suf = "C1"; m = 1; break; - - case 0x00200064: mid = "SR"; suf = "B"; break; - case 0x00300065: mid = "SR"; suf = "C"; break; - case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; - case 0x05010000: suf = "D3"; m = 1; break; - case 0x05020000: suf = "D4"; m = 1; break; - /* this value is not documented anywhere */ - case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; - /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ - case 0x08010004: /* Rev. A.0 */ - suf = "A"; - /* fall through */ - case 0x08000003: /* Rev. 0.3 */ - pre = 'M'; m = 1; - if (id_str == NULL) - id_str = -# if defined(CONFIG_MPC859T) - "PC859T"; -# else - "PC866x"; /* Unknown chip from MPC866 family */ -# endif - break; - case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; - if (id_str == NULL) - id_str = "PC885"; /* 870/875/880/885 */ - break; - - default: suf = NULL; break; - } - - if (id_str == NULL) - id_str = "PC86x"; /* Unknown 86x chip */ - if (suf) - printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); - else - printf ("unknown M%s (0x%08x)", id_str, k); - - -#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX) - printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", - strmhz (buf, clock), - CONFIG_SYS_8xx_CPUCLK_MIN / 1000000, - ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, - CONFIG_SYS_8xx_CPUCLK_MAX / 1000000, - ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 - ); -#else - printf (" at %s MHz: ", strmhz (buf, clock)); -#endif - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* do we have a FEC (860T/P or 852/859/866/885)? */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - -#ifdef DEBUG - if(clock != measure_gclk()) { - printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); - } -#endif - - return 0; -} - -#elif defined(CONFIG_MPC862) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char pre = 'X'; - __maybe_unused char *mid = "xx"; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; - m = 0; - - switch (k) { - - /* this value is not documented anywhere */ - case 0x06000000: mid = "P"; suf = "0"; break; - case 0x06010001: mid = "P"; suf = "A"; m = 1; break; - case 0x07000003: mid = "P"; suf = "B"; m = 1; break; - default: suf = NULL; break; - } - -#ifndef CONFIG_MPC857 - if (suf) - printf ("%cPC862%sZPnn%s", pre, mid, suf); - else - printf ("unknown MPC862 (0x%08x)", k); -#else - if (suf) - printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ - else - printf ("unknown MPC857 (0x%08x)", k); -#endif - - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* lets check and see if we're running on a 862T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} - -#elif defined(CONFIG_MPC823) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]); - m = 0; - - switch (k) { - /* MPC823 */ - case 0x20000000: suf = "0"; break; - case 0x20010000: suf = "0.1"; break; - case 0x20020000: suf = "Z2/3"; break; - case 0x20020001: suf = "Z3"; break; - case 0x21000000: suf = "A"; break; - case 0x21010000: suf = "B"; m = 1; break; - case 0x21010001: suf = "B2"; m = 1; break; - /* MPC823E */ - case 0x24010000: suf = NULL; - puts ("PPC823EZTnnB2"); - m = 1; - break; - default: - suf = NULL; - printf ("unknown MPC823 (0x%08x)", k); - break; - } - if (suf) - printf ("PPC823ZTnn%s", suf); - - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* lets check and see if we're running on a 860T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - puts (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} - -#elif defined(CONFIG_MPC850) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]; - m = 0; - - switch (k) { - case 0x20020001: - printf ("XPC850xxZT"); - break; - case 0x21000065: - printf ("XPC850xxZTA"); - break; - case 0x21010067: - printf ("XPC850xxZTB"); - m = 1; - break; - case 0x21020068: - printf ("XPC850xxZTC"); - m = 1; - break; - default: - printf ("unknown MPC850 (0x%08x)", k); - } - printf(" at %s MHz: ", strmhz(buf, clock)); - - print_size(checkicache(), " I-Cache "); - print_size(checkdcache(), " D-Cache"); - - /* lets check and see if we're running on a 850T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} -#else -#error CPU undefined -#endif -/* ------------------------------------------------------------------------- */ - -int checkcpu (void) -{ - ulong clock = gd->cpu_clk; - uint immr = get_immr (0); /* Return full IMMR contents */ - uint pvr = get_pvr (); - - puts ("CPU: "); - - /* 850 has PARTNUM 20 */ - /* 801 has PARTNUM 10 */ - return check_CPU (clock, pvr, immr); -} - -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ -/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ -/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ - -int checkicache (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - u32 cacheon = rd_ic_cst () & IDC_ENABLED; - -#ifdef CONFIG_IP86x - u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ -#else - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ -#endif - u32 m; - u32 lines = -1; - - wr_ic_cst (IDC_UNALL); - wr_ic_cst (IDC_INVALL); - wr_ic_cst (IDC_DISABLE); - __asm__ volatile ("isync"); - - while (!((m = rd_ic_cst ()) & IDC_CERR2)) { - wr_ic_adr (k); - wr_ic_cst (IDC_LDLCK); - __asm__ volatile ("isync"); - - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_ic_cst (IDC_UNALL); - wr_ic_cst (IDC_INVALL); - - if (cacheon) - wr_ic_cst (IDC_ENABLE); - else - wr_ic_cst (IDC_DISABLE); - - __asm__ volatile ("isync"); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ -/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ -/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ -/* call with cache disabled */ - -int checkdcache (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - u32 cacheon = rd_dc_cst () & IDC_ENABLED; - -#ifdef CONFIG_IP86x - u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ -#else - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ -#endif - u32 m; - u32 lines = -1; - - wr_dc_cst (IDC_UNALL); - wr_dc_cst (IDC_INVALL); - wr_dc_cst (IDC_DISABLE); - - while (!((m = rd_dc_cst ()) & IDC_CERR2)) { - wr_dc_adr (k); - wr_dc_cst (IDC_LDLCK); - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_dc_cst (IDC_UNALL); - wr_dc_cst (IDC_INVALL); - - if (cacheon) - wr_dc_cst (IDC_ENABLE); - else - wr_dc_cst (IDC_DISABLE); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ - -void upmconfig (uint upm, uint * table, uint size) -{ - uint i; - uint addr = 0; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - for (i = 0; i < size; i++) { - memctl->memc_mdr = table[i]; /* (16-15) */ - memctl->memc_mcr = addr | upm; /* (16-16) */ - addr++; - } -} - -/* ------------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong msr, addr; - - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ volatile ("mtspr 81, 0"); - __asm__ volatile ("mfmsr %0":"=r" (msr)); - - msr &= ~0x1030; - __asm__ volatile ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - * See sections 14.2 and 14.6 of the User's Manual - */ -unsigned long get_tbclk (void) -{ - uint immr = get_immr (0); /* Return full IMMR contents */ - volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); - ulong oscclk, factor, pll; - - if (immap->im_clkrst.car_sccr & SCCR_TBS) { - return (gd->cpu_clk / 16); - } - - pll = immap->im_clkrst.car_plprcr; - -#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) - - /* - * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication - * factor is calculated as follows: - * - * MFN - * MFI + ------- - * MFD + 1 - * factor = ----------------- - * (PDF + 1) * 2^S - * - * For older chips, it's just MF field of PLPRCR plus one. - */ - if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ - factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ - (PLPRCR_val(PDF)+1) / (1<cpu_clk / factor; - - if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { - return (oscclk / 4); - } - return (oscclk / 16); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); - if (re_enable) - enable_interrupts (); -} -#endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_WATCHDOG) - -void reset_8xx_watchdog (volatile immap_t * immr) -{ - /* - * All other boards use the MPC8xx Internal Watchdog - */ - immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ - immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ -} -#endif /* CONFIG_WATCHDOG */ - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ -#if defined(SCC_ENET) && defined(CONFIG_CMD_NET) - scc_initialize(bis); -#endif -#if defined(FEC_ENET) - fec_initialize(bis); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c deleted file mode 100644 index f621d62..0000000 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include -#include - -#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) -DECLARE_GLOBAL_DATA_PTR; -#endif - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ - defined(CONFIG_SYS_SMC_UCODE_PATCH) -void cpm_load_patch (volatile immap_t * immr); -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * immr) -{ - volatile memctl8xx_t *memctl = &immr->im_memctl; -# ifdef CONFIG_SYS_PLPRCR - ulong mfmask; -# endif - ulong reg; - - /* SYPCR - contains watchdog control (11-9) */ - - immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; - -#if defined(CONFIG_WATCHDOG) - reset_8xx_watchdog (immr); -#endif /* CONFIG_WATCHDOG */ - - /* SIUMCR - contains debug pin configuration (11-6) */ - immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; - /* initialize timebase status and control register (11-26) */ - /* unlock TBSCRK */ - - immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; - - /* initialize the PIT (11-31) */ - - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - - /* System integration timers. Don't change EBDF! (15-27) */ - - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; - reg |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = reg; - - /* PLL (CPU clock) settings (15-30) */ - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, - * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF - * field value. - * - * For newer (starting MPC866) chips PLPRCR layout is different. - */ -#ifdef CONFIG_SYS_PLPRCR - if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) - mfmask = PLPRCR_MFACT_MSK; - else - mfmask = PLPRCR_MF_MSK; - - if ((CONFIG_SYS_PLPRCR & mfmask) != 0) - reg = CONFIG_SYS_PLPRCR; /* reset control bits */ - else { - reg = immr->im_clkrst.car_plprcr; - reg &= mfmask; /* isolate MF-related fields */ - reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ - } - immr->im_clkrst.car_plprcr = reg; -#endif - - /* - * Memory Controller: - */ - - /* perform BR0 reset that MPC850 Rev. A can't guarantee */ - reg = memctl->memc_br0; - reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ - reg |= BR_V; /* then add just the "Bank Valid" bit */ - memctl->memc_br0 = reg; - - /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at - * preliminary addresses - these have to be modified later - * when FLASH size has been determined - * - * Depending on the size of the memory region defined by - * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the - * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't - * map CONFIG_SYS_MONITOR_BASE. - * - * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is - * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. - * - * If BR0 wasn't loaded with address base 0xff000000, then BR0's - * base address remains as 0x00000000. However, the address mask - * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped - * into the Bank0. - * - * This is why CONFIG_IVMS8 and similar boards must load BR0 with - * CONFIG_SYS_BR0_PRELIM in advance. - * - * [Thanks to Michael Liao for this explanation. - * I owe him a free beer. - wd] - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; -#endif -#if defined(CONFIG_SYS_OR5_REMAP) - memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; -#endif - - /* now restrict to preliminary range */ - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; - -#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) - memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; - memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) - memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; - memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; -#endif - - /* - * Reset CPM - */ - immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - -#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ - /* write config value */ - immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; -#endif - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ - defined(CONFIG_SYS_SMC_UCODE_PATCH) - cpm_load_patch (immr); /* load mpc8xx microcode patch */ -#endif -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ -#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) - bd_t *bd = gd->bd; - volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); -#endif - -#ifdef CONFIG_SYS_RTCSC - /* Unlock RTSC register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - /* write config value */ - immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC; -#endif - -#ifdef CONFIG_SYS_RMDS - /* write config value */ - immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS; -#endif - return (0); -} diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c deleted file mode 100644 index 34d3647..0000000 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2008 (C) Bryan O'Donoghue - * - * Code copied & edited from Freescale mpc85xx stuff. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void ft_cpu_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", get_tbclk(), 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", - gd->arch.brg_clk, 1); - - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -} diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c deleted file mode 100644 index b27310f..0000000 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ /dev/null @@ -1,933 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -#undef ET_DEBUG - -#if defined(CONFIG_CMD_NET) && \ - (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) - -/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ -#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_ETHER_ON_FEC1 1 -#endif - -/* define WANT_MII when MII support is required */ -#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) -#define WANT_MII -#else -#undef WANT_MII -#endif - -#if defined(WANT_MII) -#include - -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#endif - -#if defined(CONFIG_RMII) && !defined(WANT_MII) -#error RMII support is unusable without a working PHY. -#endif - -#ifdef CONFIG_SYS_DISCOVER_PHY -static int mii_discover_phy(struct eth_device *dev); -#endif - -int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); -int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value); - -static struct ether_fcc_info_s -{ - int ether_index; - int fecp_offset; - int phy_addr; - int actual_phy_addr; - int initialized; -} - ether_fcc_info[] = { -#if defined(CONFIG_ETHER_ON_FEC1) - { - 0, - offsetof(immap_t, im_cpm.cp_fec1), -#if defined(CONFIG_FEC1_PHY) - CONFIG_FEC1_PHY, -#else - -1, /* discover */ -#endif - -1, - 0, - - }, -#endif -#if defined(CONFIG_ETHER_ON_FEC2) - { - 1, - offsetof(immap_t, im_cpm.cp_fec2), -#if defined(CONFIG_FEC2_PHY) - CONFIG_FEC2_PHY, -#else - -1, -#endif - -1, - 0, - }, -#endif -}; - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - -#ifdef __GNUC__ -static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); -#else -#error txbuf must be aligned. -#endif - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx = NULL; - -static int fec_send(struct eth_device *dev, void *packet, int length); -static int fec_recv(struct eth_device* dev); -static int fec_init(struct eth_device* dev, bd_t * bd); -static void fec_halt(struct eth_device* dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -static void __mii_init(void); -#endif - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - struct ether_fcc_info_s *efis; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - hang(); - - memset(dev, 0, sizeof(*dev)); - - /* for FEC1 make sure that the name of the interface is the same - as the old one for compatibility reasons */ - if (i == 0) { - strcpy(dev->name, "FEC"); - } else { - sprintf (dev->name, "FEC%d", - ether_fcc_info[i].ether_index + 1); - } - - efis = ðer_fcc_info[i]; - - /* - * reset actual phy addr - */ - efis->actual_phy_addr = -1; - - dev->priv = efis; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = fec8xx_miiphy_read; - mdiodev->write = fec8xx_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - return 1; -} - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int j, rc; - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { - printf("TX not ready\n"); - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; - __asm__ ("eieio"); - - /* Activate transmit Buffer Descriptor polling */ - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ - - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { - printf("TX timeout\n"); - } -#ifdef ET_DEBUG - printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc, - (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2); -#endif - /* return only status bits */; - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); - - txIdx = (txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -static int fec_recv (struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = - (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); - int length; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - uchar *rx = net_rx_packets[rxIdx]; - - length -= 4; - -#if defined(CONFIG_CMD_CDP) - if ((rx[0] & 1) != 0 && - memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && - !is_cdp_packet((uchar *)rx)) - rx = NULL; -#endif - /* - * Pass the packet up to the protocol layers. - */ - if (rx != NULL) - net_process_received_packet(rx, length); - } - - /* Give the buffer back to the FEC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - - __asm__ ("eieio"); - - /* Try to fill Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ - -#define FEC_ECNTRL_PINMUX 0x00000004 -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -#define FEC_RESET_DELAY 50 - -#if defined(CONFIG_RMII) - -static inline void fec_10Mbps(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - int fecidx = efis->ether_index; - uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; - - if ((unsigned int)fecidx >= 2) - hang(); - - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask; -} - -static inline void fec_100Mbps(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - int fecidx = efis->ether_index; - uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; - - if ((unsigned int)fecidx >= 2) - hang(); - - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask; -} - -#endif - -static inline void fec_full_duplex(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - - fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; - fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ -} - -static inline void fec_half_duplex(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - - fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; - fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ -} - -static void fec_pin_init(int fecidx) -{ - bd_t *bd = gd->bd; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Set MII speed to 2.5 MHz or slightly below. - * - * According to the MPC860T (Rev. D) Fast ethernet controller user - * manual (6.2.14), - * the MII management interface clock must be less than or equal - * to 2.5 MHz. - * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * Then MII_SPEED = system_clock / 2 * 2,5 MHz. - * - * All MII configuration is done via FEC1 registers: - */ - immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; - -#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) - /* use MDC for MII */ - immr->im_ioport.iop_pdpar |= 0x0080; - immr->im_ioport.iop_pddir &= ~0x0080; -#endif - - if (fecidx == 0) { -#if defined(CONFIG_ETHER_ON_FEC1) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - - immr->im_ioport.iop_papar |= 0xf830; - immr->im_ioport.iop_padir |= 0x0830; - immr->im_ioport.iop_padir &= ~0xf000; - - immr->im_cpm.cp_pbpar |= 0x00001001; - immr->im_cpm.cp_pbdir &= ~0x00001001; - - immr->im_ioport.iop_pcpar |= 0x000c; - immr->im_ioport.iop_pcdir &= ~0x000c; - - immr->im_cpm.cp_pepar |= 0x00000003; - immr->im_cpm.cp_pedir |= 0x00000003; - immr->im_cpm.cp_peso &= ~0x00000003; - - immr->im_cpm.cp_cptr &= ~0x00000100; - -#else - -#if !defined(CONFIG_FEC1_PHY_NORXERR) - immr->im_ioport.iop_papar |= 0x1000; - immr->im_ioport.iop_padir &= ~0x1000; -#endif - immr->im_ioport.iop_papar |= 0xe810; - immr->im_ioport.iop_padir |= 0x0810; - immr->im_ioport.iop_padir &= ~0xe000; - - immr->im_cpm.cp_pbpar |= 0x00000001; - immr->im_cpm.cp_pbdir &= ~0x00000001; - - immr->im_cpm.cp_cptr |= 0x00000100; - immr->im_cpm.cp_cptr &= ~0x00000050; - -#endif /* !CONFIG_RMII */ - -#else - /* - * Configure all of port D for MII. - */ - immr->im_ioport.iop_pdpar = 0x1fff; - - /* - * Bits moved from Rev. D onward - */ - if ((get_immr(0) & 0xffff) < 0x0501) - immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ - else - immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ -#endif - -#endif /* CONFIG_ETHER_ON_FEC1 */ - } else if (fecidx == 1) { - -#if defined(CONFIG_ETHER_ON_FEC2) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - immr->im_cpm.cp_pepar |= 0x0003fffc; - immr->im_cpm.cp_pedir |= 0x0003fffc; - immr->im_cpm.cp_peso &= ~0x000087fc; - immr->im_cpm.cp_peso |= 0x00037800; - - immr->im_cpm.cp_cptr &= ~0x00000080; -#else - -#if !defined(CONFIG_FEC2_PHY_NORXERR) - immr->im_cpm.cp_pepar |= 0x00000010; - immr->im_cpm.cp_pedir |= 0x00000010; - immr->im_cpm.cp_peso &= ~0x00000010; -#endif - immr->im_cpm.cp_pepar |= 0x00039620; - immr->im_cpm.cp_pedir |= 0x00039620; - immr->im_cpm.cp_peso |= 0x00031000; - immr->im_cpm.cp_peso &= ~0x00008620; - - immr->im_cpm.cp_cptr |= 0x00000080; - immr->im_cpm.cp_cptr &= ~0x00000028; -#endif /* CONFIG_RMII */ - -#endif /* CONFIG_MPC885_FAMILY */ - -#endif /* CONFIG_ETHER_ON_FEC2 */ - - } -} - -static int fec_reset(volatile fec_t *fecp) -{ - int i; - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) - return -1; - - return 0; -} - -static int fec_init (struct eth_device *dev, bd_t * bd) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile fec_t *fecp = - (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); - int i; - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - /* the MII interface is connected to FEC1 - * so for the miiphy_xxx function to work we must - * call mii_init since fec_halt messes the thing up - */ - if (efis->ether_index != 0) - __mii_init(); -#endif - - if (fec_reset(fecp) < 0) - printf ("FEC_RESET_DELAY timeout\n"); - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffc0; - - /* No need to set the IVEC register */ - - /* Set station address - */ -#define ea dev->enetaddr - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); -#undef ea - -#if defined(CONFIG_CMD_CDP) - /* - * Turn on multicast address hash table - */ - fecp->fec_hash_table_high = 0xffffffff; - fecp->fec_hash_table_low = 0xffffffff; -#else - /* Clear multicast address hash table - */ - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; -#endif - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - - /* Set maximum frame length - */ - fecp->fec_r_hash = PKT_MAXBUF_SIZE; - - /* - * Setup Buffers and Buffer Desriptors - */ - rxIdx = 0; - txIdx = 0; - - if (!rtx) - rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE); - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Last, Tx CRC - */ - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* Set receive and transmit descriptor base - */ - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); - - /* Enable MII mode - */ -#if 0 /* Full duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; -#endif - - /* Enable big endian and don't care about SDMA FC. - */ - fecp->fec_fun_code = 0x78000000; - - /* - * Setup the pin configuration of the FEC - */ - fec_pin_init (efis->ether_index); - - rxIdx = 0; - txIdx = 0; - - /* - * Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; - - if (efis->phy_addr == -1) { -#ifdef CONFIG_SYS_DISCOVER_PHY - /* - * wait for the PHY to wake up after reset - */ - efis->actual_phy_addr = mii_discover_phy (dev); - - if (efis->actual_phy_addr == -1) { - printf ("Unable to discover phy!\n"); - return -1; - } -#else - efis->actual_phy_addr = -1; -#endif - } else { - efis->actual_phy_addr = efis->phy_addr; - } - -#if defined(CONFIG_MII) && defined(CONFIG_RMII) - /* - * adapt the RMII speed to the speed of the phy - */ - if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) { - fec_100Mbps (dev); - } else { - fec_10Mbps (dev); - } -#endif - -#if defined(CONFIG_MII) - /* - * adapt to the half/full speed settings - */ - if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) { - fec_full_duplex (dev); - } else { - fec_half_duplex (dev); - } -#endif - - /* And last, try to fill Rx Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - - efis->initialized = 1; - - return 0; -} - - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); - int i; - - /* avoid halt if initialized; mii gets stuck otherwise */ - if (!efis->initialized) - return; - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - efis->initialized = 0; -} - -#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - -/* Make MII read/write commands for the FEC. -*/ - -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* PHY identification - */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ -#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */ - -/* send command to phy using mii, wait for result */ -static uint -mii_send(uint mii_cmd) -{ - uint mii_reply; - volatile fec_t *ep; - int cnt; - - ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec); - - ep->fec_mii_data = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - cnt = 0; - while (!(ep->fec_ievent & FEC_ENET_MII)) { - if (++cnt > 1000) { - printf("mii_send STUCK!\n"); - break; - } - } - mii_reply = ep->fec_mii_data; /* result from phy */ - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ -#if 0 - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply); -#endif - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif - -#if defined(CONFIG_SYS_DISCOVER_PHY) -static int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - uint phyno; - int pass; - uint phytype; - int phyaddr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type ", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype |= mii_send(mk_mii_read(phyno, - MII_PHYSID1)) << 16; - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ",phyno,pass); - switch (phytype & 0xfffffff0) { - case PHY_ID_LXT970: - printf("LXT970\n"); - break; - case PHY_ID_LXT971: - printf("LXT971\n"); - break; - case PHY_ID_82555: - printf("82555\n"); - break; - case PHY_ID_QS6612: - printf("QS6612\n"); - break; - case PHY_ID_AMD79C784: - printf("AMD79C784\n"); - break; - case PHY_ID_LSI80225B: - printf("LSI L80225/B\n"); - break; - case PHY_ID_DM9161: - printf("Davicom DM9161\n"); - break; - case PHY_ID_KSM8995M: - printf("MICREL KS8995M\n"); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) { - printf("No PHY device found.\n"); - } - return phyaddr; -} -#endif /* CONFIG_SYS_DISCOVER_PHY */ - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) - -/**************************************************************************** - * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -static void __mii_init(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile fec_t *fecp = &(immr->im_cpm.cp_fec); - - if (fec_reset(fecp) < 0) - printf ("FEC_RESET_DELAY timeout\n"); - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffc0; - - /* Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; -} - -void mii_init (void) -{ - int i; - - __mii_init(); - - /* Setup the pin configuration of the FEC(s) - */ - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - fec_pin_init(ether_fcc_info[i].ether_index); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - unsigned short value = 0; - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - value = rdreg; -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - return value; -} - -int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value) -{ -#ifdef MII_DEBUG - printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - (void)mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - return 0; -} -#endif - -#endif diff --git a/arch/powerpc/cpu/mpc8xx/fec.h b/arch/powerpc/cpu/mpc8xx/fec.h deleted file mode 100644 index e025c3f..0000000 --- a/arch/powerpc/cpu/mpc8xx/fec.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FEC_H_ -#define _FEC_H_ - - -#endif /* _FEC_H_ */ diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c deleted file mode 100644 index 482ceec..0000000 --- a/arch/powerpc/cpu/mpc8xx/interrupts.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************************************************************/ - -/* - * CPM interrupt vector functions. - */ -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; -}; - -static struct interrupt_action cpm_vecs[CPMVEC_NR]; -static struct interrupt_action irq_vecs[NR_IRQS]; - -static void cpm_interrupt_init (void); -static void cpm_interrupt (void *regs); - -/************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; - - /* disable all interrupts */ - immr->im_siu_conf.sc_simask = 0; - - /* Configure CPM interrupts */ - cpm_interrupt_init (); - - return (0); -} - -/************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - int irq; - ulong simask, newmask; - ulong vec, v_bit; - - /* - * read the SIVEC register and shift the bits down - * to get the irq number - */ - vec = immr->im_siu_conf.sc_sivec; - irq = vec >> 26; - v_bit = 0x80000000UL >> irq; - - /* - * Read Interrupt Mask Register and Mask Interrupts - */ - simask = immr->im_siu_conf.sc_simask; - newmask = simask & (~(0xFFFF0000 >> irq)); - immr->im_siu_conf.sc_simask = newmask; - - if (!(irq & 0x1)) { /* External Interrupt ? */ - ulong siel; - - /* - * Read Interrupt Edge/Level Register - */ - siel = immr->im_siu_conf.sc_siel; - - if (siel & v_bit) { /* edge triggered interrupt ? */ - /* - * Rewrite SIPEND Register to clear interrupt - */ - immr->im_siu_conf.sc_sipend = v_bit; - } - } - - if (irq_vecs[irq].handler != NULL) { - irq_vecs[irq].handler (irq_vecs[irq].arg); - } else { - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", - irq, vec); - /* turn off the bogus interrupt to avoid it from now */ - simask &= ~v_bit; - } - /* - * Re-Enable old Interrupt Mask - */ - immr->im_siu_conf.sc_simask = simask; -} - -/************************************************************************/ - -/* - * CPM interrupt handler - */ -static void cpm_interrupt (void *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - uint vec; - - /* - * Get the vector by setting the ACK bit - * and then reading the register. - */ - immr->im_cpic.cpic_civr = 1; - vec = immr->im_cpic.cpic_civr; - vec >>= 11; - - if (cpm_vecs[vec].handler != NULL) { - (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); - } else { - immr->im_cpic.cpic_cimr &= ~(1 << vec); - printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); - } - /* - * After servicing the interrupt, - * we have to remove the status indicator. - */ - immr->im_cpic.cpic_cisr |= (1 << vec); -} - -/* - * The CPM can generate the error interrupt when there is a race - * condition between generating and masking interrupts. All we have - * to do is ACK it and return. This is a no-op function so we don't - * need any special tests in the interrupt handler. - */ -static void cpm_error_interrupt (void *dummy) -{ -} - -/************************************************************************/ -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, - void *arg) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - if ((vec & CPMVEC_OFFSET) != 0) { - /* CPM interrupt */ - vec &= 0xffff; - if (cpm_vecs[vec].handler != NULL) { - printf ("CPM interrupt 0x%x replacing 0x%x\n", - (uint) handler, - (uint) cpm_vecs[vec].handler); - } - cpm_vecs[vec].handler = handler; - cpm_vecs[vec].arg = arg; - immr->im_cpic.cpic_cimr |= (1 << vec); -#if 0 - printf ("Install CPM interrupt for vector %d ==> %p\n", - vec, handler); -#endif - } else { - /* SIU interrupt */ - if (irq_vecs[vec].handler != NULL) { - printf ("SIU interrupt %d 0x%x replacing 0x%x\n", - vec, - (uint) handler, - (uint) cpm_vecs[vec].handler); - } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; - immr->im_siu_conf.sc_simask |= 1 << (31 - vec); -#if 0 - printf ("Install SIU interrupt for vector %d ==> %p\n", - vec, handler); -#endif - } -} - -void irq_free_handler (int vec) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - if ((vec & CPMVEC_OFFSET) != 0) { - /* CPM interrupt */ - vec &= 0xffff; -#if 0 - printf ("Free CPM interrupt for vector %d ==> %p\n", - vec, cpm_vecs[vec].handler); -#endif - immr->im_cpic.cpic_cimr &= ~(1 << vec); - cpm_vecs[vec].handler = NULL; - cpm_vecs[vec].arg = NULL; - } else { - /* SIU interrupt */ -#if 0 - printf ("Free CPM interrupt for vector %d ==> %p\n", - vec, cpm_vecs[vec].handler); -#endif - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; - } -} - -/************************************************************************/ - -static void cpm_interrupt_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* - * Initialize the CPM interrupt controller. - */ - - immr->im_cpic.cpic_cicr = - (CICR_SCD_SCC4 | - CICR_SCC_SCC3 | - CICR_SCB_SCC2 | - CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; - - immr->im_cpic.cpic_cimr = 0; - - /* - * Install the error handler. - */ - irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); - - immr->im_cpic.cpic_cicr |= CICR_IEN; - - /* - * Install the cpm interrupt handler - */ - irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); -} - -/************************************************************************/ - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void timer_interrupt_cpu (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if 0 - printf ("*** Timer Interrupt *** "); -#endif - /* Reset Timer Expired and Timers Interrupt Status */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - __asm__ ("nop"); - /* - Clear TEXPS (and TMIST on older chips). SPLSS (on older - chips) is cleared too. - - Bitwise OR is a read-modify-write operation so ALL bits - which are cleared by writing `1' would be cleared by - operations like - - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; - - The same can be achieved by simple writing of the PLPRCR - to itself. If a bit value should be preserved, read the - register, ZERO the bit and write, not OR, the result back. - */ - immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; -} - -/************************************************************************/ diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S deleted file mode 100644 index 0ea1a06..0000000 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include -#include - -#include -#include - -#if defined(CONFIG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 - sync - lis r3, IDC_INVALL@h - mtspr IC_CST, r3 - SYNC - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CONFIG_SYS_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CONFIG_SYS_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CONFIG_SYS_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif diff --git a/arch/powerpc/cpu/mpc8xx/plprcr_write.S b/arch/powerpc/cpu/mpc8xx/plprcr_write.S deleted file mode 100644 index e28292f..0000000 --- a/arch/powerpc/cpu/mpc8xx/plprcr_write.S +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define CACHE_CMD_ENABLE 0x02000000 -#define CACHE_CMD_DISABLE 0x04000000 -#define CACHE_CMD_LOAD_LOCK 0x06000000 -#define CACHE_CMD_UNLOCK_LINE 0x08000000 -#define CACHE_CMD_UNLOCK_ALL 0x0A000000 -#define CACHE_CMD_INVALIDATE 0x0C000000 -#define SPEED_PLPRCR_WAIT_5CYC 150 -#define _CACHE_ALIGN_SIZE 16 - - - .text - .align 2 - .globl plprcr_write_866 - -/* - * void plprcr_write_866 (long plprcr) - * Write PLPRCR, including workaround for device errata SIU4 and SIU9. - */ - -plprcr_write_866: - mfspr r10, LR /* save the Link Register value */ - - /* turn instruction cache on (no MMU required for instructions) - */ - lis r4, CACHE_CMD_ENABLE@h - ori r4, r4, CACHE_CMD_ENABLE@l - mtspr IC_CST, r4 - isync - - /* clear IC_CST error bits - */ - mfspr r4, IC_CST - - bl plprcr_here - -plprcr_here: - mflr r5 - - /* calculate relocation offset - */ - lis r4, plprcr_here@h - ori r4, r4, plprcr_here@l - sub r5, r5, r4 - - /* calculate first address of this function - */ - lis r6, plprcr_write_866@h - ori r6, r6, plprcr_write_866@l - add r6, r6, r5 - - /* calculate end address of this function - */ - lis r7, plprcr_end@h - ori r7, r7, plprcr_end@l - add r7, r7, r5 - - /* load and lock code addresses - */ - mr r5, r6 - -plprcr_loop: - mtspr IC_ADR, r5 - addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */ - - lis r4, CACHE_CMD_LOAD_LOCK@h - ori r4, r4, CACHE_CMD_LOAD_LOCK@l - mtspr IC_CST, r4 - isync - - cmpw r5, r7 - blt plprcr_loop - - /* IC_CST error bits not evaluated - */ - - /* switch PLPRCR - */ - mfspr r4, IMMR /* read IMMR */ - rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */ - - /* write sequence according to MPC866 Errata - */ - stw r3, PLPRCR(r4) - isync - - lis r3, SPEED_PLPRCR_WAIT_5CYC@h - ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l - -plprcr_wait: - cmpwi r3, 0 - beq plprcr_wait_end - nop - subi r3, r3, 1 - b plprcr_wait - -plprcr_wait_end: - - /* unlock instruction cache but leave it enabled - */ - lis r4, CACHE_CMD_UNLOCK_ALL@h - ori r4, r4, CACHE_CMD_UNLOCK_ALL@l - mtspr IC_CST, r4 - isync - - mtspr LR, r10 /* restore original Link Register value */ - blr - -plprcr_end: diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c deleted file mode 100644 index 17bcc2f..0000000 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * File: scc.c - * Description: - * Basic ET HW initialization and packet RX/TX routines - * - * NOTE <<>>: - * Do not cache Rx/Tx buffers! - */ - -/* - * MPC823 <-> MC68160 Connections: - * - * Setup MPC823 to work with MC68160 Enhanced Ethernet - * Serial Tranceiver as follows: - * - * MPC823 Signal MC68160 Comments - * ------ ------ ------- -------- - * PA-12 ETHTX --------> TX Eth. Port Transmit Data - * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable - * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock - * PA-13 ETHRX <-------- RX Eth. Port Receive Data - * PC-8 E_RENA <-------- RENA Eth. Receive Enable - * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock - * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication - * - * FADS Board Signal MC68160 Comments - * ----------------- ------- -------- - * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable - * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable - * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex - * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back - * - */ - -#include -#include -#include -#include -#include - -#if defined(CONFIG_CMD_NET) && defined(SCC_ENET) - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */ - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - -static int scc_send(struct eth_device *dev, void *packet, int length); -static int scc_recv(struct eth_device* dev); -static int scc_init (struct eth_device* dev, bd_t * bd); -static void scc_halt(struct eth_device* dev); - -int scc_initialize(bd_t *bis) -{ - struct eth_device* dev; - - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - strcpy(dev->name, "SCC"); - dev->iobase = 0; - dev->priv = 0; - dev->init = scc_init; - dev->halt = scc_halt; - dev->send = scc_send; - dev->recv = scc_recv; - - eth_register(dev); - - return 1; -} - -static int scc_send(struct eth_device *dev, void *packet, int length) -{ - int i, j=0; -#if 0 - volatile char *in, *out; -#endif - - /* section 16.9.23.3 - * Wait for ready - */ -#if 0 - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); - out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); - in = packet; - for(i = 0; i < length; i++) { - *out++ = *in++; - } - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; - -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - - /* wrap around buffer index when necessary */ - if (txIdx >= TX_BUF_CNT) txIdx = 0; -#endif - - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX timeout\n"); -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - return i; -} - -static int scc_recv (struct eth_device *dev) -{ - int length; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], - length - 4); - } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ - -static int scc_init (struct eth_device *dev, bd_t * bis) -{ - - int i; - scc_enet_t *pram_ptr; - - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); - - rxIdx = 0; - txIdx = 0; - - if (!rtx) - rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_SCC_BASE); - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdir |= PC_ENET_LBK; - immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = - (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) - */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - -#define ea eth_get_ethaddr() - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* - * Enter Command: Initialize Tx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Mask all Events in SCCM - we use polling mode - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; - - /* - * Clear Events in SCCE -- Clear bits by writing 1's - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * FDE = Full Duplex Enable - * LPB = Loopback Enable (Needed when FDE is set) - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packets regardless of dest. MAC adress - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | -#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) - SCC_PSMR_FDE | SCC_PSMR_LPB | -#endif -#if defined(CONFIG_SCC_ENET_NO_BROADCAST) - SCC_PSMR_BRO | -#endif -#if defined(CONFIG_SCC_ENET_PROMISCOUS) - SCC_PSMR_PRO | -#endif - 0; - - /* - * Configure Ethernet TENA Signal - */ - -#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) - immr->im_ioport.iop_pcpar |= PC_ENET_TENA; - immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) - immr->im_cpm.cp_pbpar |= PB_ENET_TENA; - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; -#else -#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif - - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - return 1; -} - - -static void scc_halt (struct eth_device *dev) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); -} - -#if 0 -void restart (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} -#endif -#endif diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c deleted file mode 100644 index b6e12d0..0000000 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ /dev/null @@ -1,676 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ - -#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ -#define SMC_INDEX 1 -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 - -#endif /* CONFIG_8xx_CONS_SMCx */ - -#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC1 - -#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC2 - -#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC3 - -#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC4 - -#endif /* CONFIG_8xx_CONS_SCCx */ - -#if !defined(CONFIG_SYS_SMC_RXBUFLEN) -#define CONFIG_SYS_SMC_RXBUFLEN 1 -#define CONFIG_SYS_MAXIDLE 0 -#else -#if !defined(CONFIG_SYS_MAXIDLE) -#error "you must define CONFIG_SYS_MAXIDLE" -#endif -#endif - -typedef volatile struct serialbuffer { - cbd_t rxbd; /* Rx BD */ - cbd_t txbd; /* Tx BD */ - uint rxindex; /* index for next character to read */ - volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ - volatile uchar txbuf; /* tx buffers */ -} serialbuffer_t; - -static void serial_setdivisor(volatile cpm8xx_t *cp) -{ - int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; - - if(divisor/16>0x1000) { - /* bad divisor, assume 50MHz clock and 9600 baud */ - divisor=(50*1000*1000 + 8*9600)/16/9600; - } - -#ifdef CONFIG_SYS_BRGCLK_PRESCALE - divisor /= CONFIG_SYS_BRGCLK_PRESCALE; -#endif - - if(divisor<=0x1000) { - cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; - } else { - cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; - } -} - -#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -static void smc_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SMCx - */ - - cp->cp_simode = 0x00000000; - - serial_setdivisor(cp); -} - -static int smc_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cpm8xx_t *cp = &(im->im_cpm); -#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) - volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); -#endif - uint dpaddr; - volatile serialbuffer_t *rtx; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; -#else - /* Disable relocation */ - up->smc_rpbase = 0; -#endif - - /* Disable transmitter/receiver. */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - -#if defined(CONFIG_8xx_CONS_SMC1) - /* Use Port B for SMC1 instead of other functions. */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; -#else /* CONFIG_8xx_CONS_SMC2 */ -# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - /* Use Port A for SMC2 instead of other functions. */ - ip->iop_papar |= 0x00c0; - ip->iop_padir &= ~0x00c0; - ip->iop_paodr &= ~0x00c0; -# else /* must be a 860 then */ - /* Use Port B for SMC2 instead of other functions. - */ - cp->cp_pbpar |= 0x00000c00; - cp->cp_pbdir &= ~0x00000c00; - cp->cp_pbodr &= ~0x00000c00; -# endif -#endif - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - dpaddr = CPM_SERIAL_BASE; - - rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr]; - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; - rtx->rxbd.cbd_sc = 0; - - rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; - rtx->txbd.cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; -#if defined (CONFIG_SYS_SMC_UCODE_PATCH) - up->smc_rbptr = up->smc_rbase; - up->smc_tbptr = up->smc_tbase; - up->smc_rstate = 0; - up->smc_tstate = 0; -#endif - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - -#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4 - /* clock source is PLD */ - - /* set freq to 19200 Baud */ - *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3; - /* configure clk4 as input */ - im->im_ioport.iop_pdpar |= 0x800; - im->im_ioport.iop_pddir &= ~0x800; - - cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); -#else - /* Set up the baud rate generator */ - smc_setbrg (); -#endif - - /* Make the first buffer the only buffer. */ - rtx->txbd.cbd_sc |= BD_SC_WRAP; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* single/multi character receive. */ - up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; - up->smc_maxidl = CONFIG_SYS_MAXIDLE; - rtx->rxindex = 0; - - /* Initialize Tx/Rx parameters. */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -static void -smc_putc(const char c) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - volatile serialbuffer_t *rtx; - - if (c == '\n') - smc_putc ('\r'); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif - - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for last character to go. */ - rtx->txbuf = c; - rtx->txbd.cbd_datlen = 1; - rtx->txbd.cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (rtx->txbd.cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -static void -smc_puts (const char *s) -{ - while (*s) { - smc_putc (*s++); - } -} - -static int -smc_getc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - volatile serialbuffer_t *rtx; - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. */ - while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - /* the characters are read one by one, - * use the rxindex to know the next char to deliver - */ - c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex); - rtx->rxindex++; - - /* check if all char are readout, then make prepare for next receive */ - if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { - rtx->rxindex = 0; - rtx->rxbd.cbd_sc |= BD_SC_EMPTY; - } - return(c); -} - -static int -smc_tstc(void) -{ - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - volatile serialbuffer_t *rtx; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif - - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); -} - -struct serial_device serial_smc_device = -{ - .name = "serial_smc", - .start = smc_init, - .stop = NULL, - .setbrg = smc_setbrg, - .getc = smc_getc, - .tstc = smc_tstc, - .putc = smc_putc, - .puts = smc_puts, -}; - -#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ - -#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ - defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - -static void -scc_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCx - */ - - cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); - - serial_setdivisor(cp); -} - -static int scc_init (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; -#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) - volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); -#endif - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); - up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; - - /* Disable transmitter/receiver. */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - -#if (SCC_INDEX == 2) && defined(CONFIG_MPC850) - /* - * The MPC850 has SCC3 on Port B - */ - cp->cp_pbpar |= 0x06; - cp->cp_pbdir &= ~0x06; - cp->cp_pbodr &= ~0x06; - -#elif (SCC_INDEX < 2) - /* - * Standard configuration for SCC's is on Part A - */ - ip->iop_papar |= ((3 << (2 * SCC_INDEX))); - ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); - ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); -#endif - - /* Allocate space for two buffer descriptors in the DP ram. */ - dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8); - - /* Enable SDMA. */ - im->im_siu_conf.sc_sdcr = 0x0001; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the baud rate generator. */ - scc_setbrg (); - - /* Set up the uart parameters in the parameter ram. */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - - /* Initialize Tx/Rx parameters. */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - up->scc_genscc.scc_rfcr = SCC_EB | 0x05; - up->scc_genscc.scc_tfcr = SCC_EB | 0x05; - - up->scc_genscc.scc_mrblr = 1; /* Single character receive */ - up->scc_maxidl = 0; /* disable max idle */ - up->scc_brkcr = 1; /* send one break character on stop TX */ - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = 0x8000; - up->scc_char2 = 0x8000; - up->scc_char3 = 0x8000; - up->scc_char4 = 0x8000; - up->scc_char5 = 0x8000; - up->scc_char6 = 0x8000; - up->scc_char7 = 0x8000; - up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Set low latency / small fifo. */ - sp->scc_gsmrh = SCC_GSMRH_RFW; - - /* Set SCC(x) clock mode to 16x - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCn - */ - - /* Set UART mode, clock divider 16 on Tx and Rx */ - sp->scc_gsmrl &= ~0xF; - sp->scc_gsmrl |= - (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - sp->scc_psmr = 0; - sp->scc_psmr |= SCU_PSMR_CL; - - /* Mask all interrupts and remove anything pending. */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - sp->scc_dsr = 0x7e7e; - sp->scc_psmr = 0x3000; - - /* Make the first buffer the only buffer. */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Enable transmitter/receiver. */ - sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - return (0); -} - -static void -scc_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - if (c == '\n') - scc_putc ('\r'); - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - __asm__("eieio"); - WATCHDOG_RESET (); - } -} - -static void -scc_puts (const char *s) -{ - while (*s) { - scc_putc (*s++); - } -} - -static int -scc_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -static int -scc_tstc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -struct serial_device serial_scc_device = -{ - .name = "serial_scc", - .start = scc_init, - .stop = NULL, - .setbrg = scc_setbrg, - .getc = scc_getc, - .tstc = scc_tstc, - .putc = scc_putc, - .puts = scc_puts, -}; - -#endif /* CONFIG_8xx_CONS_SCCx */ - -__weak struct serial_device *default_serial_console(void) -{ -#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) - return &serial_smc_device; -#else - return &serial_scc_device; -#endif -} - -void mpc8xx_serial_initialize(void) -{ -#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) - serial_register(&serial_smc_device); -#endif -#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ - defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - serial_register(&serial_scc_device); -#endif -} - -#if defined(CONFIG_CMD_KGDB) - -void -kgdb_serial_init(void) -{ - int i = -1; - - if (strcmp(default_serial_console()->name, "serial_smc") == 0) - { -#if defined(CONFIG_8xx_CONS_SMC1) - i = 1; -#elif defined(CONFIG_8xx_CONS_SMC2) - i = 2; -#endif - } - else if (strcmp(default_serial_console()->name, "serial_scc") == 0) - { -#if defined(CONFIG_8xx_CONS_SCC1) - i = 1; -#elif defined(CONFIG_8xx_CONS_SCC2) - i = 2; -#elif defined(CONFIG_8xx_CONS_SCC3) - i = 3; -#elif defined(CONFIG_8xx_CONS_SCC4) - i = 4; -#endif - } - - if (i >= 0) - { - serial_printf("[on %s%d] ", default_serial_console()->name, i); - } -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif - -#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c deleted file mode 100644 index e2295d2..0000000 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG) - -#define PITC_SHIFT 16 -#define PITR_SHIFT 16 -/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */ -#define SPEED_PIT_COUNTS 58 -#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT) -#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT) - -/* Access functions for the Machine State Register */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Measure CPU clock speed (core clock GCLK1, GCLK2), - * also determine bus clock speed (checking bus divider factor) - * - * (Approx. GCLK frequency in Hz) - * - * Initializes timer 2 and PIT, but disables them before return. - * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4] - * - * When measuring the CPU clock against the PIT, we count cpu clocks - * for 58/8192 seconds with a prescale divide by 177 for the cpu clock. - * These strange values for the timing interval and prescaling are used - * because the formula for the CPU clock is: - * - * CPU clock = count * (177 * (8192 / 58)) - * - * = count * 24999.7241 - * - * which is very close to - * - * = count * 25000 - * - * Since the count gives the CPU clock divided by 25000, we can get - * the CPU clock rounded to the nearest 0.1 MHz by - * - * CPU clock = ((count + 2) / 4) * 100000; - * - * The rounding is important since the measurement is sometimes going - * to be high or low by 0.025 MHz, depending on exactly how the clocks - * and counters interact. By rounding we get the exact answer for any - * CPU clock that is an even multiple of 0.1 MHz. - */ - -unsigned long measure_gclk(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; - ulong timer2_val; - ulong msr_val; - -#ifdef CONFIG_SYS_8XX_XIN - /* dont use OSCM, only use EXTCLK/512 */ - immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; -#else - immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV); -#endif - - /* Reset + Stop Timer 2, no cascading - */ - timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2); - - /* Keep stopped, halt in debug mode - */ - timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2); - - /* Timer 2 setup: - * Output ref. interrupt disable, int. clock - * Prescale by 177. Note that prescaler divides by value + 1 - * so we must subtract 1 here. - */ - timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN; - - timerp->cpmt_tcn2 = 0; /* reset state */ - timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */ - - /* - * PIT setup: - * - * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz), - * so the count value would be SPEED_PITC_COUNTS - 1. - * But there would be an uncertainty in the start time of 1/4 - * count since when we enable the PIT the count is not - * synchronized to the 32768 Hz oscillator. The trick here is - * to start the count higher and wait until the PIT count - * changes to the required value before starting timer 2. - * - * One count high should be enough, but occasionally the start - * is off by 1 or 2 counts of 32768 Hz. With the start value - * set two counts high it seems very reliable. - */ - - immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */ - immr->im_sit.sit_pitc = SPEED_PITC_INIT; - - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; - - /* - * Start measurement - disable interrupts, just in case - */ - msr_val = get_msr (); - set_msr (msr_val & ~MSR_EE); - - immr->im_sit.sit_piscr |= PISCR_PTE; - - /* spin until get exact count when we want to start */ - while (immr->im_sit.sit_pitr > SPEED_PITC); - - timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */ - while ((immr->im_sit.sit_piscr & PISCR_PS) == 0); - timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */ - - /* re-enable external interrupts if they were on */ - set_msr (msr_val); - - /* Disable timer and PIT - */ - timer2_val = timerp->cpmt_tcn2; /* save before reset timer */ - - timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); - immr->im_sit.sit_piscr &= ~PISCR_PTE; - -#if defined(CONFIG_SYS_8XX_XIN) - /* not using OSCM, using XIN, so scale appropriately */ - return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L; -#else - return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ -#endif -} - -#endif - -void get_brgclk(uint sccr) -{ - uint divider = 0; - - switch((sccr&SCCR_DFBRG11)>>11){ - case 0: - divider = 1; - break; - case 1: - divider = 4; - break; - case 2: - divider = 16; - break; - case 3: - divider = 64; - break; - } - gd->arch.brg_clk = gd->cpu_clk/divider; -} - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) - -/* - * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ - * or (if it is not defined) measure_gclk() (which uses the ref clock) - * from above. - */ -int get_clocks (void) -{ - uint immr = get_immr (0); /* Return full IMMR contents */ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint sccr = immap->im_clkrst.car_sccr; - /* - * If for some reason measuring the gclk frequency won't - * work, we return the hardwired value. - * (For example, the cogent CMA286-60 CPU module has no - * separate oscillator for PITRTCLK) - */ -#if defined(CONFIG_8xx_GCLK_FREQ) - gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; -#elif defined(CONFIG_8xx_OSCLK) -#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) - uint pll = immap->im_clkrst.car_plprcr; - uint clk; - - if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ - clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) * - (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) / - (1<cpu_clk = clk / (2 << ((sccr >> 8) & 7)); - } else { /* High frequency division factor is used */ - gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7)); - } -#else - gd->cpu_clk = measure_gclk(); -#endif /* CONFIG_8xx_GCLK_FREQ */ - - if ((sccr & SCCR_EBDF11) == 0) { - /* No Bus Divider active */ - gd->bus_clk = gd->cpu_clk; - } else { - /* The MPC8xx has only one BDF: half clock speed */ - gd->bus_clk = gd->cpu_clk / 2; - } - - get_brgclk(sccr); - - return (0); -} - -#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */ - -static long init_pll_866 (long clk); - -/* Adjust sdram refresh rate to actual CPU clock. - */ -static int sdram_adjust_866(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - long mamr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - return 0; -} - -/* - * Adjust sdram refresh rate to actual CPU clock - * and set timebase source according to actual CPU clock - */ -static int adjust_sdram_tbs_8xx(void) -{ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \ - !defined(CONFIG_TQM885D) - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - long mamr; - long sccr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - if (gd->cpu_clk < 67000000) { - sccr = immr->im_clkrst.car_sccr; - sccr |= SCCR_TBS; - immr->im_clkrst.car_sccr = sccr; - } -#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ - - return 0; -} - -/* This function sets up PLL (init_pll_866() is called) and - * fills gd->cpu_clk and gd->bus_clk according to the environment - * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' - * contains invalid value). - * This functions requires an MPC866 or newer series CPU. - */ -int get_clocks(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - char tmp[64]; - long cpuclk = 0; - long sccr_reg; - int ret; - - if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - - if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk)) - cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; - - gd->cpu_clk = init_pll_866 (cpuclk); -#if defined(CONFIG_SYS_MEASURE_CPUCLK) - gd->cpu_clk = measure_gclk (); -#endif - - get_brgclk(immr->im_clkrst.car_sccr); - - /* if cpu clock <= 66 MHz then set bus division factor to 1, - * otherwise set it to 2 - */ - sccr_reg = immr->im_clkrst.car_sccr; - sccr_reg &= ~SCCR_EBDF11; - - if (gd->cpu_clk <= 66000000) { - sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ - gd->bus_clk = gd->cpu_clk; - } else { - sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */ - gd->bus_clk = gd->cpu_clk / 2; - } - immr->im_clkrst.car_sccr = sccr_reg; - - ret = sdram_adjust_866(); - if (ret) - return ret; - - return adjust_sdram_tbs_8xx(); -} - -/* Configure PLL for MPC866/859/885 CPU series - * PLL multiplication factor is set to the value nearest to the desired clk, - * assuming a oscclk of 10 MHz. - */ -static long init_pll_866 (long clk) -{ - extern void plprcr_write_866 (long); - - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - long n, plprcr; - char mfi, mfn, mfd, s, pdf; - long step_mfi, step_mfn; - - if (clk < 20000000) { - clk *= 2; - pdf = 1; - } else { - pdf = 0; - } - - if (clk < 40000000) { - s = 2; - step_mfi = CONFIG_8xx_OSCLK / 4; - mfd = 7; - step_mfn = CONFIG_8xx_OSCLK / 30; - } else if (clk < 80000000) { - s = 1; - step_mfi = CONFIG_8xx_OSCLK / 2; - mfd = 14; - step_mfn = CONFIG_8xx_OSCLK / 30; - } else { - s = 0; - step_mfi = CONFIG_8xx_OSCLK; - mfd = 29; - step_mfn = CONFIG_8xx_OSCLK / 30; - } - - /* Calculate integer part of multiplication factor - */ - n = clk / step_mfi; - mfi = (char)n; - - /* Calculate numerator of fractional part of multiplication factor - */ - n = clk - (n * step_mfi); - mfn = (char)(n / step_mfn); - - /* Calculate effective clk - */ - n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1); - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK - | PLPRCR_MFD_MSK | PLPRCR_S_MSK - | PLPRCR_MFI_MSK | PLPRCR_DBRMO - | PLPRCR_PDF_MSK)) - | (mfn << PLPRCR_MFN_SHIFT) - | (mfd << PLPRCR_MFD_SHIFT) - | (s << PLPRCR_S_SHIFT) - | (mfi << PLPRCR_MFI_SHIFT) - | (pdf << PLPRCR_PDF_SHIFT); - - if( (mfn > 0) && ((mfd / mfn) > 10) ) - plprcr |= PLPRCR_DBRMO; - - plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */ - immr->im_clkrstk.cark_plprcrk = 0x00000000; - - return (n); -} - -#endif /* CONFIG_8xx_CPUCLK_DEFAULT */ diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c deleted file mode 100644 index 35b425e..0000000 --- a/arch/powerpc/cpu/mpc8xx/spi.c +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * , - * - * Copyright (c) 2001 Gerd Mennchen - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI) - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f (void) -{ - unsigned int dpaddr; - - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpm8xx_t *cp; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - cp->cp_pbpar |= 0x0000000E; /* set bits */ - cp->cp_pbpar &= ~0x00000001; /* reset bit */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - cp->cp_pbdir |= 0x0000000F; - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - cp->cp_pbodr |= 0x00000008; - cp->cp_pbodr &= ~0x00000007; - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - spi->spi_rstate = 0; - spi->spi_rdp = 0; - spi->spi_rbptr = 0; - spi->spi_rbc = 0; - spi->spi_rxtmp = 0; - spi->spi_tstate = 0; - spi->spi_tdp = 0; - spi->spi_tbptr = 0; - spi->spi_tbc = 0; - spi->spi_txtmp = 0; - - dpaddr = CPM_SPI_BASE; - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - spi->spi_rbase = dpaddr; - spi->spi_tbase = dpaddr + sizeof (cbd_t); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - spi->spi_rbptr = spi->spi_rbase; - spi->spi_tbptr = spi->spi_tbase; - -/* 4 */ -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - /* - * Initialize required parameters if using microcode patch. - */ - spi->spi_rstate = 0; - spi->spi_tstate = 0; -#else - /* Init SPI Tx + Rx Parameters */ - while (cp->cp_cpcr & CPM_CR_FLG) - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG) - ; -#endif /* CONFIG_SYS_SPI_UCODE_PATCH */ - -/* 5 */ - /* Set SDMA configuration register */ - immr->im_siu_conf.sc_sdcr = 0x0001; - -/* 6 */ - /* Set to big endian. */ - spi->spi_tfcr = SMC_EB; - spi->spi_rfcr = SMC_EB; - -/* 7 */ - /* Set maximum receive size. */ - spi->spi_mrblr = MAX_BUFFER; - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - tbdf->cbd_sc &= ~BD_SC_READY; - rbdf->cbd_sc &= ~BD_SC_EMPTY; - - /* Set the bd's rx and tx buffer address pointers */ - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - -/* 10 + 11 */ - cp->cp_spim = 0; /* Mask all SPI events */ - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r (void) -{ - volatile cpm8xx_t *cp; - volatile spi_t *spi; - volatile immap_t *immr; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *) malloc (MAX_BUFFER); - txbuf = (uchar *) malloc (MAX_BUFFER); - - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile cpm8xx_t *cp; - volatile spi_t *spi; - cbd_t *tbdf, *rbdf; - ushort loop; - int tm; - - DPRINT (("*** spi_xfer entered ***\n")); - - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - /* Set CS for device */ - cp->cp_pbdat &= ~0x0001; - - /* Setting tx bd status and data length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; - tbdf->cbd_datlen = count; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", - tbdf->cbd_datlen)); - - /* Setting rx bd status and data length */ - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - rbdf->cbd_datlen = 0; /* rx length has no significance */ - - loop = cp->cp_spmode & SPMODE_LOOP; - cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */ - loop | - SPMODE_REV | - SPMODE_MSTR | - SPMODE_EN | - SPMODE_LEN(8) | /* 8 Bits per char */ - SPMODE_PM(0x8) ; /* medium speed */ - cp->cp_spim = 0; /* Mask all SPI events */ - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - cp->cp_spcom |= SPI_STR; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */ - DPRINT (("*** spi_xfer: Tx buffer empty\n")); - break; - } - if ((tbdf->cbd_sc & BD_SC_READY) == 0) { - DPRINT (("*** spi_xfer: Tx BD done\n")); - break; - } - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } - DPRINT (("*** spi_xfer: ... transfer ended\n")); - -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ - printf ("\n"); -#endif - - /* Clear CS for device */ - cp->cp_pbdat |= 0x0001; - - return count; -} -#endif /* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */ - -/* - * SPI test - * - * The Serial Peripheral Interface (SPI) is tested in the local loopback mode. - * The interface is configured accordingly and several packets - * are transferred. The configurable test parameters are: - * TEST_MIN_LENGTH - minimum size of packet to transfer - * TEST_MAX_LENGTH - maximum size of packet to transfer - * TEST_NUM - number of tests - */ - -#if CONFIG_POST & CONFIG_SYS_POST_SPI - -#define TEST_MIN_LENGTH 1 -#define TEST_MAX_LENGTH MAX_BUFFER -#define TEST_NUM 1 - -static void packet_fill (char * packet, int length) -{ - char c = (char) length; - int i; - - for (i = 0; i < length; i++) - { - packet[i] = c++; - } -} - -static int packet_check (char * packet, int length) -{ - char c = (char) length; - int i; - - for (i = 0; i < length; i++) { - if (packet[i] != c++) return -1; - } - - return 0; -} - -int spi_post_test (int flags) -{ - int res = -1; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm; - int i; - int l; - - spi_init_f (); - spi_init_r (); - - cp->cp_spmode |= SPMODE_LOOP; - - for (i = 0; i < TEST_NUM; i++) { - for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) { - packet_fill ((char *)txbuf, l); - - spi_xfer (l); - - if (packet_check ((char *)rxbuf, l) < 0) { - goto Done; - } - } - } - - res = 0; - - Done: - - cp->cp_spmode &= ~SPMODE_LOOP; - - /* - * SCC2 parameter RAM space overlaps - * the SPI parameter RAM space. So we need to restore - * the SCC2 configuration if it is used by UART. - */ - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - - if (res != 0) { - post_log ("SPI test failed\n"); - } - - return res; -} -#endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */ diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S deleted file mode 100644 index f8aa93d..0000000 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0x00000100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating, - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memory map. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ - -/* - * Set up GOT: Global Offset Table - * - * Use r12 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - lis r3, CONFIG_SYS_IMMR@h /* position IMMR */ - mtspr 638, r3 - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - mfspr r3, ICR /* clear Interrupt Cause Register */ - - /* Initialize debug port registers */ - /*----------------------------------------------------------------------*/ - xor r0, r0, r0 /* Clear R0 */ - mtspr LCTRL1, r0 /* Initialize debug port regs */ - mtspr LCTRL2, r0 - mtspr COUNTA, r0 - mtspr COUNTB, r0 - - /* Reset the caches */ - /*----------------------------------------------------------------------*/ - - mfspr r3, IC_CST /* Clear error bits */ - mfspr r3, DC_CST - - lis r3, IDC_UNALL@h /* Unlock all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_INVALL@h /* Invalidate all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_DISABLE@h /* Disable data cache */ - mtspr DC_CST, r3 - -#if !defined(CONFIG_SYS_DELAYED_ICACHE) - /* On IP860 and PCU E, - * we cannot enable IC yet - */ - lis r3, IDC_ENABLE@h /* Enable instruction cache */ -#endif - mtspr IC_CST, r3 - - /* invalidate all tlb's */ - /*----------------------------------------------------------------------*/ - - tlbia - isync - - /* - * Calculate absolute address in FLASH and jump there - *----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_MONITOR_BASE@h - ori r3, r3, CONFIG_SYS_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - - /* initialize some SPRs that are hard to access from C */ - /*----------------------------------------------------------------------*/ - - lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */ - ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ - /* Note: R0 is still 0 here */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* - * Disable serialized ifetch and show cycles - * (i.e. set processor to normal mode). - * This is also a silicon bug workaround, see errata - */ - - li r2, 0x0007 - mtspr ICTRL, r2 - - /* Set up debug mode entry */ - - lis r2, CONFIG_SYS_DER@h - ori r2, r2, CONFIG_SYS_DER@l - mtspr DER, r2 - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - bl board_init_f /* run 1st part of board init code (from Flash) */ - - /* NOTREACHED - board_init_f() does not return */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, - MSR_KERNEL, COPY_EE) - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* Cache functions. -*/ - .globl icache_enable -icache_enable: - SYNC - lis r3, IDC_INVALL@h - mtspr IC_CST, r3 - lis r3, IDC_ENABLE@h - mtspr IC_CST, r3 - blr - - .globl icache_disable -icache_disable: - SYNC - lis r3, IDC_DISABLE@h - mtspr IC_CST, r3 - blr - - .globl icache_status -icache_status: - mfspr r3, IC_CST - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: -#if 0 - SYNC -#endif -#if 1 - lis r3, 0x0400 /* Set cache mode with MMU off */ - mtspr MD_CTR, r3 -#endif - - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 -#if 0 - lis r3, DC_SFWT@h - mtspr DC_CST, r3 -#endif - lis r3, IDC_ENABLE@h - mtspr DC_CST, r3 - blr - - .globl dcache_disable -dcache_disable: - SYNC - lis r3, IDC_DISABLE@h - mtspr DC_CST, r3 - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 - blr - - .globl dcache_status -dcache_status: - mfspr r3, DC_CST - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dc_read -dc_read: - mtspr DC_ADR, r3 - mfspr r3, DC_DAT - blr - -/* - * unsigned int get_immr (unsigned int mask) - * - * return (mask ? (IMMR & mask) : IMMR); - */ - .globl get_immr -get_immr: - mr r4,r3 /* save mask */ - mfspr r3, IMMR /* IMMR */ - cmpwi 0,r4,0 /* mask != 0 ? */ - beq 4f - and r3,r3,r4 /* IMMR & mask */ -4: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - - .globl wr_ic_cst -wr_ic_cst: - mtspr IC_CST, r3 - blr - - .globl rd_ic_cst -rd_ic_cst: - mfspr r3, IC_CST - blr - - .globl wr_ic_adr -wr_ic_adr: - mtspr IC_ADR, r3 - blr - - - .globl wr_dc_cst -wr_dc_cst: - mtspr DC_CST, r3 - blr - - .globl rd_dc_cst -rd_dc_cst: - mfspr r3, DC_CST - blr - - .globl wr_dc_adr -wr_dc_adr: - mtspr DC_ADR, r3 - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - GET_GOT - mr r3, r5 /* Destination Address */ - lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CONFIG_SYS_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r12, r12, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r12 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - cmpwi r0,0 - beq- 2f - add r0,r0,r11 - stw r0,0(r3) -2: bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ - li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - cmpwi r0,0 - add r0,r0,r11 - stw r4,0(r3) - beq- 5f - stw r0,0(r4) -5: bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - mflr r4 /* save link register */ - GET_GOT - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c deleted file mode 100644 index 01f24ac..0000000 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * linux/arch/powerpc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include - -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -static void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs *regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -static void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void AlignmentException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void ProgramCheckException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void SoftEmuException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void UnknownException(struct pt_regs *regs) -{ -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -void DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xx/upatch.c b/arch/powerpc/cpu/mpc8xx/upatch.c deleted file mode 100644 index a8cb735..0000000 --- a/arch/powerpc/cpu/mpc8xx/upatch.c +++ /dev/null @@ -1,194 +0,0 @@ -#include -#include - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ - defined(CONFIG_SYS_SMC_UCODE_PATCH) - -static void UcodeCopy (volatile cpm8xx_t *cpm); - -void cpm_load_patch (volatile immap_t *immr) -{ - immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */ - - UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */ -#ifdef CONFIG_SYS_SPI_UCODE_PATCH - { - volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the SPI parameters (not I2C). */ - immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */ - immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */ - spi->spi_rpbase = CONFIG_SYS_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */ - } -#endif - -#ifdef CONFIG_SYS_I2C_UCODE_PATCH - { - volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the I2C parameters (not SPI). */ - immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */ - immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */ - iip->iic_rpbase = CONFIG_SYS_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */ - } -#endif - -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - { - volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the SMC parameters. */ - immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */ - immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */ - up->smc_rpbase = CONFIG_SYS_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */ - } -#endif - - /* - * Enable DPRAM microcode to execute from the first 512 bytes - * and a 256 byte extension of DPRAM. - */ -#ifdef CONFIG_SYS_SMC_UCODE_PATCH - immr->im_cpm.cp_rccr |= 0x0002; -#else - immr->im_cpm.cp_rccr |= 0x0001; -#endif -} - -#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCh) -static ulong patch_2000[] = { - 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, - 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7, - 0x3A9CFBC8, 0x77CAE1BB, 0xF4DE7FAD, 0xABAE9330, - 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF, 0xFDAFF9CF, - 0xABF88DC8, 0xAB5879F7, 0xB0927383, 0xDFD079F7, - 0xB090E6BB, 0xE5BBE74F, 0xB3FA6F0F, 0x6FFB76CE, - 0xEE0CF9CF, 0x2BFBEFEF, 0xCFEEF9CF, 0x76CEAD23, - 0x90B3DF99, 0x7FDDD0C1, 0x4BF847FD, 0x7CCF76CE, - 0xCFEF77CA, 0x7EAF7FAD, 0x7DFDF0B7, 0xEF7A7FCA, - 0x77CAFBC8, 0x6079E722, 0xFBC85FFF, 0xDFFF5FB3, - 0xFFFBFBC8, 0xF3C894A5, 0xE7C9EDF9, 0x7F9A7FAD, - 0x5F36AFE8, 0x5F5BFFDF, 0xDF95CB9E, 0xAF7D5FC3, - 0xAFED8C1B, 0x5FC3AFDD, 0x5FC5DF99, 0x7EFDB0B3, - 0x5FB3FFFE, 0xABAE5FB3, 0xFFFE5FD0, 0x600BE6BB, - 0x600B5FD0, 0xDFC827FB, 0xEFDF5FCA, 0xCFDE3A9C, - 0xE7C9EDF9, 0xF3C87F9E, 0x54CA7FED, 0x2D3A3637, - 0x756F7E9A, 0xF1CE37EF, 0x2E677FEE, 0x10EBADF8, - 0xEFDECFEA, 0xE52F7D9F, 0xE12BF1CE, 0x5F647E9A, - 0x4DF8CFEA, 0x5F717D9B, 0xEFEECFEA, 0x5F73E522, - 0xEFDE5F73, 0xCFDA0B61, 0x7385DF61, 0xE7C9EDF9, - 0x7E9A30D5, 0x1458BFFF, 0xF3C85FFF, 0xDFFFA7F8, - 0x5F5BBFFE, 0x7F7D10D0, 0x144D5F33, 0xBFFFAF78, - 0x5F5BBFFD, 0xA7F85F33, 0xBFFE77FD, 0x30BD4E08, - 0xFDCFE5FF, 0x6E0FAFF8, 0x7EEF7E9F, 0xFDEFF1CF, - 0x5F17ABF8, 0x0D5B5F5B, 0xFFEF79F7, 0x309EAFDD, - 0x5F3147F8, 0x5F31AFED, 0x7FDD50AF, 0x497847FD, - 0x7F9E7FED, 0x7DFD70A9, 0xEF7E7ECE, 0x6BA07F9E, - 0x2D227EFD, 0x30DB5F5B, 0xFFFD5F5B, 0xFFEF5F5B, - 0xFFDF0C9C, 0xAFED0A9A, 0xAFDD0C37, 0x5F37AFBD, - 0x7FBDB081, 0x5F8147F8, -}; - -static ulong patch_2F00[] = { - 0x3E303430, 0x34343737, 0xABBF9B99, 0x4B4FBDBD, - 0x59949334, 0x9FFF37FB, 0x9B177DD9, 0x936956BB, - 0xFBDD697B, 0xDD2FD113, 0x1DB9F7BB, 0x36313963, - 0x79373369, 0x3193137F, 0x7331737A, 0xF7BB9B99, - 0x9BB19795, 0x77FDFD3D, 0x573B773F, 0x737933F7, - 0xB991D115, 0x31699315, 0x31531694, 0xBF4FBDBD, - 0x35931497, 0x35376956, 0xBD697B9D, 0x96931313, - 0x19797937, 0x69350000, -}; -#else - -static ulong patch_2000[] = { - 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000, - 0x5fefeff8, 0x5f91eff8, 0x3ff30000, 0x3ff10000, - 0x3a11e710, 0xedf0ccb9, 0xf318ed66, 0x7f0e5fe2, - 0x7fedbb38, 0x3afe7468, 0x7fedf4d8, 0x8ffbb92d, - 0xb83b77fd, 0xb0bb5eb9, 0xdfda7fed, 0x90bde74d, - 0x6f0dcbd3, 0xe7decfed, 0xcb50cfed, 0xcfeddf6d, - 0x914d4f74, 0x5eaedfcb, 0x9ee0e7df, 0xefbb6ffb, - 0xe7ef7f0e, 0x9ee57fed, 0xebb7effa, 0xeb30affb, - 0x7fea90b3, 0x7e0cf09f, 0xbffff318, 0x5fffdfff, - 0xac35efea, 0x7fce1fc1, 0xe2ff5fbd, 0xaffbe2ff, - 0x5fbfaffb, 0xf9a87d0f, 0xaef8770f, 0x7d0fb0a2, - 0xeffbbfff, 0xcfef5fba, 0x7d0fbfff, 0x5fba4cf8, - 0x7fddd09b, 0x49f847fd, 0x7efdf097, 0x7fedfffd, - 0x7dfdf093, 0xef7e7e1e, 0x5fba7f0e, 0x3a11e710, - 0xedf0cc87, 0xfb18ad0a, 0x1f85bbb8, 0x74283b7e, - 0x7375e4bb, 0x2ab64fb8, 0x5c7de4bb, 0x32fdffbf, - 0x5f0843f8, 0x7ce3e1bb, 0xe74f7ded, 0x6f0f4fe8, - 0xc7ba32be, 0x73f2efeb, 0x600b4f78, 0xe5bb760b, - 0x5388aef8, 0x4ef80b6a, 0xcfef9ee5, 0xabf8751f, - 0xefef5b88, 0x741f4fe8, 0x751e760d, 0x7fdb70dd, - 0x741cafce, 0xefcc7fce, 0x751e7088, 0x741ce7bb, - 0x334ecfed, 0xafdbefeb, 0xe5bb760b, 0x53ceaef8, - 0xafe8e7eb, 0x4bf8771e, 0x7e007fed, 0x4fcbe2cc, - 0x7fbc3085, 0x7b0f7a0f, 0x34b177fd, 0xb0e75e93, - 0xdf313e3b, 0xaf78741f, 0x741f30cc, 0xcfef5f08, - 0x741f3e88, 0xafb8771e, 0x5f437fed, 0x0bafe2cc, - 0x741ccfec, 0xe5ca53a9, 0x6fcb4f74, 0x5e89df27, - 0x2a923d14, 0x4b8fdf0c, 0x751f741c, 0x6c1eeffa, - 0xefea7fce, 0x6ffc309a, 0xefec3fca, 0x308fdf0a, - 0xadf85e7a, 0xaf7daefd, 0x5e7adf0a, 0x5e7aafdd, - 0x761f1088, 0x1e7c7efd, 0x3089fffe, 0x4908fb18, - 0x5fffdfff, 0xafbbf0f7, 0x4ef85f43, 0xadf81489, - 0x7a0f7089, 0xcfef5089, 0x7a0fdf0c, 0x5e7cafed, - 0xbc6e780f, 0xefef780f, 0xefef790f, 0xa7f85eeb, - 0xffef790f, 0xefef790f, 0x1489df0a, 0x5e7aadfd, - 0x5f09fffb, 0xe79aded9, 0xeff96079, 0x607ae79a, - 0xded8eff9, 0x60795edb, 0x607acfef, 0xefefefdf, - 0xefbfef7f, 0xeeffedff, 0xebffe7ff, 0xafefafdf, - 0xafbfaf7f, 0xaeffadff, 0xabffa7ff, 0x6fef6fdf, - 0x6fbf6f7f, 0x6eff6dff, 0x6bff67ff, 0x2fef2fdf, - 0x2fbf2f7f, 0x2eff2dff, 0x2bff27ff, 0x4e08fd1f, - 0xe5ff6e0f, 0xaff87eef, 0x7e0ffdef, 0xf11f6079, - 0xabf8f51e, 0x7e0af11c, 0x37cfae16, 0x7fec909a, - 0xadf8efdc, 0xcfeae52f, 0x7d0fe12b, 0xf11c6079, - 0x7e0a4df8, 0xcfea5ea0, 0x7d0befec, 0xcfea5ea2, - 0xe522efdc, 0x5ea2cfda, 0x4e08fd1f, 0x6e0faff8, - 0x7c1f761f, 0xfdeff91f, 0x6079abf8, 0x761cee00, - 0xf91f2bfb, 0xefefcfec, 0xf91f6079, 0x761c27fb, - 0xefdf5e83, 0xcfdc7fdd, 0x50f84bf8, 0x47fd7c1f, - 0x761ccfcf, 0x7eef7fed, 0x7dfd70ef, 0xef7e7f1e, - 0x771efb18, 0x6079e722, 0xe6bbe5bb, 0x2e66e5bb, - 0x600b2ee1, 0xe2bbe2bb, 0xe2bbe2bb, 0x2f5ee2bb, - 0xe2bb2ff9, 0x6079e2bb, -}; - -static ulong patch_2F00[] = { - 0x30303030, 0x3e3e3030, 0xaf79b9b3, 0xbaa3b979, - 0x9693369f, 0x79f79777, 0x97333fff, 0xfb3b9e9f, - 0x79b91d11, 0x9e13f3ff, 0x3f9b6bd9, 0xe173d136, - 0x695669d1, 0x697b3daf, 0x79b93a3a, 0x3f979f91, - 0x379ff976, 0xf99777fd, 0x9779737d, 0xe9d6bbf9, - 0xbfffd9df, 0x97f7fd97, 0x6f7b9bff, 0xf9bd9683, - 0x397db973, 0xd97b3b9f, 0xd7f9f733, 0x9993bb9e, - 0xe1f9ef93, 0x73773337, 0xb936917d, 0x11f87379, - 0xb979d336, 0x8b7ded73, 0x1b7d9337, 0x31f3f22f, - 0x3f2327ee, 0xeeeeeeee, 0xeeeeeeee, 0xeeeeeeee, - 0xeeeeee4b, 0xf4fbdbd2, 0x58bb1878, 0x577fdfd2, - 0xd573b773, 0xf7374b4f, 0xbdbd25b8, 0xb177d2d1, - 0x7376856b, 0xbfdd687b, 0xdd2fff8f, 0x78ffff8f, - 0xf22f0000, -}; -#endif - -static void UcodeCopy (volatile cpm8xx_t *cpm) -{ - vu_long *p; - int i; - - p = (vu_long *)&(cpm->cp_dpmem[0x0000]); - for (i=0; i < sizeof(patch_2000)/4; ++i) { - p[i] = patch_2000[i]; - } - - p = (vu_long *)&(cpm->cp_dpmem[0x0F00]); - for (i=0; i < sizeof(patch_2F00)/4; ++i) { - p[i] = patch_2F00[i]; - } -} - -#endif /* CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_SPI_UCODE_PATCH */ diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c deleted file mode 100644 index c35406d..0000000 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * (C) Copyright 2002 - * Wolfgang Denk, wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* #define DEBUG */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_VIDEO - -DECLARE_GLOBAL_DATA_PTR; - -/************************************************************************/ -/* ** DEBUG SETTINGS */ -/************************************************************************/ - -#if 0 -#define VIDEO_DEBUG_COLORBARS /* Force colorbars output */ -#endif - -/************************************************************************/ -/* ** VIDEO MODE SETTINGS */ -/************************************************************************/ - -#if 0 -#define VIDEO_MODE_EXTENDED /* Allow screen size bigger than visible area */ -#define VIDEO_MODE_NTSC -#endif - -#define VIDEO_MODE_PAL - -#if 0 -#define VIDEO_BLINK /* This enables cursor blinking (under construction) */ -#endif - -#define VIDEO_INFO /* Show U-Boot information */ -#define VIDEO_INFO_X VIDEO_LOGO_WIDTH+8 -#define VIDEO_INFO_Y 16 - -/************************************************************************/ -/* ** VIDEO MODE CONSTANTS */ -/************************************************************************/ - -#ifdef VIDEO_MODE_EXTENDED -#define VIDEO_COLS VIDEO_ACTIVE_COLS -#define VIDEO_ROWS VIDEO_ACTIVE_ROWS -#else -#define VIDEO_COLS VIDEO_VISIBLE_COLS -#define VIDEO_ROWS VIDEO_VISIBLE_ROWS -#endif - -#define VIDEO_PIXEL_SIZE (VIDEO_MODE_BPP/8) -#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Total size of buffer */ -#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) /* Number of ints */ -#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Number of bytes per line */ -#define VIDEO_BURST_LEN (VIDEO_COLS/8) - -#ifdef VIDEO_MODE_YUYV -#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ -#else -#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ -#endif - -/************************************************************************/ -/* ** FONT AND LOGO DATA */ -/************************************************************************/ - -#include /* Get font data, width and height */ - -#ifdef CONFIG_VIDEO_LOGO -#include /* Get logo data, width and height */ - -#define VIDEO_LOGO_WIDTH DEF_U_BOOT_LOGO_WIDTH -#define VIDEO_LOGO_HEIGHT DEF_U_BOOT_LOGO_HEIGHT -#define VIDEO_LOGO_ADDR &u_boot_logo -#endif - -/************************************************************************/ -/* ** VIDEO CONTROLLER CONSTANTS */ -/************************************************************************/ - -/* VCCR - VIDEO CONTROLLER CONFIGURATION REGISTER */ - -#define VIDEO_VCCR_VON 0 /* Video controller ON */ -#define VIDEO_VCCR_CSRC 1 /* Clock source */ -#define VIDEO_VCCR_PDF 13 /* Pixel display format */ -#define VIDEO_VCCR_IEN 11 /* Interrupt enable */ - -/* VSR - VIDEO STATUS REGISTER */ - -#define VIDEO_VSR_CAS 6 /* Active set */ -#define VIDEO_VSR_EOF 0 /* End of frame */ - -/* VCMR - VIDEO COMMAND REGISTER */ - -#define VIDEO_VCMR_BD 0 /* Blank display */ -#define VIDEO_VCMR_ASEL 1 /* Active set selection */ - -/* VBCB - VIDEO BACKGROUND COLOR BUFFER REGISTER */ - -#define VIDEO_BCSR4_RESET_BIT 21 /* BCSR4 - Extern video encoder reset */ -#define VIDEO_BCSR4_EXTCLK_BIT 22 /* BCSR4 - Extern clock enable */ -#define VIDEO_BCSR4_VIDLED_BIT 23 /* BCSR4 - Video led disable */ - -/************************************************************************/ -/* ** CONSOLE CONSTANTS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_LOGO -#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) -#define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH) -#else -#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) -#endif - -#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) -#define CONSOLE_ROW_FIRST (video_console_address) -#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) -#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) -#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) - -/* - * Simple color definitions - */ -#define CONSOLE_COLOR_BLACK 0 -#define CONSOLE_COLOR_RED 1 -#define CONSOLE_COLOR_GREEN 2 -#define CONSOLE_COLOR_YELLOW 3 -#define CONSOLE_COLOR_BLUE 4 -#define CONSOLE_COLOR_MAGENTA 5 -#define CONSOLE_COLOR_CYAN 6 -#define CONSOLE_COLOR_GREY 13 -#define CONSOLE_COLOR_GREY2 14 -#define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ - -/************************************************************************/ -/* ** BITOPS MACROS */ -/************************************************************************/ - -#define HISHORT(i) ((i >> 16)&0xffff) -#define LOSHORT(i) (i & 0xffff) -#define HICHAR(s) ((i >> 8)&0xff) -#define LOCHAR(s) (i & 0xff) -#define HI(c) ((c >> 4)&0xf) -#define LO(c) (c & 0xf) -#define SWAPINT(i) (HISHORT(i) | (LOSHORT(i) << 16)) -#define SWAPSHORT(s) (HICHAR(s) | (LOCHAR(s) << 8)) -#define SWAPCHAR(c) (HI(c) | (LO(c) << 4)) -#define BITMASK(b) (1 << (b)) -#define GETBIT(v,b) (((v) & BITMASK(b)) > 0) -#define SETBIT(v,b,d) (v = (((d)>0) ? (v) | BITMASK(b): (v) & ~BITMASK(b))) - -/************************************************************************/ -/* ** STRUCTURES */ -/************************************************************************/ - -typedef struct { - unsigned char V, Y1, U, Y2; -} tYUYV; - -/* This structure is based on the Video Ram in the MPC823. */ -typedef struct VRAM { - unsigned hx:2, /* Horizontal sync */ - vx:2, /* Vertical sync */ - fx:2, /* Frame */ - bx:2, /* Blank */ - res1:6, /* Reserved */ - vds:2, /* Video Data Select */ - inter:1, /* Interrupt */ - res2:2, /* Reserved */ - lcyc:11, /* Loop/video cycles */ - lp:1, /* Loop start/end */ - lst:1; /* Last entry */ -} VRAM; - -/************************************************************************/ -/* ** VARIABLES */ -/************************************************************************/ - -static int - video_panning_range_x = 0, /* Video mode invisible pixels x range */ - video_panning_range_y = 0, /* Video mode invisible pixels y range */ - video_panning_value_x = 0, /* Video mode x panning value (absolute) */ - video_panning_value_y = 0, /* Video mode y panning value (absolute) */ - video_panning_factor_x = 0, /* Video mode x panning value (-127 +127) */ - video_panning_factor_y = 0, /* Video mode y panning value (-127 +127) */ - console_col = 0, /* Cursor col */ - console_row = 0, /* Cursor row */ - video_palette[16]; /* Our palette */ - -static const int video_font_draw_table[] = - { 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; - -static char - video_color_fg = 0, /* Current fg color index (0-15) */ - video_color_bg = 0, /* Current bg color index (0-15) */ - video_enable = 0; /* Video has been initialized? */ - -static void - *video_fb_address, /* Frame buffer address */ - *video_console_address; /* Console frame buffer start address */ - -/************************************************************************/ -/* ** MEMORY FUNCTIONS (32bit) */ -/************************************************************************/ - -static void memsetl (int *p, int c, int v) -{ - while (c--) - *(p++) = v; -} - -static void memcpyl (int *d, int *s, int c) -{ - while (c--) - *(d++) = *(s++); -} - -/************************************************************************/ -/* ** VIDEO DRAWING AND COLOR FUNCTIONS */ -/************************************************************************/ - -static int video_maprgb (int r, int g, int b) -{ -#ifdef VIDEO_MODE_YUYV - unsigned int pR, pG, pB; - tYUYV YUYV; - unsigned int *ret = (unsigned int *) &YUYV; - - /* Transform (0-255) components to (0-100) */ - - pR = r * 100 / 255; - pG = g * 100 / 255; - pB = b * 100 / 255; - - /* Calculate YUV values (0-255) from RGB beetween 0-100 */ - - YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16; - YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128; - YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128; - return *ret; -#endif -#ifdef VIDEO_MODE_RGB - return ((r >> 3) << 11) | ((g > 2) << 6) | (b >> 3); -#endif -} - -static void video_setpalette (int color, int r, int g, int b) -{ - color &= 0xf; - - video_palette[color] = video_maprgb (r, g, b); - - /* Swap values if our panning offset is odd */ - if (video_panning_value_x & 1) - video_palette[color] = SWAPINT (video_palette[color]); -} - -static void video_fill (int color) -{ - memsetl (video_fb_address, VIDEO_PIX_BLOCKS, color); -} - -static void video_setfgcolor (int i) -{ - video_color_fg = i & 0xf; -} - -static void video_setbgcolor (int i) -{ - video_color_bg = i & 0xf; -} - -static int video_pickcolor (int i) -{ - return video_palette[i & 0xf]; -} - -/* Absolute console plotting functions */ - -#ifdef VIDEO_BLINK -static void video_revchar (int xx, int yy) -{ - int rows; - u8 *dest; - - dest = video_fb_address + yy * VIDEO_LINE_LEN + xx * 2; - - for (rows = VIDEO_FONT_HEIGHT; rows--; dest += VIDEO_LINE_LEN) { - switch (VIDEO_FONT_WIDTH) { - case 16: - ((u32 *) dest)[6] ^= 0xffffffff; - ((u32 *) dest)[7] ^= 0xffffffff; - /* FALL THROUGH */ - case 12: - ((u32 *) dest)[4] ^= 0xffffffff; - ((u32 *) dest)[5] ^= 0xffffffff; - /* FALL THROUGH */ - case 8: - ((u32 *) dest)[2] ^= 0xffffffff; - ((u32 *) dest)[3] ^= 0xffffffff; - /* FALL THROUGH */ - case 4: - ((u32 *) dest)[0] ^= 0xffffffff; - ((u32 *) dest)[1] ^= 0xffffffff; - } - } -} -#endif - -static void video_drawchars (int xx, int yy, unsigned char *s, int count) -{ - u8 *cdat, *dest, *dest0; - int rows, offset, c; - u32 eorx, fgx, bgx; - - offset = yy * VIDEO_LINE_LEN + xx * 2; - dest0 = video_fb_address + offset; - - fgx = video_pickcolor (video_color_fg); - bgx = video_pickcolor (video_color_bg); - - if (xx & 1) { - fgx = SWAPINT (fgx); - bgx = SWAPINT (bgx); - } - - eorx = fgx ^ bgx; - - switch (VIDEO_FONT_WIDTH) { - case 4: - case 8: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - if (VIDEO_FONT_WIDTH == 8) { - ((u32 *) dest)[2] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[3] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - } - } - dest0 += VIDEO_FONT_WIDTH * 2; - s++; - } - break; - case 12: - case 16: - while (count--) { - cdat = video_fontdata + (*s) * (VIDEO_FONT_HEIGHT << 1); - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; - dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - ((u32 *) dest)[2] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[3] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - bits = *cdat++; - ((u32 *) dest)[4] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[5] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - if (VIDEO_FONT_WIDTH == 16) { - ((u32 *) dest)[6] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[7] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - } - } - s++; - dest0 += VIDEO_FONT_WIDTH * 2; - } - break; - } -} - -static inline void video_drawstring (int xx, int yy, char *s) -{ - video_drawchars (xx, yy, (unsigned char *)s, strlen (s)); -} - -/* Relative to console plotting functions */ - -static void video_putchars (int xx, int yy, unsigned char *s, int count) -{ -#ifdef CONFIG_VIDEO_LOGO - video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, s, count); -#else - video_drawchars (xx, yy, s, count); -#endif -} - -static void video_putchar (int xx, int yy, unsigned char c) -{ -#ifdef CONFIG_VIDEO_LOGO - video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1); -#else - video_drawchars (xx, yy, &c, 1); -#endif -} - -static inline void video_putstring (int xx, int yy, unsigned char *s) -{ - video_putchars (xx, yy, (unsigned char *)s, strlen ((char *)s)); -} - -/************************************************************************/ -/* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ -/************************************************************************/ - -static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) -{ - int i; - - for (i = 0; i < entries; i++) { - dest[i] = source[i]; /* Copy the entire record */ - dest[i].fx = (!dest[i].fx) * 3; /* Negate field bit */ - } - - dest[0].lcyc++; /* Add a cycle to the first entry */ - dest[entries - 1].lst = 1; /* Set end of ram entries */ -} - -static void inline video_mode_addentry (VRAM * vr, - int Hx, int Vx, int Fx, int Bx, - int VDS, int INT, int LCYC, int LP, int LST) -{ - vr->hx = Hx; - vr->vx = Vx; - vr->fx = Fx; - vr->bx = Bx; - vr->vds = VDS; - vr->inter = INT; - vr->lcyc = LCYC; - vr->lp = LP; - vr->lst = LST; -} - -#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i) - -static int video_mode_generate (void) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */ - int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo; - - /* CHECKING PARAMETERS */ - - if (video_panning_factor_y < -128) - video_panning_factor_y = -128; - - if (video_panning_factor_y > 128) - video_panning_factor_y = 128; - - if (video_panning_factor_x < -128) - video_panning_factor_x = -128; - - if (video_panning_factor_x > 128) - video_panning_factor_x = 128; - - /* Setting panning */ - - DX = video_panning_range_x = (VIDEO_ACTIVE_COLS - VIDEO_COLS) * 2; - DY = video_panning_range_y = (VIDEO_ACTIVE_ROWS - VIDEO_ROWS) / 2; - - video_panning_value_x = (video_panning_factor_x + 128) * DX / 256; - video_panning_value_y = (video_panning_factor_y + 128) * DY / 256; - - /* We assume these are burst units (multiplied by 2, we need it pari) */ - X1 = video_panning_value_x & 0xfffe; - X2 = DX - X1; - - /* We assume these are field line units (divided by 2, we need it pari) */ - Y1 = video_panning_value_y & 0xfffe; - Y2 = DY - Y1; - - debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n", - X1, X2, Y1, Y2, DX, DY, VIDEO_COLS); - -#ifdef VIDEO_MODE_NTSC -/* - * Hx Vx Fx Bx VDS INT LCYC LP LST - * - * Retrace blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 3, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 18, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); -/* - * Odd field active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - } -/* - * Odd field active area - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 240 - DY, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 0, 3, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - -/* - * Odd field active area (BOTTOM) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - } -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 4, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 19, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Even field active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 3, 0, 1, 0, Y1, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); - } -/* - * Even field active area (CENTER) - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 240 - DY, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 3, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 3, 3, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Even field active area (BOTTOM) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 3, 0, 1, 0, Y2, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); - } -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 1, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 1, 32, 1, 1); -#endif - -#ifdef VIDEO_MODE_PAL - -/* - * Hx Vx Fx Bx VDS INT LCYC LP LST - * - * vertical; blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 22, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); /* 11? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); - } -/* - * field active area (CENTER) - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 288 - DY, 1, 0); /* 265? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 0, 1, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * field active area (BOTTOM) - */ - if (Y2 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); /* 12? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); - } -/* - * field vertical; blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 2, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * Create the other field (like this, but whit other field selected, - * one more cycle loop and a last identifier) - */ - video_mode_dupefield (vr, &vr[entry], entry); - -#endif /* VIDEO_MODE_PAL */ - - /* See what FIFO are we using */ - fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS); - - /* Set number of lines and burst (only one frame for now) */ - if (fifo) { - immap->im_vid.vid_vfcr0 = VIDEO_BURST_LEN | - (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); - } else { - immap->im_vid.vid_vfcr1 = VIDEO_BURST_LEN | - (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); - } - - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_ASEL, !fifo); - -/* - * Wait until changes are applied (not done) - * while (GETBIT(immap->im_vid.vid_vsr, VIDEO_VSR_CAS) == fifo) ; - */ - - /* Return number of VRAM entries */ - return entry * 2; -} - -static void video_encoder_init (void) -{ - return; -} - -static void video_ctrl_init (void *memptr) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - video_fb_address = memptr; - - /* Set background */ - debug ("[VIDEO CTRL] Setting background color...\n"); - immap->im_vid.vid_vbcb = VIDEO_BG_COL; - - /* Show the background */ - debug ("[VIDEO CTRL] Forcing background...\n"); - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 1); - - /* Turn off video controller */ - debug ("[VIDEO CTRL] Turning off video controller...\n"); - SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0); - - /* Generate and make active a new video mode */ - debug ("[VIDEO CTRL] Generating video mode...\n"); - video_mode_generate (); - - /* Start of frame buffer (even and odd frame, to make it working with */ - /* any selected active set) */ - debug ("[VIDEO CTRL] Setting frame buffer address...\n"); - immap->im_vid.vid_vfaa1 = - immap->im_vid.vid_vfaa0 = (u32) video_fb_address; - immap->im_vid.vid_vfba1 = - immap->im_vid.vid_vfba0 = - (u32) video_fb_address + VIDEO_LINE_LEN; - - /* YUV, Big endian, SHIFT/CLK/CLK input (BEFORE ENABLING 27MHZ EXT CLOCK) */ - debug ("[VIDEO CTRL] Setting pixel mode and clocks...\n"); - immap->im_vid.vid_vccr = 0x2042; - - /* Configure port pins */ - debug ("[VIDEO CTRL] Configuring input/output pins...\n"); - immap->im_ioport.iop_pdpar = 0x1fff; - immap->im_ioport.iop_pddir = 0x0000; - - /* Blanking the screen. */ - debug ("[VIDEO CTRL] Blanking the screen...\n"); - video_fill (VIDEO_BG_COL); - - /* - * Turns on Aggressive Mode. Normally, turning on the caches - * will cause the screen to flicker when the caches try to - * fill. This gives the FIFO's for the Video Controller - * higher priority and prevents flickering because of - * underrun. This may still be an issue when using FLASH, - * since accessing data from Flash is so slow. - */ - debug ("[VIDEO CTRL] Turning on aggressive mode...\n"); - immap->im_siu_conf.sc_sdcr = 0x40; - - /* Turn on video controller */ - debug ("[VIDEO CTRL] Turning on video controller...\n"); - SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 1); - - /* Show the display */ - debug ("[VIDEO CTRL] Enabling the video...\n"); - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 0); -} - -/************************************************************************/ -/* ** CONSOLE FUNCTIONS */ -/************************************************************************/ - -static void console_scrollup (void) -{ - /* Copy up rows ignoring the first one */ - memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE >> 2); - - /* Clear the last one */ - memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, VIDEO_BG_COL); -} - -static inline void console_back (void) -{ - console_col--; - - if (console_col < 0) { - console_col = CONSOLE_COLS - 1; - console_row--; - if (console_row < 0) - console_row = 0; - } - - video_putchar ( console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); -} - -static inline void console_newline (void) -{ - console_row++; - console_col = 0; - - /* Check if we need to scroll the terminal */ - if (console_row >= CONSOLE_ROWS) { - /* Scroll everything up */ - console_scrollup (); - - /* Decrement row number */ - console_row--; - } -} - -void video_putc(struct stdio_dev *dev, const char c) -{ - if (!video_enable) { - serial_putc (c); - return; - } - - switch (c) { - case 13: /* Simply ignore this */ - break; - - case '\n': /* Next line, please */ - console_newline (); - break; - - case 9: /* Tab (8 chars alignment) */ - console_col |= 0x0008; /* Next 8 chars boundary */ - console_col &= ~0x0007; /* Set this bit to zero */ - - if (console_col >= CONSOLE_COLS) - console_newline (); - break; - - case 8: /* Eat last character */ - console_back (); - break; - - default: /* Add to the console */ - video_putchar ( console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, c); - console_col++; - /* Check if we need to go to next row */ - if (console_col >= CONSOLE_COLS) - console_newline (); - } -} - -void video_puts(struct stdio_dev *dev, const char *s) -{ - int count = strlen (s); - - if (!video_enable) - while (count--) - serial_putc (*s++); - else - while (count--) - video_putc(dev, *s++); -} - -/************************************************************************/ -/* ** CURSOR BLINKING FUNCTIONS */ -/************************************************************************/ - -#ifdef VIDEO_BLINK - -#define BLINK_TIMER_ID 0 -#define BLINK_TIMER_HZ 2 - -static unsigned char blink_enabled = 0; -static timer_t blink_timer; - -static void blink_update (void) -{ - static int blink_row = -1, blink_col = -1, blink_old = 0; - - /* Check if we have a new position to invert */ - if ((console_row != blink_row) || (console_col != blink_col)) { - /* Check if we need to reverse last character */ - if (blink_old) - video_revchar ( blink_col * VIDEO_FONT_WIDTH, - (blink_row -#ifdef CONFIG_VIDEO_LOGO - + VIDEO_LOGO_HEIGHT -#endif - ) * VIDEO_FONT_HEIGHT); - - /* Update values */ - blink_row = console_row; - blink_col = console_col; - blink_old = 0; - } - -/* Reverse this character */ - blink_old = !blink_old; - video_revchar ( console_col * VIDEO_FONT_WIDTH, - (console_row -#ifdef CONFIG_VIDEO_LOGO - + VIDEO_LOGO_HEIGHT -#endif - ) * VIDEO_FONT_HEIGHT); - -} - -/* - * Handler for blinking cursor - */ -static void blink_handler (void *arg) -{ -/* Blink */ - blink_update (); -/* Ack the timer */ - timer_ack (&blink_timer); -} - -int blink_set (int blink) -{ - int ret = blink_enabled; - - if (blink) - timer_enable (&blink_timer); - else - timer_disable (&blink_timer); - - blink_enabled = blink; - - return ret; -} - -static inline void blink_close (void) -{ - timer_close (&blink_timer); -} - -static inline void blink_init (void) -{ - timer_init (&blink_timer, - BLINK_TIMER_ID, BLINK_TIMER_HZ, - blink_handler); -} -#endif - -/************************************************************************/ -/* ** LOGO PLOTTING FUNCTIONS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_LOGO -void easylogo_plot (fastimage_t * image, void *screen, int width, int x, - int y) -{ - int skip = width - image->width, xcount, ycount = image->height; - -#ifdef VIDEO_MODE_YUYV - ushort *source = (ushort *) image->data; - ushort *dest = (ushort *) screen + y * width + x; - - while (ycount--) { - xcount = image->width; - while (xcount--) - *dest++ = *source++; - dest += skip; - } -#endif -#ifdef VIDEO_MODE_RGB - unsigned char - *source = (unsigned short *) image->data, - *dest = (unsigned short *) screen + ((y * width) + x) * 3; - - while (ycount--) { - xcount = image->width * 3; - memcpy (dest, source, xcount); - source += xcount; - dest += ycount; - } -#endif -} - -static void *video_logo (void) -{ - u16 *screen = video_fb_address, width = VIDEO_COLS; -#ifdef VIDEO_INFO - char temp[32]; - char info[80]; -#endif /* VIDEO_INFO */ - - easylogo_plot (VIDEO_LOGO_ADDR, screen, width, 0, 0); - -#ifdef VIDEO_INFO - sprintf (info, "%s (%s - %s) ", - U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info); - - strcpy(info, "(C) 2002 DENX Software Engineering"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - info); - - strcpy(info, " Wolfgang DENK, wd@denx.de"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, - info); - - /* leave one blank line */ - - sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4, - info); -#endif - - return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN; -} -#endif - -/************************************************************************/ -/* ** VIDEO HIGH-LEVEL FUNCTIONS */ -/************************************************************************/ - -static int video_init (void *videobase) -{ - /* Initialize the encoder */ - debug ("[VIDEO] Initializing video encoder...\n"); - video_encoder_init (); - - /* Initialize the video controller */ - debug ("[VIDEO] Initializing video controller at %08x...\n", - (int) videobase); - video_ctrl_init (videobase); - - /* Setting the palette */ - video_setpalette (CONSOLE_COLOR_BLACK, 0, 0, 0); - video_setpalette (CONSOLE_COLOR_RED, 0xFF, 0, 0); - video_setpalette (CONSOLE_COLOR_GREEN, 0, 0xFF, 0); - video_setpalette (CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); - video_setpalette (CONSOLE_COLOR_BLUE, 0, 0, 0xFF); - video_setpalette (CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); - video_setpalette (CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); - video_setpalette (CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); - video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8); - video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); - -#ifndef CONFIG_SYS_WHITE_ON_BLACK - video_setfgcolor (CONSOLE_COLOR_BLACK); - video_setbgcolor (CONSOLE_COLOR_GREY2); -#else - video_setfgcolor (CONSOLE_COLOR_GREY2); - video_setbgcolor (CONSOLE_COLOR_BLACK); -#endif /* CONFIG_SYS_WHITE_ON_BLACK */ - -#ifdef CONFIG_VIDEO_LOGO - /* Paint the logo and retrieve tv base address */ - debug ("[VIDEO] Drawing the logo...\n"); - video_console_address = video_logo (); -#else - video_console_address = video_fb_address; -#endif - -#ifdef VIDEO_BLINK - /* Enable the blinking (under construction) */ - blink_init (); - blink_set (0); /* To Fix! */ -#endif - - /* Initialize the console */ - console_col = 0; - console_row = 0; - video_enable = 1; - -#ifdef VIDEO_MODE_PAL -# define VIDEO_MODE_TMP1 "PAL" -#endif -#ifdef VIDEO_MODE_NTSC -# define VIDEO_MODE_TMP1 "NTSC" -#endif -#ifdef VIDEO_MODE_YUYV -# define VIDEO_MODE_TMP2 "YCbYCr" -#endif -#ifdef VIDEO_MODE_RGB -# define VIDEO_MODE_TMP2 "RGB" -#endif - debug ( VIDEO_MODE_TMP1 - " %dx%dx%d (" VIDEO_MODE_TMP2 ") on %s - console %dx%d\n", - VIDEO_COLS, VIDEO_ROWS, VIDEO_MODE_BPP, - VIDEO_ENCODER_NAME, CONSOLE_COLS, CONSOLE_ROWS); - return 0; -} - -int drv_video_init (void) -{ - int error, devices = 1; - - struct stdio_dev videodev; - - video_init ((void *)(gd->fb_base)); /* Video initialization */ - -/* Device initialization */ - - memset (&videodev, 0, sizeof (videodev)); - - strcpy (videodev.name, "video"); - videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ - - error = stdio_register (&videodev); - - return (error == 0) ? devices : error; -} - -/************************************************************************/ -/* ** ROM capable initialization part - needed to reserve FB memory */ -/************************************************************************/ - -/* - * This is called early in the system initialization to grab memory - * for the video controller. - * Returns new address for monitor, after reserving video buffer memory - * - * Note that this is running from ROM, so no write access to global data. - */ -ulong video_setmem (ulong addr) -{ - /* Allocate pages for the frame buffer. */ - addr -= VIDEO_SIZE; - - debug ("Reserving %dk for Video Framebuffer at: %08lx\n", - VIDEO_SIZE>>10, addr); - - return (addr); -} - -#endif diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c index bfe48a2..0227a72 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c @@ -56,6 +56,7 @@ #include #include #include +#include #ifdef CONFIG_PCI diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index c02058f..bca8393 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index 45997d6..599f2c2 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -22,7 +22,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index f0fc098..6273772 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c index a42327e..59de04a 100644 --- a/arch/powerpc/cpu/ppc4xx/reginfo.c +++ b/arch/powerpc/cpu/ppc4xx/reginfo.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 3e1a701..49a8295 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -709,7 +709,7 @@ unsigned long determine_pci_clock_per(void) pci_period = PERIOD_66_66MHZ; break; default: - pci_period = PERIOD_33_33MHZ;; + pci_period = PERIOD_33_33MHZ; break; } diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c index fb453b1..acc232d 100644 --- a/arch/powerpc/cpu/ppc4xx/uic.c +++ b/arch/powerpc/cpu/ppc4xx/uic.c @@ -22,7 +22,6 @@ #include #include #include -#include #if (UIC_MAX > 3) #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \ diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index 27423e3..45f0093 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -782,9 +782,6 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) } else td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); } -#ifdef CONFIG_MPC5200 - td_list->hwNextTD = 0; -#endif } td_list->next_dl_td = td_rev; diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.h b/arch/powerpc/cpu/ppc4xx/usb_ohci.h index 2c3dc4f..9e7da0d 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.h +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.h @@ -125,13 +125,8 @@ typedef struct td td_t; #define NUM_INTS 32 /* part of the OHCI standard */ struct ohci_hcca { __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) - __u16 pad1; /* set to 0 on each frame_no change */ - __u16 frame_no; /* current frame number */ -#else __u16 frame_no; /* current frame number */ __u16 pad1; /* set to 0 on each frame_no change */ -#endif __u32 done_head; /* info returned for an interrupt */ u8 reserved_for_hc[116]; } __attribute__((aligned(256))); diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c index 1a2e917..acb933e 100644 --- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c +++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/include/asm/4xx_pci.h b/arch/powerpc/include/asm/4xx_pci.h index f686e7c..276a780 100644 --- a/arch/powerpc/include/asm/4xx_pci.h +++ b/arch/powerpc/include/asm/4xx_pci.h @@ -56,5 +56,7 @@ int pci_arbiter_enabled(void); int __pci_pre_init(struct pci_controller *hose); void __pci_target_init(struct pci_controller *hose); void __pci_master_init(struct pci_controller *hose); +void pci_target_init(struct pci_controller *); +void pcie_setup_hoses(int busno); #endif diff --git a/arch/powerpc/include/asm/5xx_immap.h b/arch/powerpc/include/asm/5xx_immap.h deleted file mode 100644 index 0a333c2..0000000 --- a/arch/powerpc/include/asm/5xx_immap.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: 5xx_immap.h - * - * Discription: MPC555 Internal Memory Map - * - */ - -#ifndef __IMMAP_5XX__ -#define __IMMAP_5XX__ - -/* System Configuration Registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - uint sc_sgpiodt1; - uint sc_sgpiodt2; - uint sc_sgpiocr; - uint sc_emcr; - uint sc_res1aa; - uint sc_res1ab; - uint sc_pdmcr; - char res3[192]; -} sysconf5xx_t; - - -/* Memory Controller Registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - char res1[32]; - uint memc_dmbr; - uint memc_dmor; - char res2[48]; - ushort memc_mstat; - ushort memc_res4a; - char res3[132]; -} memctl5xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res1[2]; - uint sit_tbref0; - uint sit_tbref1; - char res2[20]; - ushort sit_rtcsc; - char res3[2]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[52]; -} sit5xx_t; - -/* Clocks and Reset -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - ushort car_rsr; - ushort car_res7a; - ushort car_colir; - ushort car_res7b; - ushort car_vsrmcr; - ushort car_res7c; - char res1[108]; - -} car5xx_t; - -#define TBSCR_TBE ((ushort)0x0001) - -/* System Integration Timer Keys -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbref0k; - uint sitk_tbref1k; - uint sitk_tbk; - char res1[16]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[16]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[56]; -} sitk5xx_t; - -/* Clocks and Reset Keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res1[1140]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Flash Configuration -*/ -typedef struct fl { - uint fl_cmfmcr; - uint fl_cmftst; - uint fl_cmfctl; - char res1[52]; -} fl5xx_t; - -/* Dpram Control -*/ -typedef struct dprc { - ushort dprc_dptmcr; - ushort dprc_ramtst; - ushort dprc_rambar; - ushort dprc_misrh; - ushort dprc_misrl; - ushort dprc_miscnt; -} dprc5xx_t; - -/* Time Processor Unit -*/ -typedef struct tpu { - ushort tpu_tpumcr; - ushort tpu_tcr; - ushort tpu_dscr; - ushort tpu_dssr; - ushort tpu_ticr; - ushort tpu_cier; - ushort tpu_cfsr0; - ushort tpu_cfsr1; - ushort tpu_cfsr2; - ushort tpu_cfsr3; - ushort tpu_hsqr0; - ushort tpu_hsqr1; - ushort tpu_hsrr0; - ushort tpu_hsrr1; - ushort tpu_cpr0; - ushort tpu_cpr1; - ushort tpu_cisr; - ushort tpu_lr; - ushort tpu_sglr; - ushort tpu_dcnr; - ushort tpu_tpumcr2; - ushort tpu_tpumcr3; - ushort tpu_isdr; - ushort tpu_iscr; - char res1[208]; - char tpu[16][16]; - char res2[512]; -} tpu5xx_t; - -/* QADC -*/ -typedef struct qadc { - ushort qadc_64mcr; - ushort qadc_64test; - ushort qadc_64int; - u_char qadc_portqa; - u_char qadc_portqb; - ushort qadc_ddrqa; - ushort qadc_qacr0; - ushort qadc_qacr1; - ushort qadc_qacr2; - ushort qadc_qasr0; - ushort qadc_qasr1; - char res1[492]; - /* command convertion word table */ - ushort qadc_ccw[64]; - /* result word table, unsigned right justified */ - ushort qadc_rjurr[64]; - /* result word table, signed left justified */ - ushort qadc_ljsrr[64]; - /* result word table, unsigned left justified */ - ushort qadc_ljurr[64]; -} qadc5xx_t; - -/* QSMCM -*/ -typedef struct qsmcm { - ushort qsmcm_qsmcr; - ushort qsmcm_qtest; - ushort qsmcm_qdsci_il; - ushort qsmcm_qspi_il; - ushort qsmcm_scc1r0; - ushort qsmcm_scc1r1; - ushort qsmcm_sc1sr; - ushort qsmcm_sc1dr; - char res1[2]; - char res2[2]; - ushort qsmcm_portqs; - u_char qsmcm_pqspar; - u_char qsmcm_ddrqs; - ushort qsmcm_spcr0; - ushort qsmcm_spcr1; - ushort qsmcm_spcr2; - u_char qsmcm_spcr3; - u_char qsmcm_spsr; - ushort qsmcm_scc2r0; - ushort qsmcm_scc2r1; - ushort qsmcm_sc2sr; - ushort qsmcm_sc2dr; - ushort qsmcm_qsci1cr; - ushort qsmcm_qsci1sr; - ushort qsmcm_sctq[16]; - ushort qsmcm_scrq[16]; - char res3[212]; - ushort qsmcm_recram[32]; - ushort qsmcm_tranram[32]; - u_char qsmcm_comdram[32]; - char res[3616]; -} qsmcm5xx_t; - - -/* MIOS -*/ - -typedef struct mios { - ushort mios_mpwmsm0perr; /* mpwmsm0 */ - ushort mios_mpwmsm0pulr; - ushort mios_mpwmsm0cntr; - ushort mios_mpwmsm0scr; - ushort mios_mpwmsm1perr; /* mpwmsm1 */ - ushort mios_mpwmsm1pulr; - ushort mios_mpwmsm1cntr; - ushort mios_mpwmsm1scr; - ushort mios_mpwmsm2perr; /* mpwmsm2 */ - ushort mios_mpwmsm2pulr; - ushort mios_mpwmsm2cntr; - ushort mios_mpwmsm2scr; - ushort mios_mpwmsm3perr; /* mpwmsm3 */ - ushort mios_mpwmsm3pulr; - ushort mios_mpwmsm3cntr; - ushort mios_mpwmsm3scr; - char res1[16]; - ushort mios_mmcsm6cnt; /* mmcsm6 */ - ushort mios_mmcsm6mlr; - ushort mios_mmcsm6scrd, mmcsm6scr; - char res2[32]; - ushort mios_mdasm11ar; /* mdasm11 */ - ushort mios_mdasm11br; - ushort mios_mdasm11scrd, mdasm11scr; - ushort mios_mdasm12ar; /* mdasm12 */ - ushort mios_mdasm12br; - ushort mios_mdasm12scrd, mdasm12scr; - ushort mios_mdasm13ar; /* mdasm13 */ - ushort mios_mdasm13br; - ushort mios_mdasm13scrd, mdasm13scr; - ushort mios_mdasm14ar; /* mdasm14 */ - ushort mios_mdasm14br; - ushort mios_mdasm14scrd, mdasm14scr; - ushort mios_mdasm15ar; /* mdasm15 */ - ushort mios_mdasm15br; - ushort mios_mdasm15scrd, mdasm15scr; - ushort mios_mpwmsm16perr; /* mpwmsm16 */ - ushort mios_mpwmsm16pulr; - ushort mios_mpwmsm16cntr; - ushort mios_mpwmsm16scr; - ushort mios_mpwmsm17perr; /* mpwmsm17 */ - ushort mios_mpwmsm17pulr; - ushort mios_mpwmsm17cntr; - ushort mios_mpwmsm17scr; - ushort mios_mpwmsm18perr; /* mpwmsm18 */ - ushort mios_mpwmsm18pulr; - ushort mios_mpwmsm18cntr; - ushort mios_mpwmsm18scr; - ushort mios_mpwmsm19perr; /* mpwmsm19 */ - ushort mios_mpwmsm19pulr; - ushort mios_mpwmsm19cntr; - ushort mios_mpwmsm19scr; - char res3[16]; - ushort mios_mmcsm22cnt; /* mmcsm22 */ - ushort mios_mmcsm22mlr; - ushort mios_mmcsm22scrd, mmcsm22scr; - char res4[32]; - ushort mios_mdasm27ar; /* mdasm27 */ - ushort mios_mdasm27br; - ushort mios_mdasm27scrd, mdasm27scr; - ushort mios_mdasm28ar; /*mdasm28 */ - ushort mios_mdasm28br; - ushort mios_mdasm28scrd, mdasm28scr; - ushort mios_mdasm29ar; /* mdasm29 */ - ushort mios_mdasm29br; - ushort mios_mdasm29scrd, mdasm29scr; - ushort mios_mdasm30ar; /* mdasm30 */ - ushort mios_mdasm30br; - ushort mios_mdasm30scrd, mdasm30scr; - ushort mios_mdasm31ar; /* mdasm31 */ - ushort mios_mdasm31br; - ushort mios_mdasm31scrd, mdasm31scr; - ushort mios_mpiosm32dr; - ushort mios_mpiosm32ddr; - char res5[1788]; - ushort mios_mios1tpcr; - char mios_res13[2]; - ushort mios_mios1vnr; - ushort mios_mios1mcr; - char res6[12]; - ushort mios_res42z; - ushort mios_mcpsmscr; - char res7[1000]; - ushort mios_mios1sr0; - char res12[2]; - ushort mios_mios1er0; - ushort mios_mios1rpr0; - char res8[40]; - ushort mios_mios1lvl0; - char res9[14]; - ushort mios_mios1sr1; - char res10[2]; - ushort mios_mios1er1; - ushort mios_mios1rpr1; - char res11[40]; - ushort mios_mios1lvl1; - char res13[1038]; -} mios5xx_t; - -/* Toucan Module -*/ -typedef struct tcan { - ushort tcan_tcnmcr; - ushort tcan_cantcr; - ushort tcan_canicr; - u_char tcan_canctrl0; - u_char tcan_canctrl1; - u_char tcan_presdiv; - u_char tcan_canctrl2; - ushort tcan_timer; - char res1[4]; - ushort tcan_rxgmskhi; - ushort tcan_rxgmsklo; - ushort tcan_rx14mskhi; - ushort tcan_rx14msklo; - ushort tcan_rx15mskhi; - ushort tcan_rx15msklo; - char res2[4]; - ushort tcan_estat; - ushort tcan_imask; - ushort tcan_iflag; - u_char tcan_rxectr; - u_char tcan_txectr; - char res3[88]; - struct { - ushort scr; - ushort id_high; - ushort id_low; - u_char data[8]; - char res4[2]; - } tcan_mbuff[16]; - char res5[640]; -} tcan5xx_t; - -/* UIMB -*/ -typedef struct uimb { - uint uimb_umcr; - char res1[12]; - uint uimb_utstcreg; - char res2[12]; - uint uimb_uipend; -} uimb5xx_t; - - -/* Internal Memory Map MPC555 -*/ -typedef struct immap { - char res1[262144]; /* CMF Flash A 256 Kbytes */ - char res2[196608]; /* CMF Flash B 192 Kbytes */ - char res3[2670592]; /* Reserved for Flash */ - sysconf5xx_t im_siu_conf; /* SIU Configuration */ - memctl5xx_t im_memctl; /* Memory Controller */ - sit5xx_t im_sit; /* System Integration Timers */ - car5xx_t im_clkrst; /* Clocks and Reset */ - sitk5xx_t im_sitk; /* System Integration Timer Keys*/ - cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ - fl5xx_t im_fla; /* Flash Module A */ - fl5xx_t im_flb; /* Flash Module B */ - char res4[14208]; /* Reserved for SIU */ - dprc5xx_t im_dprc; /* Dpram Control Register */ - char res5[8180]; /* Reserved */ - char dptram[6144]; /* Dptram */ - char res6[2048]; /* Reserved */ - tpu5xx_t im_tpua; /* Time Proessing Unit A */ - tpu5xx_t im_tpub; /* Time Processing Unit B */ - qadc5xx_t im_qadca; /* QADC A */ - qadc5xx_t im_qadcb; /* QADC B */ - qsmcm5xx_t im_qsmcm; /* SCI and SPI */ - mios5xx_t im_mios; /* MIOS */ - tcan5xx_t im_tcana; /* Toucan A */ - tcan5xx_t im_tcanb; /* Toucan B */ - char res7[1792]; /* Reserved */ - uimb5xx_t im_uimb; /* UIMB */ -} immap_t; - -#endif /* __IMMAP_5XX__ */ diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h deleted file mode 100644 index dfaddb6..0000000 --- a/arch/powerpc/include/asm/8xx_immap.h +++ /dev/null @@ -1,515 +0,0 @@ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - uint sc_swt; - char res1[2]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - char res2[0xc]; - uint sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - uint pcmc_pbr0; - uint pcmc_por0; - uint pcmc_pbr1; - uint pcmc_por1; - uint pcmc_pbr2; - uint pcmc_por2; - uint pcmc_pbr3; - uint pcmc_por3; - uint pcmc_pbr4; - uint pcmc_por4; - uint pcmc_pbr5; - uint pcmc_por5; - uint pcmc_pbr6; - uint pcmc_por6; - uint pcmc_pbr7; - uint pcmc_por7; - char res1[0x20]; - uint pcmc_pgcra; - uint pcmc_pgcrb; - uint pcmc_pscr; - char res2[4]; - uint pcmc_pipr; - char res3[4]; - uint pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - char res1[0x24]; - uint memc_mar; - uint memc_mcr; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - ushort memc_mstat; - ushort memc_mptpr; - uint memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - ushort sit_tbscr; - char res0[0x02]; - uint sit_tbreff0; - uint sit_tbreff1; - char res1[0x14]; - ushort sit_rtcsc; - char res2[0x02]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res3[0x10]; - ushort sit_piscr; - char res4[2]; - uint sit_pitc; - uint sit_pitr; - char res5[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((ushort)0xff00) -#define TBSCR_REFA ((ushort)0x0080) -#define TBSCR_REFB ((ushort)0x0040) -#define TBSCR_REFAE ((ushort)0x0008) -#define TBSCR_REFBE ((ushort)0x0004) -#define TBSCR_TBF ((ushort)0x0002) -#define TBSCR_TBE ((ushort)0x0001) - -#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) -#define RTCSC_SEC ((ushort)0x0080) -#define RTCSC_ALR ((ushort)0x0040) -#define RTCSC_38K ((ushort)0x0010) -#define RTCSC_SIE ((ushort)0x0008) -#define RTCSC_ALE ((ushort)0x0004) -#define RTCSC_RTF ((ushort)0x0002) -#define RTCSC_RTE ((ushort)0x0001) - -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - uint car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbreff0k; - uint sitk_tbreff1k; - uint sitk_tbk; - char res1[0x10]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[0x10]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - uint cark_sccrk; - uint cark_plprcrk; - uint cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* Video interface. MPC823 Only. -*/ -typedef struct vid823 { - ushort vid_vccr; - ushort res1; - u_char vid_vsr; - u_char res2; - u_char vid_vcmr; - u_char res3; - uint vid_vbcb; - uint res4; - uint vid_vfcr0; - uint vid_vfaa0; - uint vid_vfba0; - uint vid_vfcr1; - uint vid_vfaa1; - uint vid_vfba1; - u_char res5[0x18]; -} vid823_t; - -/* LCD interface. 823 Only. -*/ -typedef struct lcd { - uint lcd_lccr; - uint lcd_lchcr; - uint lcd_lcvcr; - char res1[4]; - uint lcd_lcfaa; - uint lcd_lcfba; - char lcd_lcsr; - char res2[0x7]; -} lcd823_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - uint sdma_sdar; - u_char sdma_sdsr; - char res3[3]; - u_char sdma_sdmr; - char res4[3]; - u_char sdma_idsr1; - char res5[3]; - u_char sdma_idmr1; - char res6[3]; - u_char sdma_idsr2; - char res7[3]; - u_char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - ushort cpic_civr; - char res[0xe]; - uint cpic_cicr; - uint cpic_cipr; - uint cpic_cimr; - uint cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - ushort iop_padir; - ushort iop_papar; - ushort iop_paodr; - ushort iop_padat; - char res1[8]; - ushort iop_pcdir; - ushort iop_pcpar; - ushort iop_pcso; - ushort iop_pcdat; - ushort iop_pcint; - char res2[6]; - ushort iop_pddir; - ushort iop_pdpar; - char res3[2]; - ushort iop_pddat; - uint utmode; - char res4[4]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - ushort cpmt_tgcr; - char res1[0xe]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ - -typedef struct fec { - uint fec_addr_low; /* lower 32 bits of station address */ - ushort fec_addr_high; /* upper 16 bits of station address */ - ushort res1; /* reserved */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res6[17]; /* reserved */ - uint fec_fun_code; /* fec SDMA function code */ - uint res7[3]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x1e]; /* reserved */ -} fec_t; - -/* The FEC and LCD color map share the same address space.... - * I guess we will never see an 823T :-). - */ -union fec_lcd { - fec_t fl_un_fec; - u_char fl_un_cmap[0x200]; -}; - -typedef struct comm_proc { - /* General control and status registers. - */ - ushort cp_cpcr; - u_char res1[2]; - ushort cp_rccr; - u_char res2; - u_char cp_rmds; - u_char res3[4]; - ushort cp_cpmcr1; - ushort cp_cpmcr2; - ushort cp_cpmcr3; - ushort cp_cpmcr4; - u_char res4[2]; - ushort cp_rter; - u_char res5[2]; - ushort cp_rtmr; - u_char res6[0x14]; - - /* Baud rate generators. - */ - uint cp_brgc1; - uint cp_brgc2; - uint cp_brgc3; - uint cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - ushort cp_spmode; - u_char res7[4]; - u_char cp_spie; - u_char res8[3]; - u_char cp_spim; - u_char res9[2]; - u_char cp_spcom; - u_char res10[2]; - - /* Parallel Interface Port. - */ - u_char res11[2]; - ushort cp_pipc; - u_char res12[2]; - ushort cp_ptpr; - uint cp_pbdir; - uint cp_pbpar; - u_char res13[2]; - ushort cp_pbodr; - uint cp_pbdat; - - /* Port E - MPC87x/88x only. - */ - uint cp_pedir; - uint cp_pepar; - uint cp_peso; - uint cp_peodr; - uint cp_pedat; - - /* Communications Processor Timing Register - - Contains RMII Timing for the FECs on MPC87x/88x only. - */ - uint cp_cptr; - - /* Serial Interface and Time Slot Assignment. - */ - uint cp_simode; - u_char cp_sigmr; - u_char res15; - u_char cp_sistr; - u_char cp_sicmr; - u_char res16[4]; - uint cp_sicr; - uint cp_sirp; - u_char res17[0xc]; - - /* 256 bytes of MPC823 video controller RAM array. - */ - u_char cp_vcram[0x100]; - u_char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - * The LCD color map is also here. - */ - union fec_lcd fl_un; -#define cp_fec fl_un.fl_un_fec -#define lcd_cmap fl_un.fl_un_cmap - char res18[0xE00]; - - /* The MPC885 family has a second FEC here */ - fec_t cp_fec2; -#define cp_fec1 cp_fec /* consistency macro */ - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - * Some processors don't have all of it populated. - */ - u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ - - /* Parameter RAM */ - union { - u_char cp_dparam[0x400]; - u16 cp_dparam16[0x200]; - }; -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - vid823_t im_vid; /* Video (823 only) */ - lcd823_t im_lcd; /* LCD (823 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index d3a8391..20c52fc 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -7,9 +7,7 @@ #include /* bytes per L1 cache line */ -#if defined(CONFIG_8xx) -#define L1_CACHE_SHIFT 4 -#elif defined(CONFIG_PPC64BRIDGE) +#if defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 #elif defined(CONFIG_E500MC) #define L1_CACHE_SHIFT 6 @@ -72,41 +70,4 @@ void disable_cpc_sram(void); #define L2CACHE_NONE 0x03 /* NONE */ #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ -#ifdef CONFIG_8xx -/* Cache control on the MPC8xx is provided through some additional - * special purpose registers. - */ -#define IC_CST 560 /* Instruction cache control/status */ -#define IC_ADR 561 /* Address needed for some commands */ -#define IC_DAT 562 /* Read-only data register */ -#define DC_CST 568 /* Data cache control/status */ -#define DC_ADR 569 /* Address needed for some commands */ -#define DC_DAT 570 /* Read-only data register */ - -/* Commands. Only the first few are available to the instruction cache. -*/ -#define IDC_ENABLE 0x02000000 /* Cache enable */ -#define IDC_DISABLE 0x04000000 /* Cache disable */ -#define IDC_LDLCK 0x06000000 /* Load and lock */ -#define IDC_UNLINE 0x08000000 /* Unlock line */ -#define IDC_UNALL 0x0a000000 /* Unlock all */ -#define IDC_INVALL 0x0c000000 /* Invalidate all */ - -#define DC_FLINE 0x0e000000 /* Flush data cache line */ -#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ -#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ -#define DC_SLES 0x05000000 /* Set little endian swap mode */ -#define DC_CLES 0x07000000 /* Clear little endian swap mode */ - -/* Status. -*/ -#define IDC_ENABLED 0x80000000 /* Cache is enabled */ -#define IDC_CERR1 0x00200000 /* Cache error 1 */ -#define IDC_CERR2 0x00100000 /* Cache error 2 */ -#define IDC_CERR3 0x00080000 /* Cache error 3 */ - -#define DC_DFWT 0x40000000 /* Data cache is forced write through */ -#define DC_LES 0x20000000 /* Caches are little endian mode */ -#endif /* CONFIG_8xx */ - #endif diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h deleted file mode 100644 index 4f78186..0000000 --- a/arch/powerpc/include/asm/cpm_8260.h +++ /dev/null @@ -1,795 +0,0 @@ -/* - * MPC8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels found in the dual port RAM or parameter RAM. - * All CPM control and status is available through the MPC8260 internal - * memory map. See immap.h for details. - */ -#ifndef __CPM_82XX__ -#define __CPM_82XX__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((uint)0x80000000) -#define CPM_CR_PAGE ((uint)0x7c000000) -#define CPM_CR_SBLOCK ((uint)0x03e00000) -#define CPM_CR_FLG ((uint)0x00010000) -#define CPM_CR_MCN ((uint)0x00003fc0) -#define CPM_CR_OPCODE ((uint)0x0000000f) - -/* Device sub-block and page codes. -*/ -#define CPM_CR_SCC1_SBLOCK (0x04) -#define CPM_CR_SCC2_SBLOCK (0x05) -#define CPM_CR_SCC3_SBLOCK (0x06) -#define CPM_CR_SCC4_SBLOCK (0x07) -#define CPM_CR_SMC1_SBLOCK (0x08) -#define CPM_CR_SMC2_SBLOCK (0x09) -#define CPM_CR_SPI_SBLOCK (0x0a) -#define CPM_CR_I2C_SBLOCK (0x0b) -#define CPM_CR_TIMER_SBLOCK (0x0f) -#define CPM_CR_RAND_SBLOCK (0x0e) -#define CPM_CR_FCC1_SBLOCK (0x10) -#define CPM_CR_FCC2_SBLOCK (0x11) -#define CPM_CR_FCC3_SBLOCK (0x12) -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_MCC1_SBLOCK (0x1c) - -#define CPM_CR_SCC1_PAGE (0x00) -#define CPM_CR_SCC2_PAGE (0x01) -#define CPM_CR_SCC3_PAGE (0x02) -#define CPM_CR_SCC4_PAGE (0x03) -#define CPM_CR_SMC1_PAGE (0x07) -#define CPM_CR_SMC2_PAGE (0x08) -#define CPM_CR_SPI_PAGE (0x09) -#define CPM_CR_I2C_PAGE (0x0a) -#define CPM_CR_TIMER_PAGE (0x0a) -#define CPM_CR_RAND_PAGE (0x0a) -#define CPM_CR_FCC1_PAGE (0x04) -#define CPM_CR_FCC2_PAGE (0x05) -#define CPM_CR_FCC3_PAGE (0x06) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define CPM_CR_MCC1_PAGE (0x07) -#define CPM_CR_MCC2_PAGE (0x08) - -/* Some opcodes (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - -/* Dual Port RAM addresses. The first 16K is available for almost - * any CPM use, so we put the BDs there. The first 128 bytes are - * used for SMC1 and SMC2 parameter RAM, so we start allocating - * BDs above that. All of this must change when we start - * downloading RAM microcode. - */ -#define CPM_DATAONLY_BASE ((uint)128) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) -#ifndef CONFIG_MPC8272_FAMILY -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) -#else /* 8247/48/71/72 */ -#define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE) -#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) -#endif /* !CONFIG_MPC8272_FAMILY */ - -/* The number of pages of host memory we allocate for CPM. This is - * done early in kernel initialization to get physically contiguous - * pages. - */ -#define NUM_CPM_HOST_PAGES 2 - - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8260_t *cpmp; /* Pointer to comm processor */ -uint m8260_cpm_dpalloc(uint size, uint align); -uint m8260_cpm_hostalloc(uint size, uint align); -void m8260_cpm_setbrg(uint brg, uint rate); -void m8260_cpm_fastbrg(uint brg, uint rate, int div16); -void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - -/* Function code bits, usually generic to devices. -*/ -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ - -/* Parameter RAM offsets from the base. -*/ -#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR -#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ -#else -#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR -#endif - -#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) -#else -#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#endif - -#define PROFF_SCC1 ((uint)0x8000) -#define PROFF_SCC2 ((uint)0x8100) -#define PROFF_SCC3 ((uint)0x8200) -#define PROFF_SCC4 ((uint)0x8300) -#define PROFF_FCC1 ((uint)0x8400) -#define PROFF_FCC2 ((uint)0x8500) -#define PROFF_FCC3 ((uint)0x8600) -#define PROFF_MCC1 ((uint)0x8700) -#define PROFF_SMC1_BASE ((uint)0x87fc) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_MCC2 ((uint)0x8800) -#define PROFF_SMC2_BASE ((uint)0x88fc) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_SPI_BASE ((uint)0x89fc) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_TIMERS ((uint)0x8ae0) -#define PROFF_REVNUM ((uint)0x8af0) -#define PROFF_RAND ((uint)0x8af8) -#define PROFF_I2C_BASE ((uint)0x8afc) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -/* The SMCs are relocated to any of the first eight DPRAM pages. - * We will fix these at the first locations of DPRAM, until we - * get some microcode patches :-). - * The parameter ram space for the SMCs is fifty-some bytes, and - * they are required to start on a 64 byte boundary. - */ -#define PROFF_SMC1 (0) -#define PROFF_SMC2 (64) -#define PROFF_SPI ((16*1024) - 128) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - uint smc_stmp; /* SDMA Temp */ -} smc_uart_t; - -/* SMC uart mode register (Internal memory map). -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC Event and Mask register. -*/ -#define SMCM_TXE ((unsigned char)0x10) -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* SCC as HDLC controller - taken from commproc.h - */ -typedef struct scc_hdlc { - sccp_t sh_genscc; - /* - * HDLC specific parameter RAM - */ - uchar res[4]; /* reserved */ - ulong sh_cmask; /* CRC constant */ - ulong sh_cpres; /* CRC preset */ - ushort sh_disfc; /* discarded frame counter */ - ushort sh_crcec; /* CRC error counter */ - ushort sh_abtsc; /* abort sequence counter */ - ushort sh_nmarc; /* nonmatching address rx cnt */ - ushort sh_retrc; /* frame retransmission cnt */ - ushort sh_mflr; /* maximum frame length reg */ - ushort sh_maxcnt; /* maximum length counter */ - ushort sh_rfthr; /* received frames threshold */ - ushort sh_rfcnt; /* received frames count */ - ushort sh_hmask; /* user defined frm addr mask */ - ushort sh_haddr1; /* user defined frm address 1 */ - ushort sh_haddr2; /* user defined frm address 2 */ - ushort sh_haddr3; /* user defined frm address 3 */ - ushort sh_haddr4; /* user defined frm address 4 */ - ushort tmp; /* temp */ - ushort tmp_mb; /* temp */ -} scc_hdlc_t; - -/* How about some FCCs..... -*/ -#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) -#define FCC_GFMR_DIAG_LE ((uint)0x40000000) -#define FCC_GFMR_DIAG_AE ((uint)0x80000000) -#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) -#define FCC_GFMR_TCI ((uint)0x20000000) -#define FCC_GFMR_TRX ((uint)0x10000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_TTX ((uint)0x08000000) -#define FCC_GFMR_CDP ((uint)0x04000000) -#define FCC_GFMR_CTSP ((uint)0x02000000) -#define FCC_GFMR_CDS ((uint)0x01000000) -#define FCC_GFMR_CTSS ((uint)0x00800000) -#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) -#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) -#define FCC_GFMR_SYNL_8 ((uint)0x00008000) -#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) -#define FCC_GFMR_RTSM ((uint)0x00002000) -#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) -#define FCC_GFMR_REVD ((uint)0x00000400) -#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) -#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) -#define FCC_GFMR_TCRC_16 ((uint)0x00000000) -#define FCC_GFMR_TCRC_32 ((uint)0x00000080) -#define FCC_GFMR_ENR ((uint)0x00000020) -#define FCC_GFMR_ENT ((uint)0x00000010) -#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) -#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) -#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) - -/* Generic FCC parameter ram. -*/ -typedef struct fcc_param { - ushort fcc_riptr; /* Rx Internal temp pointer */ - ushort fcc_tiptr; /* Tx Internal temp pointer */ - ushort fcc_res1; - ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ - uint fcc_rstate; /* Upper byte is Func code, must be set */ - uint fcc_rbase; /* Receive BD base */ - ushort fcc_rbdstat; /* RxBD status */ - ushort fcc_rbdlen; /* RxBD down counter */ - uint fcc_rdptr; /* RxBD internal data pointer */ - uint fcc_tstate; /* Upper byte is Func code, must be set */ - uint fcc_tbase; /* Transmit BD base */ - ushort fcc_tbdstat; /* TxBD status */ - ushort fcc_tbdlen; /* TxBD down counter */ - uint fcc_tdptr; /* TxBD internal data pointer */ - uint fcc_rbptr; /* Rx BD Internal buf pointer */ - uint fcc_tbptr; /* Tx BD Internal buf pointer */ - uint fcc_rcrc; /* Rx temp CRC */ - uint fcc_res2; - uint fcc_tcrc; /* Tx temp CRC */ -} fccp_t; - - -/* Ethernet controller through FCC. -*/ -typedef struct fcc_enet { - fccp_t fen_genfcc; - uint fen_statbuf; /* Internal status buffer */ - uint fen_camptr; /* CAM address */ - uint fen_cmask; /* Constant mask for CRC */ - uint fen_cpres; /* Preset CRC */ - uint fen_crcec; /* CRC Error counter */ - uint fen_alec; /* alignment error counter */ - uint fen_disfc; /* discard frame counter */ - ushort fen_retlim; /* Retry limit */ - ushort fen_retcnt; /* Retry counter */ - ushort fen_pper; /* Persistence */ - ushort fen_boffcnt; /* backoff counter */ - uint fen_gaddrh; /* Group address filter, high 32-bits */ - uint fen_gaddrl; /* Group address filter, low 32-bits */ - ushort fen_tfcstat; /* out of sequence TxBD */ - ushort fen_tfclen; - uint fen_tfcptr; - ushort fen_mflr; /* Maximum frame length (1518) */ - ushort fen_paddrh; /* MAC address */ - ushort fen_paddrm; - ushort fen_paddrl; - ushort fen_ibdcount; /* Internal BD counter */ - ushort fen_idbstart; /* Internal BD start pointer */ - ushort fen_ibdend; /* Internal BD end pointer */ - ushort fen_txlen; /* Internal Tx frame length counter */ - uint fen_ibdbase[8]; /* Internal use */ - uint fen_iaddrh; /* Individual address filter */ - uint fen_iaddrl; - ushort fen_minflr; /* Minimum frame length (64) */ - ushort fen_taddrh; /* Filter transfer MAC address */ - ushort fen_taddrm; - ushort fen_taddrl; - ushort fen_padptr; /* Pointer to pad byte buffer */ - ushort fen_cftype; /* control frame type */ - ushort fen_cfrange; /* control frame range */ - ushort fen_maxb; /* maximum BD count */ - ushort fen_maxd1; /* Max DMA1 length (1520) */ - ushort fen_maxd2; /* Max DMA2 length (1520) */ - ushort fen_maxd; /* internal max DMA count */ - ushort fen_dmacnt; /* internal DMA counter */ - uint fen_octc; /* Total octect counter */ - uint fen_colc; /* Total collision counter */ - uint fen_broc; /* Total broadcast packet counter */ - uint fen_mulc; /* Total multicast packet count */ - uint fen_uspc; /* Total packets < 64 bytes */ - uint fen_frgc; /* Total packets < 64 bytes with errors */ - uint fen_ospc; /* Total packets > 1518 */ - uint fen_jbrc; /* Total packets > 1518 with errors */ - uint fen_p64c; /* Total packets == 64 bytes */ - uint fen_p65c; /* Total packets 64 < bytes <= 127 */ - uint fen_p128c; /* Total packets 127 < bytes <= 255 */ - uint fen_p256c; /* Total packets 256 < bytes <= 511 */ - uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ - uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ - uint fen_cambuf; /* Internal CAM buffer poiner */ - ushort fen_rfthr; /* Received frames threshold */ - ushort fen_rfcnt; /* Received frames count */ -} fcc_enet_t; - -/* FCC Event/Mask register as used by Ethernet. -*/ -#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ -#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ -#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ -#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* FCC Mode Register (FPSMR) as used by Ethernet. -*/ -#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ -#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ -#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ -#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ -#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ -#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ -#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ -#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ -#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ -#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ -#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ -#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ -#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ -#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; /* Tx temp. */ - uint spi_res1[4]; /* SDMA temp. */ -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -/* SPI Event/Mask register. -*/ -#define SPI_EMASK 0x37 /* Event Mask */ -#define SPI_MME 0x20 /* Multi-Master Error */ -#define SPI_TXE 0x10 /* Transmit Error */ -#define SPI_BSY 0x04 /* Busy */ -#define SPI_TXB 0x02 /* Tx Buffer Empty */ -#define SPI_RXB 0x01 /* RX Buffer full/closed */ - -#define SPI_STR 0x80 /* SPCOM: Start transmit */ - -#define SPI_EB ((u_char)0x10) /* big endian byte order */ - -#define BD_IIC_START ((ushort)0x0400) - -#endif /* __CPM_82XX__ */ diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 3943d0e..d0c3fa0 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -19,9 +19,6 @@ struct arch_global_data { u8 sdhc_adapter; #endif #endif -#if defined(CONFIG_8xx) - unsigned long brg_clk; -#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; @@ -84,13 +81,6 @@ struct arch_global_data { #if defined(CONFIG_E500) u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; #endif -#if defined(CONFIG_MPC5xxx) - unsigned long ipb_clk; -#endif -#if defined(CONFIG_MPC512X) - u32 ips_clk; - u32 csb_clk; -#endif /* CONFIG_MPC512X */ unsigned long reset_status; /* reset status register at boot */ #if defined(CONFIG_MPC83xx) unsigned long arbiter_event_attributes; diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h deleted file mode 100644 index bed80aa..0000000 --- a/arch/powerpc/include/asm/immap_512x.h +++ /dev/null @@ -1,1264 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * MPC512x Internal Memory Map - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Based on the MPC83xx header. - */ - -#ifndef __IMMAP_512x__ -#define __IMMAP_512x__ - -#include -#if defined(CONFIG_E300) -#include -#endif - -/* - * System reset offset (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET - -#define SPR_5121E 0x80180000 - -/* - * IMMRBAR - Internal Memory Register Base Address - */ -#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ -#define IMMRBAR 0x0000 /* Register offset to immr */ -#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ -#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) - - -#ifndef __ASSEMBLY__ -typedef struct law512x { - u32 bar; /* Base Addr Register */ - u32 ar; /* Attributes Register */ -} law512x_t; - -/* - * System configuration registers - */ -typedef struct sysconf512x { - u32 immrbar; /* Internal memory map base address register */ - u8 res0[0x1c]; - u32 lpbaw; /* LP Boot Access Window */ - u32 lpcs0aw; /* LP CS0 Access Window */ - u32 lpcs1aw; /* LP CS1 Access Window */ - u32 lpcs2aw; /* LP CS2 Access Window */ - u32 lpcs3aw; /* LP CS3 Access Window */ - u32 lpcs4aw; /* LP CS4 Access Window */ - u32 lpcs5aw; /* LP CS5 Access Window */ - u32 lpcs6aw; /* LP CS6 Access Window */ - u32 lpcs7aw; /* LP CS7 Access Window */ - u8 res1[0x1c]; - law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ - u8 res2[0x28]; - law512x_t ddrlaw; /* DDR Local Access Window */ - u8 res3[0x18]; - u32 mbxbar; /* MBX Base Address */ - u32 srambar; /* SRAM Base Address */ - u32 nfcbar; /* NFC Base Address */ - u8 res4[0x34]; - u32 spridr; /* System Part and Revision ID Register */ - u32 spcr; /* System Priority Configuration Register */ - u8 res5[0xf8]; -} sysconf512x_t; - -#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ - -/* - * Watch Dog Timer (WDT) Registers - */ -typedef struct wdt512x { - u8 res0[4]; - u32 swcrr; /* System watchdog control register */ - u32 swcnr; /* System watchdog count register */ - u8 res1[2]; - u16 swsrr; /* System watchdog service register */ - u8 res2[0xF0]; -} wdt512x_t; - -/* - * RTC Module Registers - */ -typedef struct rtclk512x { - u8 fixme[0x100]; -} rtclk512x_t; - -/* - * General Purpose Timer - */ -typedef struct gpt512x { - u8 fixme[0x100]; -} gpt512x_t; - -/* - * Integrated Programmable Interrupt Controller - */ -typedef struct ipic512x { - u8 fixme[0x100]; -} ipic512x_t; - -/* - * System Arbiter Registers - */ -typedef struct arbiter512x { - u32 acr; /* Arbiter Configuration Register */ - u32 atr; /* Arbiter Timers Register */ - u32 ater; /* Arbiter Transfer Error Register */ - u32 aer; /* Arbiter Event Register */ - u32 aidr; /* Arbiter Interrupt Definition Register */ - u32 amr; /* Arbiter Mask Register */ - u32 aeatr; /* Arbiter Event Attributes Register */ - u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register */ - u8 res1[0xDC]; -} arbiter512x_t; - -/* - * Reset Module - */ -typedef struct reset512x { - u32 rcwl; /* Reset Configuration Word Low Register */ - u32 rcwh; /* Reset Configuration Word High Register */ - u8 res0[8]; - u32 rsr; /* Reset Status Register */ - u32 rmr; /* Reset Mode Register */ - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ - u32 rcer; /* Reset Control Enable Register */ - u8 res1[0xDC]; -} reset512x_t; - -/* RSR - Reset Status Register */ -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ - RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ - RSR_BMRS | RSR_SRS | RSR_HRS) - -/* RMR - Reset Mode Register */ -#define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 -#define RMR_RES (~(RMR_CSRE)) - -/* RCR - Reset Control Register */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ -#define RCR_RES (~(RCR_SWHR | RCR_SWSR)) - -/* RCER - Reset Control Enable Register */ -#define RCER_CRE 0x00000001 /* software hard reset */ -#define RCER_RES (~(RCER_CRE)) - -/* - * Clock Module - */ -typedef struct clk512x { - u32 spmr; /* System PLL Mode Register */ - u32 sccr[2]; /* System Clock Control Registers */ - u32 scfr[2]; /* System Clock Frequency Registers */ - u8 res0[4]; - u32 bcr; /* Bread Crumb Register */ - u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ - u32 spccr; /* SPDIF Clock Control Register */ - u32 cccr; /* CFM Clock Control Register */ - u32 dccr; /* DIU Clock Control Register */ - u32 msccr[4]; /* MSCAN1-4 Clock Control Registers */ - u8 res1[0x98]; -} clk512x_t; - -/* SPMR - System PLL Mode Register */ -#define SPMR_SPMF 0x0F000000 -#define SPMR_SPMF_SHIFT 24 -#define SPMR_CPMF 0x000F0000 -#define SPMR_CPMF_SHIFT 16 - -/* System Clock Control Register 1 commands */ -#define CLOCK_SCCR1_CFG_EN 0x80000000 -#define CLOCK_SCCR1_LPC_EN 0x40000000 -#define CLOCK_SCCR1_NFC_EN 0x20000000 -#define CLOCK_SCCR1_PATA_EN 0x10000000 -#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) -#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 -#define CLOCK_SCCR1_SATA_EN 0x00004000 -#define CLOCK_SCCR1_FEC_EN 0x00002000 -#define CLOCK_SCCR1_TPR_EN 0x00001000 -#define CLOCK_SCCR1_PCI_EN 0x00000800 -#define CLOCK_SCCR1_DDR_EN 0x00000400 - -/* System Clock Control Register 2 commands */ -#define CLOCK_SCCR2_DIU_EN 0x80000000 -#define CLOCK_SCCR2_AXE_EN 0x40000000 -#define CLOCK_SCCR2_MEM_EN 0x20000000 -#define CLOCK_SCCR2_USB1_EN 0x10000000 -#define CLOCK_SCCR2_USB2_EN 0x08000000 -#define CLOCK_SCCR2_I2C_EN 0x04000000 -#define CLOCK_SCCR2_BDLC_EN 0x02000000 -#define CLOCK_SCCR2_SDHC_EN 0x01000000 -#define CLOCK_SCCR2_SPDIF_EN 0x00800000 -#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 -#define CLOCK_SCCR2_MBX_EN 0x00200000 -#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 -#define CLOCK_SCCR2_IIM_EN 0x00080000 - -/* SCFR1 System Clock Frequency Register 1 */ -#ifndef SCFR1_IPS_DIV -#define SCFR1_IPS_DIV 0x3 -#endif -#define SCFR1_IPS_DIV_MASK 0x03800000 -#define SCFR1_IPS_DIV_SHIFT 23 - -#define SCFR1_PCI_DIV 0x6 -#define SCFR1_PCI_DIV_MASK 0x00700000 -#define SCFR1_PCI_DIV_SHIFT 20 - -#define SCFR1_LPC_DIV_MASK 0x00003800 -#define SCFR1_LPC_DIV_SHIFT 11 - -#define SCFR1_NFC_DIV_MASK 0x00000700 -#define SCFR1_NFC_DIV_SHIFT 8 - -#define SCFR1_DIU_DIV_MASK 0x000000FF -#define SCFR1_DIU_DIV_SHIFT 0 - -/* SCFR2 System Clock Frequency Register 2 */ -#define SCFR2_SYS_DIV 0xFC000000 -#define SCFR2_SYS_DIV_SHIFT 26 - -/* SPCR - System Priority Configuration Register */ -#define SPCR_TBEN 0x00400000 /* E300 core time base unit enable */ - -/* - * Power Management Control Module - */ -typedef struct pmc512x { - u8 fixme[0x100]; -} pmc512x_t; - -/* - * General purpose I/O module - */ -typedef struct gpio512x { - u32 gpdir; - u32 gpodr; - u32 gpdat; - u32 gpier; - u32 gpimr; - u32 gpicr1; - u32 gpicr2; - u8 res0[0xE4]; -} gpio512x_t; - -/* - * DDR Memory Controller Memory Map - */ -typedef struct ddr512x { - u32 ddr_sys_config; /* System Configuration Register */ - u32 ddr_time_config0; /* Timing Configuration Register */ - u32 ddr_time_config1; /* Timing Configuration Register */ - u32 ddr_time_config2; /* Timing Configuration Register */ - u32 ddr_command; /* Command Register */ - u32 ddr_compact_command; /* Compact Command Register */ - u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ - u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ - u32 dqs_config_offset_count; /* DQS Config Offset Count */ - u32 dqs_config_offset_time; /* DQS Config Offset Time */ - u32 DQS_delay_status; /* DQS Delay Status */ - u32 res0[0xF]; - u32 prioman_config1; /* Priority Manager Configuration */ - u32 prioman_config2; /* Priority Manager Configuration */ - u32 hiprio_config; /* High Priority Configuration */ - u32 lut_table0_main_upper; /* LUT0 Main Upper */ - u32 lut_table1_main_upper; /* LUT1 Main Upper */ - u32 lut_table2_main_upper; /* LUT2 Main Upper */ - u32 lut_table3_main_upper; /* LUT3 Main Upper */ - u32 lut_table4_main_upper; /* LUT4 Main Upper */ - u32 lut_table0_main_lower; /* LUT0 Main Lower */ - u32 lut_table1_main_lower; /* LUT1 Main Lower */ - u32 lut_table2_main_lower; /* LUT2 Main Lower */ - u32 lut_table3_main_lower; /* LUT3 Main Lower */ - u32 lut_table4_main_lower; /* LUT4 Main Lower */ - u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ - u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ - u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ - u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ - u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ - u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ - u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ - u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ - u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ - u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ - u32 performance_monitor_config; - u32 event_time_counter; - u32 event_time_preset; - u32 performance_monitor1_address_low; - u32 performance_monitor2_address_low; - u32 performance_monitor1_address_hi; - u32 performance_monitor2_address_hi; - u32 res1[2]; - u32 performance_monitor1_read_counter; - u32 performance_monitor2_read_counter; - u32 performance_monitor1_write_counter; - u32 performance_monitor2_write_counter; - u32 granted_ack_counter0; - u32 granted_ack_counter1; - u32 granted_ack_counter2; - u32 granted_ack_counter3; - u32 granted_ack_counter4; - u32 cumulative_wait_counter0; - u32 cumulative_wait_counter1; - u32 cumulative_wait_counter2; - u32 cumulative_wait_counter3; - u32 cumulative_wait_counter4; - u32 summed_priority_counter0; - u32 summed_priority_counter1; - u32 summed_priority_counter2; - u32 summed_priority_counter3; - u32 summed_priority_counter4; - u32 res2[0x3AD]; -} ddr512x_t; - -/* MDDRC SYS CFG and Timing CFG0 Registers */ -#define MDDRC_SYS_CFG_EN 0xF0000000 -#define MDDRC_SYS_CFG_CKE_MASK 0x40000000 -#define MDDRC_SYS_CFG_CMD_MASK 0x10000000 -#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF - -/* - * DDR Memory Controller Configuration settings - */ -typedef struct ddr512x_config { - u32 ddr_sys_config; /* System Configuration Register */ - u32 ddr_time_config0; /* Timing Configuration Register */ - u32 ddr_time_config1; /* Timing Configuration Register */ - u32 ddr_time_config2; /* Timing Configuration Register */ -} ddr512x_config_t; - -typedef struct sdram_conf_s { - unsigned long size; - ddr512x_config_t cfg; -} sdram_conf_t; - -/* - * DMA/Messaging Unit - */ -typedef struct dma512x { - u8 fixme[0x1800]; -} dma512x_t; - -/* - * PCI Software Configuration Registers - */ -typedef struct pciconf512x { - u32 config_address; - u32 config_data; - u32 int_ack; - u8 res[116]; -} pciconf512x_t; - -/* - * PCI Outbound Translation Register - */ -typedef struct pci_outbound_window { - u32 potar; - u8 res0[4]; - u32 pobar; - u8 res1[4]; - u32 pocmr; - u8 res2[4]; -} pot512x_t; - -/* POTAR - PCI Outbound Translation Address Register */ -#define POTAR_TA_MASK 0x000fffff - -/* POBAR - PCI Outbound Base Address Register */ -#define POBAR_BA_MASK 0x000fffff - -/* POCMR - PCI Outbound Comparision Mask Register */ -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ -#define POCMR_PRE 0x20000000 /* prefetch enable */ -#define POCMR_SBS 0x00100000 /* special byte swap enable */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF - -/* - * Sequencer - */ -typedef struct ios512x { - pot512x_t pot[6]; - u8 res0[0x60]; - u32 pmcr; - u8 res1[4]; - u32 dtcr; - u8 res2[4]; -} ios512x_t; - -/* - * PCI Controller - */ -typedef struct pcictrl512x { - u32 esr; - u32 ecdr; - u32 eer; - u32 eatcr; - u32 eacr; - u32 eeacr; - u32 edlcr; - u32 edhcr; - u32 gcr; - u32 ecr; - u32 gsr; - u8 res0[12]; - u32 pitar2; - u8 res1[4]; - u32 pibar2; - u32 piebar2; - u32 piwar2; - u8 res2[4]; - u32 pitar1; - u8 res3[4]; - u32 pibar1; - u32 piebar1; - u32 piwar1; - u8 res4[4]; - u32 pitar0; - u8 res5[4]; - u32 pibar0; - u8 res6[4]; - u32 piwar0; - u8 res7[132]; -} pcictrl512x_t; - - -/* PITAR - PCI Inbound Translation Address Register - */ -#define PITAR_TA_MASK 0x000fffff - -/* PIBAR - PCI Inbound Base/Extended Address Register - */ -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff - -/* PIWAR - PCI Inbound Windows Attributes Register - */ -#define PIWAR_EN 0x80000000 -#define PIWAR_SBS 0x40000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 - -/* - * MSCAN - */ -typedef struct mscan512x { - u8 fixme[0x100]; -} mscan512x_t; - -/* - * BDLC - */ -typedef struct bdlc512x { - u8 fixme[0x100]; -} bdlc512x_t; - -/* - * SDHC - */ -typedef struct sdhc512x { - u8 fixme[0x100]; -} sdhc512x_t; - -/* - * SPDIF - */ -typedef struct spdif512x { - u8 fixme[0x100]; -} spdif512x_t; - -/* - * I2C - */ -typedef struct i2c512x_dev { - volatile u32 madr; /* I2Cn + 0x00 */ - volatile u32 mfdr; /* I2Cn + 0x04 */ - volatile u32 mcr; /* I2Cn + 0x08 */ - volatile u32 msr; /* I2Cn + 0x0C */ - volatile u32 mdr; /* I2Cn + 0x10 */ - u8 res0[0x0C]; -} i2c512x_dev_t; - -/* Number of I2C buses */ -#define I2C_BUS_CNT 3 - -typedef struct i2c512x { - i2c512x_dev_t dev[I2C_BUS_CNT]; - volatile u32 icr; - volatile u32 mifr; - u8 res0[0x98]; -} i2c512x_t; - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -/* - * AXE - */ -typedef struct axe512x { - u8 fixme[0x100]; -} axe512x_t; - -/* - * DIU - */ -typedef struct diu512x { - u8 fixme[0x100]; -} diu512x_t; - -/* - * CFM - */ -typedef struct cfm512x { - u8 fixme[0x100]; -} cfm512x_t; - -/* - * FEC - */ -typedef struct fec512x { - u32 fec_id; /* FEC_ID register */ - u32 ievent; /* Interrupt event register */ - u32 imask; /* Interrupt mask register */ - u32 reserved_01; - u32 r_des_active; /* Receive ring updated flag */ - u32 x_des_active; /* Transmit ring updated flag */ - u32 reserved_02[3]; - u32 ecntrl; /* Ethernet control register */ - u32 reserved_03[6]; - u32 mii_data; /* MII data register */ - u32 mii_speed; /* MII speed register */ - u32 reserved_04[7]; - u32 mib_control; /* MIB control/status register */ - u32 reserved_05[7]; - u32 r_cntrl; /* Receive control register */ - u32 r_hash; /* Receive hash */ - u32 reserved_06[14]; - u32 x_cntrl; /* Transmit control register */ - u32 reserved_07[7]; - u32 paddr1; /* Physical address low */ - u32 paddr2; /* Physical address high + type field */ - u32 op_pause; /* Opcode + pause duration */ - u32 reserved_08[10]; - u32 iaddr1; /* Upper 32 bits of individual hash table */ - u32 iaddr2; /* Lower 32 bits of individual hash table */ - u32 gaddr1; /* Upper 32 bits of group hash table */ - u32 gaddr2; /* Lower 32 bits of group hash table */ - u32 reserved_09[7]; - u32 x_wmrk; /* Transmit FIFO watermark */ - u32 reserved_10; - u32 r_bound; /* End of RAM */ - u32 r_fstart; /* Receive FIFO start address */ - u32 reserved_11[11]; - u32 r_des_start; /* Beginning of receive descriptor ring */ - u32 x_des_start; /* Pointer to beginning of transmit descriptor ring */ - u32 r_buff_size; /* Receive buffer size */ - u32 reserved_12[26]; - u32 dma_control; /* DMA control for IP bus, AMBA IF + DMA revision */ - u32 reserved_13[2]; - - u32 mib[128]; /* MIB Block Counters */ - - u32 fifo[256]; /* used by FEC, can only be accessed by DMA */ -} fec512x_t; - -/* - * ULPI - */ -typedef struct ulpi512x { - u8 fixme[0x600]; -} ulpi512x_t; - -/* - * UTMI - */ -typedef struct utmi512x { - u8 fixme[0x3000]; -} utmi512x_t; - -/* - * PCI DMA - */ -typedef struct pcidma512x { - u8 fixme[0x300]; -} pcidma512x_t; - -/* - * IO Control - */ -typedef struct ioctrl512x { - u32 io_control_mem; /* MEM pad ctrl reg */ - u32 io_control_gp; /* GP pad ctrl reg */ - u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ - u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ - u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ - u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ - u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ - u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ - u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ - u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ - u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ - u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ - u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ - u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ - u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ - u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ - u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ - u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ - u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ - u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ - u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ - u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ - u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ - u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ - u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ - u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ - u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ - u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ - u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ - u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ - u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ - u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ - u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ - u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ - u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ - u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ - u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ - u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ - u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ - u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ - u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ - u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ - u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ - u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ - u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ - u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ - u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ - u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ - u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ - u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ - u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ - u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ - u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ - u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ - u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ - u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ - u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ - u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ - u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ - u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ - u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ - u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ - u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ - u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ - u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ - u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ - u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ - u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ - u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ - u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ - u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ - u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ - u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ - u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ - u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ - u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ - u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ - u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ - u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ - u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ - u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ - u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ - u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ - u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ - u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ - u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ - u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ - u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ - u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ - u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ - u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ - u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ - u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ - u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ - u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ - u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ - u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ - u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ - u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ - u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ - u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ - u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ - u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ - u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ - u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ - u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ - u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ - u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ - u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ - u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ - u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ - u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ - u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ - u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ - u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ - u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ - u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ - u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ - u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ - u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ - u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ - u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ - u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ - u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ - u32 io_control_irq0; /* IRQ0 pad ctrl reg */ - u32 io_control_irq1; /* IRQ1 pad ctrl reg */ - u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ - u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ - u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ - u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ - u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ - u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ - u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ - u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ - u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ - u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ - u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ - u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ - u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ - u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ - u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ - u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ - u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ - u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ - u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ - u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ - u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ - u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ - u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ - u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ - u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ - u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ - u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ - u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ - u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ - u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ - u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ - u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ - u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ - u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ - u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ - u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ - u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ - u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ - u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ - u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ - u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ - u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ - u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ - u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ - u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ - u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ - u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ - u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ - u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ - u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ - u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ - u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ - u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ - u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ - u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ - u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ - u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ - u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ - u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ - u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ - u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ - u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ - u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ - u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ - u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ - u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ - u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ - u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ -} ioctrl512x_t; - -/* IO pin fields */ -#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ -#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ -#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ -#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ -#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ -#define IO_PIN_DS(v) ((v)) /* slew rate */ - -typedef struct iopin_t { - int p_offset; /* offset from IOCTL_MEM_OFFSET */ - int nr_pins; /* number of pins to set this way */ - int bit_or; /* or in the value instead of overwrite */ - u_long val; /* value to write or or */ -}iopin_t; - -void iopin_initialize(iopin_t *,int); - -/* - * support to adjust individual parts of the IO pin setup - */ - -#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ -#define IO_PIN_OVER_FMUX (1 << 1) -#define IO_PIN_OVER_HOLD (1 << 2) -#define IO_PIN_OVER_PULL (1 << 3) -#define IO_PIN_OVER_STRIG (1 << 4) -#define IO_PIN_OVER_DRVSTR (1 << 5) - -void iopin_initialize_bits(iopin_t *, int); - -/* - * IIM - */ -typedef struct iim512x { - u32 stat; /* IIM status register */ - u32 statm; /* IIM status IRQ mask */ - u32 err; /* IIM errors register */ - u32 emask; /* IIM error IRQ mask */ - u32 fctl; /* IIM fuse control register */ - u32 ua; /* IIM upper address register */ - u32 la; /* IIM lower address register */ - u32 sdat; /* IIM explicit sense data */ - u8 res0[0x08]; - u32 prg_p; /* IIM program protection register */ - u8 res1[0x10]; - u32 divide; /* IIM divide factor register */ - u8 res2[0x7c0]; - u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ - u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ - u8 res3[0x380]; - u32 fbac1; /* IIM fuse bank 1 protection */ - u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ - u8 res4[0x380]; -} iim512x_t; - -/* - * LPC - */ -typedef struct lpc512x { - u32 cs_cfg[8]; /* Chip Select N Configuration Registers - No dedicated entry for CS Boot as == CS0 */ - u32 cs_cr; /* Chip Select Control Register */ - u32 cs_sr; /* Chip Select Status Register */ - u32 cs_bcr; /* Chip Select Burst Control Register */ - u32 cs_dccr; /* Chip Select Deadcycle Control Register */ - u32 cs_hccr; /* Chip Select Holdcycle Control Register */ - u32 altr; /* Address Latch Timing Register */ - u8 res0[0xc8]; - u32 sclpc_psr; /* SCLPC Packet Size Register */ - u32 sclpc_sar; /* SCLPC Start Address Register */ - u32 sclpc_cr; /* SCLPC Control Register */ - u32 sclpc_er; /* SCLPC Enable Register */ - u32 sclpc_nar; /* SCLPC NextAddress Register */ - u32 sclpc_sr; /* SCLPC Status Register */ - u32 sclpc_bdr; /* SCLPC Bytes Done Register */ - u32 emb_scr; /* EMB Share Counter Register */ - u32 emb_pcr; /* EMB Pause Control Register */ - u8 res1[0x1c]; - u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ - u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ - u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ - u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ - u8 res2[0xb0]; -} lpc512x_t; - -/* - * PATA - */ -typedef struct pata512x { - /* LOCAL Registers */ - u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ - u32 pata_time2; /* Time register 2: PIO timing parameter */ - u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ - u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ - u32 pata_time5; /* Time register 5: UDMA timing parameter */ - u32 pata_time6; /* Time register 6: UDMA timing parameter */ - u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ - u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ - u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ - u32 pata_ata_control; /* ATA Interface control register */ - u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ - u32 pata_irq_enable; /* Interrupt enable register */ - u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ - u32 pata_fifo_alarm; /* fifo alarm threshold */ - u32 res1[0x1A]; - /* DRIVE Registers */ - u32 pata_drive_data; /* drive data register*/ - u32 pata_drive_features;/* drive features register */ - u32 pata_drive_sectcnt; /* drive sector count register */ - u32 pata_drive_sectnum; /* drive sector number register */ - u32 pata_drive_cyllow; /* drive cylinder low register */ - u32 pata_drive_cylhigh; /* drive cylinder high register */ - u32 pata_drive_dev_head;/* drive device head register */ - u32 pata_drive_command; /* write = drive command, read = drive status reg */ - u32 res2[0x06]; - u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ - u32 res3[0x09]; -} pata512x_t; - -/* - * PSC - */ -typedef struct psc512x { - volatile u8 mode; /* PSC + 0x00 */ - volatile u8 res0[3]; - union { /* PSC + 0x04 */ - volatile u16 status; - volatile u16 clock_select; - } sr_csr; -#define psc_status sr_csr.status -#define psc_clock_select sr_csr.clock_select - volatile u16 res1; - volatile u8 command; /* PSC + 0x08 */ - volatile u8 res2[3]; - union { /* PSC + 0x0c */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } buffer; -#define psc_buffer_8 buffer.buffer_8 -#define psc_buffer_16 buffer.buffer_16 -#define psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - volatile u8 ipcr; - volatile u8 acr; - } ipcr_acr; -#define psc_ipcr ipcr_acr.ipcr -#define psc_acr ipcr_acr.acr - volatile u8 res3[3]; - union { /* PSC + 0x14 */ - volatile u16 isr; - volatile u16 imr; - } isr_imr; -#define psc_isr isr_imr.isr -#define psc_imr isr_imr.imr - volatile u16 res4; - volatile u8 ctur; /* PSC + 0x18 */ - volatile u8 res5[3]; - volatile u8 ctlr; /* PSC + 0x1c */ - volatile u8 res6[3]; - volatile u32 ccr; /* PSC + 0x20 */ - volatile u8 res7[12]; - volatile u8 ivr; /* PSC + 0x30 */ - volatile u8 res8[3]; - volatile u8 ip; /* PSC + 0x34 */ - volatile u8 res9[3]; - volatile u8 op1; /* PSC + 0x38 */ - volatile u8 res10[3]; - volatile u8 op0; /* PSC + 0x3c */ - volatile u8 res11[3]; - volatile u32 sicr; /* PSC + 0x40 */ - volatile u8 res12[60]; - volatile u32 tfcmd; /* PSC + 0x80 */ - volatile u32 tfalarm; /* PSC + 0x84 */ - volatile u32 tfstat; /* PSC + 0x88 */ - volatile u32 tfintstat; /* PSC + 0x8C */ - volatile u32 tfintmask; /* PSC + 0x90 */ - volatile u32 tfcount; /* PSC + 0x94 */ - volatile u16 tfwptr; /* PSC + 0x98 */ - volatile u16 tfrptr; /* PSC + 0x9A */ - volatile u32 tfsize; /* PSC + 0x9C */ - volatile u8 res13[28]; - union { /* PSC + 0xBC */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } tfdata_buffer; -#define tfdata_8 tfdata_buffer.buffer_8 -#define tfdata_16 tfdata_buffer.buffer_16 -#define tfdata_32 tfdata_buffer.buffer_32 - - volatile u32 rfcmd; /* PSC + 0xC0 */ - volatile u32 rfalarm; /* PSC + 0xC4 */ - volatile u32 rfstat; /* PSC + 0xC8 */ - volatile u32 rfintstat; /* PSC + 0xCC */ - volatile u32 rfintmask; /* PSC + 0xD0 */ - volatile u32 rfcount; /* PSC + 0xD4 */ - volatile u16 rfwptr; /* PSC + 0xD8 */ - volatile u16 rfrptr; /* PSC + 0xDA */ - volatile u32 rfsize; /* PSC + 0xDC */ - volatile u8 res18[28]; - union { /* PSC + 0xFC */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } rfdata_buffer; -#define rfdata_8 rfdata_buffer.buffer_8 -#define rfdata_16 rfdata_buffer.buffer_16 -#define rfdata_32 rfdata_buffer.buffer_32 -} psc512x_t; - -/* PSC FIFO Command values */ -#define PSC_FIFO_RESET_SLICE 0x80 -#define PSC_FIFO_ENABLE_SLICE 0x01 - -/* PSC FIFO Controller Command values */ -#define FIFOC_ENABLE_CLOCK_GATE 0x01 -#define FIFOC_DISABLE_CLOCK_GATE 0x00 - -/* PSC FIFO status */ -#define PSC_FIFO_EMPTY 0x01 - -/* PSC Command values */ -#define PSC_RX_ENABLE 0x01 -#define PSC_RX_DISABLE 0x02 -#define PSC_TX_ENABLE 0x04 -#define PSC_TX_DISABLE 0x08 -#define PSC_SEL_MODE_REG_1 0x10 -#define PSC_RST_RX 0x20 -#define PSC_RST_TX 0x30 -#define PSC_RST_ERR_STAT 0x40 -#define PSC_RST_BRK_CHG_INT 0x50 -#define PSC_START_BRK 0x60 -#define PSC_STOP_BRK 0x70 - -/* PSC status register bits */ -#define PSC_SR_CDE 0x0080 -#define PSC_SR_TXEMP 0x0800 -#define PSC_SR_OE 0x1000 -#define PSC_SR_PE 0x2000 -#define PSC_SR_FE 0x4000 -#define PSC_SR_RB 0x8000 - -/* PSC mode fields */ -#define PSC_MODE_5_BITS 0x00 -#define PSC_MODE_6_BITS 0x01 -#define PSC_MODE_7_BITS 0x02 -#define PSC_MODE_8_BITS 0x03 -#define PSC_MODE_PAREVEN 0x00 -#define PSC_MODE_PARODD 0x04 -#define PSC_MODE_PARFORCE 0x08 -#define PSC_MODE_PARNONE 0x10 -#define PSC_MODE_ENTIMEOUT 0x20 -#define PSC_MODE_RXRTS 0x80 -#define PSC_MODE_1_STOPBIT 0x07 - -/* - * FIFOC - */ -typedef struct fifoc512x { - u32 fifoc_cmd; - u32 fifoc_int; - u32 fifoc_dma; - u32 fifoc_axe; - u32 fifoc_debug; - u8 fixme[0xEC]; -} fifoc512x_t; - -/* - * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs - * - * NOTE: individual PSC units are free to use whatever area (and size) of the - * FIFOC internal memory, so make sure memory areas for FIFO slices used by - * different PSCs do not overlap! - * - * Overall size of FIFOC memory is not documented in the MPC5121e RM, but - * tests indicate that it is 1024 words total. - * - * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice. - */ -#define FIFOC_PSC0_TX_SIZE 0x04 -#define FIFOC_PSC0_TX_ADDR 0x0 -#define FIFOC_PSC0_RX_SIZE 0x04 -#define FIFOC_PSC0_RX_ADDR 0x10 - -#define FIFOC_PSC1_TX_SIZE 0x04 -#define FIFOC_PSC1_TX_ADDR 0x20 -#define FIFOC_PSC1_RX_SIZE 0x04 -#define FIFOC_PSC1_RX_ADDR 0x30 - -#define FIFOC_PSC2_TX_SIZE 0x04 -#define FIFOC_PSC2_TX_ADDR 0x40 -#define FIFOC_PSC2_RX_SIZE 0x04 -#define FIFOC_PSC2_RX_ADDR 0x50 - -#define FIFOC_PSC3_TX_SIZE 0x04 -#define FIFOC_PSC3_TX_ADDR 0x60 -#define FIFOC_PSC3_RX_SIZE 0x04 -#define FIFOC_PSC3_RX_ADDR 0x70 - -#define FIFOC_PSC4_TX_SIZE 0x04 -#define FIFOC_PSC4_TX_ADDR 0x80 -#define FIFOC_PSC4_RX_SIZE 0x04 -#define FIFOC_PSC4_RX_ADDR 0x90 - -#define FIFOC_PSC5_TX_SIZE 0x04 -#define FIFOC_PSC5_TX_ADDR 0xa0 -#define FIFOC_PSC5_RX_SIZE 0x04 -#define FIFOC_PSC5_RX_ADDR 0xb0 - -#define FIFOC_PSC6_TX_SIZE 0x04 -#define FIFOC_PSC6_TX_ADDR 0xc0 -#define FIFOC_PSC6_RX_SIZE 0x04 -#define FIFOC_PSC6_RX_ADDR 0xd0 - -#define FIFOC_PSC7_TX_SIZE 0x04 -#define FIFOC_PSC7_TX_ADDR 0xe0 -#define FIFOC_PSC7_RX_SIZE 0x04 -#define FIFOC_PSC7_RX_ADDR 0xf0 - -#define FIFOC_PSC8_TX_SIZE 0x04 -#define FIFOC_PSC8_TX_ADDR 0x100 -#define FIFOC_PSC8_RX_SIZE 0x04 -#define FIFOC_PSC8_RX_ADDR 0x110 - -#define FIFOC_PSC9_TX_SIZE 0x04 -#define FIFOC_PSC9_TX_ADDR 0x120 -#define FIFOC_PSC9_RX_SIZE 0x04 -#define FIFOC_PSC9_RX_ADDR 0x130 - -#define FIFOC_PSC10_TX_SIZE 0x04 -#define FIFOC_PSC10_TX_ADDR 0x140 -#define FIFOC_PSC10_RX_SIZE 0x04 -#define FIFOC_PSC10_RX_ADDR 0x150 - -#define FIFOC_PSC11_TX_SIZE 0x04 -#define FIFOC_PSC11_TX_ADDR 0x160 -#define FIFOC_PSC11_RX_SIZE 0x04 -#define FIFOC_PSC11_RX_ADDR 0x170 - -/* - * SATA - */ -typedef struct sata512x { - u8 fixme[0x2000]; -} sata512x_t; - -typedef struct immap { - sysconf512x_t sysconf; /* System configuration */ - u8 res0[0x700]; - wdt512x_t wdt; /* Watch Dog Timer (WDT) */ - rtclk512x_t rtc; /* Real Time Clock Module */ - gpt512x_t gpt; /* General Purpose Timer */ - ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter512x_t arbiter; /* CSB Arbiter */ - reset512x_t reset; /* Reset Module */ - clk512x_t clk; /* Clock Module */ - pmc512x_t pmc; /* Power Management Control Module */ - gpio512x_t gpio; /* General purpose I/O module */ - u8 res1[0x100]; - mscan512x_t mscan; /* MSCAN */ - bdlc512x_t bdlc; /* BDLC */ - sdhc512x_t sdhc; /* SDHC */ - spdif512x_t spdif; /* SPDIF */ - i2c512x_t i2c; /* I2C Controllers */ - u8 res2[0x800]; - axe512x_t axe; /* AXE */ - diu512x_t diu; /* Display Interface Unit */ - cfm512x_t cfm; /* Clock Frequency Measurement */ - u8 res3[0x500]; - fec512x_t fec; /* Fast Ethernet Controller */ - ulpi512x_t ulpi; /* USB ULPI */ - u8 res4[0xa00]; - utmi512x_t utmi; /* USB UTMI */ - u8 res5[0x1000]; - pcidma512x_t pci_dma; /* PCI DMA */ - pciconf512x_t pci_conf; /* PCI Configuration */ - u8 res6[0x80]; - ios512x_t ios; /* PCI Sequencer */ - pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ - u8 res7[0xa00]; - ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ - ioctrl512x_t io_ctrl; /* IO Control */ - iim512x_t iim; /* IC Identification module */ - u8 res8[0x4000]; - lpc512x_t lpc; /* LocalPlus Controller */ - pata512x_t pata; /* Parallel ATA */ - u8 res9[0xd00]; - psc512x_t psc[12]; /* PSCs */ - u8 res10[0x300]; - fifoc512x_t fifoc; /* FIFO Controller */ - u8 res11[0x2000]; - dma512x_t dma; /* DMA */ - u8 res12[0xa800]; - sata512x_t sata; /* Serial ATA */ - u8 res13[0xde000]; -} immap_t; - -/* provide interface to get PATA base address */ -static inline u32 get_pata_base (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - return (u32)(&im->pata); -} -#endif /* __ASSEMBLY__ */ - -#define CONFIG_SYS_MPC512x_USB1_OFFSET 0x4000 -#define CONFIG_SYS_MPC512x_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET) - -#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim)) - -#endif /* __IMMAP_512x__ */ diff --git a/arch/powerpc/include/asm/immap_8260.h b/arch/powerpc/include/asm/immap_8260.h deleted file mode 100644 index c7021a7..0000000 --- a/arch/powerpc/include/asm/immap_8260.h +++ /dev/null @@ -1,604 +0,0 @@ -/* - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * - * The Internal Memory Map of the 8260. I don't know how generic - * this will be, as I don't have any knowledge of the subsequent - * parts at this time. I copied this from the 8xx_immap.h. - */ -#ifndef __IMMAP_82XX__ -#define __IMMAP_82XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - char res2[20]; - uint sc_bcr; - u_char sc_ppc_acr; - char res3[3]; - uint sc_ppc_alrh; - uint sc_ppc_alrl; - u_char sc_lcl_acr; - char res4[3]; - uint sc_lcl_alrh; - uint sc_lcl_alrl; - uint sc_tescr1; - uint sc_tescr2; - uint sc_ltescr1; - uint sc_ltescr2; - uint sc_pdtea; - u_char sc_pdtem; - char res5[3]; - uint sc_ldtea; - u_char sc_ldtem; - char res6[163]; -} sysconf8260_t; - - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - uint memc_br4; - uint memc_or4; - uint memc_br5; - uint memc_or5; - uint memc_br6; - uint memc_or6; - uint memc_br7; - uint memc_or7; - uint memc_br8; - uint memc_or8; - uint memc_br9; - uint memc_or9; - uint memc_br10; - uint memc_or10; - uint memc_br11; - uint memc_or11; - char res1[8]; - uint memc_mar; - char res2[4]; - uint memc_mamr; - uint memc_mbmr; - uint memc_mcmr; - char res3[8]; - ushort memc_mptpr; - char res4[2]; - uint memc_mdr; - char res5[4]; - uint memc_psdmr; - uint memc_lsdmr; - u_char memc_purt; - char res6[3]; - u_char memc_psrt; - char res7[3]; - u_char memc_lurt; - char res8[3]; - u_char memc_lsrt; - char res9[3]; - uint memc_immr; - uint memc_pcibr0; - uint memc_pcibr1; - char res10[16]; - uint memc_pcimsk0; - uint memc_pcimsk1; - char res11[52]; -} memctl8260_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - char res1[32]; - ushort sit_tmcntsc; - char res2[2]; - uint sit_tmcnt; - char res3[4]; - uint sit_tmcntal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[94]; - char res7[390]; -} sit8260_t; - -/* PCI - */ -typedef struct pci_config { - uint pci_omisr; - uint pci_ominr; - char res1[8]; - uint pci_ifqpr; - uint pci_ofqpr; - char res2[8]; - uint pci_imr0; - uint pci_imr1; - uint pci_omr0; - uint pci_omr1; - uint pci_odr; - char res3[4]; - uint pci_idr; - char res4[20]; - uint pci_imisr; - uint pci_imimr; - char res5[24]; - uint pci_ifhpr; - char res5_2[4]; - uint pci_iftpr; - char res6[4]; - uint pci_iphpr; - char res6_2[4]; - uint pci_iptpr; - char res7[4]; - uint pci_ofhpr; - char res7_2[4]; - uint pci_oftpr; - char res8[4]; - uint pci_ophpr; - char res8_2[4]; - uint pci_optpr; - char res9[8]; - uint pci_mucr; - char res10[8]; - uint pci_qbar; - char res11[12]; - uint pci_dmamr0; - uint pci_dmasr0; - uint pci_dmacdar0; - char res12[4]; - uint pci_dmasar0; - char res13[4]; - uint pci_dmadar0; - char res14[4]; - uint pci_dmabcr0; - uint pci_dmandar0; - char res15[88]; - uint pci_dmamr1; - uint pci_dmasr1; - uint pci_dmacdar1; - char res16[4]; - uint pci_dmasar1; - char res17[4]; - uint pci_dmadar1; - char res18[4]; - uint pci_dmabcr1; - uint pci_dmandar1; - char res19[88]; - uint pci_dmamr2; - uint pci_dmasr2; - uint pci_dmacdar2; - char res20[4]; - uint pci_dmasar2; - char res21[4]; - uint pci_dmadar2; - char res22[4]; - uint pci_dmabcr2; - uint pci_dmandar2; - char res23[88]; - uint pci_dmamr3; - uint pci_dmasr3; - uint pci_dmacdar3; - char res24[4]; - uint pci_dmasar3; - char res25[4]; - uint pci_dmadar3; - char res26[4]; - uint pci_dmabcr3; - uint pci_dmandar3; - char res27[344]; - uint pci_potar0; - char res28[4]; - uint pci_pobar0; - char res29[4]; - uint pci_pocmr0; - char res30[4]; - uint pci_potar1; - char res31[4]; - uint pci_pobar1; - char res32[4]; - uint pci_pocmr1; - char res33[4]; - uint pci_potar2; - char res34[4]; - uint pci_pobar2; - char res35[4]; - uint pci_pocmr2; - char res36[52]; - uint pci_ptcr; - uint pci_gpcr; - uint pci_gcr; - uint pci_esr; - uint pci_emr; - uint pci_ecr; - uint pci_eacr; - char res37[4]; - uint pci_edcr; - char res38[4]; - uint pci_eccr; - char res39[44]; - uint pci_pitar1; - char res40[4]; - uint pci_pibar1; - char res41[4]; - uint pci_picmr1; - char res42[4]; - uint pci_pitar0; - char res43[4]; - uint pci_pibar0; - char res44[4]; - uint pci_picmr0; - char res45[4]; - uint pci_cfg_addr; - uint pci_cfg_data; - uint pci_int_ack; - char res46[756]; -}pci8260_t; -#define PISCR_PIRQ_MASK ((ushort)0xff00) -#define PISCR_PS ((ushort)0x0080) -#define PISCR_PIE ((ushort)0x0004) -#define PISCR_PTF ((ushort)0x0002) -#define PISCR_PTE ((ushort)0x0001) - -/* Interrupt Controller. -*/ -typedef struct interrupt_controller { - ushort ic_sicr; - char res1[2]; - uint ic_sivec; - uint ic_sipnrh; - uint ic_sipnrl; - uint ic_siprr; - uint ic_scprrh; - uint ic_scprrl; - uint ic_simrh; - uint ic_simrl; - uint ic_siexr; - char res2[88]; -} intctl8260_t; - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - uint car_sccr; - char res1[4]; - uint car_scmr; - char res2[4]; - uint car_rsr; - uint car_rmr; - char res[104]; -} car8260_t; - -/* Input/Output Port control/status registers. - * Names consistent with processor manual, although they are different - * from the original 8xx names....... - */ -typedef struct io_port { - uint iop_pdira; - uint iop_ppara; - uint iop_psora; - uint iop_podra; - uint iop_pdata; - char res1[12]; - uint iop_pdirb; - uint iop_pparb; - uint iop_psorb; - uint iop_podrb; - uint iop_pdatb; - char res2[12]; - uint iop_pdirc; - uint iop_pparc; - uint iop_psorc; - uint iop_podrc; - uint iop_pdatc; - char res3[12]; - uint iop_pdird; - uint iop_ppard; - uint iop_psord; - uint iop_podrd; - uint iop_pdatd; - char res4[12]; -} iop8260_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - u_char cpmt_tgcr1; - char res1[3]; - u_char cpmt_tgcr2; - char res2[11]; - ushort cpmt_tmr1; - ushort cpmt_tmr2; - ushort cpmt_trr1; - ushort cpmt_trr2; - ushort cpmt_tcr1; - ushort cpmt_tcr2; - ushort cpmt_tcn1; - ushort cpmt_tcn2; - ushort cpmt_tmr3; - ushort cpmt_tmr4; - ushort cpmt_trr3; - ushort cpmt_trr4; - ushort cpmt_tcr3; - ushort cpmt_tcr4; - ushort cpmt_tcn3; - ushort cpmt_tcn4; - ushort cpmt_ter1; - ushort cpmt_ter2; - ushort cpmt_ter3; - ushort cpmt_ter4; - char res3[584]; -} cpmtimer8260_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res0[24]; - u_char sdma_sdsr; - char res1[3]; - u_char sdma_sdmr; - char res2[3]; - u_char sdma_idsr1; - char res3[3]; - u_char sdma_idmr1; - char res4[3]; - u_char sdma_idsr2; - char res5[3]; - u_char sdma_idmr2; - char res6[3]; - u_char sdma_idsr3; - char res7[3]; - u_char sdma_idmr3; - char res8[3]; - u_char sdma_idsr4; - char res9[3]; - u_char sdma_idmr4; - char res10[707]; -} sdma8260_t; - -/* Fast controllers -*/ -typedef struct fcc { - uint fcc_gfmr; - uint fcc_fpsmr; - ushort fcc_ftodr; - char res1[2]; - ushort fcc_fdsr; - char res2[2]; - ushort fcc_fcce; - char res3[2]; - ushort fcc_fccm; - char res4[2]; - u_char fcc_fccs; - char res5[3]; - u_char fcc_ftirr_phy[4]; -} fcc_t; - -/* Fast controllers continued - */ -typedef struct fcc_c { - uint fcc_firper; - uint fcc_firer; - uint fcc_firsr_hi; - uint fcc_firsr_lo; - u_char fcc_gfemr; - char res1[15]; -} fcc_c_t; - -/* TC Layer - */ -typedef struct tclayer { - ushort tc_tcmode; - ushort tc_cdsmr; - ushort tc_tcer; - ushort tc_rcc; - ushort tc_tcmr; - ushort tc_fcc; - ushort tc_ccc; - ushort tc_icc; - ushort tc_tcc; - ushort tc_ecc; - char res1[12]; -} tclayer_t; - -/* I2C -*/ -typedef struct i2c { - u_char i2c_i2mod; - char res1[3]; - u_char i2c_i2add; - char res2[3]; - u_char i2c_i2brg; - char res3[3]; - u_char i2c_i2com; - char res4[3]; - u_char i2c_i2cer; - char res5[3]; - u_char i2c_i2cmr; - char res6[331]; -} i2c8260_t; - -typedef struct scc { /* Serial communication channels */ - uint scc_gsmrl; - uint scc_gsmrh; - ushort scc_psmr; - char res1[2]; - ushort scc_todr; - ushort scc_dsr; - ushort scc_scce; - char res2[2]; - ushort scc_sccm; - char res3; - u_char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - ushort smc_smcmr; - char res2[2]; - u_char smc_smce; - char res3[3]; - u_char smc_smcm; - char res4[5]; -} smc_t; - -/* Serial Peripheral Interface. -*/ -typedef struct im_spi { - ushort spi_spmode; - char res1[4]; - u_char spi_spie; - char res2[3]; - u_char spi_spim; - char res3[2]; - u_char spi_spcom; - char res4[82]; -} im_spi_t; - -/* CPM Mux. -*/ -typedef struct cpmux { - u_char cmx_si1cr; - char res1; - u_char cmx_si2cr; - char res2; - uint cmx_fcr; - uint cmx_scr; - u_char cmx_smr; - char res3; - ushort cmx_uar; - char res4[16]; -} cpmux_t; - -/* SIRAM control -*/ -typedef struct siram { - ushort si_amr; - ushort si_bmr; - ushort si_cmr; - ushort si_dmr; - u_char si_gmr; - char res1; - u_char si_cmdr; - char res2; - u_char si_str; - char res3; - ushort si_rsr; -} siramctl_t; - -typedef struct mcc { - ushort mcc_mcce; - char res1[2]; - ushort mcc_mccm; - char res2[2]; - u_char mcc_mccf; - char res3[7]; -} mcc_t; - -typedef struct comm_proc { - uint cp_cpcr; - uint cp_rccr; - char res1[14]; - ushort cp_rter; - char res2[2]; - ushort cp_rtmr; - ushort cp_rtscr; - char res3[2]; - uint cp_rtsr; - char res4[12]; -} cpm8260_t; - -/* ...and the whole thing wrapped up.... -*/ -typedef struct immap { - /* Some references are into the unique and known dpram spaces, - * others are from the generic base. - */ - union { - struct { - u_char im_dpram1[16 * 1024]; - char res1[16 * 1024]; - u_char im_dpram2[4 * 1024]; - char res2[8 * 1024]; - u_char im_dpram3[4 * 1024]; - char res3[16 * 1024]; - }; - u8 im_dprambase[64 * 1024]; - u16 im_dprambase16[32 * 1024]; - }; - - sysconf8260_t im_siu_conf; /* SIU Configuration */ - memctl8260_t im_memctl; /* Memory Controller */ - sit8260_t im_sit; /* System Integration Timers */ - pci8260_t im_pci; /* PCI Configuration */ - intctl8260_t im_intctl; /* Interrupt Controller */ - car8260_t im_clkrst; /* Clocks and reset */ - iop8260_t im_ioport; /* IO Port control/status */ - cpmtimer8260_t im_cpmtimer; /* CPM timers */ - sdma8260_t im_sdma; /* SDMA control/status */ - - fcc_t im_fcc[3]; /* Three FCCs */ - - char res4[32]; - fcc_c_t im_fcc_c[3]; /* Continued FCCs */ - char res4a[32]; - - tclayer_t im_tclayer[8]; /* Eight TCLayers */ - ushort tc_tcgsr; - ushort tc_tcger; - - /* First set of baud rate generators. - */ - char res4b[236]; - uint im_brgc5; - uint im_brgc6; - uint im_brgc7; - uint im_brgc8; - - char res5[608]; - - i2c8260_t im_i2c; /* I2C control/status */ - cpm8260_t im_cpm; /* Communication processor */ - - /* Second set of baud rate generators. - */ - uint im_brgc1; - uint im_brgc2; - uint im_brgc3; - uint im_brgc4; - - scc_t im_scc[4]; /* Four SCCs */ - smc_t im_smc[2]; /* Couple of SMCs */ - im_spi_t im_spi; /* A SPI */ - cpmux_t im_cpmux; /* CPM clock route mux */ - siramctl_t im_siramctl1; /* First SI RAM Control */ - mcc_t im_mcc1; /* First MCC */ - siramctl_t im_siramctl2; /* Second SI RAM Control */ - mcc_t im_mcc2; /* Second MCC */ - - char res6[1184]; - - ushort im_si1txram[256]; - char res7[512]; - ushort im_si1rxram[256]; - char res8[512]; - ushort im_si2txram[256]; - char res9[512]; - ushort im_si2rxram[256]; - char res10[512]; - char res11[4096]; -} immap_t; - -#endif /* __IMMAP_82XX__ */ diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h deleted file mode 100644 index 617584d..0000000 --- a/arch/powerpc/include/asm/iopin_8260.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * MPC8260 I/O port pin manipulation functions - */ - -#ifndef _ASM_IOPIN_8260_H_ -#define _ASM_IOPIN_8260_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef - struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ - } -iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -static __inline__ void -iopin_set_high(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_low(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_high(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_low(iopin_t *iopin) -{ - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; - return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_out(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_in(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_out(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_in(iopin_t *iopin) -{ - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; - return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_odr(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_act(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_odr(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_act(iopin_t *iopin) -{ - volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; - return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_ded(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_gen(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_ded(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_gen(iopin_t *iopin) -{ - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; - return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -static __inline__ void -iopin_set_opt2(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); -} - -static __inline__ void -iopin_set_opt1(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); -} - -static __inline__ uint -iopin_is_opt2(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; -} - -static __inline__ uint -iopin_is_opt1(iopin_t *iopin) -{ - volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; - return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_8260_H_ */ diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h deleted file mode 100644 index 8db0fa2..0000000 --- a/arch/powerpc/include/asm/iopin_8xx.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx I/O port pin manipulation functions - * Roughly based on iopin_8260.h - */ - -#ifndef _ASM_IOPIN_8XX_H_ -#define _ASM_IOPIN_8XX_H_ - -#include -#include - -#ifdef __KERNEL__ - -typedef struct { - u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ - u_char pin:5; /* port pin (0-31) */ - u_char flag:1; /* for whatever */ -} iopin_t; - -#define IOPIN_PORTA 0 -#define IOPIN_PORTB 1 -#define IOPIN_PORTC 2 -#define IOPIN_PORTD 3 - -static __inline__ void -iopin_set_high(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - *datp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - *datp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - *datp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - *datp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_low(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - *datp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - *datp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - *datp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - *datp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_high(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - return (*datp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - return (*datp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - return (*datp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - return (*datp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_low(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; - return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_out(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - *dirp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - *dirp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - *dirp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - *dirp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_in(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - *dirp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - *dirp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - *dirp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - *dirp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_out(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - return (*dirp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - return (*dirp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - return (*dirp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - return (*dirp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_in(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; - return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_odr(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - *odrp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - *odrp |= (1 << (31 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_act(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - *odrp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - *odrp &= ~(1 << (31 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_odr(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - return (*odrp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - return (*odrp >> (31 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_act(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; - return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; - return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_ded(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - *parp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - *parp |= (1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - *parp |= (1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - *parp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_gen(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - *parp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - *parp &= ~(1 << (31 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - *parp &= ~(1 << (15 - iopin->pin)); - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - *parp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_ded(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - return (*parp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - return (*parp >> (31 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - return (*parp >> (15 - iopin->pin)) & 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - return (*parp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_gen(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; - return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_opt2(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - *sorp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_opt1(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - *sorp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_opt2(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - return (*sorp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_opt1(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; - return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -static __inline__ void -iopin_set_falledge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - *intp |= (1 << (15 - iopin->pin)); - } -} - -static __inline__ void -iopin_set_anyedge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - *intp &= ~(1 << (15 - iopin->pin)); - } -} - -static __inline__ uint -iopin_is_falledge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - return (*intp >> (15 - iopin->pin)) & 1; - } - return 0; -} - -static __inline__ uint -iopin_is_anyedge(iopin_t *iopin) -{ - if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; - return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; - } - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IOPIN_8XX_H_ */ diff --git a/arch/powerpc/include/asm/m8260_pci.h b/arch/powerpc/include/asm/m8260_pci.h deleted file mode 100644 index 6daca4f..0000000 --- a/arch/powerpc/include/asm/m8260_pci.h +++ /dev/null @@ -1,165 +0,0 @@ -#ifndef _PPC_KERNEL_M8260_PCI_H -#define _PPC_KERNEL_M8260_PCI_H - -#define M8265_PCIBR0 0x101ac -#define M8265_PCIBR1 0x101b0 -#define M8265_PCIMSK0 0x101c4 -#define M8265_PCIMSK1 0x101c8 - -/* Bit definitions for PCIBR registers */ - -#define PCIBR_ENABLE 0x00000001 - -/* Bit definitions for PCIMSK registers */ - -#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ -#define PCIMSK_64KB 0xFFFF0000 -#define PCIMSK_128KB 0xFFFE0000 -#define PCIMSK_256KB 0xFFFC0000 -#define PCIMSK_512KB 0xFFF80000 -#define PCIMSK_1MB 0xFFF00000 -#define PCIMSK_2MB 0xFFE00000 -#define PCIMSK_4MB 0xFFC00000 -#define PCIMSK_8MB 0xFF800000 -#define PCIMSK_16MB 0xFF000000 -#define PCIMSK_32MB 0xFE000000 -#define PCIMSK_64MB 0xFC000000 -#define PCIMSK_128MB 0xF8000000 -#define PCIMSK_256MB 0xF0000000 -#define PCIMSK_512MB 0xE0000000 -#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ - - -#define M826X_SCCR_PCI_MODE_EN 0x100 - - -/* - * Outbound ATU registers (3 sets). These registers control how 60x bus (local) - * addresses are translated to PCI addresses when the MPC826x is a PCI bus - * master (initiator). - */ - -#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ -#define POTAR_REG1 0x10818 -#define POTAR_REG2 0x10830 - -#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ -#define POBAR_REG1 0x10820 -#define POBAR_REG2 0x10838 - -#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ -#define POCMR_REG1 0x10828 -#define POCMR_REG2 0x10840 - -/* Bit definitions for POMCR registers */ - -#define POCMR_MASK_4KB 0x000FFFFF -#define POCMR_MASK_8KB 0x000FFFFE -#define POCMR_MASK_16KB 0x000FFFFC -#define POCMR_MASK_32KB 0x000FFFF8 -#define POCMR_MASK_64KB 0x000FFFF0 -#define POCMR_MASK_128KB 0x000FFFE0 -#define POCMR_MASK_256KB 0x000FFFC0 -#define POCMR_MASK_512KB 0x000FFF80 -#define POCMR_MASK_1MB 0x000FFF00 -#define POCMR_MASK_2MB 0x000FFE00 -#define POCMR_MASK_4MB 0x000FFC00 -#define POCMR_MASK_8MB 0x000FF800 -#define POCMR_MASK_16MB 0x000FF000 -#define POCMR_MASK_32MB 0x000FE000 -#define POCMR_MASK_64MB 0x000FC000 -#define POCMR_MASK_128MB 0x000F8000 -#define POCMR_MASK_256MB 0x000F0000 -#define POCMR_MASK_512MB 0x000E0000 -#define POCMR_MASK_1GB 0x000C0000 - -#define POCMR_ENABLE 0x80000000 -#define POCMR_PCI_IO 0x40000000 -#define POCMR_PREFETCH_EN 0x20000000 - -/* Soft PCI reset */ - -#define PCI_GCR_REG 0x10880 - -/* Bit definitions for PCI_GCR registers */ - -#define PCIGCR_PCI_BUS_EN 0x1 - -/* - * Inbound ATU registers (2 sets). These registers control how PCI addresses - * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. - */ - -#define PITAR_REG1 0x108D0 -#define PIBAR_REG1 0x108D8 -#define PICMR_REG1 0x108E0 -#define PITAR_REG0 0x108E8 -#define PIBAR_REG0 0x108F0 -#define PICMR_REG0 0x108F8 - -/* Bit definitions for PCI Inbound Comparison Mask registers */ - -#define PICMR_MASK_4KB 0x000FFFFF -#define PICMR_MASK_8KB 0x000FFFFE -#define PICMR_MASK_16KB 0x000FFFFC -#define PICMR_MASK_32KB 0x000FFFF8 -#define PICMR_MASK_64KB 0x000FFFF0 -#define PICMR_MASK_128KB 0x000FFFE0 -#define PICMR_MASK_256KB 0x000FFFC0 -#define PICMR_MASK_512KB 0x000FFF80 -#define PICMR_MASK_1MB 0x000FFF00 -#define PICMR_MASK_2MB 0x000FFE00 -#define PICMR_MASK_4MB 0x000FFC00 -#define PICMR_MASK_8MB 0x000FF800 -#define PICMR_MASK_16MB 0x000FF000 -#define PICMR_MASK_32MB 0x000FE000 -#define PICMR_MASK_64MB 0x000FC000 -#define PICMR_MASK_128MB 0x000F8000 -#define PICMR_MASK_256MB 0x000F0000 -#define PICMR_MASK_512MB 0x000E0000 -#define PICMR_MASK_1GB 0x000C0000 - -#define PICMR_ENABLE 0x80000000 -#define PICMR_NO_SNOOP_EN 0x40000000 -#define PICMR_PREFETCH_EN 0x20000000 - -/* PCI error Registers */ - -#define PCI_ERROR_STATUS_REG 0x10884 -#define PCI_ERROR_MASK_REG 0x10888 -#define PCI_ERROR_CONTROL_REG 0x1088C -#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 -#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 -#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 - -/* PCI error Register bit defines */ - -#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 -#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 -#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 -#define PCI_ERROR_PCI_NO_RSP 0x00000008 -#define PCI_ERROR_PCI_TAR_ABT 0x00000010 -#define PCI_ERROR_PCI_SERR 0x00000020 -#define PCI_ERROR_PCI_PERR_RD 0x00000040 -#define PCI_ERROR_PCI_PERR_WR 0x00000080 -#define PCI_ERROR_I2O_OFQO 0x00000100 -#define PCI_ERROR_I2O_IPQO 0x00000200 -#define PCI_ERROR_IRA 0x00000400 -#define PCI_ERROR_NMI 0x00000800 -#define PCI_ERROR_I2O_DBMC 0x00001000 - -/* - * Register pair used to generate configuration cycles on the PCI bus - * and access the MPC826x's own PCI configuration registers. - */ - -#define PCI_CFG_ADDR_REG 0x10900 -#define PCI_CFG_DATA_REG 0x10904 - -/* Bus parking decides where the bus control sits when idle */ -/* If modifying memory controllers for PCI park on the core */ - -#define PPC_ACR_BUS_PARK_CORE 0x6 -#define PPC_ACR_BUS_PARK_PCI 0x3 - -#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h deleted file mode 100644 index 9167a57..0000000 --- a/arch/powerpc/include/asm/mpc512x.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-ppc/mpc512x.h - * - * Prototypes, etc. for the Freescale MPC512x embedded cpu chips - * - * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASMPPC_MPC512X_H -#define __ASMPPC_MPC512X_H - -/* - * macros for manipulating CSx_START/STOP - */ -#define CSAW_START(start) ((start) & 0xFFFF0000) -#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) - -/* - * Inlines - */ - -/* - * According to MPC5121e RM, configuring local access windows should - * be followed by a dummy read of the config register that was - * modified last and an isync. - */ -static inline void sync_law(volatile void *addr) -{ - in_be32(addr); - __asm__ __volatile__ ("isync"); -} - -/* - * Prototypes - */ -extern long int fixed_sdram(ddr512x_config_t *mddrc_config, - u32 *dram_init_seq, int seq_sz); -extern int mpc5121_diu_init(void); -extern void ide_set_reset(int idereset); - -#endif /* __ASMPPC_MPC512X_H */ diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h new file mode 100644 index 0000000..4d9af6c --- /dev/null +++ b/arch/powerpc/include/asm/ppc.h @@ -0,0 +1,107 @@ +/* + * Ugly header containing required header files. This could be adjusted + * so that including asm/arch/hardware includes the correct file. + * + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_PPC_H +#define __ASM_PPC_H + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_MPC86xx +#include +#include +#endif +#ifdef CONFIG_MPC85xx +#include +#include +#endif +#ifdef CONFIG_MPC83xx +#include +#include +#endif +#ifdef CONFIG_4xx +#include +#endif +#ifdef CONFIG_SOC_DA8XX +#include +#endif +#ifdef CONFIG_FSL_LSCH3 +#include +#endif +#ifdef CONFIG_FSL_LSCH2 +#include +#endif + +uint get_pvr(void); +uint get_svr(void); +uint rd_ic_cst(void); +void wr_ic_cst(uint); +void wr_ic_adr(uint); +uint rd_dc_cst(void); +void wr_dc_cst(uint); +void wr_dc_adr(uint); + +#if defined(CONFIG_4xx) || \ + defined(CONFIG_MPC85xx) || \ + defined(CONFIG_MPC86xx) || \ + defined(CONFIG_MPC83xx) +unsigned char in8(unsigned int); +void out8(unsigned int, unsigned char); +unsigned short in16(unsigned int); +unsigned short in16r(unsigned int); +void out16(unsigned int, unsigned short value); +void out16r(unsigned int, unsigned short value); +unsigned long in32(unsigned int); +unsigned long in32r(unsigned int); +void out32(unsigned int, unsigned long value); +void out32r(unsigned int, unsigned long value); +void ppcDcbf(unsigned long value); +void ppcDcbi(unsigned long value); +void ppcSync(void); +void ppcDcbz(unsigned long value); +#endif +#if defined(CONFIG_MPC83xx) +void ppcDWload(unsigned int *addr, unsigned int *ret); +void ppcDWstore(unsigned int *addr, unsigned int *value); +void disable_addr_trans(void); +void enable_addr_trans(void); +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +void ddr_enable_ecc(unsigned int dram_size); +#endif +#endif + +#if defined(CONFIG_MPC85xx) +typedef MPC85xx_SYS_INFO sys_info_t; +void get_sys_info(sys_info_t *); +void ft_fixup_cpu(void *, u64); +void ft_fixup_num_cores(void *); +#endif +#if defined(CONFIG_MPC86xx) +ulong get_bus_freq(ulong); +typedef MPC86xx_SYS_INFO sys_info_t; +void get_sys_info(sys_info_t *); +static inline ulong get_ddr_freq(ulong dummy) +{ + return get_bus_freq(dummy); +} +#else +ulong get_ddr_freq(ulong); +#endif + +#endif /* !__ASSEMBLY__ */ + +#ifdef CONFIG_PPC +/* + * Has to be included outside of the #ifndef __ASSEMBLY__ section. + * Otherwise might lead to compilation errors in assembler files. + */ +#include +#endif + +#endif diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index b8b0ff9..45ff5db 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -289,6 +289,13 @@ static inline void set_mcsr(u32 val) int ppc4xx_pci_sync_clock_config(u32 async); +unsigned long get_OPB_freq(void); +unsigned long get_PCI_freq(void); + +typedef PPC4xx_SYS_INFO sys_info_t; +int ppc440spe_revB(void); +void get_sys_info(sys_info_t *); + #endif /* __ASSEMBLY__ */ /* for multi-cpu support */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fd38da9..6549a09 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1361,15 +1361,9 @@ int prt_8260_clks(void); #endif /* ndef ASSEMBLY*/ #ifdef CONFIG_MACH_SPECIFIC -#if defined(CONFIG_8xx) -#define _machine _MACH_8xx -#define have_of 0 -#elif defined(CONFIG_WALNUT) +#if defined(CONFIG_WALNUT) #define _machine _MACH_walnut #define have_of 0 -#elif defined(CONFIG_MPC8260) -#define _machine _MACH_8260 -#define have_of 0 #else #error "Machine not defined correctly" #endif diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h deleted file mode 100644 index 1ae1b17..0000000 --- a/arch/powerpc/include/asm/status_led.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * asm/status_led.h - * - * MPC8xx/MPC8260/MPC5xx based status led support functions - */ - -#ifndef __ASM_STATUS_LED_H__ -#define __ASM_STATUS_LED_H__ - -/* if not overridden */ -#ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC -# if defined(CONFIG_8xx) -# include -# elif defined(CONFIG_MPC8260) -# include -# elif defined(CONFIG_5xx) -# include -# else -# error CPU specific Status LED header file missing. -#endif - -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -static inline void __led_init (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#ifdef STATUS_LED_PAR - immr->STATUS_LED_PAR &= ~mask; -#endif -#ifdef STATUS_LED_ODR - immr->STATUS_LED_ODR &= ~mask; -#endif - -#if (STATUS_LED_ACTIVE == 0) - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif -#ifdef STATUS_LED_DIR - immr->STATUS_LED_DIR |= mask; -#endif -} - -static inline void __led_toggle (led_id_t mask) -{ - ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask; -} - -static inline void __led_set (led_id_t mask, int state) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - -#if (STATUS_LED_ACTIVE == 0) - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT &= ~mask; - else - immr->STATUS_LED_DAT |= mask; -#else - if (state == CONFIG_LED_STATUS_ON) - immr->STATUS_LED_DAT |= mask; - else - immr->STATUS_LED_DAT &= ~mask; -#endif - -} - -#endif - -#endif /* __ASM_STATUS_LED_H__ */ diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 74b6202..34e44e1 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -16,6 +16,7 @@ /* Use the generic board which requires a unified bd_info */ #include +#include /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_PPC diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig deleted file mode 100644 index 987cec9..0000000 --- a/arch/powerpc/lib/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CMD_IMMAP - bool "Enable various commands to dump IMMR information" - help - This enables various commands such as: - - siuinfo - print System Interface Unit (SIU) registers - memcinfo - print Memory Controller registers - sitinfo - print System Integration Timers (SIT) registers diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index e09bd9a..4e47e83 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -33,30 +33,10 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o -obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o -obj-$(CONFIG_IDE) += ide.o obj-y += stack.o obj-y += time.o - -# Don't include the MPC5xxx special memcpy into the -# SPL U-Boot image. memcpy is used in the SPL NOR -# flash driver. And we need the real, fast memcpy -# here. We have no problems with unaligned access. -ifndef CONFIG_SPL_BUILD -# Workaround for local bus unaligned access problems -# on MPC512x and MPC5200 -ifdef CONFIG_MPC512X -AFLAGS_ppcstring.o += -Dmemcpy=__memcpy -obj-y += memcpy_mpc5200.o -endif -ifdef CONFIG_MPC5200 -AFLAGS_ppcstring.o += -Dmemcpy=__memcpy -obj-y += memcpy_mpc5200.o -endif -endif - endif # not minimal ifdef CONFIG_SPL_BUILD diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 17c5ed1..42a6afb 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -283,10 +283,6 @@ static void set_clocks_in_mhz (bd_t *kbd) kbd->bi_sccfreq /= 1000000L; kbd->bi_vco /= 1000000L; #endif -#if defined(CONFIG_MPC5xxx) - kbd->bi_ipbfreq /= 1000000L; - kbd->bi_pcifreq /= 1000000L; -#endif /* CONFIG_MPC5xxx */ } } diff --git a/arch/powerpc/lib/ide.c b/arch/powerpc/lib/ide.c deleted file mode 100644 index b4ead72..0000000 --- a/arch/powerpc/lib/ide.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Code taken from cmd_ide.c */ -#include -#include -#include "ide.h" - -#ifdef CONFIG_IDE_8xx_DIRECT -#include -#include -DECLARE_GLOBAL_DATA_PTR; - -/* Timings for IDE Interface - * - * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk - * 70 165 30 PIO-Mode 0, [ns] - * 4 9 2 [Cycles] - * 50 125 20 PIO-Mode 1, [ns] - * 3 7 2 [Cycles] - * 30 100 15 PIO-Mode 2, [ns] - * 2 6 1 [Cycles] - * 30 80 10 PIO-Mode 3, [ns] - * 2 5 1 [Cycles] - * 25 70 10 PIO-Mode 4, [ns] - * 2 4 1 [Cycles] - */ - -static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = { - /* Setup Length Hold */ - { 70, 165, 30 }, /* PIO-Mode 0, [ns] */ - { 50, 125, 20 }, /* PIO-Mode 1, [ns] */ - { 30, 101, 15 }, /* PIO-Mode 2, [ns] */ - { 30, 80, 10 }, /* PIO-Mode 3, [ns] */ - { 25, 70, 10 }, /* PIO-Mode 4, [ns] */ -}; - -static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1]; - -#ifndef CONFIG_SYS_PIO_MODE -#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */ -#endif -static int pio_mode = CONFIG_SYS_PIO_MODE; - -/* Make clock cycles and always round up */ - -#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U) - -static void set_pcmcia_timing(int pmode) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); - ulong timings; - - debug("Set timing for PIO Mode %d\n", pmode); - - timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold) - | PCMCIA_SST(pio_config_clk[pmode].t_setup) - | PCMCIA_SL(pio_config_clk[pmode].t_length); - - /* - * IDE 0 - */ - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0; -#if (CONFIG_SYS_PCMCIA_POR0 != 0) - pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings; -#else - pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0; -#endif - debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0); - - pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1; -#if (CONFIG_SYS_PCMCIA_POR1 != 0) - pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings; -#else - pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1; -#endif - debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1); - - pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2; -#if (CONFIG_SYS_PCMCIA_POR2 != 0) - pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings; -#else - pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2; -#endif - debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2); - - pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3; -#if (CONFIG_SYS_PCMCIA_POR3 != 0) - pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings; -#else - pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3; -#endif - debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3); - - /* - * IDE 1 - */ - pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4; -#if (CONFIG_SYS_PCMCIA_POR4 != 0) - pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings; -#else - pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4; -#endif - debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4); - - pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5; -#if (CONFIG_SYS_PCMCIA_POR5 != 0) - pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings; -#else - pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5; -#endif - debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5); - - pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6; -#if (CONFIG_SYS_PCMCIA_POR6 != 0) - pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings; -#else - pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6; -#endif - debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6); - - pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7; -#if (CONFIG_SYS_PCMCIA_POR7 != 0) - pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings; -#else - pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7; -#endif - debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7); - -} - -int ide_preinit(void) -{ - int i; - /* Initialize PIO timing tables */ - for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) { - pio_config_clk[i].t_setup = - PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk); - pio_config_clk[i].t_length = - PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk); - pio_config_clk[i].t_hold = - PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk); - debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk" - " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup, - pio_config_clk[i].t_setup, pio_config_ns[i].t_length, - pio_config_clk[i].t_length, pio_config_ns[i].t_hold, - pio_config_clk[i].t_hold); - } - - return 0; -} - -int ide_init_postreset(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); - - /* PCMCIA / IDE initialization for common mem space */ - pcmp->pcmc_pgcrb = 0; - - /* start in PIO mode 0 - most relaxed timings */ - pio_mode = 0; - set_pcmcia_timing(pio_mode); - return 0; -} -#endif /* CONFIG_IDE_8xx_DIRECT */ - -#ifdef CONFIG_IDE_8xx_PCCARD -int ide_preinit(void) -{ - ide_devices_found = 0; - /* initialize the PCMCIA IDE adapter card */ - pcmcia_on(); - if (!ide_devices_found) - return 1; - udelay(1000000);/* 1 s */ - return 0; -} -#endif diff --git a/arch/powerpc/lib/ide.h b/arch/powerpc/lib/ide.h deleted file mode 100644 index e0b2e61..0000000 --- a/arch/powerpc/lib/ide.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2012 - * Pavel Herrmann - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MPC8XX_IDE_H_ -#define _MPC8XX_IDE_H_ 1 - -#ifdef CONFIG_IDE_8xx_PCCARD -int pcmcia_on(void); -extern int ide_devices_found; -#endif -#endif diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/lib/immap.c deleted file mode 100644 index 1414f9a..0000000 --- a/arch/powerpc/lib/immap.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx/MPC8260 Internal Memory Map Functions - */ - -#include -#include - -#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) - -#if defined(CONFIG_8xx) -#include -#include -#include -#elif defined(CONFIG_MPC8260) -#include -#include -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static void -unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf ("Sorry, but the '%s' command has not been implemented\n", - cmdtp->name); -} - -int -do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_8xx) - volatile sysconf8xx_t *sc = &immap->im_siu_conf; -#elif defined(CONFIG_MPC8260) - volatile sysconf8260_t *sc = &immap->im_siu_conf; -#endif - - printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr); -#if defined(CONFIG_8xx) - printf ("SWT = %08x\n", sc->sc_swt); - printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); - printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); - printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); -#elif defined(CONFIG_MPC8260) - printf ("BCR = %08x\n", sc->sc_bcr); - printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", - sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); - printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n", - sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl); - printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2); - printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2); - printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem); - printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem); -#endif - return 0; -} - -int -do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_8xx) - volatile memctl8xx_t *memctl = &immap->im_memctl; - int nbanks = 8; -#elif defined(CONFIG_MPC8260) - volatile memctl8260_t *memctl = &immap->im_memctl; - int nbanks = 12; -#endif - volatile uint *p = &memctl->memc_br0; - int i; - - for (i = 0; i < nbanks; i++, p += 2) { - if (i < 10) { - printf ("BR%d = %08x OR%d = %08x\n", - i, p[0], i, p[1]); - } else { - printf ("BR%d = %08x OR%d = %08x\n", - i, p[0], i, p[1]); - } - } - - printf ("MAR = %08x", memctl->memc_mar); -#if defined(CONFIG_8xx) - printf (" MCR = %08x\n", memctl->memc_mcr); -#elif defined(CONFIG_MPC8260) - putc ('\n'); -#endif - printf ("MAMR = %08x MBMR = %08x", - memctl->memc_mamr, memctl->memc_mbmr); -#if defined(CONFIG_8xx) - printf ("\nMSTAT = %04x\n", memctl->memc_mstat); -#elif defined(CONFIG_MPC8260) - printf (" MCMR = %08x\n", memctl->memc_mcmr); -#endif - printf ("MPTPR = %04x MDR = %08x\n", - memctl->memc_mptpr, memctl->memc_mdr); -#if defined(CONFIG_MPC8260) - printf ("PSDMR = %08x LSDMR = %08x\n", - memctl->memc_psdmr, memctl->memc_lsdmr); - printf ("PURT = %02x PSRT = %02x\n", - memctl->memc_purt, memctl->memc_psrt); - printf ("LURT = %02x LSRT = %02x\n", - memctl->memc_lurt, memctl->memc_lsrt); - printf ("IMMR = %08x\n", memctl->memc_immr); -#endif - return 0; -} - -int -do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -#ifdef CONFIG_MPC8260 -int -do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} -#endif - -int -do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_8xx) - volatile car8xx_t *car = &immap->im_clkrst; -#elif defined(CONFIG_MPC8260) - volatile car8260_t *car = &immap->im_clkrst; -#endif - -#if defined(CONFIG_8xx) - printf ("SCCR = %08x\n", car->car_sccr); - printf ("PLPRCR= %08x\n", car->car_plprcr); - printf ("RSR = %08x\n", car->car_rsr); -#elif defined(CONFIG_MPC8260) - printf ("SCCR = %08x\n", car->car_sccr); - printf ("SCMR = %08x\n", car->car_scmr); - printf ("RSR = %08x\n", car->car_rsr); - printf ("RMR = %08x\n", car->car_rmr); -#endif - return 0; -} - -static int counter; - -static void -header(void) -{ - char *data = "\ - -------------------------------- --------------------------------\ - 00000000001111111111222222222233 00000000001111111111222222222233\ - 01234567890123456789012345678901 01234567890123456789012345678901\ - -------------------------------- --------------------------------\ - "; - int i; - - if (counter % 2) - putc('\n'); - counter = 0; - - for (i = 0; i < 4; i++, data += 79) - printf("%.79s\n", data); -} - -static void binary (char *label, uint value, int nbits) -{ - uint mask = 1 << (nbits - 1); - int i, second = (counter++ % 2); - - if (second) - putc (' '); - puts (label); - for (i = 32 + 1; i != nbits; i--) - putc (' '); - - while (mask != 0) { - if (value & mask) - putc ('1'); - else - putc ('0'); - mask >>= 1; - } - - if (second) - putc ('\n'); -} - -#if defined(CONFIG_8xx) -#define PA_NBITS 16 -#define PA_NB_ODR 8 -#define PB_NBITS 18 -#define PB_NB_ODR 16 -#define PC_NBITS 12 -#define PD_NBITS 13 -#elif defined(CONFIG_MPC8260) -#define PA_NBITS 32 -#define PA_NB_ODR 32 -#define PB_NBITS 28 -#define PB_NB_ODR 28 -#define PC_NBITS 32 -#define PD_NBITS 28 -#endif - -int -do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_8xx) - volatile iop8xx_t *iop = &immap->im_ioport; - volatile ushort *l, *r; -#elif defined(CONFIG_MPC8260) - volatile iop8260_t *iop = &immap->im_ioport; - volatile uint *l, *r; -#endif - volatile uint *R; - - counter = 0; - header (); - - /* - * Ports A & B - */ - -#if defined(CONFIG_8xx) - l = &iop->iop_padir; - R = &immap->im_cpm.cp_pbdir; -#elif defined(CONFIG_MPC8260) - l = &iop->iop_pdira; - R = &iop->iop_pdirb; -#endif - binary ("PA_DIR", *l++, PA_NBITS); - binary ("PB_DIR", *R++, PB_NBITS); - binary ("PA_PAR", *l++, PA_NBITS); - binary ("PB_PAR", *R++, PB_NBITS); -#if defined(CONFIG_MPC8260) - binary ("PA_SOR", *l++, PA_NBITS); - binary ("PB_SOR", *R++, PB_NBITS); -#endif - binary ("PA_ODR", *l++, PA_NB_ODR); - binary ("PB_ODR", *R++, PB_NB_ODR); - binary ("PA_DAT", *l++, PA_NBITS); - binary ("PB_DAT", *R++, PB_NBITS); - - header (); - - /* - * Ports C & D - */ - -#if defined(CONFIG_8xx) - l = &iop->iop_pcdir; - r = &iop->iop_pddir; -#elif defined(CONFIG_MPC8260) - l = &iop->iop_pdirc; - r = &iop->iop_pdird; -#endif - binary ("PC_DIR", *l++, PC_NBITS); - binary ("PD_DIR", *r++, PD_NBITS); - binary ("PC_PAR", *l++, PC_NBITS); - binary ("PD_PAR", *r++, PD_NBITS); -#if defined(CONFIG_8xx) - binary ("PC_SO ", *l++, PC_NBITS); - binary (" ", 0, 0); - r++; -#elif defined(CONFIG_MPC8260) - binary ("PC_SOR", *l++, PC_NBITS); - binary ("PD_SOR", *r++, PD_NBITS); - binary ("PC_ODR", *l++, PC_NBITS); - binary ("PD_ODR", *r++, PD_NBITS); -#endif - binary ("PC_DAT", *l++, PC_NBITS); - binary ("PD_DAT", *r++, PD_NBITS); -#if defined(CONFIG_8xx) - binary ("PC_INT", *l++, PC_NBITS); -#endif - - header (); - return 0; -} - -/* - * set the io pins - * this needs a clean up for smaller tighter code - * use *uint and set the address based on cmd + port - */ -int -do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uint rcode = 0; - iopin_t iopin; - static uint port = 0; - static uint pin = 0; - static uint value = 0; - static enum { - DIR, - PAR, - SOR, - ODR, - DAT, -#if defined(CONFIG_8xx) - INT -#endif - } cmd = DAT; - - if (argc != 5) { - puts ("iopset PORT PIN CMD VALUE\n"); - return 1; - } - port = argv[1][0] - 'A'; - if (port > 3) - port -= 0x20; - if (port > 3) - rcode = 1; - pin = simple_strtol (argv[2], NULL, 10); - if (pin > 31) - rcode = 1; - - - switch (argv[3][0]) { - case 'd': - if (argv[3][1] == 'a') - cmd = DAT; - else if (argv[3][1] == 'i') - cmd = DIR; - else - rcode = 1; - break; - case 'p': - cmd = PAR; - break; - case 'o': - cmd = ODR; - break; - case 's': - cmd = SOR; - break; -#if defined(CONFIG_8xx) - case 'i': - cmd = INT; - break; -#endif - default: - printf ("iopset: unknown command %s\n", argv[3]); - rcode = 1; - } - if (argv[4][0] == '1') - value = 1; - else if (argv[4][0] == '0') - value = 0; - else - rcode = 1; - if (rcode == 0) { - iopin.port = port; - iopin.pin = pin; - iopin.flag = 0; - switch (cmd) { - case DIR: - if (value) - iopin_set_out (&iopin); - else - iopin_set_in (&iopin); - break; - case PAR: - if (value) - iopin_set_ded (&iopin); - else - iopin_set_gen (&iopin); - break; - case SOR: - if (value) - iopin_set_opt2 (&iopin); - else - iopin_set_opt1 (&iopin); - break; - case ODR: - if (value) - iopin_set_odr (&iopin); - else - iopin_set_act (&iopin); - break; - case DAT: - if (value) - iopin_set_high (&iopin); - else - iopin_set_low (&iopin); - break; -#if defined(CONFIG_8xx) - case INT: - if (value) - iopin_set_falledge (&iopin); - else - iopin_set_anyedge (&iopin); - break; -#endif - } - - } - return rcode; -} - -int -do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -static void prbrg (int n, uint val) -{ - uint extc = (val >> 14) & 3; - uint cd = (val & CPM_BRG_CD_MASK) >> 1; - uint div16 = (val & CPM_BRG_DIV16) != 0; - -#if defined(CONFIG_8xx) - ulong clock = gd->cpu_clk; -#elif defined(CONFIG_MPC8260) - ulong clock = gd->arch.brg_clk; -#endif - - printf ("BRG%d:", n); - - if (val & CPM_BRG_RST) - puts (" RESET"); - else - puts (" "); - - if (val & CPM_BRG_EN) - puts (" ENABLED"); - else - puts (" DISABLED"); - - printf (" EXTC=%d", extc); - - if (val & CPM_BRG_ATB) - puts (" ATB"); - else - puts (" "); - - printf (" DIVIDER=%4d", cd); - if (extc == 0 && cd != 0) { - uint baudrate; - - if (div16) - baudrate = (clock / 16) / (cd + 1); - else - baudrate = clock / (cd + 1); - - printf ("=%6d bps", baudrate); - } else { - puts (" "); - } - - if (val & CPM_BRG_DIV16) - puts (" DIV16"); - else - puts (" "); - - putc ('\n'); -} - -int -do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_8xx) - volatile cpm8xx_t *cp = &immap->im_cpm; - volatile uint *p = &cp->cp_brgc1; -#elif defined(CONFIG_MPC8260) - volatile uint *p = &immap->im_brgc1; -#endif - int i = 1; - - while (i <= 4) - prbrg (i++, *p++); - -#if defined(CONFIG_MPC8260) - p = &immap->im_brgc5; - while (i <= 8) - prbrg (i++, *p++); -#endif - return 0; -} - -int -do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - -#if defined(CONFIG_8xx) - volatile i2c8xx_t *i2c = &immap->im_i2c; - volatile cpm8xx_t *cp = &immap->im_cpm; - volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC]; -#elif defined(CONFIG_MPC8260) - volatile i2c8260_t *i2c = &immap->im_i2c; - volatile iic_t *iip; - uint dpaddr; - - dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)]; - if (dpaddr == 0) - iip = NULL; - else - iip = (iic_t *) & immap->im_dprambase[dpaddr]; -#endif - - printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add); - printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com); - printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr); - - if (iip == NULL) - puts ("i2c parameter ram not allocated\n"); - else { - printf ("RBASE = %08x TBASE = %08x\n", - iip->iic_rbase, iip->iic_tbase); - printf ("RFCR = %02x TFCR = %02x\n", - iip->iic_rfcr, iip->iic_tfcr); - printf ("MRBLR = %04x\n", iip->iic_mrblr); - printf ("RSTATE= %08x RDP = %08x\n", - iip->iic_rstate, iip->iic_rdp); - printf ("RBPTR = %04x RBC = %04x\n", - iip->iic_rbptr, iip->iic_rbc); - printf ("RXTMP = %08x\n", iip->iic_rxtmp); - printf ("TSTATE= %08x TDP = %08x\n", - iip->iic_tstate, iip->iic_tdp); - printf ("TBPTR = %04x TBC = %04x\n", - iip->iic_tbptr, iip->iic_tbc); - printf ("TXTMP = %08x\n", iip->iic_txtmp); - } - return 0; -} - -int -do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -int -do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unimplemented (cmdtp, flag, argc, argv); - return 0; -} - -/***************************************************/ - -U_BOOT_CMD( - siuinfo, 1, 1, do_siuinfo, - "print System Interface Unit (SIU) registers", - "" -); - -U_BOOT_CMD( - memcinfo, 1, 1, do_memcinfo, - "print Memory Controller registers", - "" -); - -U_BOOT_CMD( - sitinfo, 1, 1, do_sitinfo, - "print System Integration Timers (SIT) registers", - "" -); - -#ifdef CONFIG_MPC8260 -U_BOOT_CMD( - icinfo, 1, 1, do_icinfo, - "print Interrupt Controller registers", - "" -); -#endif - -U_BOOT_CMD( - carinfo, 1, 1, do_carinfo, - "print Clocks and Reset registers", - "" -); - -U_BOOT_CMD( - iopinfo, 1, 1, do_iopinfo, - "print I/O Port registers", - "" -); - -U_BOOT_CMD( - iopset, 5, 0, do_iopset, - "set I/O Port registers", - "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" -); - -U_BOOT_CMD( - dmainfo, 1, 1, do_dmainfo, - "print SDMA/IDMA registers", - "" -); - -U_BOOT_CMD( - fccinfo, 1, 1, do_fccinfo, - "print FCC registers", - "" -); - -U_BOOT_CMD( - brginfo, 1, 1, do_brginfo, - "print Baud Rate Generator (BRG) registers", - "" -); - -U_BOOT_CMD( - i2cinfo, 1, 1, do_i2cinfo, - "print I2C registers", - "" -); - -U_BOOT_CMD( - sccinfo, 1, 1, do_sccinfo, - "print SCC registers", - "" -); - -U_BOOT_CMD( - smcinfo, 1, 1, do_smcinfo, - "print SMC registers", - "" -); - -U_BOOT_CMD( - spiinfo, 1, 1, do_spiinfo, - "print Serial Peripheral Interface (SPI) registers", - "" -); - -U_BOOT_CMD( - muxinfo, 1, 1, do_muxinfo, - "print CPM Multiplexing registers", - "" -); - -U_BOOT_CMD( - siinfo, 1, 1, do_siinfo, - "print Serial Interface (SI) registers", - "" -); - -U_BOOT_CMD( - mccinfo, 1, 1, do_mccinfo, - "print MCC registers", - "" -); - -#endif diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 01a7708..88c2af2 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -159,20 +159,6 @@ kgdb_trap(struct pt_regs *regs) #define SPACE_REQUIRED ((32*4)+(32*8)+(6*4)) -#ifdef CONFIG_MPC8260 -/* store floating double indexed */ -#define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n])) -/* store floating double multiple */ -#define STFDM(p) { STFDI( 0,p); STFDI( 1,p); STFDI( 2,p); STFDI( 3,p); \ - STFDI( 4,p); STFDI( 5,p); STFDI( 6,p); STFDI( 7,p); \ - STFDI( 8,p); STFDI( 9,p); STFDI(10,p); STFDI(11,p); \ - STFDI(12,p); STFDI(13,p); STFDI(14,p); STFDI(15,p); \ - STFDI(16,p); STFDI(17,p); STFDI(18,p); STFDI(19,p); \ - STFDI(20,p); STFDI(21,p); STFDI(22,p); STFDI(23,p); \ - STFDI(24,p); STFDI(25,p); STFDI(26,p); STFDI(27,p); \ - STFDI(28,p); STFDI(29,p); STFDI(30,p); STFDI(31,p); } -#endif - int kgdb_getregs(struct pt_regs *regs, char *buf, int max) { @@ -190,15 +176,10 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) *ptr++ = regs->gpr[i]; /* Floating Point Regs */ -#ifdef CONFIG_MPC8260 - STFDM(ptr); - ptr += 32*2; -#else for (i = 0; i < 32; i++) { *ptr++ = 0; *ptr++ = 0; } -#endif /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ *ptr++ = regs->nip; @@ -212,23 +193,6 @@ kgdb_getregs(struct pt_regs *regs, char *buf, int max) } /* set the value of the CPU registers */ - -#ifdef CONFIG_MPC8260 -/* load floating double */ -#define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v)) -/* load floating double indexed */ -#define LFDI(n,p) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"((p)[2*n])) -/* load floating double multiple */ -#define LFDM(p) { LFDI( 0,p); LFDI( 1,p); LFDI( 2,p); LFDI( 3,p); \ - LFDI( 4,p); LFDI( 5,p); LFDI( 6,p); LFDI( 7,p); \ - LFDI( 8,p); LFDI( 9,p); LFDI(10,p); LFDI(11,p); \ - LFDI(12,p); LFDI(13,p); LFDI(14,p); LFDI(15,p); \ - LFDI(16,p); LFDI(17,p); LFDI(18,p); LFDI(19,p); \ - LFDI(20,p); LFDI(21,p); LFDI(22,p); LFDI(23,p); \ - LFDI(24,p); LFDI(25,p); LFDI(26,p); LFDI(27,p); \ - LFDI(28,p); LFDI(29,p); LFDI(30,p); LFDI(31,p); } -#endif - void kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) { @@ -251,19 +215,6 @@ kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) if (regno >= 0 && regno < 32) regs->gpr[regno] = *ptr; else switch (regno) { - -#ifdef CONFIG_MPC8260 -#define caseF(n) \ - case (n) + 32: LFD(n, *ptr); break; - -caseF( 0) caseF( 1) caseF( 2) caseF( 3) caseF( 4) caseF( 5) caseF( 6) caseF( 7) -caseF( 8) caseF( 9) caseF(10) caseF(11) caseF(12) caseF(13) caseF(14) caseF(15) -caseF(16) caseF(17) caseF(18) caseF(19) caseF(20) caseF(21) caseF(22) caseF(23) -caseF(24) caseF(25) caseF(26) caseF(27) caseF(28) caseF(29) caseF(30) caseF(31) - -#undef caseF -#endif - case 64: regs->nip = *ptr; break; case 65: regs->msr = *ptr; break; case 66: regs->ccr = *ptr; break; @@ -298,9 +249,6 @@ kgdb_putregs(struct pt_regs *regs, char *buf, int length) regs->gpr[i] = *ptr++; /* Floating Point Regs */ -#ifdef CONFIG_MPC8260 - LFDM(ptr); -#endif ptr += 32*2; /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ diff --git a/arch/powerpc/lib/memcpy_mpc5200.c b/arch/powerpc/lib/memcpy_mpc5200.c deleted file mode 100644 index 7e5a005..0000000 --- a/arch/powerpc/lib/memcpy_mpc5200.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This is a workaround for issues on the MPC5200, where unaligned - * 32-bit-accesses to the local bus will deliver corrupted data. This - * happens for example when trying to use memcpy() from an odd NOR - * flash address; the behaviour can be also seen when using "md" on an - * odd NOR flash address (but there it is not a bug in U-Boot, which - * only shows the behaviour of this processor). - * - * For memcpy(), we test if either the source or the target address - * are not 32 bit aligned, and - if so - if the source address is in - * NOR flash: in this case we perform a byte-wise (slow) then; for - * aligned operations of non-flash areas we use the optimized (fast) - * real __memcpy(). This way we minimize the performance impact of - * this workaround. - * - */ - -#include -#include -#include - -void *memcpy(void *trg, const void *src, size_t len) -{ - extern void* __memcpy(void *, const void *, size_t); - char *s = (char *)src; - char *t = (char *)trg; - void *dest = (void *)trg; - - /* - * Check is source address is in flash: - * If not, we use the fast assembler code - */ - if (((((unsigned long)s & 3) == 0) /* source aligned */ - && /* AND */ - (((unsigned long)t & 3) == 0)) /* target aligned, */ - || /* or */ - (addr2info((ulong)s) == NULL)) { /* source not in flash */ - return __memcpy(trg, src, len); - } - - /* - * Copying from flash, perform byte by byte copy. - */ - while (len-- > 0) - *t++ = *s++; - - return dest; -} diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index de5f0be..3a5ad4d 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -64,21 +64,10 @@ int timer_init(void) { unsigned long temp; -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* unlock */ - immap->im_sitk.sitk_tbk = KAPWR_KEY; -#endif - /* reset */ asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;" : "=&r"(temp) ); -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) - /* enable */ - immap->im_sit.sit_tbscr |= TBSCR_TBE; -#endif return (0); } /* ------------------------------------------------------------------------- */ diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 3fe99b8..eefed2e 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -139,3 +139,14 @@ done: return 0; } + +ulong timer_get_boot_us(void) +{ + static uint64_t base_count; + uint64_t count = os_get_nsec(); + + if (!base_count) + base_count = count; + + return (count - base_count) / 1000; +} diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 35ea00c..7243bfc 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -395,7 +395,7 @@ const char *os_dirent_typename[OS_FILET_COUNT] = { const char *os_dirent_get_typename(enum os_dirent_t type) { - if (type >= 0 && type < OS_FILET_COUNT) + if (type >= OS_FILET_REG && type < OS_FILET_COUNT) return os_dirent_typename[type]; return os_dirent_typename[OS_FILET_UNKNOWN]; diff --git a/arch/sandbox/include/asm/u-boot.h b/arch/sandbox/include/asm/u-boot.h index 8279894..ddcd6fb 100644 --- a/arch/sandbox/include/asm/u-boot.h +++ b/arch/sandbox/include/asm/u-boot.h @@ -22,6 +22,7 @@ /* Use the generic board which requires a unified bd_info */ #include +#include /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_SANDBOX diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 1c8ac37..6c85186 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -17,4 +17,8 @@ config INTERNAL_UART reason, it is recommended that the UART port be used for debug purposes only, eg: U-Boot console. +config DEBUG_UART + bool + select DEBUG_UART_BOARD_INIT + endif diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index 471d592..afab21f 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -80,3 +80,8 @@ int setup_internal_uart(int enable) return 0; } + +void board_debug_uart_init(void) +{ + setup_internal_uart(1); +} diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index d49b8d2..45f9bf9 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -148,10 +148,10 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, "fsp,mrc-init-tseg-size", - 0); + MRC_INIT_TSEG_SIZE_1MB); fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, "fsp,mrc-init-mmio-size", - 0x800); + MRC_INIT_MMIO_SIZE_2048MB); fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, "fsp,mrc-init-spd-addr1", 0xa0); @@ -159,7 +159,8 @@ void update_fsp_configs(struct fsp_config_data *config, "fsp,mrc-init-spd-addr2", 0xa2); fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, - "fsp,emmc-boot-mode", 2); + "fsp,emmc-boot-mode", + EMMC_BOOT_MODE_EMMC41); fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, "fsp,enable-sdcard"); @@ -169,13 +170,15 @@ void update_fsp_configs(struct fsp_config_data *config, "fsp,enable-hsuart1"); fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); - fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1); + fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", + SATA_MODE_AHCI); fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia"); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); - fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe"); - fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node, - "fsp,lpss-sio-enable-pci-mode"); + fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", + LPE_MODE_PCI); + fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode", + LPSS_SIO_MODE_PCI); fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); @@ -189,25 +192,22 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, - "fsp,igd-dvmt50-pre-alloc", 2); + "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB); fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", - 2); - fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2); - fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node, - "fsp,serial-debug-port-address", 0x3f8); - fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node, - "fsp,serial-debug-port-type", 1); + APERTURE_SIZE_256MB); + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", + GTT_SIZE_2MB); fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, "fsp,mrc-debug-msg"); fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); - fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node, - "fsp,scc-enable-pci-mode"); + fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode", + SCC_MODE_PCI); fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, "fsp,igd-render-standby"); fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, "fsp,txe-uma-enable"); fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", - 4); + OS_SELECTION_LINUX); fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, "fsp,emmc45-ddr50-enabled"); fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, @@ -228,30 +228,32 @@ void update_fsp_configs(struct fsp_config_data *config, } else { mem->dram_speed = fdtdec_get_int(blob, node, "fsp,dram-speed", - 0x02); + DRAM_SPEED_1333MTS); mem->dram_type = fdtdec_get_int(blob, node, - "fsp,dram-type", 0x01); + "fsp,dram-type", + DRAM_TYPE_DDR3L); mem->dimm_0_enable = fdtdec_get_bool(blob, node, "fsp,dimm-0-enable"); mem->dimm_1_enable = fdtdec_get_bool(blob, node, "fsp,dimm-1-enable"); mem->dimm_width = fdtdec_get_int(blob, node, "fsp,dimm-width", - 0x00); + DIMM_WIDTH_X8); mem->dimm_density = fdtdec_get_int(blob, node, "fsp,dimm-density", - 0x01); + DIMM_DENSITY_2GBIT); mem->dimm_bus_width = fdtdec_get_int(blob, node, - "fsp,dimm-bus-width", 0x03); + "fsp,dimm-bus-width", + DIMM_BUS_WIDTH_64BITS); mem->dimm_sides = fdtdec_get_int(blob, node, "fsp,dimm-sides", - 0x00); + DIMM_SIDES_1RANKS); mem->dimm_tcl = fdtdec_get_int(blob, node, "fsp,dimm-tcl", 0x09); mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, "fsp,dimm-trpt-rcd", 0x09); mem->dimm_twr = fdtdec_get_int(blob, node, - "fsp,dimm-twr", 0x0A); + "fsp,dimm-twr", 0x0a); mem->dimm_twtr = fdtdec_get_int(blob, node, "fsp,dimm-twtr", 0x05); mem->dimm_trrd = fdtdec_get_int(blob, node, diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 1ae058d..0c314e0 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include #include @@ -236,19 +237,19 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,sata-mode = ; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -260,13 +261,11 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index aa8bfb8..171e7ff 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include @@ -259,15 +260,15 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; + fsp,sata-mode = ; fsp,enable-azalia; - fsp,lpss-sio-enable-pci-mode; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -279,14 +280,12 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,enable-igd; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; }; microcode { diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 898e9c9..ae11ccc 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include @@ -246,42 +247,42 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,sata-mode = ; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <2>; /* 2=1333MHz */ - fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; fsp,dimm-1-enable; - fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ - fsp,dimm-density = <2>; /* 2=4Gbit */ - fsp,dimm-bus-width = <3>; /* 3=64bits */ - fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; /* These following values might need a re-visit */ fsp,dimm-tcl = <8>; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 546981a..04aa95a 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include @@ -248,20 +249,20 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart0; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,sata-mode = ; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -273,24 +274,24 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <2>; /* 2=1333MHz */ - fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; - fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ - fsp,dimm-density = <3>; /* 3=8Gbit */ - fsp,dimm-bus-width = <3>; /* 3=64bits */ - fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; /* These following values might need a re-visit */ fsp,dimm-tcl = <8>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index af64c68..4c0a8fe 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include #include @@ -260,19 +261,19 @@ fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <1>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,sata-mode = ; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -284,26 +285,24 @@ fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <1>; - fsp,dram-type = <1>; + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; - fsp,dimm-width = <1>; - fsp,dimm-density = <2>; - fsp,dimm-bus-width = <3>; - fsp,dimm-sides = <0>; + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; fsp,dimm-tcl = <0xb>; fsp,dimm-trpt-rcd = <0xb>; fsp,dimm-twr = <0xc>; diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h index e539890..1c6c247 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -7,6 +7,7 @@ #ifndef __FSP_CONFIGS_H__ #define __FSP_CONFIGS_H__ +#ifndef __ASSEMBLY__ struct fsp_config_data { struct fsp_cfg_common common; struct upd_region fsp_upd; @@ -15,5 +16,91 @@ struct fsp_config_data { struct fspinit_rtbuf { struct common_buf common; /* FSP common runtime data structure */ }; +#endif + +/* FSP user configuration settings */ + +#define MRC_INIT_TSEG_SIZE_1MB 1 +#define MRC_INIT_TSEG_SIZE_2MB 2 +#define MRC_INIT_TSEG_SIZE_4MB 4 +#define MRC_INIT_TSEG_SIZE_8MB 8 + +#define MRC_INIT_MMIO_SIZE_1024MB 0x400 +#define MRC_INIT_MMIO_SIZE_1536MB 0x600 +#define MRC_INIT_MMIO_SIZE_2048MB 0x800 + +#define EMMC_BOOT_MODE_DISABLED 0 +#define EMMC_BOOT_MODE_AUTO 1 +#define EMMC_BOOT_MODE_EMMC41 2 +#define EMMC_BOOT_MODE_EMCC45 3 + +#define SATA_MODE_IDE 0 +#define SATA_MODE_AHCI 1 + +#define IGD_DVMT50_PRE_ALLOC_32MB 0x01 +#define IGD_DVMT50_PRE_ALLOC_64MB 0x02 +#define IGD_DVMT50_PRE_ALLOC_96MB 0x03 +#define IGD_DVMT50_PRE_ALLOC_128MB 0x04 +#define IGD_DVMT50_PRE_ALLOC_160MB 0x05 +#define IGD_DVMT50_PRE_ALLOC_192MB 0x06 +#define IGD_DVMT50_PRE_ALLOC_224MB 0x07 +#define IGD_DVMT50_PRE_ALLOC_256MB 0x08 +#define IGD_DVMT50_PRE_ALLOC_288MB 0x09 +#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a +#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b +#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c +#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d +#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e +#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f +#define IGD_DVMT50_PRE_ALLOC_512MB 0x10 + +#define APERTURE_SIZE_128MB 1 +#define APERTURE_SIZE_256MB 2 +#define APERTURE_SIZE_512MB 3 + +#define GTT_SIZE_1MB 1 +#define GTT_SIZE_2MB 2 + +#define OS_SELECTION_ANDROID 1 +#define OS_SELECTION_LINUX 4 + +#define DRAM_SPEED_800MTS 0 +#define DRAM_SPEED_1066MTS 1 +#define DRAM_SPEED_1333MTS 2 +#define DRAM_SPEED_1600MTS 3 + +#define DRAM_TYPE_DDR3 0 +#define DRAM_TYPE_DDR3L 1 +#define DRAM_TYPE_DDR3ECC 2 +#define DRAM_TYPE_LPDDR2 4 +#define DRAM_TYPE_LPDDR3 5 +#define DRAM_TYPE_DDR4 6 + +#define DIMM_WIDTH_X8 0 +#define DIMM_WIDTH_X16 1 +#define DIMM_WIDTH_X32 2 + +#define DIMM_DENSITY_1GBIT 0 +#define DIMM_DENSITY_2GBIT 1 +#define DIMM_DENSITY_4GBIT 2 +#define DIMM_DENSITY_8GBIT 3 + +#define DIMM_BUS_WIDTH_8BITS 0 +#define DIMM_BUS_WIDTH_16BITS 1 +#define DIMM_BUS_WIDTH_32BITS 2 +#define DIMM_BUS_WIDTH_64BITS 3 + +#define DIMM_SIDES_1RANKS 0 +#define DIMM_SIDES_2RANKS 1 + +#define LPE_MODE_DISABLED 0 +#define LPE_MODE_PCI 1 +#define LPE_MODE_ACPI 2 + +#define LPSS_SIO_MODE_ACPI 0 +#define LPSS_SIO_MODE_PCI 1 + +#define SCC_MODE_ACPI 0 +#define SCC_MODE_PCI 1 #endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 3c782a8..8c07b37 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -47,8 +47,8 @@ struct __packed upd_region { uint8_t enable_azalia; /* Offset 0x002f */ uint32_t azalia_config_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ - uint8_t enable_lpe; /* Offset 0x0035 */ - uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */ + uint8_t lpe_mode; /* Offset 0x0035 */ + uint8_t lpss_sio_mode; /* Offset 0x0036 */ uint8_t enable_dma0; /* Offset 0x0037 */ uint8_t enable_dma1; /* Offset 0x0038 */ uint8_t enable_i2_c0; /* Offset 0x0039 */ @@ -64,11 +64,10 @@ struct __packed upd_region { uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */ uint8_t aperture_size; /* Offset 0x0044 */ uint8_t gtt_size; /* Offset 0x0045 */ - uint32_t serial_debug_port_address; /* Offset 0x0046 */ - uint8_t serial_debug_port_type; /* Offset 0x004a */ + uint8_t reserved2[5]; /* Offset 0x0046 */ uint8_t mrc_debug_msg; /* Offset 0x004b */ uint8_t isp_enable; /* Offset 0x004c */ - uint8_t scc_enable_pci_mode; /* Offset 0x004d */ + uint8_t scc_mode; /* Offset 0x004d */ uint8_t igd_render_standby; /* Offset 0x004e */ uint8_t txe_uma_enable; /* Offset 0x004f */ uint8_t os_selection; /* Offset 0x0050 */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index d55455f..187fe5f 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -8,13 +8,15 @@ #ifndef _U_BOOT_I386_H_ #define _U_BOOT_I386_H_ 1 +struct global_data; + extern char gdt_rom[]; /* cpu/.../cpu.c */ int arch_cpu_init(void); int x86_cpu_init_f(void); int cpu_init_f(void); -void setup_gdt(gd_t *id, u64 *gdt_addr); +void setup_gdt(struct global_data *id, u64 *gdt_addr); /* * Setup FSP execution environment GDT to use the one we used in * arch/x86/cpu/start16.S and reload the segment registers. diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h index 623771a..4c4527e 100644 --- a/arch/x86/include/asm/u-boot.h +++ b/arch/x86/include/asm/u-boot.h @@ -22,6 +22,7 @@ /* Use the generic board which requires a unified bd_info */ #include +#include /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_I386 diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index a480361..ab8340c 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -110,10 +110,6 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct upd_region *fsp_upd; #endif -#ifdef CONFIG_INTERNAL_UART - setup_internal_uart(1); -#endif - fsp_hdr = find_fsp_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */ diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index a462941..79608f4 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -11,6 +11,8 @@ #include #endif #include +#include +#include #include #include diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c index fd1965d..3a58402 100644 --- a/board/Barix/ipam390/ipam390.c +++ b/board/Barix/ipam390/ipam390.c @@ -29,6 +29,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index b1ae079..e8c6401 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -687,7 +687,12 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(1, 0, 0, -1, -1); + int rc = 0; + + rc |= omap_mmc_init(0, 0, 0, -1, -1); + rc |= omap_mmc_init(1, 0, 0, -1, -1); + + return rc; } #endif int overwrite_console(void) diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index edf6281..736d65c 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -14,6 +14,7 @@ #include "../common/common.h" #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 263bb54..2e6e9ef 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 17e6296..16d6947 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c index 24ee679..0ef63b7 100644 --- a/board/Marvell/aspenite/aspenite.c +++ b/board/Marvell/aspenite/aspenite.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index 16040e1..05ce98b 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -19,6 +19,7 @@ #include #include #include +#include #ifdef CONFIG_ARMADA100_FEC #include diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index b0d5f1e..af0c491 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 17a6560..f6cffc8 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 8907fb5..c7dfaa2 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 83ab1bc..f444c16 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "dockstar.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index 1f4fb92..5d0a424 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c index c5349b9..18c2895 100644 --- a/board/Seagate/nas220/nas220.c +++ b/board/Seagate/nas220/nas220.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index b46c09d..0c2f525 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig deleted file mode 100644 index 444c450..0000000 --- a/board/a3m071/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_A3M071 - -config SYS_BOARD - default "a3m071" - -config SYS_CONFIG_NAME - default "a3m071" - -endif diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS deleted file mode 100644 index 975107d..0000000 --- a/board/a3m071/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -A3M071 BOARD -M: Stefan Roese -S: Maintained -F: board/a3m071/ -F: include/configs/a3m071.h -F: configs/a3m071_defconfig -F: configs/a4m2k_defconfig diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile deleted file mode 100644 index 4e31e33..0000000 --- a/board/a3m071/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := a3m071.o diff --git a/board/a3m071/README b/board/a3m071/README deleted file mode 100644 index 112c47b..0000000 --- a/board/a3m071/README +++ /dev/null @@ -1,80 +0,0 @@ ------------------------------------------------------------------------- -A3M071 board support ------------------------------------------------------------------------- - - -SPL NOR flash support: ----------------------- -To boot fast into the OS (Linux), this board port integrates the SPL -framework. This means, that a special, stripped-down version of -U-Boot runs in the beginning. In the case of the A3M071 board, this -SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either -boot the OS (Linux) or a "real", full-blown U-Boot. This detection -on whether to boot Linux or U-Boot is done by using the "boot_os" -environment variable. If "boot_os" is set to "yes", Linux will be -loaded and booted from the SPL U-Boot version. Otherwise, the -full-blown U-Boot version will be loaded and run. - -Enabling Linux booting: ------------------------ -From U-Boot: -=> setenv boot_os yes -=> saveenv - -From Linux: -$ fw_setenv boot_os yes - -Enabling U-Boot booting: ------------------------- -From U-Boot: -=> setenv boot_os no -=> saveenv - -From Linux: -$ fw_setenv boot_os no - - -Preparing Linux image(s) for booting from SPL U-Boot: ------------------------------------------------------ -To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get -prepard/patched first. U-Boot usually inserts some dynamic values into -the DT binary (blob), e.g. autodetected memory size, MAC addresses, -clocks speeds etc. To generate this patched DT blob, you can use -the following command: - -1. Load fdt blob to SDRAM: -=> tftp 1800000 a3m071/a3m071.dtb - -2. Set bootargs as desired for Linux booting (e.g. flash_mtd): -=> run mtdargs addip2 addtty - -3. Use "fdt" commands to patch the DT blob: -=> fdt addr 1800000 -=> fdt boardsetup -=> fdt chosen - -4. Display patched DT blob (optional): -=> fdt print - -5. Save fdt to NOR flash: -=> erase fc180000 fc07ffff -=> cp.b 1800000 fc180000 10000 - -All this can be integrated into an environment command: -=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \ - fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \ - cp.b 1800000 fc180000 10000' -=> saveenv - -After this, only "run upd_fdt" needs to get called to load, patch -and save the DT blob into NOR flash. - -Additionally, the Linux kernel image has to be saved uncompressed in -its uImage file (and not gzip compressed). This can be done with this -command: - -$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \ - -n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed - ------------------------------------------------------------------------- -Stefan Roese, 2012-08-23 diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c deleted file mode 100644 index 7e16aaf..0000000 --- a/board/a3m071/a3m071.c +++ /dev/null @@ -1,479 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * MicroSys GmbH - * - * Copyright 2012-2013 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_A4M2K -#include "is46r16320d.h" -#else -#include "mt46v16m16-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_SYS_RAMBOOT) && \ - (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - -#ifdef SDRAM_DDR - /* set mode register: extended mode */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); -#endif - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - - /* auto refresh */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); - - /* set mode register */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control); - - /* - * Wait a short while for the DLL to lock before accessing - * the SDRAM - */ - udelay(100); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. - */ -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#if !defined(CONFIG_SYS_RAMBOOT) && \ - (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ - - /* setup config registers */ - out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - -#ifdef SDRAM_DDR - /* set tap delay */ - out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, - 0x13 + __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) - out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -static void get_revisions(int *failsavelevel, int *digiboardversion, - int *fpgaversion) -{ - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - u8 val; - - /* read digitalboard-version from TMR[2..4] */ - val = 0; - val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; - val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0; - val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; - *digiboardversion = val; - - /* - * A4M2K only supports digiboardversion. No failsavelevel and - * fpgaversion here. - */ -#if !defined(CONFIG_A4M2K) - /* - * Figure out failsavelevel - * see ticket dsvk#59 - */ - *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ - - if (*digiboardversion == 0) { - *failsavelevel = 1; /* digiboard-version ok */ - - /* read fpga-version from TMR[5..7] */ - val = 0; - val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0; - val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0; - val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0; - *fpgaversion = val; - - if (*fpgaversion == 1) - *failsavelevel = 2; /* fpga-version ok */ - } -#endif -} - -/* - * This function is called from the SPL U-Boot version for - * early init stuff, that needs to be done for OS (e.g. Linux) - * booting. Doing it later in the real U-Boot would not work - * in case that the SPL U-Boot boots Linux directly. - */ -void spl_board_init(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - -#if defined(CONFIG_A4M2K) - /* enable CS3 and CS5 (FPGA) */ - setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21)); -#else - int digiboardversion; - int failsavelevel; - int fpgaversion; - u32 val; - - get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); - - val = in_be32(&mm->ipbi_ws_ctrl); - - /* first clear bits 19..21 (CS3...5) */ - val &= ~((1 << 19) | (1 << 20) | (1 << 21)); - if (failsavelevel == 2) { - /* FPGA ok */ - val |= (1 << 19) | (1 << 21); - } - - if (failsavelevel >= 1) { - /* at least digiboard-version ok */ - val |= (1 << 20); - } - - /* And write new value back to register */ - out_be32(&mm->ipbi_ws_ctrl, val); - - - /* Setup pin multiplexing */ - if (failsavelevel == 2) { - /* fpga-version ok */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2); -#endif - } else if (failsavelevel == 1) { - /* digiboard-version ok - fpga not */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1); -#endif - } else { - /* full failsave-mode */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); -#endif - } -#endif - - /* - * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see - * ticket #60 - * - * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT) - * set bit 0(msb) to 1 - */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN); - -#if defined(CONFIG_A4M2K) - /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */ - - /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */ - gpio->simple_ddr |= 1 << (31 - 15); - gpio->simple_ddr |= 1 << (31 - 14); - gpio->simple_ddr |= 1 << (31 - 13); - gpio->simple_ddr |= 1 << (31 - 12); - - /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 15); - gpio->simple_gpioe |= 1 << (31 - 14); - gpio->simple_gpioe |= 1 << (31 - 13); - gpio->simple_gpioe |= 1 << (31 - 12); - - /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */ - - /* set PSC2[0..2] (STSLED[0..2]) direction to output */ - gpio->simple_ddr |= 1 << (31 - 27); - gpio->simple_ddr |= 1 << (31 - 26); - gpio->simple_ddr |= 1 << (31 - 25); - - /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 27); - gpio->simple_gpioe |= 1 << (31 - 26); - gpio->simple_gpioe |= 1 << (31 - 25); - - /* Setup PSC6[2] as MRST2 self reset GPIO output */ - - /* set PSC6[2]/IRDA_TX (MRST2) direction to output */ - gpio->simple_ddr |= 1 << (31 - 3); - - /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */ - gpio->simple_ode |= 1 << (31 - 3); - - /* set PSC6[2]/IRDA_TX (MRST2) output as default high */ - gpio->simple_dvo |= 1 << (31 - 3); - - /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 3); - - /* Setup PSC6[3] as HARNSSCD harness code GPIO input */ - - /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */ - gpio->simple_ddr |= 0 << (31 - 2); - - /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 2); -#else - /* setup GPIOs for status-leds if needed - see ticket #57 */ - if (failsavelevel > 0) { - /* digiboard-version is OK */ - /* LED is LOW ACTIVE - so deactivate by set output to 1 */ - gpio->simple_dvo |= 1 << (31 - 12); - gpio->simple_dvo |= 1 << (31 - 13); - /* set GPIO direction to output */ - gpio->simple_ddr |= 1 << (31 - 12); - gpio->simple_ddr |= 1 << (31 - 13); - /* open drain config is set to "normal output" at reset */ - /* gpio->simple_ode &=~ ( 1 << (31-12) ); */ - /* gpio->simple_ode &=~ ( 1 << (31-13) ); */ - /* enable as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 12); - gpio->simple_gpioe |= 1 << (31 - 13); - } - - /* setup fpga irq - see ticket #65 */ - if (failsavelevel > 1) { - /* - * The main irq initialisation is done in interrupts.c - * mpc5xxx_init_irq - */ - struct mpc5xxx_intr *intr = - (struct mpc5xxx_intr *)(MPC5XXX_ICTL); - - setbits_be32(&intr->ctrl, 0x08C01801); - - /* - * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the - * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above - */ - } -#endif -} - -int checkboard(void) -{ - int digiboardversion; - int failsavelevel; - int fpgaversion; - - get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); - -#ifdef CONFIG_A4M2K - puts("Board: A4M2K\n"); - printf(" digiboard IO version %u\n", digiboardversion); -#else - puts("Board: A3M071\n"); - printf("Rev: failsave level %u\n", failsavelevel); - printf(" digiboard IO version %u\n", digiboardversion); - if (failsavelevel > 0) /* only if fpga-version red */ - printf(" fpga IO version %u\n", fpgaversion); -#endif - - return 0; -} - -/* miscellaneous platform dependent initialisations */ -int misc_init_r(void) -{ - /* adjust flash start and offset to detected values */ - gd->bd->bi_flashstart = flash_info[0].start[0]; - gd->bd->bi_flashoffset = 0; - - /* adjust mapping */ - out_be32((void *)MPC5XXX_BOOTCS_START, - START_REG(gd->bd->bi_flashstart)); - out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart)); - out_be32((void *)MPC5XXX_BOOTCS_STOP, - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize)); - out_be32((void *)MPC5XXX_CS0_STOP, - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize)); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#ifdef CONFIG_SPL_OS_BOOT -/* - * A3M071 specific implementation of spl_start_uboot() - * - * RETURN - * 0 if booting into OS is selected (default) - * 1 if booting into U-Boot is selected - */ -int spl_start_uboot(void) -{ - char s[8]; - - env_init(); - getenv_f("boot_os", s, sizeof(s)); - if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' || - *s == 't' || *s == 'T')) - return 0; - - return 1; -} -#endif - -#if defined(CONFIG_HW_WATCHDOG) -static int watchdog_toggle; - -void hw_watchdog_reset(void) -{ - int val; - - /* - * Check if watchdog is enabled via user command - */ - if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) { - /* Set direction to output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN); - - /* - * Toggle watchdog output - */ - val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & - CONFIG_WDOG_GPIO_PIN); - if (val) { - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, - CONFIG_WDOG_GPIO_PIN); - } else { - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, - CONFIG_WDOG_GPIO_PIN); - } - } -} - -int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 2) - goto usage; - - if (strncmp(argv[1], "on", 2) == 0) - watchdog_toggle = 1; - else if (strncmp(argv[1], "off", 3) == 0) - watchdog_toggle = 0; - else - goto usage; - - return 0; -usage: - printf("Usage: wdogtoggle %s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle, - "toggle GPIO pin to service watchdog", - "[on/off] - Switch watchdog toggling via GPIO pin on/off" -); -#endif diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h deleted file mode 100644 index 981359f..0000000 --- a/board/a3m071/is46r16320d.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */ - -/* SDRAM Config Standard timing */ -#define SDRAM_MODE 0x008d0000 -#define SDRAM_EMODE 0x40010000 -#define SDRAM_CONTROL 0x70430f00 -#define SDRAM_CONFIG1 0x33622930 -#define SDRAM_CONFIG2 0x46670000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h deleted file mode 100644 index 8f42830..0000000 --- a/board/a3m071/mt46v16m16-75.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig deleted file mode 100644 index ba5447f..0000000 --- a/board/a4m072/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_A4M072 - -config SYS_BOARD - default "a4m072" - -config SYS_CONFIG_NAME - default "a4m072" - -endif diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS deleted file mode 100644 index 83dc59e..0000000 --- a/board/a4m072/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -A4M072 BOARD -M: Sergei Poselenov -S: Maintained -F: board/a4m072/ -F: include/configs/a4m072.h -F: configs/a4m072_defconfig diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile deleted file mode 100644 index 2a40e57..0000000 --- a/board/a4m072/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := a4m072.o diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c deleted file mode 100644 index 6f0d448..0000000 --- a/board/a4m072/a4m072.c +++ /dev/null @@ -1,479 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2010 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mt46v32m16.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); - __asm__ volatile ("sync"); - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - __asm__ volatile ("sync"); - - /* auto refresh */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); - __asm__ volatile ("sync"); - - /* set mode register */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - __asm__ volatile ("sync"); - - /* normal operation */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control); - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, - 0x13 + __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); - __asm__ volatile ("sync"); - } - - gd->ram_size = dramsize; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: A4M072\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -int board_eth_init(bd_t *bis) -{ - int rv, num_if = 0; - - /* Initialize TSECs first */ - if ((rv = cpu_eth_init(bis)) >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize FEC.\n"); - - if ((rv = pci_eth_init(bis)) >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize PCI Ethernet.\n"); - - return num_if; -} -/* - * Miscellaneous late-boot configurations - * - * Initialize EEPROM write-protect GPIO pin. - */ -int misc_init_r(void) -{ -#if defined(CONFIG_SYS_EEPROM_WREN) - /* Enable GPIO pin */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP); - /* Set direction, output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP); - /* De-assert write enable */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); -#endif - return 0; -} -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access */ - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & - CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} -#endif - -#ifdef CONFIG_CMD_DISPLAY -#define DISPLAY_BUF_SIZE 2 -static u8 display_buf[DISPLAY_BUF_SIZE]; -static u8 display_putc_pos; -static u8 display_out_pos; - -void display_set(int cmd) { - - if (cmd & DISPLAY_CLEAR) { - display_buf[0] = display_buf[1] = 0; - } - - if (cmd & DISPLAY_HOME) { - display_putc_pos = 0; - } -} - -#define SEG_A (1<<0) -#define SEG_B (1<<1) -#define SEG_C (1<<2) -#define SEG_D (1<<3) -#define SEG_E (1<<4) -#define SEG_F (1<<5) -#define SEG_G (1<<6) -#define SEG_P (1<<7) -#define SEG__ 0 - -/* - * +- A -+ - * | | - * F B - * | | - * +- G -+ - * | | - * E C - * | | - * +- D -+ P - * - * 0..9 index 0..9 - * A..Z index 10..35 - * - index 36 - * _ index 37 - * . index 38 - */ - -#define SYMBOL_DASH (36) -#define SYMBOL_UNDERLINE (37) -#define SYMBOL_DOT (38) - -static u8 display_char2seg7_tbl[]= -{ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */ - SEG_B | SEG_C, /* 1 */ - SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */ - SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */ - SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */ - SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */ - SEG_A | SEG_B | SEG_C, /* 7 */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */ - SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */ - SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */ - SEG_A | SEG_D | SEG_E | SEG_F, /* C */ - SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */ - SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */ - SEG_A | SEG_E | SEG_F | SEG_G, /* F */ - 0, /* g - not displayed */ - SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */ - SEG_B | SEG_C, /* I */ - 0, /* J - not displayed */ - 0, /* K - not displayed */ - SEG_D | SEG_E | SEG_F, /* L */ - 0, /* m - not displayed */ - 0, /* n - not displayed */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */ - SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */ - 0, /* q - not displayed */ - 0, /* r - not displayed */ - SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */ - SEG_D | SEG_E | SEG_F | SEG_G, /* t */ - SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */ - 0, /* V - not displayed */ - 0, /* w - not displayed */ - 0, /* X - not displayed */ - SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */ - 0, /* Z - not displayed */ - SEG_G, /* - */ - SEG_D, /* _ */ - SEG_P /* . */ -}; - -/* Convert char to the LED segments representation */ -static u8 display_char2seg7(char c) -{ - u8 val = 0; - - if (c >= '0' && c <= '9') - c -= '0'; - else if (c >= 'a' && c <= 'z') - c -= 'a' - 10; - else if (c >= 'A' && c <= 'Z') - c -= 'A' - 10; - else if (c == '-') - c = SYMBOL_DASH; - else if (c == '_') - c = SYMBOL_UNDERLINE; - else if (c == '.') - c = SYMBOL_DOT; - else - c = ' '; /* display unsupported symbols as space */ - - if (c != ' ') - val = display_char2seg7_tbl[(int)c]; - - return val; -} - -int display_putc(char c) -{ - if (display_putc_pos >= DISPLAY_BUF_SIZE) - return -1; - - display_buf[display_putc_pos++] = display_char2seg7(c); - /* one-symbol message should be steady */ - if (display_putc_pos == 1) - display_buf[display_putc_pos] = display_char2seg7(c); - - return c; -} - -/* - * Flush current symbol to the LED display hardware - */ -static inline void display_flush(void) -{ - u32 val = display_buf[display_out_pos]; - - val |= (val << 8) | (val << 16) | (val << 24); - out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val); -} - -/* - * Output contents of the software display buffer to the LED display every 0.5s - */ -void board_show_activity(ulong timestamp) -{ - static ulong last; - static u8 once; - - if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) { - display_flush(); - display_out_pos ^= 1; - last = timestamp; - once = 1; - } -} - -/* - * Empty fake function - */ -void show_activity(int arg) -{ -} -#endif -#if defined (CONFIG_SHOW_BOOT_PROGRESS) -static int a4m072_status2code(int status, char *buf) -{ - char c = 0; - - if (((status > 0) && (status <= 8)) || - ((status >= 100) && (status <= 108)) || - ((status < 0) && (status >= -9)) || - (status == -100) || (status == -101) || - ((status <= -103) && (status >= -113))) { - c = '5'; - } else if (((status >= 9) && (status <= 14)) || - ((status >= 120) && (status <= 123)) || - ((status >= 125) && (status <= 129)) || - ((status >= -13) && (status <= -10)) || - (status == -120) || (status == -122) || - ((status <= -124) && (status >= -127)) || - (status == -129)) { - c = '8'; - } else if (status == 15) { - c = '9'; - } else if ((status <= -30) && (status >= -32)) { - c = 'A'; - } else if (((status <= -35) && (status >= -40)) || - ((status <= -42) && (status >= -51)) || - ((status <= -53) && (status >= -58)) || - (status == -64) || - ((status <= -80) && (status >= -83)) || - (status == -130) || (status == -140) || - (status == -150)) { - c = 'B'; - } - - if (c == 0) - return -EINVAL; - - buf[0] = (status < 0) ? '-' : c; - buf[1] = c; - - return 0; -} - -void show_boot_progress(int status) -{ - char buf[2]; - - if (a4m072_status2code(status, buf) < 0) - return; - - display_putc(buf[0]); - display_putc(buf[1]); - display_set(DISPLAY_HOME); - display_out_pos = 0; /* reset output position */ - - /* we want to flush status 15 now */ - if (status == BOOTSTAGE_ID_RUN_OS) - display_flush(); -} -#endif diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h deleted file mode 100644 index c0a08a8..0000000 --- a/board/a4m072/mt46v32m16.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40010000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c index b3fa789..13a9c6a 100644 --- a/board/amazon/kc1/kc1.c +++ b/board/amazon/kc1/kc1.c @@ -17,6 +17,7 @@ #include #include #include "kc1.h" +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 6a50b39..9f64207 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -1880,7 +1880,7 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) { mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN; mtsdr(SDR0_MFR, sdr0_mfr); } diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 774671d..f98231a 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -161,7 +161,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ + while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ; /* poll L2_SR for completion */ mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index fabb8b1..c3bafd4 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -24,6 +24,7 @@ #include #include "arm-ebi.h" #include "integrator-sc.h" +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 458f1d8..89ab8f7 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index 98d76a6..36f147b 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 6398bcb..b4acb74 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -21,6 +21,7 @@ #include #include #endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 3de9783..b37e9d3 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index d3bc5c6..8e37759 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 0b603ed..7966269 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 81c2aad..1e4a4a2 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -19,6 +19,7 @@ #include #include #endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c index 08e79bd..2215c29 100644 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ b/board/bluegiga/apx4devkit/apx4devkit.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 08b1401..e82c691 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index 2d1a89e..7e9da4e 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig deleted file mode 100644 index b5cf205..0000000 --- a/board/canmb/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CANMB - -config SYS_BOARD - default "canmb" - -config SYS_CONFIG_NAME - default "canmb" - -endif diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS deleted file mode 100644 index 71750ea..0000000 --- a/board/canmb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CANMB BOARD -#M: - -S: Maintained -F: board/canmb/ -F: include/configs/canmb.h -F: configs/canmb_defconfig diff --git a/board/canmb/Makefile b/board/canmb/Makefile deleted file mode 100644 index 4286a91..0000000 --- a/board/canmb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2005-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := canmb.o - diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c deleted file mode 100644 index 54de0e2..0000000 --- a/board/canmb/canmb.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m32s2-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: CANMB\n"); - return 0; -} - -int board_early_init_r (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); - return 0; -} diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h deleted file mode 100644 index 0133eaa..0000000 --- a/board/canmb/mt48lc16m32s2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c index 720b490..02e2896 100644 --- a/board/cirrus/edb93xx/edb93xx.c +++ b/board/cirrus/edb93xx/edb93xx.c @@ -18,6 +18,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig deleted file mode 100644 index ccea5c9..0000000 --- a/board/cm5200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CM5200 - -config SYS_BOARD - default "cm5200" - -config SYS_CONFIG_NAME - default "cm5200" - -endif diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS deleted file mode 100644 index 1e1df3f..0000000 --- a/board/cm5200/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM5200 BOARD -#M: - -S: Maintained -F: board/cm5200/ -F: include/configs/cm5200.h -F: configs/cm5200_defconfig diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile deleted file mode 100644 index 76f8b9f..0000000 --- a/board/cm5200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cm5200.o cmd_cm5200.o fwupdate.o diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c deleted file mode 100644 index 0c647bb..0000000 --- a/board/cm5200/cm5200.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Adapted to U-Boot 1.2 by: - * Bartlomiej Sieka : - * - HW ID readout from EEPROM - * - module detection - * Grzegorz Bernacki : - * - run-time SDRAM controller configuration - * - LIBFDT support - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_OF_LIBFDT -#include -#include -#endif /* CONFIG_OF_LIBFDT */ - - -#include "cm5200.h" -#include "fwupdate.h" - -DECLARE_GLOBAL_DATA_PTR; - -static hw_id_t hw_id; - - -#ifndef CONFIG_SYS_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr, mem_conf_t *mem_conf) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit; -} -#endif /* CONFIG_SYS_RAMBOOT */ - - -/* - * Retrieve memory configuration for a given module. board_type is the index - * in hw_id_list[] corresponding to the module we are executing on; we return - * SDRAM controller settings approprate for this module. - */ -static mem_conf_t* get_mem_config(int board_type) -{ - switch(board_type){ - case CM1_QA: - return memory_config[0]; - case CM11_QA: - case CMU1_QA: - return memory_config[1]; - default: - printf("ERROR: Unknown module, using a default SDRAM " - "configuration - things may not work!!!.\n"); - return memory_config[0]; - } -} - - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -int dram_init(void) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - mem_conf_t *mem_conf; - - mem_conf = get_mem_config(gd->board_type); - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2; - - sdram_start(0, mem_conf); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1, mem_conf); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0, mem_conf); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of - * the MPC5200B User's Manual. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - - gd->ram_size = dramsize; - - return 0; -} - - -/* - * Read module hardware identification data from the I2C EEPROM. - */ -static void read_hw_id(hw_id_t hw_id) -{ - printf("ERROR: can't read HW ID from EEPROM\n"); -} - - -/* - * Identify module we are running on, set gd->board_type to the index in - * hw_id_list[] corresponding to the module identifed, or to - * CM5200_UNKNOWN_MODULE if we can't identify the module. - */ -static void identify_module(hw_id_t hw_id) -{ - int i, j, element; - char match; - gd->board_type = CM5200_UNKNOWN_MODULE; - for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) { - match = 1; - for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) { - element = hw_id_identify[j]; - if (strncmp(hw_id_list[i][element], - &hw_id[element][0], - hw_id_format[element].length) != 0) { - match = 0; - break; - } - } - if (match) { - gd->board_type = i; - break; - } - } -} - - -/* - * Compose string with module name. - * buf is assumed to have enough space, and be null-terminated. - */ -static void compose_module_name(hw_id_t hw_id, char *buf) -{ - char tmp[MODULE_NAME_MAXLEN]; - strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); - strncat(buf, ".", 1); - strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); - strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); - strncat(buf, " (", 2); - strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0], - hw_id_format[IDENTIFICATION_NUMBER].length); - sprintf(tmp, " / %u.%u)", - hw_id[MAJOR_SW_VERSION][0], - hw_id[MINOR_SW_VERSION][0]); - strcat(buf, tmp); -} - -#if defined(CONFIG_SYS_I2C_SOFT) -/* - * Compose string with hostname. - * buf is assumed to have enough space, and be null-terminated. - */ -static void compose_hostname(hw_id_t hw_id, char *buf) -{ - char *p; - strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); - strncat(buf, "_", 1); - strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); - strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); - for (p = buf; *p; ++p) - *p = tolower(*p); - -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -/* - * Update 'model' and 'memory' properties in the blob according to the module - * that we are running on. - */ -static void ft_blob_update(void *blob, bd_t *bd) -{ - int len, ret, nodeoffset = 0; - char module_name[MODULE_NAME_MAXLEN] = {0}; - - compose_module_name(hw_id, module_name); - len = strlen(module_name) + 1; - - ret = fdt_setprop(blob, nodeoffset, "model", module_name, len); - if (ret < 0) - printf("ft_blob_update(): cannot set /model property err:%s\n", - fdt_strerror(ret)); -} -#endif /* CONFIG_OF_BOARD_SETUP */ - - -/* - * Read HW ID from I2C EEPROM and detect the modue we are running on. Note - * that we need to use local variable for readout, because global data is not - * writable yet (and we'll have to redo the readout later on). - */ -int checkboard(void) -{ - hw_id_t hw_id_tmp; - char module_name_tmp[MODULE_NAME_MAXLEN] = ""; - - read_hw_id(hw_id_tmp); - identify_module(hw_id_tmp); /* this sets gd->board_type */ - compose_module_name(hw_id_tmp, module_name_tmp); - - if (gd->board_type != CM5200_UNKNOWN_MODULE) - printf("Board: %s\n", module_name_tmp); - else - printf("Board: unrecognized cm5200 module (%s)\n", - module_name_tmp); - - return 0; -} - - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in - * flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - - /* Now that we can write to global data, read HW ID again. */ - read_hw_id(hw_id); - return 0; -} - - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#if defined(CONFIG_SYS_I2C_SOFT) - uchar buf[6]; - char str[18]; - char hostname[MODULE_NAME_MAXLEN]; - - /* Read ethaddr from EEPROM */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - /* Check if MAC addr is owned by Schindler */ - if (strstr(str, "00:06:C3") != str) - printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" - " in EEPROM.\n", str); - else { - printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", - str); - setenv("ethaddr", str); - } - } else { - printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" - " device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM, - CONFIG_MAC_OFFSET); - } - hostname[0] = 0x00; - /* set the hostname appropriate to the module we're running on */ - compose_hostname(hw_id, hostname); - setenv("hostname", hostname); - -#endif /* defined(CONFIG_SYS_I2C_SOFT) */ - if (!getenv("ethaddr")) - printf(LOG_PREFIX "MAC address not set, networking is not " - "operational\n"); - - return 0; -} -#endif /* CONFIG_MISC_INIT_R */ - - -#ifdef CONFIG_LAST_STAGE_INIT -int last_stage_init(void) -{ -#ifdef CONFIG_USB_STORAGE - cm5200_fwupdate(); -#endif /* CONFIG_USB_STORAGE */ - return 0; -} -#endif /* CONFIG_LAST_STAGE_INIT */ - - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_blob_update(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h deleted file mode 100644 index c2573f3..0000000 --- a/board/cm5200/cm5200.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2007 DENX Software Engineering - * - * Author: Bartlomiej Sieka - * Author: Grzegorz Bernacki - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CM5200_H -#define _CM5200_H - - -/* - * Definitions and declarations for the modules of the cm5200 platform. Mostly - * related to reading the hardware identification data (HW ID) from the I2C - * EEPROM, detection of the particular module we are executing on, and - * appropriate SDRAM controller initialization. - */ - - -#define CM5200_UNKNOWN_MODULE 0xffffffff - -enum { - DEVICE_NAME, /* 0 */ - GENERATION, /* 1 */ - PCB_NAME, /* 2 */ - FORM, /* 3 */ - VERSION, /* 4 */ - IDENTIFICATION_NUMBER, /* 5 */ - MAJOR_SW_VERSION, /* 6 */ - MINOR_SW_VERSION, /* 7 */ - /* add new alements above this line */ - HW_ID_ELEM_COUNT /* count */ -}; - -/* - * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition" - */ - -#define DEVICE_NAME_OFFSET 0x02 -#define GENERATION_OFFSET 0x0b -#define PCB_NAME_OFFSET 0x0c -#define FORM_OFFSET 0x15 -#define VERSION_OFFSET 0x16 -#define IDENTIFICATION_NUMBER_OFFSET 0x19 -#define MAJOR_SW_VERSION_OFFSET 0x0480 -#define MINOR_SW_VERSION_OFFSET 0x0481 - - -#define DEVICE_NAME_LEN 0x09 -#define GENERATION_LEN 0x01 -#define PCB_NAME_LEN 0x09 -#define FORM_LEN 0x01 -#define VERSION_LEN 0x03 -#define IDENTIFICATION_NUMBER_LEN 0x09 -#define MAJOR_SW_VERSION_LEN 0x01 -#define MINOR_SW_VERSION_LEN 0x01 - -#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */ - -/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */ -#define MODULE_NAME_MAXLEN 64 - - -/* storage for HW ID read from EEPROM */ -typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN]; - - -/* HW ID layout in EEPROM */ -static struct { - unsigned int offset; - unsigned int length; -} hw_id_format[HW_ID_ELEM_COUNT] = { - {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN}, - {GENERATION_OFFSET, GENERATION_LEN}, - {PCB_NAME_OFFSET, PCB_NAME_LEN}, - {FORM_OFFSET, FORM_LEN}, - {VERSION_OFFSET, VERSION_LEN}, - {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN}, - {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN}, - {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN}, -}; - - -/* HW ID data found in EEPROM on supported modules */ -static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = { - "CM", /* DEVICE_NAME */ - "1", /* GENERATION */ - "CM1", /* PCB_NAME */ - "Q", /* FORM */ - "A", /* VERSION */ - "591881", /* IDENTIFICATION_NUMBER */ - "", /* MAJOR_SW_VERSION */ - "", /* MINOR_SW_VERSION */ -}; - -static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = { - "CM", /* DEVICE_NAME */ - "1", /* GENERATION */ - "CM11", /* PCB_NAME */ - "Q", /* FORM */ - "A", /* VERSION */ - "594200", /* IDENTIFICATION_NUMBER */ - "", /* MAJOR_SW_VERSION */ - "", /* MINOR_SW_VERSION */ -}; - -static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = { - "CMU", /* DEVICE_NAME */ - "1", /* GENERATION */ - "CMU1", /* PCB_NAME */ - "Q", /* FORM */ - "A", /* VERSION */ - "594128", /* IDENTIFICATION_NUMBER */ - "", /* MAJOR_SW_VERSION */ - "", /* MINOR_SW_VERSION */ -}; - - -/* list of known modules */ -static char **hw_id_list[] = { - cm1_qa_hw_id, - cm11_qa_hw_id, - cmu1_qa_hw_id, -}; - -/* indices to the above list - keep in sync */ -enum { - CM1_QA, - CM11_QA, - CMU1_QA, -}; - - -/* identify modules based on these hw id elements */ -static int hw_id_identify[] = { - PCB_NAME, - FORM, - VERSION, -}; - - -/* Registers' settings for SDRAM controller intialization */ -typedef struct { - ulong mode; - ulong control; - ulong config1; - ulong config2; -} mem_conf_t; - -static mem_conf_t k4s561632E = { - 0x00CD0000, /* CASL 3, burst length 8 */ - 0x514F0000, - 0xE2333900, - 0x8EE70000 -}; - -static mem_conf_t mt48lc32m16a2 = { - 0x00CD0000, /* CASL 3, burst length 8 */ - 0x514F0000, - 0xD2322800, - 0x8AD70000 -}; - -static mem_conf_t* memory_config[] = { - &k4s561632E, - &mt48lc32m16a2 -}; - -#endif /* _CM5200_H */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c deleted file mode 100644 index 60097dc..0000000 --- a/board/cm5200/cmd_cm5200.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * (C) Copyright 2007 Markus Kappeler - * - * Adapted for U-Boot 1.2 by Piotr Kruszynski - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifdef CONFIG_CMD_BSP - -static int do_usb_test(char * const argv[]) -{ - int i; - static int usb_stor_curr_dev = -1; /* current device */ - - printf("Starting USB Test\n" - "Please insert USB Memmory Stick\n\n" - "Please press any key to start\n\n"); - getc(); - - usb_stop(); - printf("(Re)start USB...\n"); - i = usb_init(); -#ifdef CONFIG_USB_STORAGE - /* try to recognize storage devices immediately */ - if (i >= 0) - usb_stor_curr_dev = usb_stor_scan(1); -#endif /* CONFIG_USB_STORAGE */ - if (usb_stor_curr_dev >= 0) - printf("Found USB Storage Dev continue with Test...\n"); - else { - printf("No USB Storage Device detected.. Stop Test\n"); - return 1; - } - - usb_stor_info(); - - printf("stopping USB..\n"); - usb_stop(); - - return 0; -} - -static int do_led_test(char * const argv[]) -{ - int i = 0; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Starting LED Test\n" - "Please set Switch S500 all off\n\n" - "Please press any key to start\n\n"); - getc(); - - /* configure timer 2-3 for simple GPIO output High */ - gpt->gpt2.emsr |= 0x00000034; - gpt->gpt3.emsr |= 0x00000034; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; - printf("Please press any key to stop\n\n"); - while (!tstc()) { - if (i == 1) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr &= ~0x00000010; - } else if (i == 2) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr |= 0x00000010; - } else if (i >= 3) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt3.emsr &= ~0x00000010; - gpt->gpt2.emsr |= 0x00000010; - i = 0; - } - i++; - udelay(200000); - } - getc(); - - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr |= 0x00000010; - gpt->gpt3.emsr |= 0x00000010; - - return 0; -} - -static int do_rs232_test(char * const argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - /* Configure PSC 2-3-6 as GPIO */ - gpio->port_config &= 0xFF0FF80F; - - switch (simple_strtoul(argv[2], NULL, 10)) { - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - printf("Uart 1 test: RX TX tested by using U-Boot\n" - "Please connect RTS with CTS on Uart1 plug\n\n" - "Press any key to start\n\n"); - getc(); - - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - break; - case 2: - /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ - printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x000000F0); - gpio->simple_gpioe |= 0x000000F0; - gpio->simple_ddr &= ~(0x000000F0); - gpio->simple_ddr |= 0x00000050; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000020) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000080) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - break; - case 3: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - break; - case 4: - /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ - printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0xF0000000); - gpio->simple_gpioe |= 0x30000000; - - gpio->simple_ddr &= ~(0xf0000000); - gpio->simple_ddr |= 0x30000000; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x10000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %lu " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %lu " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x20000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %lu " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %lu " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - break; - default: - printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F); - - return error_status; -} - -static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = -1; - - switch (argc) { - case 2: - if (strncmp(argv[1], "led", 3) == 0) - rcode = do_led_test(argv); - else if (strncmp(argv[1], "usb", 3) == 0) - rcode = do_usb_test(argv); - break; - case 3: - if (strncmp(argv[1], "rs232", 3) == 0) - rcode = do_rs232_test(argv); - break; - } - - switch (rcode) { - case -1: - printf("Usage:\n" - "fkt { i2c | led | usb }\n" - "fkt rs232 number\n"); - rcode = 1; - break; - case 0: - printf("Test passed\n"); - break; - default: - printf("Test failed with code: %d\n", rcode); - } - - return rcode; -} - -U_BOOT_CMD( - fkt, 4, 1, cmd_fkt, - "Function test routines", - "i2c\n" - " - Test I2C communication\n" - "fkt led\n" - " - Test LEDs\n" - "fkt rs232 number\n" - " - Test RS232 (loopback plug(s) for RS232 required)\n" - "fkt usb\n" - " - Test USB communication" -); -#endif /* CONFIG_CMD_BSP */ diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c deleted file mode 100644 index 4740c83..0000000 --- a/board/cm5200/fwupdate.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * (C) Copyright 2007 DENX Software Engineering - * - * Author: Michel Marti - * Adapted for U-Boot 1.2 by Piotr Kruszynski : - * - code clean-up - * - bugfix for overwriting bootargs by user - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "fwupdate.h" - -static int load_rescue_image(ulong); - -void cm5200_fwupdate(void) -{ - cmd_tbl_t *bcmd; - char *rsargs; - char *tmp = NULL; - char ka[16]; - char * const argv[3] = { "bootm", ka, NULL }; - - /* Check if rescue system is disabled... */ - if (getenv("norescue")) { - printf(LOG_PREFIX "Rescue System disabled.\n"); - return; - } - - /* Check if we have a USB storage device and load image */ - if (load_rescue_image(LOAD_ADDR)) - return; - - bcmd = find_cmd("bootm"); - if (!bcmd) - return; - - sprintf(ka, "%lx", (ulong)LOAD_ADDR); - - /* prepare our bootargs */ - rsargs = getenv("rs-args"); - if (!rsargs) - rsargs = RS_BOOTARGS; - else { - tmp = malloc(strlen(rsargs+1)); - if (!tmp) { - printf(LOG_PREFIX "Memory allocation failed\n"); - return; - } - strcpy(tmp, rsargs); - rsargs = tmp; - } - - setenv("bootargs", rsargs); - - if (rsargs == tmp) - free(rsargs); - - printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); - do_bootm(bcmd, 0, 2, argv); -} - -static int load_rescue_image(ulong addr) -{ - disk_partition_t info; - int devno; - int partno; - int i; - char fwdir[64]; - char nxri[128]; - char *tmp; - char dev[7]; - char addr_str[16]; - char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; - struct blk_desc *stor_dev = NULL; - cmd_tbl_t *bcmd; - - /* Get name of firmware directory */ - tmp = getenv("fw-dir"); - - /* Copy it into fwdir */ - strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); - fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ - - printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" - " storage...\n", fwdir); - usb_stop(); - if (usb_init() != 0) - return 1; - - /* Check for storage device */ - if (usb_stor_scan(1) != 0) { - usb_stop(); - return 1; - } - - /* Detect storage device */ - for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { - stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno); - if (stor_dev->type != DEV_TYPE_UNKNOWN) - break; - } - if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { - printf(LOG_PREFIX "No valid storage device found...\n"); - usb_stop(); - return 1; - } - - /* Detect partition */ - for (partno = -1, i = 0; i < 6; i++) { - if (part_get_info(stor_dev, i, &info) == 0) { - if (fat_register_device(stor_dev, i) == 0) { - /* Check if rescue image is present */ - FW_DEBUG("Looking for firmware directory '%s'" - " on partition %d\n", fwdir, i); - if (!fat_exists(fwdir)) { - FW_DEBUG("No NX rescue image on " - "partition %d.\n", i); - partno = -2; - } else { - partno = i; - FW_DEBUG("Partition %d contains " - "firmware directory\n", partno); - break; - } - } - } - } - - if (partno < 0) { - switch (partno) { - case -1: - printf(LOG_PREFIX "Error: No valid (FAT) partition " - "detected\n"); - break; - case -2: - printf(LOG_PREFIX "Error: No NX rescue image on FAT " - "partition\n"); - break; - default: - printf(LOG_PREFIX "Error: Failed with code %d\n", - partno); - } - usb_stop(); - return 1; - } - - /* Load the rescue image */ - bcmd = find_cmd("fatload"); - if (!bcmd) { - printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); - usb_stop(); - return 1; - } - - tmp = getenv("nx-rescue-image"); - sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); - sprintf(dev, "%d:%d", devno, partno); - sprintf(addr_str, "%lx", addr); - - FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", - dev, addr_str, nxri); - - if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { - usb_stop(); - return 1; - } - - /* Stop USB */ - usb_stop(); - return 0; -} diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h deleted file mode 100644 index 6ddf0ba..0000000 --- a/board/cm5200/fwupdate.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * - * Author: Michel Marti - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FW_UPDATE_H -#define __FW_UPDATE_H - -/* Default prefix for output messages */ -#define LOG_PREFIX "CM5200:" - -/* Extra debug macro */ -#ifdef CONFIG_FWUPDATE_DEBUG -#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) -#else -#define FW_DEBUG(fmt...) -#endif - -/* Name of the directory holding firmware images */ -#define FW_DIR "nx-fw" -#define RESCUE_IMAGE "nxrs.img" -#define LOAD_ADDR 0x400000 -#define RS_BOOTARGS "ramdisk_size=8192K" - -/* Main function for fwupdate */ -void cm5200_fwupdate(void); - -#endif /* __FW_UPDATE_H */ diff --git a/board/compulab/cl-som-am57x/spl.c b/board/compulab/cl-som-am57x/spl.c index 855678f..de2dadc 100644 --- a/board/compulab/cl-som-am57x/spl.c +++ b/board/compulab/cl-som-am57x/spl.c @@ -19,7 +19,12 @@ static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = { void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { + /* Disable SDRAM controller EMIF2 for single core SOC */ *dmm_lisa_regs = &cl_som_am57x_lisa_regs; + if (omap_revision() == DRA722_ES1_0) { + ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 = + 0x80640100; + } } static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = { diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c index b25d9a2..bf2ac7b 100644 --- a/board/compulab/common/common.c +++ b/board/compulab/common/common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "common.h" #include "eeprom.h" diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index b5f1aa6..bb4c9e9 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "eeprom.h" diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig deleted file mode 100644 index 54a86b9..0000000 --- a/board/davedenx/aria/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ARIA - -config SYS_BOARD - default "aria" - -config SYS_VENDOR - default "davedenx" - -config SYS_CONFIG_NAME - default "aria" - -endif diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS deleted file mode 100644 index a6152c9..0000000 --- a/board/davedenx/aria/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ARIA BOARD -M: Wolfgang Denk -S: Maintained -F: board/davedenx/aria/ -F: include/configs/aria.h -F: configs/aria_defconfig diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile deleted file mode 100644 index dd38b7f..0000000 --- a/board/davedenx/aria/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2009 Wolfgang Denk -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := aria.o diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c deleted file mode 100644 index e389819..0000000 --- a/board/davedenx/aria/aria.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk - * (C) Copyright 2009 Dave Srl www.dave.eu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MISC_INIT_R -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = fixed_sdram(NULL, NULL, 0); - - return 0; -} - -int misc_init_r(void) -{ - u32 tmp; - - tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE); - printf("FPGA: %u-%u.%u.%u\n", - (tmp & 0xFF000000) >> 24, - (tmp & 0x00FF0000) >> 16, - (tmp & 0x0000FF00) >> 8, - tmp & 0x000000FF - ); - - return 0; -} - -static iopin_t ioregs_init[] = { - /* - * FEC - */ - - /* FEC on PSCx_x*/ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - { - offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - - /* - * DIU - */ - /* FUNC2=DIU CLK */ - { - offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU_HSYNC */ - { - offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ - { - offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* - * On board SRAM - */ - /* FUNC2=/LPC CS6 */ - { - offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, -}; - -int checkboard (void) -{ - puts("Board: ARIA\n"); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 9e17eb8..11ea52f 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -23,6 +23,7 @@ #include #include #include +#include #ifdef CONFIG_MMC_DAVINCI #include diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index d941285..52bb736 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #ifdef CONFIG_MMC_DAVINCI #include diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 6edfa17..2a187f1 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig deleted file mode 100644 index 3f2a411..0000000 --- a/board/esd/mecp5123/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MECP5123 - -config SYS_BOARD - default "mecp5123" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "mecp5123" - -endif diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS deleted file mode 100644 index ae5fcea..0000000 --- a/board/esd/mecp5123/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MECP5123 BOARD -M: Reinhard Arlt -S: Maintained -F: board/esd/mecp5123/ -F: include/configs/mecp5123.h -F: configs/mecp5123_defconfig diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile deleted file mode 100644 index f5ebb01..0000000 --- a/board/esd/mecp5123/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2009 Wolfgang Denk -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mecp5123.o diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c deleted file mode 100644 index 78a6b66..0000000 --- a/board/esd/mecp5123/mecp5123.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk - * (C) Copyright 2009 Dave Srl www.dave.eu - * (C) Copyright 2009 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int eeprom_write_enable(unsigned dev_addr, int state) -{ - return -ENOSYS; -} - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - int i; - - /* - * Initialize Local Window for boot access - */ - out_be32(&im->sysconf.lpbaw, - CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000)); - sync_law(&im->sysconf.lpbaw); - - /* - * Configure MSCAN clocks - */ - for (i=0; i<4; ++i) { - out_be32(&im->clk.msccr[i], 0x00300000); - out_be32(&im->clk.msccr[i], 0x00310000); - } - - /* - * Configure GPIO's - */ - clrbits_be32(&im->gpio.gpodr, 0x000000e0); - clrbits_be32(&im->gpio.gpdir, 0x00ef0000); - setbits_be32(&im->gpio.gpdir, 0x001000e0); - setbits_be32(&im->gpio.gpdat, 0x00100000); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0)); - - return 0; -} - -int misc_init_r(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 val; - - /* - * Optimize access to profibus chip (VPC3) on the local bus - */ - - /* - * Select 1:1 for LPC_DIV - */ - val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK; - out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT)); - - /* - * Configure LPC Chips Select Deadcycle Control Register - * CS0 - device can drive data 2 clock cycle(s) after CS deassertion - * CS1 - device can drive data 1 clock cycle(s) after CS deassertion - */ - clrbits_be32(&im->lpc.cs_dccr, 0x000000ff); - setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0)); - - /* - * Configure LPC Chips Select Holdcycle Control Register - * CS0 - data is valid 2 clock cycle(s) after CS deassertion - * CS1 - data is valid 1 clock cycle(s) after CS deassertion - */ - clrbits_be32(&im->lpc.cs_hccr, 0x000000ff); - setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0)); - - return 0; -} - -static iopin_t ioregs_init[] = { - /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=SELECT LPC_CS1 */ - { - offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC5_2 */ - { - offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC5_3 */ - { - offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC7_3 */ - { - offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC9_0 */ - { - offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC10_0 */ - { - offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC10_3 */ - { - offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC11_0 */ - { - offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC0=SELECT IRQ0 */ - { - offsetof(struct ioctrl512x, io_control_irq0), 4, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -static iopin_t rev2_silicon_pci_ioregs_init[] = { - /* FUNC0=PCI Sets next 54 to PCI pads */ - { - offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) - } -}; - -int checkboard(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr; - - puts("Board: MECP_5123\n"); - - /* - * Initialize function mux & slew rate IO inter alia on IO - * Pins - */ - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - spridr = in_be32(&im->sysconf.spridr); - if (SVR_MJREV(spridr) >= 2) - iopin_initialize(rev2_silicon_pci_ioregs_init, 1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 19b673e..e4bda79 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS index 97304c5..34ac099 100644 --- a/board/freescale/b4860qds/MAINTAINERS +++ b/board/freescale/b4860qds/MAINTAINERS @@ -1,5 +1,5 @@ B4860QDS BOARD -#M: - +M: Ashish Kumar S: Maintained F: board/freescale/b4860qds/ F: include/configs/B4860QDS.h diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index d16a69f..2ee8749 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index b22d378..f219a77 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -10,6 +10,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include #endif +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 36d27ec..354b864 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -11,6 +11,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include #endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 5fcfa0f..e1858d6 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -10,6 +10,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include #endif +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index ae5046c..fb4f6ab 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -11,6 +11,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include #endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index 9d176d3..025e5aa 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 22a2676..20b8c1f 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 7002dfb..01f7d82 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig deleted file mode 100644 index f125f9e..0000000 --- a/board/freescale/mpc5121ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC5121ADS - -config SYS_BOARD - default "mpc5121ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mpc5121ads" - -endif diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS deleted file mode 100644 index d4aab8f..0000000 --- a/board/freescale/mpc5121ads/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC5121ADS BOARD -#M: - -S: Maintained -F: board/freescale/mpc5121ads/ -F: include/configs/mpc5121ads.h -F: configs/mpc5121ads_defconfig -F: configs/mpc5121ads_rev2_defconfig diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile deleted file mode 100644 index 67cf555..0000000 --- a/board/freescale/mpc5121ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mpc5121ads.o diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README deleted file mode 100644 index 741bc40..0000000 --- a/board/freescale/mpc5121ads/README +++ /dev/null @@ -1,7 +0,0 @@ -To configure for the current (Rev 3.x) ADS5121 - make mpc5121ads_config -This will automatically include PCI, the Real Time CLock, add backup flash -ability and set the correct frequency and memory configuration. - -To configure for the older Rev 2 ADS5121 type (this will not have PCI) - make mpc5121ads_rev2_config diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c deleted file mode 100644 index d729056..0000000 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MISC_INIT_R -#include -#endif -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip); - -/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */ -extern int mpc5121_nfc_chip; - -/* Control chips select signal on MPC5121ADS board */ -void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) -{ - unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09; - u8 v; - - v = in_8(csreg); - v |= 0x0F; - - if (chip >= 0) { - __mpc5121_nfc_select_chip(mtd, 0); - v &= ~(1 << mpc5121_nfc_chip); - } else { - __mpc5121_nfc_select_chip(mtd, -1); - } - - out_8(csreg, v); -} - -int board_early_init_f(void) -{ - /* - * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control - * - * Without this the flash identification routine fails, as it needs to issue - * write commands in order to establish the device ID. - */ - -#ifdef CONFIG_MPC5121ADS_REV2 - out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); -#else - if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { - out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); - } else { - /* running from Backup flash */ - out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); - } -#endif - return 0; -} - -int is_micron(void){ - - ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00); - uchar macaddr[6]; - u32 brddate, macchk, ismicron; - - /* - * MAC address has serial number with date of manufacture - * Boards made before Nov-08 #1180 use Micron memory; - * 001e59 is the STx vendor # - * Default is Elpida since it works for both but is slightly slower - */ - ismicron = 0; - if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) { - brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; - macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; - debug("brddate = %d\n\t", brddate); - - if (macchk == 0x001e59 && brddate <= 8111180) - ismicron = 1; - } else if (brd_rev < 0x400) { - ismicron = 1; - } - debug("Using %s Memory settings\n\t", - ismicron ? "Micron" : "Elpida"); - return(ismicron); -} - -int dram_init(void) -{ - u32 msize = 0; - /* - * Elpida MDDRC and initialization settings are an alternative - * to the Default Micron ones for all but the earliest Rev 4 boards - */ - ddr512x_config_t elpida_mddrc_config = { - .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, - .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, - .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, - .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - }; - - u32 elpida_init_sequence[] = { - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_EM3, - CONFIG_SYS_DDRCMD_EN_DLL, - CONFIG_SYS_ELPIDA_RES_DLL, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_ELPIDA_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_OCD_DEFAULT, - CONFIG_SYS_ELPIDA_OCD_EXIT, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP - }; - - if (is_micron()) { - msize = fixed_sdram(NULL, NULL, 0); - } else { - msize = fixed_sdram(&elpida_mddrc_config, - elpida_init_sequence, - sizeof(elpida_init_sequence)/sizeof(u32)); - } - - gd->ram_size = msize; - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -static iopin_t ioregs_init[] = { - /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* Set highest Slew on 9 PATA pins */ - { - offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=SPDIF_TXCLK */ - { - offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ - { - offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU CLK */ - { - offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU_HSYNC */ - { - offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ - { - offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -static iopin_t rev2_silicon_pci_ioregs_init[] = { - /* FUNC0=PCI Sets next 54 to PCI pads */ - { - offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) - } -}; - -int checkboard (void) -{ - ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); - uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 spridr = in_be32(&im->sysconf.spridr); - - printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n", - brd_rev, cpld_rev); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - if (SVR_MJREV (spridr) >= 2) - iopin_initialize(rev2_silicon_pci_ioregs_init, 1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS index 953072c..af221f9 100644 --- a/board/freescale/mpc8536ds/MAINTAINERS +++ b/board/freescale/mpc8536ds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8536DS BOARD -#M: - +M: York Sun S: Maintained F: board/freescale/mpc8536ds/ F: include/configs/MPC8536DS.h diff --git a/board/freescale/mpc8540ads/Kconfig b/board/freescale/mpc8540ads/Kconfig deleted file mode 100644 index 35a8545..0000000 --- a/board/freescale/mpc8540ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8540ADS - -config SYS_BOARD - default "mpc8540ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8540ADS" - -endif diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS deleted file mode 100644 index acc4821..0000000 --- a/board/freescale/mpc8540ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8540ADS BOARD -#M: Kumar Gala -S: Orphan (since 2014-06) -F: board/freescale/mpc8540ads/ -F: include/configs/MPC8540ADS.h -F: configs/MPC8540ADS_defconfig diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile deleted file mode 100644 index 6f82c7f..0000000 --- a/board/freescale/mpc8540ads/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8540ads.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c deleted file mode 100644 index 10fb2b3..0000000 --- a/board/freescale/mpc8540ads/ddr.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c deleted file mode 100644 index 41f2e02..0000000 --- a/board/freescale/mpc8540ads/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c deleted file mode 100644 index 1069e2c..0000000 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - #ifndef CONFIG_SYS_RAMBOOT - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - - -static struct pci_controller hose; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } - - return 0; -} -#endif diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c deleted file mode 100644 index d5ee791..0000000 --- a/board/freescale/mpc8540ads/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS index d421b12..1d969f1 100644 --- a/board/freescale/mpc8541cds/MAINTAINERS +++ b/board/freescale/mpc8541cds/MAINTAINERS @@ -1,6 +1,6 @@ MPC8541CDS BOARD -#M: Kumar Gala -S: Orphan (since 2014-06) +M: York Sun +S: Maintained F: board/freescale/mpc8541cds/ F: include/configs/MPC8541CDS.h F: configs/MPC8541CDS_defconfig diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS index 328be7f..3c6f80e 100644 --- a/board/freescale/mpc8544ds/MAINTAINERS +++ b/board/freescale/mpc8544ds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8544DS BOARD -#M: - +M: York Sun S: Maintained F: board/freescale/mpc8544ds/ F: include/configs/MPC8544DS.h diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS index 6f22922..a99f84b 100644 --- a/board/freescale/mpc8548cds/MAINTAINERS +++ b/board/freescale/mpc8548cds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8548CDS BOARD -#M: - +M: York Sun S: Maintained F: board/freescale/mpc8548cds/ F: include/configs/MPC8548CDS.h diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS index 1ef6690..3be1598 100644 --- a/board/freescale/mpc8555cds/MAINTAINERS +++ b/board/freescale/mpc8555cds/MAINTAINERS @@ -1,6 +1,6 @@ MPC8555CDS BOARD -#M: Kumar Gala -S: Orphan (since 2014-06) +M: York Sun +S: Maintained F: board/freescale/mpc8555cds/ F: include/configs/MPC8555CDS.h F: configs/MPC8555CDS_defconfig diff --git a/board/freescale/mpc8560ads/Kconfig b/board/freescale/mpc8560ads/Kconfig deleted file mode 100644 index 828c068..0000000 --- a/board/freescale/mpc8560ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8560ADS - -config SYS_BOARD - default "mpc8560ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8560ADS" - -endif diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS deleted file mode 100644 index 96e6da2..0000000 --- a/board/freescale/mpc8560ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8560ADS BOARD -#M: Kumar Gala -S: Orphan (since 2014-06) -F: board/freescale/mpc8560ads/ -F: include/configs/MPC8560ADS.h -F: configs/MPC8560ADS_defconfig diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile deleted file mode 100644 index 685168e..0000000 --- a/board/freescale/mpc8560ads/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8560ads.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c deleted file mode 100644 index 10fb2b3..0000000 --- a/board/freescale/mpc8560ads/ddr.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c deleted file mode 100644 index 41f2e02..0000000 --- a/board/freescale/mpc8560ads/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c deleted file mode 100644 index f99d639..0000000 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - - -void local_bus_init(void); - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - - -/* - * MPC8560ADS Board Status & Control Registers - */ -typedef struct bcsr_ { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; -} bcsr_t; - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -} - - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } - - return 0; -} -#endif diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c deleted file mode 100644 index d5ee791..0000000 --- a/board/freescale/mpc8560ads/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS index 379d8cc..56c5373 100644 --- a/board/freescale/mpc8568mds/MAINTAINERS +++ b/board/freescale/mpc8568mds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8568MDS BOARD -#M: - +M: York Sun S: Maintained F: board/freescale/mpc8568mds/ F: include/configs/MPC8568MDS.h diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS index c181407..49a9361 100644 --- a/board/freescale/mpc8569mds/MAINTAINERS +++ b/board/freescale/mpc8569mds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8569MDS BOARD -#M: - +M: York Sun S: Maintained F: board/freescale/mpc8569mds/ F: include/configs/MPC8569MDS.h diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS index de6ab89..8986c11 100644 --- a/board/freescale/mpc8610hpcd/MAINTAINERS +++ b/board/freescale/mpc8610hpcd/MAINTAINERS @@ -1,5 +1,5 @@ MPC8610HPCD BOARD -#M: - +M: York Sun S: Maintained F: board/freescale/mpc8610hpcd/ F: include/configs/MPC8610HPCD.h diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS index 9790247..86dcf6b 100644 --- a/board/freescale/mpc8641hpcn/MAINTAINERS +++ b/board/freescale/mpc8641hpcn/MAINTAINERS @@ -1,6 +1,6 @@ MPC8641HPCN BOARD -#M: Kumar Gala -S: Orphan (since 2014-06) +M: York Sun +S: Maintained F: board/freescale/mpc8641hpcn/ F: include/configs/MPC8641HPCN.h F: configs/MPC8641HPCN_defconfig diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 123fb11..ea0bd8f 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -24,6 +24,7 @@ #include #include #include +#include #ifndef CONFIG_BOARD_LATE_INIT #error "CONFIG_BOARD_LATE_INIT must be set for this board" diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS index db00143..c9f7fa3 100644 --- a/board/freescale/p1010rdb/MAINTAINERS +++ b/board/freescale/p1010rdb/MAINTAINERS @@ -1,5 +1,5 @@ P1010RDB BOARD -#M: - +M: Qiang Zhao S: Maintained F: board/freescale/p1010rdb/ F: include/configs/P1010RDB.h diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS index c19d436..0f9f98f 100644 --- a/board/freescale/p1_twr/MAINTAINERS +++ b/board/freescale/p1_twr/MAINTAINERS @@ -1,5 +1,5 @@ P1_TWR BOARD -#M: - +M: Xiaobo Xie S: Maintained F: board/freescale/p1_twr/ F: include/configs/p1_twr.h diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c index d218c21..e8996e0 100644 --- a/board/freescale/s32v234evb/clock.c +++ b/board/freescale/s32v234evb/clock.c @@ -45,7 +45,7 @@ static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) pll_idx = 1; break; case DDR_PLL: - pll_idx = 2;; + pll_idx = 2; break; default: pll_idx = pll; diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 0578989..8e32679 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -1,5 +1,5 @@ T104XRDB BOARD -M: Priyanka Jain +M: Priyanka Jain S: Maintained F: board/freescale/t104xrdb/ F: include/configs/T104xRDB.h @@ -18,7 +18,7 @@ F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig T1040RDB_SDCARD BOARD -#M: - +M: Priyanka Jain S: Maintained F: configs/T1040RDB_SDCARD_defconfig F: configs/T1040D4RDB_SDCARD_defconfig diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index a68ec69..6b950ee 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig new file mode 100644 index 0000000..41aa8fb --- /dev/null +++ b/board/geekbuying/geekbox/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GEEKBOX + +config SYS_BOARD + default "geekbox" + +config SYS_VENDOR + default "geekbuying" + +config SYS_CONFIG_NAME + default "geekbox" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/geekbuying/geekbox/MAINTAINERS b/board/geekbuying/geekbox/MAINTAINERS new file mode 100644 index 0000000..7a4989f --- /dev/null +++ b/board/geekbuying/geekbox/MAINTAINERS @@ -0,0 +1,6 @@ +GEEKBOX +M: Andreas Färber +S: Maintained +F: board/geekbuying/geekbox +F: include/configs/geekbox.h +F: configs/geekbox_defconfig diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile new file mode 100644 index 0000000..5c1d66c --- /dev/null +++ b/board/geekbuying/geekbox/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Andreas Färber +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += geekbox.o diff --git a/board/geekbuying/geekbox/README b/board/geekbuying/geekbox/README new file mode 100644 index 0000000..de980f2 --- /dev/null +++ b/board/geekbuying/geekbox/README @@ -0,0 +1 @@ +see board/rockchip/sheep_rk3368/README diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c new file mode 100644 index 0000000..75d121d --- /dev/null +++ b/board/geekbuying/geekbox/geekbox.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = 0x80000000; + + return 0; +} diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c index fefcde8..849224e 100644 --- a/board/gumstix/duovero/duovero.c +++ b/board/gumstix/duovero/duovero.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "duovero_mux_data.h" diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c index 01f8e67..2a2b797 100644 --- a/board/h2200/h2200.c +++ b/board/h2200/h2200.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README index 0f6aab7..4c2021f 100644 --- a/board/hisilicon/hikey/README +++ b/board/hisilicon/hikey/README @@ -56,7 +56,7 @@ Compile U-Boot Compile ARM Trusted Firmware (ATF) ================================== - > cd ~/hikey/src/atf + > cd ~/hikey/src/arm-trusted-firmware > make CROSS_COMPILE=aarch64-linux-gnu- all fip \ BL30=~/hikey/bin/mcuimage.bin \ BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey @@ -67,10 +67,10 @@ Copy resulting binaries Compile l-loader =============== - > cd ~/hikey/l-loader + > cd ~/hikey/src/l-loader > make BL1=~/hikey/bin/bl1.bin all > cp *.img ~/hikey/bin - > cp l-loader.bin ~/hikey.bin + > cp l-loader.bin ~/hikey/bin These instructions are adapted from https://github.com/96boards/documentation/wiki/HiKeyUEFI @@ -82,7 +82,7 @@ FLASHING the hisi-idt.py utility. The command below assumes HiKey enumerated as the first USB serial port - > sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin + > sudo ~/hikey/src/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin 2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable). diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig deleted file mode 100644 index 97e80d5..0000000 --- a/board/ifm/ac14xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_AC14XX - -config SYS_BOARD - default "ac14xx" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "ac14xx" - -endif diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS deleted file mode 100644 index 8fd74e5..0000000 --- a/board/ifm/ac14xx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -AC14XX BOARD -M: Anatolij Gustschin -S: Maintained -F: board/ifm/ac14xx/ -F: include/configs/ac14xx.h -F: configs/ac14xx_defconfig diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile deleted file mode 100644 index 55def60..0000000 --- a/board/ifm/ac14xx/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2009 Wolfgang Denk -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ac14xx.o diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c deleted file mode 100644 index cd79e80..0000000 --- a/board/ifm/ac14xx/ac14xx.c +++ /dev/null @@ -1,569 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk - * (C) Copyright 2009 Dave Srl www.dave.eu - * (C) Copyright 2010 ifm ecomatic GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MISC_INIT_R -#include -#endif - -static int mac_diag; -static int gpio_diag; - -DECLARE_GLOBAL_DATA_PTR; - -static void gpio_configure(void) -{ - immap_t *im; - gpio512x_t *gpioregs; - - im = (immap_t *) CONFIG_SYS_IMMR; - gpioregs = &im->gpio; - out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */ - out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */ - - /* - * out_be32(&gpioregs->gpdir, 0xC2293020); - * workaround for a hardware effect: configure direction in pieces, - * setting all outputs at once drops the reset line too low and - * makes us lose the MII connection (breaks ethernet for us) - */ - out_be32(&gpioregs->gpdir, 0x02003060); /* direction */ - setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */ - udelay(10); - setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */ - udelay(10); - setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */ - udelay(10); - setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */ - - /* to turn from red to yellow when U-Boot runs */ - setbits_be32(&gpioregs->gpdat, 0x00002020); - out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */ - out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */ - out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */ - out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */ -} - -/* the physical location of the pins */ -#define GPIOKEY_ROW_BITMASK 0x40000000 -#define GPIOKEY_ROW_UPPER 0 -#define GPIOKEY_ROW_LOWER 1 - -#define GPIOKEY_COL0_BITMASK 0x20000000 -#define GPIOKEY_COL1_BITMASK 0x10000000 -#define GPIOKEY_COL2_BITMASK 0x08000000 - -/* the logical presentation of pressed keys */ -#define GPIOKEY_BIT_FNLEFT (1 << 5) -#define GPIOKEY_BIT_FNRIGHT (1 << 4) -#define GPIOKEY_BIT_DIRUP (1 << 3) -#define GPIOKEY_BIT_DIRLEFT (1 << 2) -#define GPIOKEY_BIT_DIRRIGHT (1 << 1) -#define GPIOKEY_BIT_DIRDOWN (1 << 0) - -/* the hotkey combination which starts recovery */ -#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \ - GPIOKEY_BIT_DIRDOWN) - -static void gpio_selectrow(gpio512x_t *gpioregs, u32 row) -{ - - if (row) - setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); - else - clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); - udelay(10); -} - -static u32 gpio_querykbd(void) -{ - immap_t *im; - gpio512x_t *gpioregs; - u32 keybits; - u32 input; - - im = (immap_t *)CONFIG_SYS_IMMR; - gpioregs = &im->gpio; - keybits = 0; - - /* query upper row */ - gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER); - input = in_be32(&gpioregs->gpdat); - if ((input & GPIOKEY_COL0_BITMASK) == 0) - keybits |= GPIOKEY_BIT_FNLEFT; - if ((input & GPIOKEY_COL1_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRUP; - if ((input & GPIOKEY_COL2_BITMASK) == 0) - keybits |= GPIOKEY_BIT_FNRIGHT; - - /* query lower row */ - gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER); - input = in_be32(&gpioregs->gpdat); - if ((input & GPIOKEY_COL0_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRLEFT; - if ((input & GPIOKEY_COL1_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRRIGHT; - if ((input & GPIOKEY_COL2_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRDOWN; - - /* return bit pattern for keys */ - return keybits; -} - -/* excerpt from the recovery's hw_info.h */ - -struct __attribute__ ((__packed__)) eeprom_layout { - char magic[3]; /** 'ifm' */ - u8 len[2]; /** content length without magic/len fields */ - u8 version[3]; /** structure version */ - u8 type; /** type of PCB */ - u8 reserved[0x37]; /** padding up to offset 0x40 */ - u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */ -}; - -#define HW_COMP_MAINCPU 2 - -static struct eeprom_layout eeprom_content; -static int eeprom_is_valid; -static int eeprom_version; - -#define get_eeprom_field_int(name) ({ \ - int value; \ - int idx; \ - value = 0; \ - for (idx = 0; idx < sizeof(name); idx++) { \ - value <<= 8; \ - value |= name[idx]; \ - } \ - value; \ -}) - -static int read_eeprom(void) -{ - return -ENOSYS; -} - -int mac_read_from_eeprom(void) -{ - const u8 *mac; - const char *mac_txt; - - if (read_eeprom()) { - printf("I2C EEPROM read failed.\n"); - return -1; - } - - if (!eeprom_is_valid) { - printf("I2C EEPROM content not valid\n"); - return -1; - } - - mac = NULL; - switch (eeprom_version) { - case 1: - case 2: - mac = (const u8 *)&eeprom_content.macaddress; - break; - } - - if (mac && is_valid_ethaddr(mac)) { - eth_setenv_enetaddr("ethaddr", mac); - if (mac_diag) { - mac_txt = getenv("ethaddr"); - if (mac_txt) - printf("DIAG: MAC value [%s]\n", mac_txt); - else - printf("DIAG: failed to setup MAC env\n"); - } - } - - return 0; -} - -/* - * BEWARE! - * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2 - * which the ADS, Aria or PDM360NG boards are using - * (the steps outlined here refer to the Micron datasheet) - */ -u32 sdram_init_seq[] = { - /* item 6, at least one NOP after CKE went high */ - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - /* item 7, precharge all; item 8, tRP (20ns) */ - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - /* item 9, extended mode register; item 10, tMRD 10ns) */ - CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 11, (base) mode register _with_ reset DLL; - * item 12, tMRD (10ns) - */ - CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL | - CONFIG_SYS_MICRON_BMODE_PARAM, - CONFIG_SYS_DDRCMD_NOP, - /* item 13, precharge all; item 14, tRP (20ns) */ - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 15, auto refresh (i.e. refresh with CKE held high); - * item 16, tRFC (70ns) - */ - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 17, auto refresh (i.e. refresh with CKE held high); - * item 18, tRFC (70ns) - */ - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */ - CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 21, "actually done", but make sure 200 DRAM clock cycles - * have passed after DLL reset before READ requests are issued - * (200 cycles at 160MHz -> 1.25 usec) - */ - /* EMPTY, optional, we don't do it */ -}; - -int dram_init(void) -{ - gd->ram_size = fixed_sdram(NULL, sdram_init_seq, - ARRAY_SIZE(sdram_init_seq)); - - return 0; -} - -int misc_init_r(void) -{ - u32 keys; - char *s; - int want_recovery; - - /* setup GPIO directions and initial values */ - gpio_configure(); - - /* - * enforce the start of the recovery system when - * - the appropriate keys were pressed - * - "some" external software told us to - * - a previous installation was aborted or has failed - */ - want_recovery = 0; - keys = gpio_querykbd(); - if (gpio_diag) - printf("GPIO keyboard status [0x%02X]\n", keys); - if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) { - printf("detected recovery request (keyboard)\n"); - want_recovery = 1; - } - s = getenv("want_recovery"); - if ((s != NULL) && (*s != '\0')) { - printf("detected recovery request (environment)\n"); - want_recovery = 1; - } - s = getenv("install_in_progress"); - if ((s != NULL) && (*s != '\0')) { - printf("previous installation has not completed\n"); - want_recovery = 1; - } - s = getenv("install_failed"); - if ((s != NULL) && (*s != '\0')) { - printf("previous installation has failed\n"); - want_recovery = 1; - } - if (want_recovery) { - printf("enforced start of the recovery system\n"); - setenv("bootcmd", "run recovery"); - } - - /* - * boot the recovery system without waiting; boot the - * production system without waiting by default, only - * insert a pause (to provide a chance to get a prompt) - * when GPIO keys were pressed during power on - */ - if (want_recovery) - setenv("bootdelay", "0"); - else if (!keys) - setenv("bootdelay", "0"); - else - setenv("bootdelay", "2"); - - /* get the ethernet MAC from I2C EEPROM */ - mac_read_from_eeprom(); - - return 0; -} - -/* setup specific IO pad configuration */ -static iopin_t ioregs_init[] = { - { /* LPC CS3 */ - offsetof(struct ioctrl512x, io_control_nfc_ce0), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* LPC CS1 */ - offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC CS2 */ - offsetof(struct ioctrl512x, io_control_lpc_cs2), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC CS4, CS5 */ - offsetof(struct ioctrl512x, io_control_pata_ce1), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* SDHC CLK, CMD, D0, D1, D2, D3 */ - offsetof(struct ioctrl512x, io_control_pata_ior), 6, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* GPIO keyboard */ - offsetof(struct ioctrl512x, io_control_pci_ad30), 4, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO DN1 PF, LCD power, DN2 PF */ - offsetof(struct ioctrl512x, io_control_pci_ad26), 3, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO reset AS-i */ - offsetof(struct ioctrl512x, io_control_pci_ad21), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO reset safety */ - offsetof(struct ioctrl512x, io_control_pci_ad19), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO reset netX */ - offsetof(struct ioctrl512x, io_control_pci_ad16), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO ma2 en */ - offsetof(struct ioctrl512x, io_control_pci_ad15), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO SD CD, SD WP */ - offsetof(struct ioctrl512x, io_control_pci_ad08), 2, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* FEC RX DV */ - offsetof(struct ioctrl512x, io_control_pci_ad06), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(2), - }, - { /* GPIO AS-i prog, AS-i done, LCD backlight */ - offsetof(struct ioctrl512x, io_control_pci_ad05), 3, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO AS-i wdg */ - offsetof(struct ioctrl512x, io_control_pci_req2), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO safety wdg */ - offsetof(struct ioctrl512x, io_control_pci_req1), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO netX wdg */ - offsetof(struct ioctrl512x, io_control_pci_req0), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO IRQ powerfail */ - offsetof(struct ioctrl512x, io_control_pci_inta), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO AS-i PWRD */ - offsetof(struct ioctrl512x, io_control_pci_frame), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO LED0, LED1 */ - offsetof(struct ioctrl512x, io_control_pci_idsel), 2, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */ - offsetof(struct ioctrl512x, io_control_pci_irdy), 3, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* DIU clk */ - offsetof(struct ioctrl512x, io_control_spdif_txclk), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(2), - }, - { /* FEC TX ER, CRS */ - offsetof(struct ioctrl512x, io_control_spdif_tx), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */ - offsetof(struct ioctrl512x, io_control_irq0), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* - * FEC col, tx en, tx clk, txd 0-3, mdc, rx er, - * rdx 3-0, mdio, rx clk - */ - offsetof(struct ioctrl512x, io_control_psc0_0), 15, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - /* optional: make sure PSC3 remains the serial console */ - { /* LPC CS6 */ - offsetof(struct ioctrl512x, io_control_psc3_4), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - /* make sure PSC4 remains available for SPI, - *BUT* PSC4_1 is a GPIO kind of SS! */ - { /* enforce drive strength on the SPI pin */ - offsetof(struct ioctrl512x, io_control_psc4_0), 5, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { - offsetof(struct ioctrl512x, io_control_psc4_1), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - /* optional: make sure PSC5 remains available for SPI */ - { /* enforce drive strength on the SPI pin */ - offsetof(struct ioctrl512x, io_control_psc5_0), 5, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(1), - }, - { /* LPC TSIZ1 */ - offsetof(struct ioctrl512x, io_control_psc6_0), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* DIU hsync */ - offsetof(struct ioctrl512x, io_control_psc6_1), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* DIU vsync */ - offsetof(struct ioctrl512x, io_control_psc6_4), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* PSC7, part of DIU RGB */ - offsetof(struct ioctrl512x, io_control_psc7_0), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* PSC7, safety UART */ - offsetof(struct ioctrl512x, io_control_psc7_2), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(0) | IO_PIN_DS(1), - }, - { /* DIU (part of) RGB[] */ - offsetof(struct ioctrl512x, io_control_psc8_3), 16, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* DIU data enable */ - offsetof(struct ioctrl512x, io_control_psc11_4), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - /* reduce LPB drive strength for improved EMI */ - { /* LPC OE, LPC RW */ - offsetof(struct ioctrl512x, io_control_lpc_oe), 2, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC AX03 through LPC AD00 */ - offsetof(struct ioctrl512x, io_control_lpc_ax03), 36, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC CS5 */ - offsetof(struct ioctrl512x, io_control_pata_ce2), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* SDHC CLK */ - offsetof(struct ioctrl512x, io_control_nfc_wp), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* SDHC DATA */ - offsetof(struct ioctrl512x, io_control_nfc_ale), 4, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, -}; - -int checkboard(void) -{ - puts("Board: ifm AC14xx\n"); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init)); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig deleted file mode 100644 index e9d32dd..0000000 --- a/board/ifm/o2dnt2/Kconfig +++ /dev/null @@ -1,77 +0,0 @@ -if TARGET_O2D - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2d" - -endif - -if TARGET_O2D300 - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2d300" - -endif - -if TARGET_O2DNT2 - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2dnt2" - -endif - -if TARGET_O2I - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2i" - -endif - -if TARGET_O2MNT - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2mnt" - -endif - -if TARGET_O3DNT - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o3dnt" - -endif diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS deleted file mode 100644 index 002f89e..0000000 --- a/board/ifm/o2dnt2/MAINTAINERS +++ /dev/null @@ -1,20 +0,0 @@ -O2DNT2 BOARD -M: Anatolij Gustschin -S: Maintained -F: board/ifm/o2dnt2/ -F: include/configs/o2d.h -F: configs/O2D_defconfig -F: include/configs/o2d300.h -F: configs/O2D300_defconfig -F: include/configs/o2dnt2.h -F: configs/O2DNT2_defconfig -F: configs/O2DNT2_RAMBOOT_defconfig -F: include/configs/o2i.h -F: configs/O2I_defconfig -F: include/configs/o2mnt.h -F: configs/O2MNT_defconfig -F: configs/O2MNT_O2M110_defconfig -F: configs/O2MNT_O2M112_defconfig -F: configs/O2MNT_O2M113_defconfig -F: include/configs/o3dnt.h -F: configs/O3DNT_defconfig diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile deleted file mode 100644 index 64d6ba8..0000000 --- a/board/ifm/o2dnt2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2005-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := o2dnt2.o diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c deleted file mode 100644 index 7770806..0000000 --- a/board/ifm/o2dnt2/o2dnt2.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Partially derived from board code for digsyMTC, - * (C) Copyright 2009 - * Grzegorz Bernacki, Semihalf, gjb@semihalf.com - * - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -enum ifm_sensor_type { - O2DNT = 0x00, /* !< O2DNT 32MB */ - O2DNT2 = 0x01, /* !< O2DNT2 64MB */ - O3DNT = 0x02, /* !< O3DNT 32MB */ - O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */ - UNKNOWN = 0xff, /* !< Unknow sensor */ -}; - -static enum ifm_sensor_type gt_ifm_sensor_type; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32(&sdram->ctrl, control | 0x80000000); - - /* precharge all banks */ - out_be32(&sdram->ctrl, control | 0x80000002); - - /* auto refresh */ - out_be32(&sdram->ctrl, control | 0x80000004); - - /* set mode register */ - out_be32(&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32(&sdram->ctrl, control); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. - */ -int dram_init(void) -{ - struct mpc5xxx_mmap_ctl *mmap_ctl = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - - if (gt_ifm_sensor_type == O2DNT2) { - /* activate SDRAM CS1 */ - setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000); - } - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */ - out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */ - - /* setup config registers */ - out_be32(&sdram->config1, SDRAM_CONFIG1); - out_be32(&sdram->config2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32(&mmap_ctl->sdram0, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - out_be32(&mmap_ctl->sdram0, 0); /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), - 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), - 0x80000000); - } - - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - out_be32(&mmap_ctl->sdram1, (dramsize | - (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); - } else { - out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) - out_be32(&sdram->sdelay, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - - -#define GPT_GPIO_IN 0x4 - -int checkboard(void) -{ - struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; - unsigned char board_config = 0; - int i; - - /* switch gpt0 - gpt7 to input */ - for (i = 0; i < 7; i++) - out_be32(&gpt[i].emsr, GPT_GPIO_IN); - - /* get configuration byte on timer-port */ - for (i = 0; i < 7; i++) - board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i); - - puts("Board: "); - - switch (board_config) { - case 0: - puts("O2DNT\n"); - gt_ifm_sensor_type = O2DNT; - break; - case 1: - puts("O3DNT\n"); - gt_ifm_sensor_type = O3DNT; - break; - case 2: - puts("O2DNT2\n"); - gt_ifm_sensor_type = O2DNT2; - break; - case 64: - puts("O3DNT Minerva\n"); - gt_ifm_sensor_type = O3DNT_MIN; - break; - default: - puts("Unknown\n"); - gt_ifm_sensor_type = UNKNOWN; - break; - } - - return 0; -} - -int board_early_init_r(void) -{ - struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in flash. - */ - clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */ - /* disable CS_BOOT */ - clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); - /* enable CS0 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); - - return 0; -} - -#define MIIM_LXT971_LED_CFG_REG 0x14 -#define LXT971_LED_CFG_LINK_STATUS 0x4000 -#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700 -#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0 -#define LXT971_LED_CFG_PULSE_STRETCH 0x0002 -/* - * Additional PHY intialization after reset in mpc5xxx_fec_init_phy() - */ -void reset_phy(void) -{ - /* - * Set LED configuration bits. - * It can't be done in misc_init_r() since FEC is not - * initialized at this time. Therefore we do it here. - */ - miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG, - LXT971_LED_CFG_LINK_STATUS | - LXT971_LED_CFG_RX_TX_ACTIVITY | - LXT971_LED_CFG_LINK_ACTIVITY | - LXT971_LED_CFG_PULSE_STRETCH); -} - -#if defined(CONFIG_POST) -/* - * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 - * is left open, no keypress is detected. - */ -int post_hotkeys_pressed(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - - /* - * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in - * CODEC or UART mode. Consumer IrDA should still be possible. - */ - clrbits_be32(&gpio->port_config, 0x07000000); - setbits_be32(&gpio->port_config, 0x03000000); - - /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ - setbits_be32(&gpio->simple_gpioe, 0x20000000); - - /* Configure GPIO_IRDA_1 as input */ - clrbits_be32(&gpio->simple_ddr, 0x20000000); - - return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1; -} -#endif - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -static void ft_adapt_flash_base(void *blob) -{ - flash_info_t *dev = &flash_info[0]; - int off; - struct fdt_property *prop; - int len; - u32 *reg, *reg2; - - off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); - if (off < 0) { - printf("Could not find fsl,mpc5200b-lpb node.\n"); - return; - } - - /* found compatible property */ - prop = fdt_get_property_w(blob, off, "ranges", &len); - if (prop) { - reg = reg2 = (u32 *)&prop->data[0]; - - reg[2] = dev->start[0]; - reg[3] = dev->size; - fdt_setprop(blob, off, "ranges", reg2, len); - } else - printf("Could not find ranges\n"); -} - -extern ulong flash_get_size(phys_addr_t base, int banknum); - -/* Update the flash baseaddr settings */ -int update_flash_size(int flash_size) -{ - struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - flash_info_t *dev; - int i; - int size = 0; - unsigned long base = 0x0; - u32 *cs_reg = (u32 *)&mm->cs0_start; - - for (i = 0; i < 2; i++) { - dev = &flash_info[i]; - - if (dev->size) { - /* calculate new base addr for this chipselect */ - base -= dev->size; - out_be32(cs_reg, START_REG(base)); - cs_reg++; - out_be32(cs_reg, STOP_REG(base, dev->size)); - cs_reg++; - /* recalculate the sectoraddr in the cfi driver */ - size += flash_get_size(base, i); - } - } - flash_protect_default(); - gd->bd->bi_flashstart = base; - return 0; -} -#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ - -int ft_board_setup(void *blob, bd_t *bd) -{ - int phy_addr = CONFIG_PHY_ADDR; - char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; - - ft_cpu_setup(blob, bd); - -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE - /* Update reg property in all nor flash nodes too */ - fdt_fixup_nor_flash_size(blob); -#endif - ft_adapt_flash_base(blob); -#endif - /* fix up the phy address */ - do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 3f45e4e..6532466 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -11,6 +11,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig deleted file mode 100644 index 94a41f0..0000000 --- a/board/inka4x0/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_INKA4X0 - -config SYS_BOARD - default "inka4x0" - -config SYS_CONFIG_NAME - default "inka4x0" - -endif diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS deleted file mode 100644 index e8cec73..0000000 --- a/board/inka4x0/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -INKA4X0 BOARD -M: Anatolij Gustschin -S: Maintained -F: board/inka4x0/ -F: include/configs/inka4x0.h -F: configs/inka4x0_defconfig diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile deleted file mode 100644 index c9a3540..0000000 --- a/board/inka4x0/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2009 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := inka4x0.o inkadiag.o diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c deleted file mode 100644 index 88cae59..0000000 --- a/board/inka4x0/inka4x0.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Andreas Pfefferle, DENX Software Engineering, ap@denx.de. - * - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#if defined(CONFIG_DDR_MT46V16M16) -#include "mt46v16m16-75.h" -#elif defined(CONFIG_SDR_MT48LC16M16A2) -#include "mt48lc16m16a2-75.h" -#elif defined(CONFIG_DDR_MT46V32M16) -#include "mt46v32m16.h" -#elif defined(CONFIG_DDR_HYB25D512160BF) -#include "hyb25d512160bf.h" -#elif defined(CONFIG_DDR_K4H511638C) -#include "k4h511638c.h" -#else -#error "INKA4x0 SDRAM: invalid chip type specified!" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit); - - /* precharge all banks */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - -#if SDRAM_DDR - /* set mode register: extended mode */ - out_be32(&sdram->mode, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32(&sdram->mode, SDRAM_MODE | 0x04000000); -#endif - - /* precharge all banks */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* auto refresh */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit); - - /* set mode register */ - out_be32(&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *) MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *) MPC5XXX_SDRAM; - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - long test1, test2; - - /* setup SDRAM chip selects */ - out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */ - out_be32(&mm->sdram1, 0x40000000); /* disabled */ - - /* setup config registers */ - out_be32(&sdram->config1, SDRAM_CONFIG1); - out_be32(&sdram->config2, SDRAM_CONFIG2); - -#if SDRAM_DDR - /* set tap delay */ - out_be32(&cdm->porcfg, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32(&mm->sdram0, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32(&mm->sdram0, 0); /* disabled */ - } - - out_be32(&mm->sdram1, dramsize); /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: INKA 4X0\n"); - return 0; -} - -void flash_preinit(void) -{ - volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT (CS0) cannot be cleared when - * executing in flash. - */ - clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */ -} - -int misc_init_f (void) -{ - volatile struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - volatile struct mpc5xxx_gpt *gpt; - char tmp[10]; - int i, br; - - i = getenv_f("brightness", tmp, sizeof(tmp)); - br = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_SYS_BRIGHTNESS; - if (br > 255) - br = 255; - - /* Initialize GPIO output pins. - */ - /* Configure GPT as GPIO output (and set them as they control low-active LEDs */ - for (i = 0; i <= 5; i++) { - gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10)); - out_be32(&gpt->emsr, 0x34); - } - - /* Configure GPT7 as PWM timer, 1kHz, no ints. */ - gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10)); - out_be32(&gpt->emsr, 0); /* Disable */ - out_be32(&gpt->cir, 0x020000fe); - out_be32(&gpt->pwmcr, (br << 16)); - out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */ - - /* Configure PSC3_6,7 as GPIO output */ - setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 | - MPC5XXX_GPIO_SIMPLE_PSC3_7); - setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 | - MPC5XXX_GPIO_SIMPLE_PSC3_7); - - /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */ - setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 | - MPC5XXX_GPIO_WKUP_7 | - MPC5XXX_GPIO_WKUP_PSC3_9); - setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 | - MPC5XXX_GPIO_WKUP_7 | - MPC5XXX_GPIO_WKUP_PSC3_9); - - /* Set LR mirror bit because it is low-active */ - setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7); - - /* Reset Coral-P graphics controller */ - setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9); - - /* Enable display backlight */ - clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8); - - /* - * Configure three wire serial interface to RTC (PSC1_4, - * PSC2_4, PSC3_4, PSC3_5) - */ - setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 | - MPC5XXX_GPIO_WKUP_PSC2_4); - setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 | - MPC5XXX_GPIO_WKUP_PSC2_4); - clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4); - clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 | - MPC5XXX_GPIO_SINT_PSC3_5); - setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 | - MPC5XXX_GPIO_SINT_PSC3_5); - setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5); - clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5); - - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c deleted file mode 100644 index 4c43205..0000000 --- a/board/inka4x0/inkadiag.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * (C) Copyright 2008, 2009 Andreas Pfefferle, - * DENX Software Engineering, ap@denx.de. - * (C) Copyright 2009 Detlev Zundel, - * DENX Software Engineering, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#include - -/* This is needed for the includes in ns16550.h */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#include - -#define GPIO_BASE ((u_char *)CONFIG_SYS_CS3_START) - -#define DIGIN_TOUCHSCR_MASK 0x00003000 /* Inputs 12-13 */ -#define DIGIN_KEYB_MASK 0x00010000 /* Input 16 */ - -#define DIGIN_DRAWER_SW1 0x00400000 /* Input 22 */ -#define DIGIN_DRAWER_SW2 0x00800000 /* Input 23 */ - -#define DIGIO_LED0 0x00000001 /* Output 0 */ -#define DIGIO_LED1 0x00000002 /* Output 1 */ -#define DIGIO_LED2 0x00000004 /* Output 2 */ -#define DIGIO_LED3 0x00000008 /* Output 3 */ -#define DIGIO_LED4 0x00000010 /* Output 4 */ -#define DIGIO_LED5 0x00000020 /* Output 5 */ - -#define DIGIO_DRAWER1 0x00000100 /* Output 8 */ -#define DIGIO_DRAWER2 0x00000200 /* Output 9 */ - -#define SERIAL_PORT_BASE ((u_char *)CONFIG_SYS_CS2_START) - -#define PSC_OP1_RTS 0x01 -#define PSC_OP0_RTS 0x01 - -/* - * Table with supported baudrates (defined in inka4x0.h) - */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; -#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) - -static unsigned int inka_digin_get_input(void) -{ - return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 | - in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24; -} - -#define LED_HIGH(NUM) \ - do { \ - setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \ - } while (0) - -#define LED_LOW(NUM) \ - do { \ - clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \ - } while (0) - -#define CHECK_LED(NUM) \ - do { \ - if (state & (1 << NUM)) { \ - LED_HIGH(NUM); \ - } else { \ - LED_LOW(NUM); \ - } \ - } while (0) - -static void inka_digio_set_output(unsigned int state, int which) -{ - volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (which == 0) { - /* other */ - CHECK_LED(0); - CHECK_LED(1); - CHECK_LED(2); - CHECK_LED(3); - CHECK_LED(4); - CHECK_LED(5); - } else { - if (which == 1) { - /* drawer1 */ - if (state) { - clrbits_be32(&gpio->simple_dvo, 0x1000); - udelay(1); - setbits_be32(&gpio->simple_dvo, 0x1000); - } else { - setbits_be32(&gpio->simple_dvo, 0x1000); - udelay(1); - clrbits_be32(&gpio->simple_dvo, 0x1000); - } - } - if (which == 2) { - /* drawer 2 */ - if (state) { - clrbits_be32(&gpio->simple_dvo, 0x2000); - udelay(1); - setbits_be32(&gpio->simple_dvo, 0x2000); - } else { - setbits_be32(&gpio->simple_dvo, 0x2000); - udelay(1); - clrbits_be32(&gpio->simple_dvo, 0x2000); - } - } - } - udelay(1); -} - -static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - unsigned int state, val; - - switch (argc) { - case 3: - /* Write a value */ - val = simple_strtol(argv[2], NULL, 16); - - if (strcmp(argv[1], "drawer1") == 0) { - inka_digio_set_output(val, 1); - } else if (strcmp(argv[1], "drawer2") == 0) { - inka_digio_set_output(val, 2); - } else if (strcmp(argv[1], "other") == 0) - inka_digio_set_output(val, 0); - else { - printf("Invalid argument: %s\n", argv[1]); - return -1; - } - /* fall through */ - case 2: - /* Read a value */ - state = inka_digin_get_input(); - - if (strcmp(argv[1], "drawer1") == 0) { - val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1); - } else if (strcmp(argv[1], "drawer2") == 0) { - val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1); - } else if (strcmp(argv[1], "other") == 0) { - val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1)) - | (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2); - } else { - printf("Invalid argument: %s\n", argv[1]); - return -1; - } - printf("exit code: 0x%X\n", val); - return 0; - default: - return cmd_usage(cmdtp); - } - - return -1; -} - -DECLARE_GLOBAL_DATA_PTR; - -static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate) -{ - unsigned long baseclk; - int div; - - /* reset PSC */ - out_8(&psc->command, PSC_SEL_MODE_REG_1); - - /* select clock sources */ - - out_be16(&psc->psc_clock_select, 0); - baseclk = (gd->arch.ipb_clk + 16) / 32; - - /* switch to UART mode */ - out_be32(&psc->sicr, 0); - - /* configure parity, bit length and so on */ - - out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); - out_8(&psc->mode, PSC_MODE_ONE_STOP); - - /* set up UART divisor */ - div = (baseclk + (baudrate / 2)) / baudrate; - out_8(&psc->ctur, (div >> 8) & 0xff); - out_8(&psc->ctlr, div & 0xff); - - /* disable all interrupts */ - out_be16(&psc->psc_imr, 0); - - /* reset and enable Rx/Tx */ - out_8(&psc->command, PSC_RST_RX); - out_8(&psc->command, PSC_RST_TX); - out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE); - - return 0; -} - -static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c) -{ - /* Wait 1 second for last character to go. */ - int i = 0; - - while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10)) - udelay(10); - psc->psc_buffer_8 = c; - -} - -static int ser_getc(volatile struct mpc5xxx_psc *psc) -{ - /* Wait for a character to arrive. */ - int i = 0; - - while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10)) - udelay(10); - - return in_8(&psc->psc_buffer_8); -} - -static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - volatile struct NS16550 *uart; - volatile struct mpc5xxx_psc *psc; - unsigned int num, mode; - int combrd, baudrate, i, j, len; - int address; - - if (argc < 5) - return cmd_usage(cmdtp); - - argc--; - argv++; - - num = simple_strtol(argv[0], NULL, 0); - if (num < 0 || num > 11) { - printf("invalid argument for num: %d\n", num); - return -1; - } - - mode = simple_strtol(argv[1], NULL, 0); - - combrd = 0; - baudrate = simple_strtoul(argv[2], NULL, 10); - for (i=0; i= 0) && (num <= 7)) { - if (mode & 1) { - /* turn on 'loopback' mode */ - out_8(&uart->mcr, UART_MCR_LOOP); - } else { - /* - * establish the UART's operational parameters - * set DLAB=1, so rbr accesses DLL - */ - out_8(&uart->lcr, UART_LCR_DLAB); - /* set baudrate */ - out_8(&uart->rbr, combrd); - /* set data-format: 8-N-1 */ - out_8(&uart->lcr, UART_LCR_WLS_8); - } - - if (mode & 2) { - /* set request to send */ - out_8(&uart->mcr, UART_MCR_RTS); - udelay(10); - /* check clear to send */ - if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00) - return -1; - } - if (mode & 4) { - /* set data terminal ready */ - out_8(&uart->mcr, UART_MCR_DTR); - udelay(10); - /* check data set ready and carrier detect */ - if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD)) - != (UART_MSR_DSR | UART_MSR_DCD)) - return -1; - } - - /* write each message-character, read it back, and display it */ - for (i = 0, len = strlen(argv[3]); i < len; ++i) { - j = 0; - while ((in_8(&uart->lsr) & UART_LSR_THRE) == 0x00) { - if (j++ > CONFIG_SYS_HZ) - break; - udelay(10); - } - out_8(&uart->rbr, argv[3][i]); - j = 0; - while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) { - if (j++ > CONFIG_SYS_HZ) - break; - udelay(10); - } - printf("%c", in_8(&uart->rbr)); - } - printf("\n\n"); - out_8(&uart->mcr, 0x00); - } else { - address = 0; - - switch (num) { - case 8: - address = MPC5XXX_PSC6; - break; - case 9: - address = MPC5XXX_PSC3; - break; - case 10: - address = MPC5XXX_PSC2; - break; - case 11: - address = MPC5XXX_PSC1; - break; - } - psc = (struct mpc5xxx_psc *)address; - ser_init(psc, simple_strtol(argv[2], NULL, 0)); - if (mode & 2) { - /* set request to send */ - out_8(&psc->op0, PSC_OP0_RTS); - udelay(10); - /* check clear to send */ - if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0) - return -1; - } - len = strlen(argv[3]); - for (i = 0; i < len; ++i) { - ser_putc(psc, argv[3][i]); - printf("%c", ser_getc(psc)); - } - printf("\n\n"); - } - return 0; -} - -#define BUZZER_GPT (MPC5XXX_GPT + 0x60) /* GPT6 */ -static void buzzer_turn_on(unsigned int freq) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT); - - const u32 prescale = gd->arch.ipb_clk / freq / 128; - const u32 count = 128; - const u32 width = 64; - - gpt->cir = (prescale << 16) | count; - gpt->pwmcr = width << 16; - gpt->emsr = 3; /* Timer enabled for PWM */ -} - -static void buzzer_turn_off(void) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT); - - gpt->emsr = 0; -} - -static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - - unsigned int period, freq; - int prev, i; - - if (argc != 3) - return cmd_usage(cmdtp); - - argc--; - argv++; - - period = simple_strtol(argv[0], NULL, 0); - if (!period) - printf("Zero period is senseless\n"); - argc--; - argv++; - - freq = simple_strtol(argv[0], NULL, 0); - /* avoid zero prescale in buzzer_turn_on() */ - if (freq > gd->arch.ipb_clk / 128) { - printf("%dHz exceeds maximum (%ldHz)\n", freq, - gd->arch.ipb_clk / 128); - } else if (!freq) - printf("Zero frequency is senseless\n"); - else - buzzer_turn_on(freq); - - clear_ctrlc(); - prev = disable_ctrlc(0); - - printf("Buzzing for %d ms. Type ^C to abort!\n\n", period); - - i = 0; - while (!ctrlc() && (i++ < CONFIG_SYS_HZ)) - udelay(period); - - clear_ctrlc(); - disable_ctrlc(prev); - - buzzer_turn_off(); - - return 0; -} - -static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -cmd_tbl_t cmd_inkadiag_sub[] = { - U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input", - " [value] - get or set specified signal"), - U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port", - " - test uart num [0..11] in mode\n" - "and baudrate with msg"), - U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer", - " - turn buzzer on for period ms with freq hz"), - U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help", - "[command] - get help for command"), -}; - -static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) { - extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items, - cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]); - /* do_help prints command name - we prepend inkadiag to our subcommands! */ -#ifdef CONFIG_SYS_LONGHELP - puts ("inkadiag "); -#endif - return _do_help(&cmd_inkadiag_sub[0], - ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv); -} - -static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - cmd_tbl_t *c; - - c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub)); - - if (c) { - argc--; - argv++; - return c->cmd(c, flag, argc, argv); - } else { - /* Unrecognized command */ - return cmd_usage(cmdtp); - } -} - -U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag, - "inkadiag - inka diagnosis\n", - "[inkadiag what ...]\n" - " - perform a diagnosis on inka hardware\n" - "'inkadiag' performs hardware tests."); diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h deleted file mode 100644 index 054ddaf..0000000 --- a/board/inka4x0/k4h511638c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h deleted file mode 100644 index 23fc6f0..0000000 --- a/board/inka4x0/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h deleted file mode 100644 index f16f450..0000000 --- a/board/inka4x0/mt46v32m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa..0000000 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig deleted file mode 100644 index 1cf2275..0000000 --- a/board/intercontrol/digsy_mtc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DIGSY_MTC - -config SYS_BOARD - default "digsy_mtc" - -config SYS_VENDOR - default "intercontrol" - -config SYS_CONFIG_NAME - default "digsy_mtc" - -endif diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS deleted file mode 100644 index c83ebcd..0000000 --- a/board/intercontrol/digsy_mtc/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -DIGSY_MTC BOARD -M: Werner Pfister -S: Maintained -F: board/intercontrol/digsy_mtc/ -F: include/configs/digsy_mtc.h -F: configs/digsy_mtc_defconfig -F: configs/digsy_mtc_RAMBOOT_defconfig -F: configs/digsy_mtc_rev5_defconfig -F: configs/digsy_mtc_rev5_RAMBOOT_defconfig diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile deleted file mode 100644 index 4d13ead..0000000 --- a/board/intercontrol/digsy_mtc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := digsy_mtc.o -obj-$(CONFIG_VIDEO) += cmd_disp.o diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c deleted file mode 100644 index 2ffa8bf..0000000 --- a/board/intercontrol/digsy_mtc/cmd_disp.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2011 DENX Software Engineering, - * Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define GPIO_USB1_0 0x00010000 - -static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (argc < 2) { - printf("%s\n", - in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off"); - return 0; - } - - if (!strncmp(argv[1], "on", 2)) { - setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); - } else if (!strncmp(argv[1], "off", 3)) { - clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0); - } else { - cmd_usage(cmdtp); - return 1; - } - return 0; -} - -U_BOOT_CMD(disp, 2, 1, cmd_disp, - "disp [on/off] - switch display on/off", - "\n - print display on/off status\n" - "on\n - turn on\n" - "off\n - turn off\n" -); diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c deleted file mode 100644 index 6c33eeb..0000000 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2009 - * Modified for InterControl digsyMTC MPC5200 board by - * Frank Bodammer, GCD Hard- & Software GmbH, - * frank.bodammer@gcd-solutions.de - * - * (C) Copyright 2009 - * Grzegorz Bernacki, Semihalf, gjb@semihalf.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "eeprom.h" -#if defined(CONFIG_DIGSY_REV5) -#include "is45s16800a2.h" -#include -#include -#else -#include "is42s16800a-7t.h" -#endif -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern int usb_cpu_init(void); - -#if defined(CONFIG_DIGSY_REV5) -/* - * The M29W128GH needs a special reset command function, - * details see the doc/README.cfi file - */ -void flash_cmd_reset(flash_info_t *info) -{ - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); -} -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - - /* auto refresh */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); - - /* set mode register */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ - - /* setup config registers */ - out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C); - - /* find RAM size using SDRAM CS1 only */ - test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), - 0x08000000); - dramsize2 = test1; - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize | - (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) - out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: InterControl digsyMTC"); -#if defined(CONFIG_DIGSY_REV5) - puts (" rev5"); -#endif - if (i > 0) { - puts(", "); - puts(buf); - } - putc('\n'); - - return 0; -} - -#if defined(CONFIG_VIDEO) - -#define GPIO_USB1_0 0x00010000 /* Power-On pin */ -#define GPIO_USB1_9 0x08 /* PX_~EN pin */ - -#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */ -#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */ -#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */ -#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */ - -#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */ - -static void exbo_hw_init(void) -{ - struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - /* configure IrDA pins (PSC6 port) as gpios */ - gpio->port_config &= 0xFF8FFFFF; - - /* Init for USB1_0, EE_CLK and EE_DI - Low */ - setbits_be32(&gpio->simple_ddr, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - clrbits_be32(&gpio->simple_ode, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - clrbits_be32(&gpio->simple_dvo, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - setbits_be32(&gpio->simple_gpioe, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - - /* Init for EE_DO, EE_CTS - Input */ - clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS); - setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS); - - /* Init for PX_~EN (USB1_9) - High */ - clrbits_8(&gpio->sint_ode, GPIO_USB1_9); - setbits_8(&gpio->sint_ddr, GPIO_USB1_9); - clrbits_8(&gpio->sint_inten, GPIO_USB1_9); - setbits_8(&gpio->sint_dvo, GPIO_USB1_9); - setbits_8(&gpio->sint_gpioe, GPIO_USB1_9); - - /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */ - out_be32(&gpt[0].emsr, GPT_GPIO_ON); - /* Init for S Switch (GPIO4) - Timer_1 GPIO High */ - out_be32(&gpt[1].emsr, GPT_GPIO_ON); - - /* Power-On camera supply */ - setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); -} -#else -static inline void exbo_hw_init(void) {} -#endif /* CONFIG_VIDEO */ - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in - * flash. - */ - /* disable CS_BOOT */ - clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); - /* enable CS1 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17)); - /* enable CS0 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - /* Low level USB init, required for proper kernel operation */ - usb_cpu_init(); -#endif - - return (0); -} - -void board_get_enetaddr (uchar * enet) -{ - ushort read = 0; - ushort addr_of_eth_addr = 0; - ushort len_sys = 0; - ushort len_sys_cfg = 0; - - /* check identification word */ - eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2); - if (read != EEPROM_IDENT) - return; - - /* calculate offset of config area */ - eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2); - eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG, - (uchar *)&len_sys_cfg, 2); - addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1; - if (addr_of_eth_addr >= EEPROM_LEN) - return; - - eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6); -} - -int misc_init_r(void) -{ - pci_dev_t devbusfn; - uchar enetaddr[6]; - - /* check if graphic extension board is present */ - devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU, - PCI_DEVICE_ID_CORAL_PA, 0); - if (devbusfn != -1) - exbo_hw_init(); - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_IDE - -#ifdef CONFIG_IDE_RESET - -void init_ide_reset(void) -{ - debug ("init_ide_reset\n"); - - /* set gpio output value to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); - /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); - /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); - /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); - -} - -void ide_set_reset(int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - /* set gpio output value to 0 */ - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); - /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); - /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); - /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); - - udelay(10000); - - /* set gpio output value to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); - /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); - /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); - /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); -} -#endif /* CONFIG_IDE_RESET */ -#endif /* CONFIG_IDE */ - -#ifdef CONFIG_OF_BOARD_SETUP -static void ft_delete_node(void *fdt, const char *compat) -{ - int off = -1; - int ret; - - off = fdt_node_offset_by_compatible(fdt, -1, compat); - if (off < 0) { - printf("Could not find %s node.\n", compat); - return; - } - - ret = fdt_del_node(fdt, off); - if (ret < 0) - printf("Could not delete %s node.\n", compat); -} -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -static void ft_adapt_flash_base(void *blob) -{ - flash_info_t *dev = &flash_info[0]; - int off; - struct fdt_property *prop; - int len; - u32 *reg, *reg2; - - off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); - if (off < 0) { - printf("Could not find fsl,mpc5200b-lpb node.\n"); - return; - } - - /* found compatible property */ - prop = fdt_get_property_w(blob, off, "ranges", &len); - if (prop) { - reg = reg2 = (u32 *)&prop->data[0]; - - reg[2] = dev->start[0]; - reg[3] = dev->size; - fdt_setprop(blob, off, "ranges", reg2, len); - } else - printf("Could not find ranges\n"); -} - -extern ulong flash_get_size (phys_addr_t base, int banknum); - -/* Update the Flash Baseaddr settings */ -int update_flash_size (int flash_size) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - flash_info_t *dev; - int i; - int size = 0; - unsigned long base = 0x0; - u32 *cs_reg = (u32 *)&mm->cs0_start; - - for (i = 0; i < 2; i++) { - dev = &flash_info[i]; - - if (dev->size) { - /* calculate new base addr for this chipselect */ - base -= dev->size; - out_be32(cs_reg, START_REG(base)); - cs_reg++; - out_be32(cs_reg, STOP_REG(base, dev->size)); - cs_reg++; - /* recalculate the sectoraddr in the cfi driver */ - size += flash_get_size(base, i); - } - } - flash_protect_default(); - gd->bd->bi_flashstart = base; - return 0; -} -#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ - -int ft_board_setup(void *blob, bd_t *bd) -{ - int phy_addr = CONFIG_PHY_ADDR; - char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; - - ft_cpu_setup(blob, bd); - /* - * There are 2 RTC nodes in the DTS, so remove - * the unneeded node here. - */ -#if defined(CONFIG_DIGSY_REV5) - ft_delete_node(blob, "dallas,ds1339"); -#else - ft_delete_node(blob, "mc,rv3029c2"); -#endif -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE - /* Update reg property in all nor flash nodes too */ - fdt_fixup_nor_flash_size(blob); -#endif - ft_adapt_flash_base(blob); -#endif - /* fix up the phy address */ - do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h deleted file mode 100644 index 17bd034..0000000 --- a/board/intercontrol/digsy_mtc/eeprom.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2009 Semihalf. - * Written by: Grzegorz Bernacki - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef CMD_EEPROM_H -#define CMD_EEPROM_H - -#define EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR -#define EEPROM_LEN 1024 /* eeprom length */ -#define EEPROM_IDENT 2408 /* identification word */ -#define EEPROM_ADDR_IDENT 0 /* identification word offset */ -#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */ -#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */ -#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */ - -#endif diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h deleted file mode 100644 index c555d2d..0000000 --- a/board/intercontrol/digsy_mtc/is42s16800a-7t.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x505F0000 -#define SDRAM_CONFIG1 0xD2322900 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h deleted file mode 100644 index c42ba38..0000000 --- a/board/intercontrol/digsy_mtc/is45s16800a2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * based on: - * (C) Copyright 2004-2009 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x50470000 -#define SDRAM_CONFIG1 0xD2322900 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig deleted file mode 100644 index 34e094d..0000000 --- a/board/ipek01/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_IPEK01 - -config SYS_BOARD - default "ipek01" - -config SYS_CONFIG_NAME - default "ipek01" - -endif diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS deleted file mode 100644 index 906d39e..0000000 --- a/board/ipek01/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IPEK01 BOARD -M: Anatolij Gustschin -S: Maintained -F: board/ipek01/ -F: include/configs/ipek01.h -F: configs/ipek01_defconfig diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile deleted file mode 100644 index a786ab2..0000000 --- a/board/ipek01/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ipek01.o diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c deleted file mode 100644 index 133db8c..0000000 --- a/board/ipek01/ipek01.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * MicroSys GmbH - * - * (C) Copyright 2009 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_OF_LIBFDT -#include -#endif /* CONFIG_OF_LIBFDT */ - -/* mt46v16m16-75 */ -#ifdef CONFIG_MPC5200_DDR -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 -#else -#error SDRAM is not supported on this board -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start (int hi_addr) -{ - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* set mode register: extended mode */ - out_be32 (&sdram->mode, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* auto refresh */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit); - - /* set mode register */ - out_be32 (&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit); -} - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. - */ - -int dram_init(void) -{ - struct mpc5xxx_mmap_ctl *mmap_ctl = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM; - ulong dramsize = 0; - ulong dramsize2 = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */ - out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */ - - /* setup config registers */ - out_be32 (&sdram->config1, SDRAM_CONFIG1); - out_be32 (&sdram->config2, SDRAM_CONFIG2); - - /* set tap delay */ - out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); - - /* find RAM size using SDRAM CS0 only */ - sdram_start (0); - test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start (1); - test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start (0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) - out_be32 (&mmap_ctl->sdram0, - 0x13 + __builtin_ffs (dramsize >> 20) - 1); - else - out_be32 (&mmap_ctl->sdram1, 0); /* disabled */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - out_be32 (&sdram->sdelay, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: IPEK01 \n"); - return 0; -} - -void flash_preinit (void) -{ - struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */ -} - -void flash_afterinit (ulong start, ulong size) -{ - struct mpc5xxx_mmap_ctl *mmap_ctl = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - -#if defined(CONFIG_BOOT_ROM) - /* adjust mapping */ - out_be32 (&mmap_ctl->cs1_start, START_REG (start)); - out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size)); -#else - /* adjust mapping */ - out_be32 (&mmap_ctl->boot_start, START_REG (start)); - out_be32 (&mmap_ctl->cs0_start, START_REG (start)); - out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size)); - out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size)); -#endif -} - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - /* adjust flash start */ - gd->bd->bi_flashstart = flash_info[0].start[0]; - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init (struct pci_controller *); - -void pci_init_board (void) -{ - pci_mpc5xxx_init (&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} - -#ifdef CONFIG_VIDEO -extern GraphicDevice mb862xx; - -static const gdc_regs init_regs[] = { - {0x0100, 0x00000900}, - {0x0020, 0x80190257}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x02570320}, - {0x0004, 0x041f0000}, - {0x0008, 0x031f031f}, - {0x000c, 0x067f0347}, - {0x0010, 0x02780000}, - {0x0014, 0x0257025c}, - {0x0018, 0x00000000}, - {0x001c, 0x02570320}, - {0x0100, 0x80010900}, - {0x0, 0x0} -}; - -const gdc_regs *board_get_regs (void) -{ - return init_regs; -} - -/* Returns Lime base address */ -unsigned int board_video_init (void) -{ - if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME) - return 0; - - mb862xx.winSizeX = 800; - mb862xx.winSizeY = 600; - mb862xx.gdfIndex = GDF_15BIT_555RGB; - mb862xx.gdfBytesPP = 2; - - return CONFIG_SYS_LIME_BASE; -} - -#if defined(CONFIG_CONSOLE_EXTRA_INFO) -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) - strcpy (info, " Board: IPEK01"); - else - info[0] = '\0'; -} -#endif -#endif /* CONFIG_VIDEO */ diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig deleted file mode 100644 index d71acbb..0000000 --- a/board/jupiter/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_JUPITER - -config SYS_BOARD - default "jupiter" - -config SYS_CONFIG_NAME - default "jupiter" - -endif diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS deleted file mode 100644 index 5a79a61..0000000 --- a/board/jupiter/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -JUPITER BOARD -M: Heiko Schocher -S: Maintained -F: board/jupiter/ -F: include/configs/jupiter.h -F: configs/jupiter_defconfig diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile deleted file mode 100644 index 4d3ef9e..0000000 --- a/board/jupiter/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := jupiter.o diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c deleted file mode 100644 index 52d2766..0000000 --- a/board/jupiter/jupiter.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#define SDRAM_DDR 0 -#if 1 -/* Settings Icecube */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 -#else -/*Settings Jupiter UB 1.0.0 */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0xD04F0000 -#define SDRAM_CONFIG1 0xf7277f00 -#define SDRAM_CONFIG2 0x88b70004 -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: Sauter (Jupiter)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -int board_early_init_r (void) -{ - flash_preinit (); - return 0; -} - -void flash_afterinit(ulong size) -{ - if (size == 0x1000000) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -} - -int update_flash_size (int flash_size) -{ - flash_afterinit (flash_size); - return 0; -} - -int board_early_init_f (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/keymile/km82xx/Kconfig b/board/keymile/km82xx/Kconfig deleted file mode 100644 index c9a093c..0000000 --- a/board/keymile/km82xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KM82XX - -config SYS_BOARD - default "km82xx" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "km82xx" - -endif diff --git a/board/keymile/km82xx/MAINTAINERS b/board/keymile/km82xx/MAINTAINERS deleted file mode 100644 index 50e06b2..0000000 --- a/board/keymile/km82xx/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KM82XX BOARD -M: Holger Brunck -S: Maintained -F: board/keymile/km82xx/ -F: include/configs/km82xx.h -F: configs/mgcoge_defconfig -F: configs/mgcoge3ne_defconfig diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile deleted file mode 100644 index 20f193a..0000000 --- a/board/keymile/km82xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := km82xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c deleted file mode 100644 index f5a98b3..0000000 --- a/board/keymile/km82xx/km82xx.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * (C) Copyright 2007 - 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include -#include -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PA31 */ - { 0, 0, 0, 0, 0, 0 }, /* PA30 */ - { 0, 0, 0, 0, 0, 0 }, /* PA29 */ - { 0, 0, 0, 0, 0, 0 }, /* PA28 */ - { 0, 0, 0, 0, 0, 0 }, /* PA27 */ - { 0, 0, 0, 0, 0, 0 }, /* PA26 */ - { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - { 0, 0, 0, 0, 0, 0 }, /* PA21 */ - { 0, 0, 0, 0, 0, 0 }, /* PA20 */ - { 0, 0, 0, 0, 0, 0 }, /* PA19 */ - { 0, 0, 0, 0, 0, 0 }, /* PA18 */ - { 0, 0, 0, 0, 0, 0 }, /* PA17 */ - { 0, 0, 0, 0, 0, 0 }, /* PA16 */ - { 0, 0, 0, 0, 0, 0 }, /* PA15 */ - { 0, 0, 0, 0, 0, 0 }, /* PA14 */ - { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */ - { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */ - { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PB31 */ - { 0, 0, 0, 0, 0, 0 }, /* PB30 */ - { 0, 0, 0, 0, 0, 0 }, /* PB29 */ - { 0, 0, 0, 0, 0, 0 }, /* PB28 */ - { 0, 0, 0, 0, 0, 0 }, /* PB27 */ - { 0, 0, 0, 0, 0, 0 }, /* PB26 */ - { 0, 0, 0, 0, 0, 0 }, /* PB25 */ - { 0, 0, 0, 0, 0, 0 }, /* PB24 */ - { 0, 0, 0, 0, 0, 0 }, /* PB23 */ - { 0, 0, 0, 0, 0, 0 }, /* PB22 */ - { 0, 0, 0, 0, 0, 0 }, /* PB21 */ - { 0, 0, 0, 0, 0, 0 }, /* PB20 */ - { 0, 0, 0, 0, 0, 0 }, /* PB19 */ - { 0, 0, 0, 0, 0, 0 }, /* PB18 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */ - { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */ - { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - { 0, 0, 0, 0, 0, 0 }, /* PC18 */ - { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */ - { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */ - { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */ - { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - { 1, 0, 0, 0, 1, 1 }, /* PD15 */ - { 1, 0, 0, 1, 1, 1 }, /* PD14 */ - { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -/* - * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init(memctl8260_t *memctl, ulong sdmr, - ulong orx, uchar *base) -{ - uchar c = 0xff; - ulong maxsize, size; - int i; - - /* - * We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - out_be32(&memctl->memc_or1, orx); - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address - * CONFIG_SYS_SDRAM_BASE. - */ - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA); - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR); - for (i = 0; i < 8; i++) - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW); - /* setting MR on address lines */ - out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN); - out_8(base, c); - - size = get_ram_size((long *)base, maxsize); - out_be32(&memctl->memc_or1, orx | ~(size - 1)); - - return size; -} - -#ifdef CONFIG_SYS_SDRAM_LIST - -/* - * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM - * configurations therein (should be from high to lower) to find the - * one actually matching the current configuration. - * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are - * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST - * (defined as the initialization value for the array of struct sdram_conf_s) - * will then be ORed with such base values. - */ - -struct sdram_conf_s { - ulong size; - int or1; - int psdmr; -}; - -static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST; - -static long probe_sdram(memctl8260_t *memctl) -{ - int n = 0; - long psize = 0; - - for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) { - psize = try_init(memctl, - CONFIG_SYS_PSDMR | sdram_conf[n].psdmr, - CONFIG_SYS_OR1 | sdram_conf[n].or1, - (uchar *) CONFIG_SYS_SDRAM_BASE); - debug("Probing %ld bytes returned %ld\n", - sdram_conf[n].size, psize); - if (psize == sdram_conf[n].size) - break; - } - return psize; -} - -#else /* CONFIG_SYS_SDRAM_LIST */ - -static long probe_sdram(memctl8260_t *memctl) -{ - return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, - (uchar *) CONFIG_SYS_SDRAM_BASE); -} -#endif /* CONFIG_SYS_SDRAM_LIST */ - - -int dram_init(void) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - - /* 60x SDRAM setup: - */ - psize = probe_sdram(memctl); - - icache_enable(); - - gd->ram_size = psize; - - return 0; -} - -int checkboard(void) -{ -#if defined(CONFIG_MGCOGE) - puts("Board: Keymile mgcoge"); -#else - puts("Board: Keymile mgcoge3ne"); -#endif - if (ethernet_present()) - puts(" with PIGGY."); - puts("\n"); - return 0; -} - -int last_stage_init(void) -{ - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE; - u8 dip_switch; - - dip_switch = in_8(&base->mswitch); - dip_switch &= BFTICU_DIPSWITCH_MASK; - /* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */ - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } - set_km_env(); - return 0; -} - -#ifdef CONFIG_MGCOGE3NE -static void set_pin(int state, unsigned long mask, int port); - -/* - * For mgcoge3ne boards, the mgcoge3un control is controlled from - * a GPIO line on the PPC CPU. If bobcatreset is set the line - * will toggle once what forces the mgocge3un part to restart - * immediately. - */ -static void handle_mgcoge3un_reset(void) -{ - char *bobcatreset = getenv("bobcatreset"); - if (bobcatreset) { - if (strcmp(bobcatreset, "true") == 0) { - puts("Forcing bobcat reset\n"); - set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */ - udelay(1000); - set_pin(1, 0x00000004, 3); - } else - set_pin(1, 0x00000004, 3); /* don't reset arm */ - } -} -#endif - -int ethernet_present(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - return in_8(&base->bprth) & PIGGY_PRESENT; -} - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - /* setup the UPIOx */ - /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ - out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED)); - /* SCC4 enable, halfduplex, FCC1 powerdown */ - out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | - H_OPORTS_FCC1_PW_DWN)); - -#ifdef CONFIG_MGCOGE3NE - handle_mgcoge3un_reset(); -#endif - return 0; -} - -int misc_init_r(void) -{ - ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} - -int hush_init_var(void) -{ - ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} - -#define SDA_MASK 0x00010000 -#define SCL_MASK 0x00020000 - -static void set_pin(int state, unsigned long mask, int port) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); - - if (state) - setbits_be32(&iop->pdat, mask); - else - clrbits_be32(&iop->pdat, mask); - - setbits_be32(&iop->pdir, mask); -} - -static int get_pin(unsigned long mask, int port) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); - - clrbits_be32(&iop->pdir, mask); - return 0 != (in_be32(&iop->pdat) & mask); -} - -void set_sda(int state) -{ - set_pin(state, SDA_MASK, 3); -} - -void set_scl(int state) -{ - set_pin(state, SCL_MASK, 3); -} - -int get_sda(void) -{ - return get_pin(SDA_MASK, 3); -} - -int get_scl(void) -{ - return get_pin(SCL_MASK, 3); -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} - -#if defined(CONFIG_MGCOGE3NE) -int get_testpin(void) -{ - /* Testpin is Port C pin 29 - enable = low */ - int testpin = !get_pin(0x00000004, 2); - return testpin; -} -#endif diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c index 0ad33ea..2653439 100644 --- a/board/lego/ev3/legoev3.c +++ b/board/lego/ev3/legoev3.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #ifdef CONFIG_MMC_DAVINCI #include diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c index 5eb2ad7..09ec247 100644 --- a/board/mini-box/picosam9g45/picosam9g45.c +++ b/board/mini-box/picosam9g45/picosam9g45.c @@ -27,6 +27,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig deleted file mode 100644 index f624f6c..0000000 --- a/board/motionpro/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MOTIONPRO - -config SYS_BOARD - default "motionpro" - -config SYS_CONFIG_NAME - default "motionpro" - -endif diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS deleted file mode 100644 index 2f8b5cb..0000000 --- a/board/motionpro/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MOTIONPRO BOARD -#M: - -S: Maintained -F: board/motionpro/ -F: include/configs/motionpro.h -F: configs/motionpro_defconfig diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile deleted file mode 100644 index 898a384..0000000 --- a/board/motionpro/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := motionpro.o diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c deleted file mode 100644 index 7883a17..0000000 --- a/board/motionpro/motionpro.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for Promess PRO - by Andy Joseph, andy@promessdev.com - * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com - * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3 - * Also changed the refresh for 100MHz operation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#if defined(CONFIG_LED_STATUS) -#include -#endif /* CONFIG_LED_STATUS */ - -DECLARE_GLOBAL_DATA_PTR; - -/* Kollmorgen DPR initialization data */ -struct init_elem { - unsigned long addr; - unsigned len; - char *data; - } init_seq[] = { - {0x500003F2, 2, "\x86\x00"}, /* HW parameter */ - {0x500003F0, 2, "\x00\x00"}, - {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */ - }; - -/* - * Initialize Kollmorgen DPR - */ -static void kollmorgen_init(void) -{ - unsigned i, j; - vu_char *p; - - for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) { - p = (vu_char *)init_seq[i].addr; - for (j = 0; j < init_seq[i].len; ++j) - *(p + j) = *(init_seq[i].data + j); - } - - printf("DPR: Kollmorgen DPR initialized\n"); -} - - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); - - /* Initialize Kollmorgen DPR */ - kollmorgen_init(); - - return 0; -} - - -/* - * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(), - * PHY goes into FX mode. To take it out of the FX mode and switch into - * desired TX operation, one needs to clear the FX_SEL bit of Mode Control - * Register. - */ -void reset_phy(void) -{ - unsigned short mode_control; - - miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control); - miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15, - mode_control & 0xfffe); - return; -} - -#ifndef CONFIG_SYS_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; -} -#endif /* !CONFIG_SYS_RAMBOOT */ - - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -int dram_init(void) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* According to AN3221 (MPC5200B SDRAM Initialization and - * Configuration), the SDelay register must be written a value of - * 0x00000004 as the first step of the SDRAM contorller configuration. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 and disable it */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; - -#else /* !CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* return total ram size */ - gd->ram_size = dramsize; - - return 0; -} - - -int checkboard(void) -{ - uchar rev = *(vu_char *)CPLD_REV_REGISTER; - printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev); - return 0; -} - - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - - -#if defined(CONFIG_LED_STATUS) -vu_long *regcode_to_regaddr(led_id_t regcode) -{ - /* GPT Enable and Mode Select Register address */ - vu_long *reg_translate[] = { - (vu_long *)MPC5XXX_GPT6_ENABLE, - (vu_long *)MPC5XXX_GPT7_ENABLE, - }; - - if (ARRAY_SIZE(reg_translate) <= regcode) - return NULL; - return reg_translate[regcode]; -} - -void __led_init(led_id_t regcode, int state) -{ - vu_long *regaddr = regcode_to_regaddr(regcode); - - *regaddr |= ENABLE_GPIO_OUT; - - if (state == CONFIG_LED_STATUS_ON) - *((vu_long *) regaddr) |= LED_ON; - else - *((vu_long *) regaddr) &= ~LED_ON; -} - -void __led_set(led_id_t regcode, int state) -{ - vu_long *regaddr = regcode_to_regaddr(regcode); - - if (state == CONFIG_LED_STATUS_ON) - *regaddr |= LED_ON; - else - *regaddr &= ~LED_ON; -} - -void __led_toggle(led_id_t regcode) -{ - vu_long *regaddr = regcode_to_regaddr(regcode); - - *regaddr ^= LED_ON; -} -#endif /* CONFIG_LED_STATUS */ diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 5ea5a51..31636b3 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -28,10 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_PATI) -#define FIRM_START 0xFFF00000 -#endif - extern int mem_test(ulong start, ulong ramsize, int quiet); #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ @@ -189,11 +185,8 @@ mpl_prg(uchar *src, ulong size) ulong start; flash_info_t *info = &flash_info[0]; int i, rc; -#if defined(CONFIG_PATI) - int start_sect; -#endif -#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ - || defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI) +#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \ + defined(CONFIG_TARGET_MIP405T) char *copystr = (char *)src; ulong *magic = (ulong *)src; @@ -219,7 +212,6 @@ mpl_prg(uchar *src, ulong size) printf("Wrong Firmware Image: %s\n", ©str[i]); return -1; } -#if !defined(CONFIG_PATI) start = 0 - size; /* unprotect sectors used by u-boot */ @@ -241,38 +233,6 @@ mpl_prg(uchar *src, ulong size) flash_perror(rc); return (1); } - -#else /* #if !defined(CONFIG_PATI) */ - start = FIRM_START; - start_sect = -1; - - /* search start sector */ - for (i = info->sector_count-1; i > 0; i--) - if (start >= info->start[i]) - break; - - start_sect = i; - - for (i = info->sector_count-1; i > 0; i--) - if ((start + size) >= info->start[i]) - break; - - /* unprotect sectors used by u-boot */ - flash_protect(FLAG_PROTECT_CLEAR, - start, - start + size, - info); - - /* now erase flash */ - printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", - start, start + size, start_sect, i, - info->start[start_sect], info->start[i]); - if ((rc = flash_erase (info, start_sect, i)) != 0) { - puts ("ERROR "); - flash_perror (rc); - return (1); - } -#endif /* defined(CONFIG_PATI) */ #endif printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", (ulong)src, size); @@ -380,7 +340,6 @@ mpl_prg_image(uchar *ld_addr) return(rc); } -#if !defined(CONFIG_PATI) void get_backup_values(backup_t *buf) { i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); @@ -541,17 +500,13 @@ void check_env(void) } } -#endif /* #if !defined(CONFIG_PATI) */ - int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong ld_addr; int result; -#if !defined(CONFIG_PATI) ulong size = IMAGE_SIZE; ulong src = MULTI_PURPOSE_SOCKET_ADDR; backup_t back; -#endif if (strcmp(argv[1], "flash") == 0) { @@ -587,15 +542,12 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) result=mpl_prg_image((uchar *)ld_addr); return result; } -#if !defined(CONFIG_PATI) if (strcmp(argv[2], "mps") == 0) { puts("\nupdating bootloader image from MPS\n"); result=mpl_prg((uchar *)src,size); return result; } -#endif /* #if !defined(CONFIG_PATI) */ } -#if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { if (strcmp(argv[2], "yes") == 0) @@ -618,7 +570,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) set_backup_values(1); return 0; } -#endif return cmd_usage(cmdtp); } diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index cd969cb..ad97ffa 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -20,26 +20,35 @@ DECLARE_GLOBAL_DATA_PTR; #include "piix4_pci.h" #include "pci_parts.h" +void pci_405gp_init(struct pci_controller *hose); + void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) + struct pci_config_table *entry) { struct pci_pip405_config_entry *table; int i; - table = (struct pci_pip405_config_entry*) entry->priv[0]; + table = (struct pci_pip405_config_entry *)entry->priv[0]; - for (i=0; table[i].width; i++) - { + for (i = 0; table[i].width; i++) { #ifdef DEBUG printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", table[i].index, table[i].val, table[i].width); #endif - switch(table[i].width) - { - case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; - case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; - case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; + switch (table[i].width) { + case 1: + pci_hose_write_config_byte(hose, dev, + table[i].index, table[i].val); + break; + case 2: + pci_hose_write_config_word(hose, dev, + table[i].index, table[i].val); + break; + case 4: + pci_hose_write_config_dword(hose, dev, + table[i].index, table[i].val); + break; } } } @@ -52,26 +61,24 @@ static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) /* * Write pci interrupt line register */ - if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ + if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */ return; pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); if ((pin == 0) || (pin > 4)) - return; + return; int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); #ifdef DEBUG printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", - PCI_DEV(dev),dev,int_line,int_line); + PCI_DEV(dev), dev, int_line, int_line); #endif } -extern void pci_405gp_init(struct pci_controller *hose); - static struct pci_controller hose = { - config_table: pci_pip405_config_table, - fixup_irq: pci_pip405_fixup_irq, +config_table: pci_pip405_config_table, +fixup_irq : pci_pip405_fixup_irq, }; @@ -81,7 +88,8 @@ void pci_init_board(void) hose.fixup_irq = pci_pip405_fixup_irq; hose.config_table = pci_pip405_config_table; #ifdef DEBUG - printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); + printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n", + pci_pip405_fixup_irq, pci_pip405_config_table, hose); #endif pci_405gp_init(&hose); } diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig deleted file mode 100644 index 0eeaf70..0000000 --- a/board/mpl/pati/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PATI - -config SYS_BOARD - default "pati" - -config SYS_VENDOR - default "mpl" - -config SYS_CONFIG_NAME - default "PATI" - -config ISO_STRING - string - default "MEV-10084-001" -endif diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS deleted file mode 100644 index 19ad05d..0000000 --- a/board/mpl/pati/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PATI BOARD -#M: - -S: Maintained -F: board/mpl/pati/ -F: include/configs/PATI.h -F: configs/PATI_defconfig diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile deleted file mode 100644 index 9822082..0000000 --- a/board/mpl/pati/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pati.o cmd_pati.o \ - ../common/common_util.o diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c deleted file mode 100644 index fcae5e0..0000000 --- a/board/mpl/pati/cmd_pati.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Adapted for PATI - */ - -#include -#include -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" -#include "pci_eeprom.h" - -extern void show_pld_regs(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -extern void user_led0(int led_on); -extern void user_led1(int led_on); - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_SYS_PCI_CON_DEVICE) -extern void pci_con_disc(void); -extern void pci_con_connect(void); -#endif - -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -unsigned long get32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void set32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE)) -#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y))) - - -/****************************************************************************** - * reload_pci_eeprom - ******************************************************************************/ - -static void reload_pci_eeprom(void) -{ - unsigned long reg; - /* Set Bit 29 and clear it again */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set it*/ - reg|=(1<<29); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* EECLK @ 33MHz = 125kHz - * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec - * use 20msec - */ - udelay(20000); /* wait 20ms */ - reg &= ~(1<<29); /* set it low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * clock_pci_eeprom - ******************************************************************************/ - -static void clock_pci_eeprom(void) -{ - unsigned long reg; - /* clock is low, data is valid */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set clck high */ - reg|=(1<<24); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - reg &= ~(1<<24); /* set clock low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * send_pci_eeprom_cmd - ******************************************************************************/ -static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) -{ - unsigned long reg; - int i; - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* Send EEPROM command - one bit at a time */ - for (i = (int)(len-1); i >= 0; i--) { - /* Check if current bit is 0 or 1 */ - if (cmd & (1 << i)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - clock_pci_eeprom(); - } -} - -/****************************************************************************** - * write_pci_eeprom_offs - ******************************************************************************/ -static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen, timeout; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send Write_Enable command to EEPROM */ - send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen); - /* Send EEPROM Write command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Make sure EEDO Input is disabled for some PLX chips */ - reg &= ~(1 << 31); - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - /* Write 16-bit value to EEPROM - one bit at a time */ - for (bitpos = 15; bitpos >= 0; bitpos--) { - /* Get bit value and shift into result */ - if (value & (1 << bitpos)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg ); - clock_pci_eeprom(); - } /* for */ - /* Deselect Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); - /* Re-select Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); - /* A small delay is needed to let EEPROM complete */ - timeout = 0; - do { - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - timeout++; - } while (((reg & (1 << 27)) == 0) && timeout < 20000); - /* Send Write_Disable command to EEPROM */ - send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * read_pci_eeprom_offs - ******************************************************************************/ -static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send EEPROM read command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen); - /* Set EEPROM write output bit */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Set EEDO Input enable */ - reg |= (1 << 31); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); - /* Get 16-bit value from EEPROM - one bit at a time */ - for (bitpos = 0; bitpos < 16; bitpos++) { - clock_pci_eeprom(); - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Get bit value and shift into result */ - if (reg & (1 << 27)) - *pvalue = (unsigned short)((*pvalue << 1) | 1); - else - *pvalue = (unsigned short)(*pvalue << 1); - } - /* Clear EEDO Input enable */ - reg &= ~(1 << 31); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * EEPROM read/writes -******************************************************************************/ - -#undef EEPROM_DBG -static int pati_pci_eeprom_erase(void) -{ - int i; - printf("Erasing EEPROM "); - for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) { - write_pci_eeprom_offs(i,0xffff); - if((i%0x10)) - printf("."); - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_prg(void) -{ - int i; - i=0; - printf("Programming EEPROM "); - while(pati_eeprom[i].offset<0xffff) { - write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value); - #else - if((i%0x10)) - printf("."); - #endif - i++; - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2); - for( i = offset; i< (offset + size); i+=2) { - value = *buffer++; - write_pci_eeprom_offs(i,value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value = 0; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2); - for( i = offset; i< (offset + size); i+=2) { - read_pci_eeprom_offs(i,&value); - *buffer++=value; - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -/****************************************************************************** - * PCI Bridge Registers Dump -*******************************************************************************/ -static void display_pci_regs(void) -{ - printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE)); - printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP)); - printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT)); - printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC)); - printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE)); - printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP)); - printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC)); - printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE)); - printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE)); - printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE)); - printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP)); - printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG)); - printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE)); - printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP)); - printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC)); - printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC)); - printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0)); - printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1)); - printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2)); - printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3)); - printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4)); - printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5)); - printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6)); - printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7)); - printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL)); - printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL)); - printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT)); - printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT)); - printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID)); - printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID)); - printf(" \n"); - printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID)); - printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND)); - printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION)); - printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE)); - printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE)); - printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE)); - printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0)); - printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1)); - printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1)); - printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2)); - printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR)); - printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID)); - printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE)); - printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR)); - printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE)); - printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID)); - printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR)); - printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID)); - printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID)); - printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA)); -} - - -int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (strcmp(argv[1], "info") == 0) - { - show_pld_regs(); - return 0; - } - if (strcmp(argv[1], "pci") == 0) - { - display_pci_regs(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - int led_nr,led_on; - led_nr = (int)simple_strtoul(argv[2], NULL, 10); - led_on = (int)simple_strtoul(argv[3], NULL, 10); - if(!led_nr) - user_led0(led_on); - else - user_led1(led_on); - return 0; - } -#if defined(CONFIG_SYS_PCI_CON_DEVICE) - if (strcmp(argv[1], "con") == 0) { - pci_con_connect(); - return 0; - } - if (strcmp(argv[1], "disc") == 0) { - pci_con_disc(); - return 0; - } -#endif - if (strcmp(argv[1], "eeprom") == 0) { - unsigned long addr; - int size, offset; - offset = 0; - size = PATI_EEPROM_LAST_OFFSET; - if(argc>2) { - if(argc>3) { - addr = simple_strtoul(argv[3], NULL, 16); - if(argc>4) - offset = (int) simple_strtoul(argv[4], NULL, 16); - if(argc>5) - size = (int) simple_strtoul(argv[5], NULL, 16); - if (strcmp(argv[2], "read") == 0) { - return (pati_pci_eeprom_read(offset, addr, size)); - } - if (strcmp(argv[2], "write") == 0) { - return (pati_pci_eeprom_write(offset, addr, size)); - } - } - if (strcmp(argv[2], "prg") == 0) { - return (pati_pci_eeprom_prg()); - } - if (strcmp(argv[2], "era") == 0) { - return (pati_pci_eeprom_erase()); - } - if (strcmp(argv[2], "reload") == 0) { - reload_pci_eeprom(); - return 0; - } - - - } - } - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} - -U_BOOT_CMD( - pati, 8, 1, do_pati, - "PATI specific Cmds", - "info - displays board information\n" - "pati pci - displays PCI registers\n" - "pati led \n" - " - switch LED \n" - "pati flash mem [SrcAddr]\n" - " - updates U-Boot with image in memory\n" - "pati eeprom - PCI EEPROM sub-system\n" - " read \n" - " - read PCI EEPROM to from words\n" - " write \n" - " - write PCI EEPROM from to words\n" - " prg - programm PCI EEPROM with default values\n" - " era - erase PCI EEPROM (write all word to 0xffff)\n" - " reload- Reload PCI Bridge with EEPROM Values\n" - " NOTE: must start on word boundary\n" - " and must be even byte values" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c deleted file mode 100644 index 1288f74..0000000 --- a/board/mpl/pati/pati.c +++ /dev/null @@ -1,610 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * Atapted for PATI - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************************** - * Bits for the SDRAM controller - * ----------------------------- - * - * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on - * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM - * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3). - * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default) - * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns. - * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns. - * If set to 1 tWR must be equal or less 50ns. - * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less - * 25ns. If set to 1 tRP must be equal or less 50ns. - * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal - * or less 75ns. If set to 1 tRC must be equal or less 100ns. - * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM - * is the Load Mode Register Command. - * IIP: Init in progress. Set to 1 for starting the init sequence - * (Precharge All). As long this bit is set, the Precharge All is still in progress. - * After command has completed, wait at least for 8 refresh (200usec) before proceed. - **********************************************************************************/ - -#include -#include -#include -#include -#include -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -#undef SDRAM_DEBUG -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - - -DECLARE_GLOBAL_DATA_PTR; - -/************************************************************************ - * Early debug routines - */ -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -#if defined(SDRAM_DEBUG) - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - -unsigned long in32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void out32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -typedef struct { - unsigned short boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */ - unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/ - unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */ - unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */ - unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */ - unsigned char sz; /* log binary => Size = (4MByte< Size 2 = 16MByte, 1=8 */ - }, - { 0xffff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; - - -extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); - -/* - * Get RAM size. - */ -int dram_init(void) -{ - unsigned char board_rev; - unsigned long reg; - unsigned long lmr; - int i,timeout; - -#if defined(SDRAM_DEBUG) - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg)); - puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg)); - puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg)); - puts(" Vers 0x"); write_4hex(SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg)); - putc('\n'); -#endif - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - board_rev=(unsigned char)(SYSCNTR_BREV(reg)); - i=0; - while(1) { - if(sdram_table[i].boardtype==0xffff) { - puts("ERROR, found no table for Board 0x"); - write_hex(board_rev); - while(1); - } - if(sdram_table[i].boardtype==(unsigned char)board_rev) - break; - i++; - } - /* Set CAL, RCD, WREQ, PR and RC Bits */ -#if defined(SDRAM_DEBUG) - puts("Set CAL, RCD, WREQ, PR and RC Bits\n"); -#endif - /* mask bits */ - reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) | - SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) | - SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0)); - /* set bits */ - reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) | - SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) | - SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) | - SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) | - SET_REG_BIT(sdram_table[i].rc,SDRAM_RC)); - - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - /* step 2 set IIP */ -#if defined(SDRAM_DEBUG) - puts("step 2 set IIP\n"); -#endif - /* step 2 set IIP */ - reg |= SET_REG_BIT(1,SDRAM_IIP); - timeout=0; - while (timeout!=0xffff) { - __asm__ volatile("eieio"); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - if((reg & SET_REG_BIT(1,SDRAM_IIP))==0) - break; - timeout++; - udelay(1); - } - /* wait for at least 8 refresh */ - udelay(1000); - /* set LMR */ - reg |= SET_REG_BIT(1,SDRAM_LMR); - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - __asm__ volatile("eieio"); - lmr=0x00000002; /* sequential burst 4 data */ - if(sdram_table[i].cal==1) - lmr|=0x00000030; /* cal = 3 */ - else - lmr|=0000000020; /* cal = 2 */ - /* rest standard operation programmed write burst length */ - /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ - lmr<<=2; - in32(CONFIG_SYS_SDRAM_BASE + lmr); - /* ok, we're done, set SDRAM size to log2 value of 4MByte*/ - gd->ram_size = 0x400000 << sdram_table[i].sz; - - return 0; -} - - -void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp) -{ - unsigned long reg; - reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE); - reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_WP)); - - reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) | - SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) | - SET_REG_BIT(ext_wp,SYSCNTR_FL_WP)); - out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg); - udelay(100); -} - - -void show_pld_regs(void) -{ - unsigned long reg,reg1; - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg)); - printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A')); - printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg)); - printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n", - GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD), - GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR), - GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR), - GET_REG_BIT(reg,SDRAM_IIP)); - reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1); - reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2); - printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n", - GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP), - GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM), - GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg), - GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM)); - printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg), - GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN), - GET_SYSCNTR_CFG(reg1)); - printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n", - GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP), - GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP)); -} - - -/**************************************************************** - * Setting IOs - * ----------- - * GPIO6 is User LED1 - * GPIO7 is Interrupt PLX (Output) - * GPIO5 is User LED0 - * GPIO2 is PLX USERi (Output) - * GPIO1 is PLX Interrupt (Input) - ****************************************************************/ - void init_ios(void) - { - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiocr; /* Data direction register */ - reg &= ~0x67000000; - reg |= 0x27000000; /* set outpupts */ - sysconf->sc_sgpiocr=reg; /* Data direction register */ - reg=sysconf->sc_sgpiodt2; /* Data register */ - /* set output to 0 */ - reg &= ~0x27000000; - /* set IRQ and USERi to 1 */ - reg |= 0x28000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led0(int led_on) -{ - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x04000000; - else - reg &= ~0x04000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led1(int led_on) -{ - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x02000000; - else - reg &= ~0x02000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -int board_early_init_f(void) -{ - spi_init_f(); - return 0; -} - -/**************************************************************** - * Last Stage Init - ****************************************************************/ -int last_stage_init (void) -{ - init_ios(); - return 0; -} - -/**************************************************************** - * Check the board - ****************************************************************/ - -#define BOARD_NAME "PATI" - -int checkboard (void) -{ - char s[50]; - ulong reg; - char rev; - int i; - - puts ("\nBoard: "); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - rev=(char)(SYSCNTR_BREV(reg)+'A'); - i = getenv_f("serial#", s, 32); - if ((i == -1)) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf(" Rev. %c\n",rev); - } - else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-1 Rev %c SN: %s\n", s,rev, - &s[sizeof(BOARD_NAME)]); - } - set_flash_vpp(1,0,0); /* set Flash VPP */ - return 0; -} - - -#ifdef CONFIG_SYS_PCI_CON_DEVICE -/************************************************************************ - * PCI Communication - * - * Alive (Pinging): - * ---------------- - * PCI Host sends message ALIVE, Local acknowledges with ALIVE - * - * PCI_CON console over PCI: - * ------------------------- - * Local side: - * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX1 to send data - * - uses PCI9056_MAILBOX0 to receive data - * PCI side: - * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX0 to send data - * - uses PCI9056_MAILBOX1 to receive data - * - * How it works: - * Send: - * - check if PCICON_TRANSMIT_REG is empty - * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG - * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data - * is waiting - * Receive: - * - get an interrupt via the PCICON_ACK_REG register message - * PCIMSG_CONN - * - write the data from the PCICON_RECEIVE_REG into the receive - * buffer and if the receive buffer is not full, clear the - * PCICON_RECEIVE_REG (this allows the counterpart to write more data) - * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG - * - * The PCICON_RECEIVE_REG must be cleared by the routine which reads - * the receive buffer if the buffer is not full any more - * - */ - -#undef PCI_CON_DEBUG - -#ifdef PCI_CON_DEBUG -#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args) -#else -#define PCI_CON_PRINTF(fmt,args...) -#endif - - -/********************************************************* - * we work only with a receive buffer on eiter side. - * Transmit buffer is free, if mailbox is cleared. - * Transmit character is or'ed with 0x80000000 - * PATI receive register MAILBOX0 - * PATI transmit register MAILBOX1 - *********************************************************/ -#define PCICON_RECEIVE_REG PCI9056_MAILBOX0 -#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1 -#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL -#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL - - -#define PCIMSG_ALIVE 0x1 -#define PCIMSG_CONN 0x2 -#define PCIMSG_DISC 0x3 -#define PCIMSG_CON_DATA 0x5 - - -#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE)) -#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y)) -#define PCICON_TX_FLAG 0x80000000 - - -#define REC_BUFFER_SIZE 0x100 -int recbuf[REC_BUFFER_SIZE]; -static int r_ptr = 0; -int w_ptr; -struct stdio_dev pci_con_dev; -int conn=0; -int buff_full=0; - -void pci_con_put_it(const char c) -{ - /* Test for completition */ - unsigned long reg; - do { - reg=PCICON_GET_REG(PCICON_TRANSMIT_REG); - }while(reg); - reg=PCICON_TX_FLAG + c; - PCICON_SET_REG(PCICON_TRANSMIT_REG,reg); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); -} - -void pci_con_putc(struct stdio_dev *dev, const char c) -{ - pci_con_put_it(c); - if(c == '\n') - pci_con_put_it('\r'); -} - - -int pci_con_getc(struct stdio_dev *dev) -{ - int res; - int diff; - while(r_ptr==(volatile int)w_ptr); - res=recbuf[r_ptr++]; - if(r_ptr==REC_BUFFER_SIZE) - r_ptr=0; - if(w_ptr(REC_BUFFER_SIZE-4)) - buff_full=1; - else - /* clear Mail box */ - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - break; - default: - serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg); - } - /* clear IRQ */ - PCICON_SET_REG(PCICON_ACK_REG,~0L); - } - return 0; -} - -void pci_con_connect(void) -{ - unsigned long reg; - conn=0; - reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); - /* default 0x0f010180 */ - reg &= 0xff000000; - reg |= 0x00030000; /* enable local dorbell */ - reg |= 0x00000300; /* enable PCI dorbell */ - PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg); - irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); - memset (&pci_con_dev, 0, sizeof (pci_con_dev)); - strcpy (pci_con_dev.name, "pci_con"); - pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; - pci_con_dev.putc = pci_con_putc; - pci_con_dev.puts = pci_con_puts; - pci_con_dev.getc = pci_con_getc; - pci_con_dev.tstc = pci_con_tstc; - stdio_register (&pci_con_dev); - printf("PATI ready for PCI connection, type ctrl-c for exit\n"); - do { - udelay(10); - if((volatile int)conn) - break; - if(ctrlc()) { - irq_free_handler(0x2); - return; - } - }while(1); - console_assign(stdin,"pci_con"); - console_assign(stderr,"pci_con"); - console_assign(stdout,"pci_con"); -} - -void pci_con_disc(void) -{ - console_assign(stdin,"serial"); - console_assign(stderr,"serial"); - console_assign(stdout,"serial"); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC); - /* reconnection */ - irq_free_handler(0x02); - pci_con_connect(); -} -#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */ - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h deleted file mode 100644 index 93a5918..0000000 --- a/board/mpl/pati/pati.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ -/************************************************************************ - * MACROS and register definitions for PATI Registers - ************************************************************************/ -#ifndef __PATI_H_ -#define __PATI_H_ 1 - -#define PLD_PART_ID 0x0 -#define PLD_BOARD_TIMING 0x4 -#define PLD_CONF_REG1 0x8 -#define PLD_CONF_REG2 0xC -#define PLD_CONF_RES 0x10 - -#define SET_REG_BIT(y,x) (y<<(31-x)) -#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L) - -/* SDRAM Controller PLD_PART_ID */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_PART3 9 -#define SDRAM_PART2 10 -#define SDRAM_PART1 11 -#define SDRAM_PART0 12 -#define SDRAM_ID3 13 -#define SDRAM_ID2 14 -#define SDRAM_ID1 19 -#define SDRAM_ID0 31 - -#define SDRAM_PART(x) ( \ - (GET_REG_BIT(x,SDRAM_PART3)<<3) |\ - (GET_REG_BIT(x,SDRAM_PART2)<<2) |\ - (GET_REG_BIT(x,SDRAM_PART1)<<1) |\ - (GET_REG_BIT(x,SDRAM_PART0))) - -#define SDRAM_ID(x) ( \ - (GET_REG_BIT(x,SDRAM_ID3)<<3) |\ - (GET_REG_BIT(x,SDRAM_ID2)<<2) |\ - (GET_REG_BIT(x,SDRAM_ID1)<<1) |\ - (GET_REG_BIT(x,SDRAM_ID0))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_PART4 0 -#define SYSCNTR_PART3 1 -#define SYSCNTR_PART2 3 -#define SYSCNTR_PART1 4 -#define SYSCNTR_PART0 5 -#define SYSCNTR_ID4 16 -#define SYSCNTR_ID3 20 -#define SYSCNTR_ID2 28 -#define SYSCNTR_ID1 29 -#define SYSCNTR_ID0 30 - -#define SYSCNTR_PART(x) ( \ - (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_PART0))) - -#define SYSCNTR_ID(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_ID0))) - -/* SDRAM Controller PLD_BOARD_TIMING */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_CAL 9 -#define SDRAM_RCD 10 -#define SDRAM_WREQ 11 -#define SDRAM_PR 12 -#define SDRAM_RC 13 -#define SDRAM_LMR 14 -#define SDRAM_IIP 19 -#define SDRAM_RES0 31 -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BREV0 0 -#define SYSCNTR_BREV1 1 -#define SYSCNTR_BREV2 3 -#define SYSCNTR_BREV3 4 -#define SYSCNTR_RES0 5 -#define SYSCNTR_RES1 16 -#define SYSCNTR_RES2 20 -#define SYSCNTR_FLWAIT2 28 -#define SYSCNTR_FLWAIT1 29 -#define SYSCNTR_FLWAIT0 30 - -#define SYSCNTR_BREV(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BREV0))) - -#define GET_SYSCNTR_FLWAIT(x) ( \ - (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT0))) - -#define SET_SYSCNTR_FLWAIT(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0))) - -/* SDRAM Controller REG 2*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_MUX0 9 -#define SDRAM_MUX1 10 -#define SDRAM_PDIS 11 -#define SDRAM_RES1 12 -#define SDRAM_RES2 13 -#define SDRAM_RES3 14 -#define SDRAM_RES4 19 -#define SDRAM_RIP 31 - -#define GET_SDRAM_MUX(x) ( \ - (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \ - (GET_REG_BIT(x,SDRAM_MUX0))) - - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_FLAG 0 -#define SYSCNTR_IP 1 -#define SYSCNTR_BIND2 3 -#define SYSCNTR_BIND1 4 -#define SYSCNTR_BIND0 5 -#define SYSCNTR_PRM 16 -#define SYSCNTR_ICW 20 -#define SYSCNTR_ISB2 28 -#define SYSCNTR_ISB1 29 -#define SYSCNTR_ISB0 30 - -#define GET_SYSCNTR_BOOTIND(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BIND0))) - -#define SET_SYSCNTR_BOOTIND(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0))) - -#define GET_SYSCNTR_ISB(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_ISB0))) - -#define SET_SYSCNTR_ISB(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0))) - -/* SDRAM Controller REG 3*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_RES5 9 -#define SDRAM_CFG1 10 -#define SDRAM_CFG2 11 -#define SDRAM_CFG3 12 -#define SDRAM_RES6 13 -#define SDRAM_CFG5 14 -#define SDRAM_CFG6 19 -#define SDRAM_RES7 31 - -#define GET_SDRAM_CFG(x) ( \ - (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\ - (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\ - (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\ - (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\ - (GET_REG_BIT(x,SDRAM_CFG1))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BDIS 0 -#define SYSCNTR_PCIM 1 -#define SYSCNTR_CFG0 3 -#define SYSCNTR_CFG1 4 -#define SYSCNTR_CFG2 5 -#define SYSCNTR_CFG3 16 -#define SYSCNTR_BOOTEN 20 -#define SYSCNTR_CPU_VPP 28 -#define SYSCNTR_FL_VPP 29 -#define SYSCNTR_FL_WP 30 - -#define GET_SYSCNTR_CFG(x) ( \ - (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \ - (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_CFG0))) - - -/*************************************************************** - * MISC Defines - ***************************************************************/ - -#define PCI_VENDOR_ID_MPL 0x18E6 -#define PCI_DEVICE_ID_PATI 0x00DA - -#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T) -#define PATI_FIRMWARE_START_OFFSET 0x00300000 -#endif - -#define PATI_ENDIAN_MODE 0x3E - -/******************************************* - * PATI Mapping: - * ------------- - * PCI Map: - * ------- - * All addreses are mapped into the memory area - * (IO Area on some areas may also be possible) - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configurable - * - pci_space1_addr configurable - * - * Local Map: - * ---------- - * Local addresses (Remap) - * - SDRAM 0x06000000 Size 16MByte mask 0xff000000 - * - EPLD CFG 0x07000000 Size 512Bytes - * - FLASH 0x03000000 Size up to 8MByte - * - CPU 0x01000000 Size 4MByte (only accessable if special configured) - * - * Implemention: - * ------------- - * To prevent using large resources reservation on the host following - * PCI mapping is choosed: - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes - * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this - * space is used to switch between SDRAM, Flash and CPU - * - */ - -/* Attribute definitions */ -#define PATI_BUS_SIZE_8 0 -#define PATI_BUS_SIZE_16 1 -#define PATI_BUS_SIZE_32 3 - -#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */ -#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */ - -#define PATI_EXTRA_LONG_EEPROM 1 - -#define SPACE0_TA_ENABLE (1<<6) -#define SPACE1_TA_ENABLE (1<<6) - -/* Config Area */ -#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ -#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ -/* Attributes */ -#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CFG_BURST 0 /* No Burst */ -#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ - -#define PATI_LOC_CFG_SPACE0_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 8) | \ - (PATI_LOC_CFG_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -/* should never be used */ -#define PATI_LOC_CFG_SPACE1_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 9) | \ - (PATI_LOC_CFG_BURST << 8)) - - -/* SDRAM Area */ -#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ -#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ -#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ -#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_SDRAM_SPACE0_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \ - (PATI_LOC_SDRAM_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_SDRAM_SPACE1_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \ - (PATI_LOC_SDRAM_BURST << 8)) - - -/* Flash Area */ -#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ -#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ -#define PATI_LOC_FLASH_BURST 0 /* No Burst */ -#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_FLASH_SPACE0_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 8) | \ - (PATI_LOC_FLASH_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_FLASH_SPACE1_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 9) | \ - (PATI_LOC_FLASH_BURST << 8)) - - -/* CPU Area */ -#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ -#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ -/* Attributes */ -#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CPU_BURST 0 /* No Burst */ -#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_CPU_SPACE0_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 8) | \ - (PATI_LOC_CPU_BURST << 24) | \ - (PATI_EXTRA_CPU_EEPROM << 25)) - -#define PATI_LOC_CPU_SPACE1_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 9) | \ - (PATI_LOC_CPU_BURST << 8)) - -/*************************************************** - * Hardware Config word definition - ***************************************************/ -#define BOOT_EXT_FLASH 0x00000000 -#define BOOT_INT_FLASH 0x00000004 -#define BOOT_FROM_PCI 0x00000006 -#define BOOT_FROM_SDRAM 0x00000005 - -#define ENABLE_INT_ARB 0x00000008 - -#define INITIAL_IRQ_PREF 0x00000010 - -#define INITIAL_MEM_0M 0x00000000 -#define INITIAL_MEM_4M 0x00000080 -#define INITIAL_MEM_8M 0x00000040 -#define INITIAL_MEM_12M 0x000000C0 -#define INITIAL_MEM_16M 0x00000020 -#define INITIAL_MEM_20M 0x000000A0 -#define INITIAL_MEM_24M 0x00000060 -#define INITIAL_MEM_28M 0x000000E0 -/* CONF */ -#define INTERNAL_HWCONF 0x00000100 -/* PRPM */ -#define LOCAL_CPU_SLAVE 0x00000200 -/* BDIS */ -#define DISABLE_MEM_CNTR 0x00000400 -/* PCIM */ -#define PCI_MASTER_ONLY 0x00000800 - - -#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) -#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) - -/*************************************************** - * Direct Master Config - ***************************************************/ -#define PATI_DMASTER_PCI_ADDR 0x01000000 -#define PATI_BUS_MASTER 1 - - -#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ -#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ - -#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ -#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ -#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ -#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 -#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008 -#define PATI_DMASTER_REL_PCI 0x00000000 -#define PATI_DMASTER_NOT_REL_PCI 0x00000010 -#define PATI_DMASTER_WR_INVAL 0x00000200 -#define PATI_DMASTER_NOT_WR_INVAL 0x00000000 -#define PATI_DMASTER_PRE_LIMIT 0x00000800 -#define PATI_DMASTER_PRE_CONT 0x00000000 -#define PATI_DMASTER_DELAY_WR_0 0x00000000 -#define PATI_DMASTER_DELAY_WR_4 0x00004000 -#define PATI_DMASTER_DELAY_WR_8 0x00008000 -#define PATI_DMASTER_DELAY_WR_16 0x0000C000 - -#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000 - -#define PATI_DMASTER_ATTR \ - PATI_DMASTER_MEMORY_EN | \ - PATI_DMASTER_READ_AHEAD | \ - PATI_DMASTER_PRE_SIZE_CNTRL_4 | \ - PATI_DMASTER_REL_PCI | \ - PATI_DMASTER_NOT_WR_INVAL | \ - PATI_DMASTER_PRE_LIMIT | \ - PATI_DMASTER_DELAY_WR_0 - - -#endif /* #ifndef __PATI_H_ */ diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h deleted file mode 100644 index 459c143..0000000 --- a/board/mpl/pati/pci_eeprom.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef __PCI_EEPROM_H_ -#define __PCI_EEPROM_H_ 1 - -#include "pati.h" -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -/********************************************** -* Definitions -**********************************************/ -#define EE46_CMD_LEN 9 /* Bits in instructions */ -#define EE56_CMD_LEN 11 /* Bits in instructions */ -#define EE66_CMD_LEN 11 /* Bits in instructions */ -#define EE_READ 0x0180 /* 01 1000 0000 read instruction */ -#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */ -#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */ -#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */ -#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */ -#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */ -#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */ -#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */ -#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */ -#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */ - -/*************************************************** - * EEPROM - ***************************************************/ -#define LOW_WORD(x) (((x) & 0xFFFF)) -#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF) - -typedef struct pci_eeprom_t { - unsigned short offset; - unsigned short value; -} pci_eeprom; - -static pci_eeprom pati_eeprom[] = { - { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ - { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ - { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ - { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ - { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ - { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ - { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ - { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ - { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ - { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ - { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ - { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ - { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ - { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ - { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ - { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ - { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ - { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ - { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ - { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ - { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ - { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ - { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ - { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ - { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ - { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ - { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ - { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ - { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ - { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ - { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ - { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ - { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ - { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ - { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ - { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ - { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ - { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ - { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ - { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ - { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ - { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ - { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ - { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ - { 0x58,0x0000 }, /* Reserved Reserved */ - { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ - { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ - { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ - { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ - { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ - { 0xFFFF,0xFFFF} /* terminaror */ -}; -#define PATI_EEPROM_LAST_OFFSET 0x64 -#endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h deleted file mode 100644 index 754e720..0000000 --- a/board/mpl/pati/plx9056.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PLX9096 register definitions -*/ -#ifndef __PLX9056_H_ -#define __PLX9056_H_ 1 - -#include - -#ifdef PLX9056_LOC -#define LOCAL_OFFSET 0x080 -/* PCI Config regs */ -#else -#define LOCAL_OFFSET 0x000 -#endif - -#define PCI9056_VENDOR_ID PCI_VENDOR_ID -/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */ -#define PCI9056_COMMAND PCI_COMMAND -/*#define PCI9656_STATUS PCI_STATUS */ -#define PCI9056_REVISION PCI_REVISION_ID - -#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE -#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 -#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 -#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 -#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 -#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 -#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 -#define PCI9056_CIS_PTR PCI_CARDBUS_CIS -#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID -#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS -#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST -#define PCI9056_INT_LINE PCI_INTERRUPT_LINE - -#if defined(PLX9056_LOC) - #define PCI9056_PM_CAP_ID 0x180 - #define PCI9056_PM_CSR 0x184 - #define PCI9056_HS_CAP_ID 0x188 - #define PCI9056_VPD_CAP_ID 0x18C - #define PCI9056_VPD_DATA 0x190 -#endif - - -#define PCI_DEVICE_ID_PLX9056 0x9056 - -/* Local Configuration Registers Accessible via the PCI Base address + Variable */ -#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) -#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) -#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) -#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) -#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) -#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) -#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) -#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) -#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) -#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) -#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) -#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) - -#ifdef PLX9056_LOC -#define PCI9056_ARBITER_CTRL 0x1A0 -#define PCI9056_ABORT_ADDRESS 0x1A4 -#endif - -/* Runtime registers PCI Address + LOCAL_OFFSET */ -#ifdef PLX9056_LOC -#define PCI9056_MAILBOX0 0x0C0 -#define PCI9056_MAILBOX1 0x0C4 -#else -#define PCI9056_MAILBOX0 0x078 -#define PCI9056_MAILBOX1 0x07c -#endif - -#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) -#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) -#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) -#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) -#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) -#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) -#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) -#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) -#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) -#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) -#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) -#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) - -#endif /* #ifndef __PLX9056_H_ */ diff --git a/board/munices/Kconfig b/board/munices/Kconfig deleted file mode 100644 index 019aaae..0000000 --- a/board/munices/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MUNICES - -config SYS_BOARD - default "munices" - -config SYS_CONFIG_NAME - default "munices" - -endif diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS deleted file mode 100644 index 50d3e7e..0000000 --- a/board/munices/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MUNICES BOARD -#M: - -S: Maintained -F: board/munices/ -F: include/configs/munices.h -F: configs/munices_defconfig diff --git a/board/munices/Makefile b/board/munices/Makefile deleted file mode 100644 index d16e2a1..0000000 --- a/board/munices/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := munices.o diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa..0000000 --- a/board/munices/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/munices/munices.c b/board/munices/munices.c deleted file mode 100644 index 468eb37..0000000 --- a/board/munices/munices.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "mt48lc16m16a2-75.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR && SDRAM_TAPDELAY - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000); - sdram_start(1); - test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: MUNICes\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index b56bc52..0d5eec9 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include diff --git a/board/nvidia/whistler/Kconfig b/board/nvidia/whistler/Kconfig deleted file mode 100644 index 5febc07..0000000 --- a/board/nvidia/whistler/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WHISTLER - -config SYS_BOARD - default "whistler" - -config SYS_VENDOR - default "nvidia" - -config SYS_CONFIG_NAME - default "whistler" - -endif diff --git a/board/nvidia/whistler/MAINTAINERS b/board/nvidia/whistler/MAINTAINERS deleted file mode 100644 index 66e2c8d..0000000 --- a/board/nvidia/whistler/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -WHISTLER BOARD -M: Tom Warren -M: Stephen Warren -S: Maintained -F: board/nvidia/whistler/ -F: include/configs/whistler.h -F: configs/whistler_defconfig diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile deleted file mode 100644 index b54c5fd..0000000 --- a/board/nvidia/whistler/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2010-2012 -# NVIDIA Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := whistler.o diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c deleted file mode 100644 index db48978..0000000 --- a/board/nvidia/whistler/whistler.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MMC_SDHCI_TEGRA -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ - struct udevice *dev; - uchar val; - int ret; - - /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ - ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev); - if (ret) { - printf("%s: Cannot find MAX8907B I2C chip\n", __func__); - return; - } - val = 0x29; - ret = dm_i2c_write(dev, 0x46, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); - val = 0x00; - ret = dm_i2c_write(dev, 0x45, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); - val = 0x1f; - ret = dm_i2c_write(dev, 0x44, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); - - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); -} -#endif - -/* this is a weak define that we are overriding */ -void pin_mux_usb(void) -{ - struct udevice *dev; - uchar val; - int ret; - - /* - * This is a hack. This should be represented in DT using the - * vbus-gpio property. However, U-Boot's DT support doesn't - * support any GPIO controller other than the Tegra's yet. - */ - - /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ - ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev); - if (ret) { - printf("%s: Cannot find TAC6416 I2C chip\n", __func__); - return; - } - val = 0x03; - ret = dm_i2c_write(dev, 2, &val, 1); - if (ret) - printf("i2c_write 0 0x20 2 failed: %d\n", ret); - val = 0xfc; - ret = dm_i2c_write(dev, 6, &val, 1); - if (ret) - printf("i2c_write 0 0x20 6 failed: %d\n", ret); -} diff --git a/board/overo/common.c b/board/overo/common.c index f6f6792..5656e2d 100644 --- a/board/overo/common.c +++ b/board/overo/common.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig deleted file mode 100644 index 33173a0..0000000 --- a/board/pdm360ng/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PDM360NG - -config SYS_BOARD - default "pdm360ng" - -config SYS_CONFIG_NAME - default "pdm360ng" - -endif diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS deleted file mode 100644 index 5c99f59..0000000 --- a/board/pdm360ng/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PDM360NG BOARD -M: Michael Weiss -S: Maintained -F: board/pdm360ng/ -F: include/configs/pdm360ng.h -F: configs/pdm360ng_defconfig diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile deleted file mode 100644 index 99201a4..0000000 --- a/board/pdm360ng/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pdm360ng.o diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c deleted file mode 100644 index 371bcd9..0000000 --- a/board/pdm360ng/pdm360ng.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - * (C) Copyright 2009, 2010 Wolfgang Denk - * - * (C) Copyright 2009-2010 - * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MISC_INIT_R -#include -#endif -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; -ulong flash_get_size (phys_addr_t base, int banknum); - -sdram_conf_t mddrc_config[] = { - { - (512 << 20), /* 512 MB RAM configuration */ - { - CONFIG_SYS_MDDRC_SYS_CFG, - CONFIG_SYS_MDDRC_TIME_CFG0, - CONFIG_SYS_MDDRC_TIME_CFG1, - CONFIG_SYS_MDDRC_TIME_CFG2 - } - }, - { - (128 << 20), /* 128 MB RAM configuration */ - { - CONFIG_SYS_MDDRC_SYS_CFG_ALT1, - CONFIG_SYS_MDDRC_TIME_CFG0_ALT1, - CONFIG_SYS_MDDRC_TIME_CFG1_ALT1, - CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 - } - }, -}; - -int dram_init(void) -{ - int i; - u32 msize = 0; - u32 pdm360ng_init_seq[] = { - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_EM3, - CONFIG_SYS_DDRCMD_EN_DLL, - CONFIG_SYS_DDRCMD_RES_DLL, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_OCD_DEFAULT, - CONFIG_SYS_DDRCMD_OCD_EXIT, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP - }; - - for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) { - msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq, - ARRAY_SIZE(pdm360ng_init_seq)); - if (msize == mddrc_config[i].size) - break; - } - - gd->ram_size = msize; - - return 0; -} - -static int set_lcd_brightness(char *); - -int misc_init_r(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Re-configure flash setup using auto-detected info - */ - if (flash_info[1].size > 0) { - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) | - CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size, - flash_info[1].size)); - sync_law(&im->sysconf.lpcs1aw); - /* - * Re-check to get correct base address - */ - flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1); - } else { - /* Disable Bank 1 */ - out_be32(&im->sysconf.lpcs1aw, 0x01000100); - sync_law(&im->sysconf.lpcs1aw); - } - - out_be32(&im->sysconf.lpcs0aw, - CSAW_START(gd->bd->bi_flashstart) | - CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size)); - sync_law(&im->sysconf.lpcs0aw); - - /* - * Re-check to get correct base address - */ - flash_get_size (gd->bd->bi_flashstart, 0); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[0]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_FSL_DIU_FB - set_lcd_brightness(0); - /* Switch LCD-Backlight and LVDS-Interface on */ - setbits_be32(&im->gpio.gpdir, 0x01040000); - clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000); -#endif - - return 0; -} - -static iopin_t ioregs_init[] = { - /* FUNC1=LPC_CS4 */ - { - offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | - IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO10 */ - { - offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC1=CAN3_TX */ - { - offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO14 */ - { - offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */ - /* DIU_LD22-DIU_LD23 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */ - /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */ - { - offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */ - /* VIU_DATA0-VIU_DATA2 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=FEC_TXD_0 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */ - /* VIU_DATA3, VIU_DATA4 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */ - /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */ - /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */ - { - offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */ - /* DIU_LD00-DIU_LD21 */ - { - offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */ - /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */ - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=CAN3_RX */ - { - offsetof(struct ioctrl512x, io_control_irq1), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* Sets lowest slew on 2 CAN_TX Pins*/ - { - offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */ - /* CAN4_TX, CAN4_RX */ - { - offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */ - /* GPIO8, GPIO9 */ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */ - /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */ - { - offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */ - /* FEC_RXD_3, FEC_RXD_2 */ - { - offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO17 */ - { - offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */ - /* GPIO2, GPIO20, GPIO21 */ - { - offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=VIU_PIX_CLK */ - { - offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */ - /* GPIO24, GPIO25 */ - { - offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC1=NFC_CE2 */ - { - offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | - IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */ - /* VIU_DATA5-VIU_DATA9 */ - { - offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */ - /* LPC_TSIZ1-LPC_TSIZ2 */ - { - offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=LPC_TS */ - { - offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO16 */ - { - offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */ - /* GPIO18-GPIO19, GPT7/GPIO7 */ - { - offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO0/GPT0 */ - { - offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */ - /* GPIO11, GPIO2, GPIO12, GPIO13 */ - { - offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=DIU_DE */ - { - offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -int checkboard (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - puts("Board: PDM360NG\n"); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */ - setbits_be32(&im->io_ctrl.io_control_gp, - (1 << 0) | /* GP_MUX7->GPIO7 */ - (1 << 5)); /* GP_MUX2->GPIO2 */ - - /* configure GPIO24 (VIU_CE), output/high */ - setbits_be32(&im->gpio.gpdir, 0x80); - setbits_be32(&im->gpio.gpdat, 0x80); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -#ifdef CONFIG_FDT_FIXUP_PARTITIONS -struct node_info nodes[] = { - { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, }, - { "cfi-flash", MTD_DEV_TYPE_NOR, }, -}; -#endif - -#if defined(CONFIG_VIDEO) -/* - * EDID block has been generated using Phoenix EDID Designer 1.3. - * This tool creates a text file containing: - * - * EDID BYTES: - * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F - * ------------------------------------------------ - * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00 - * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25 - * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 - * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80 - * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F - * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50 - * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF - * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4 - * - * Then this data has been manually converted to the char - * array below. - */ -static unsigned char edid_buf[128] = { - 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, - 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00, - 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78, - 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25, - 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C, - 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80, - 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18, - 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F, - 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50, - 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A, - 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF, - 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, - 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4, -}; -#endif - -int ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[8]; - int rc, i = 0; - - ft_cpu_setup(blob, bd); -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif -#if defined(CONFIG_VIDEO) - fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf); -#endif - - /* Fixup NOR FLASH mapping */ - val[i++] = 0; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = gd->bd->bi_flashstart; - val[i++] = gd->bd->bi_flashsize; - - /* Fixup MRAM mapping */ - val[i++] = 2; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_MRAM_BASE; - val[i++] = CONFIG_SYS_MRAM_SIZE; - - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, i * sizeof(u32), 1); - if (rc) - printf("Unable to update localbus ranges, err=%s\n", - fdt_strerror(rc)); - - /* Fixup reg property in NOR Flash node */ - i = 0; - val[i++] = 0; /* always 0 */ - val[i++] = 0; /* start at offset 0 */ - val[i++] = flash_info[0].size; /* size of Bank 0 */ - - /* Second Bank available? */ - if (flash_info[1].size > 0) { - val[i++] = 0; /* always 0 */ - val[i++] = flash_info[0].size; /* offset of Bank 1 */ - val[i++] = flash_info[1].size; /* size of Bank 1 */ - } - - rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg", - val, i * sizeof(u32), 1); - if (rc) - printf("Unable to update flash reg property, err=%s\n", - fdt_strerror(rc)); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -/* - * If argument is NULL, set the LCD brightness to the - * value from "brightness" environment variable. Set - * the LCD brightness to the value specified by the - * argument otherwise. Default brightness is zero. - */ -#define MAX_BRIGHTNESS 99 -static int set_lcd_brightness(char *brightness) -{ - struct stdio_dev *cop_port; - char *env; - char cmd_buf[20]; - int val = 0; - int cs = 0; - int len, i; - - if (brightness) { - val = simple_strtol(brightness, NULL, 10); - } else { - env = getenv("brightness"); - if (env) - val = simple_strtol(env, NULL, 10); - } - - if (val < 0) - val = 0; - - if (val > MAX_BRIGHTNESS) - val = MAX_BRIGHTNESS; - - sprintf(cmd_buf, "$SB;%04d;", val); - - len = strlen(cmd_buf); - for (i = 1; i <= len; i++) - cs += cmd_buf[i]; - - cs = (~cs + 1) & 0xff; - sprintf(cmd_buf + len, "%02X\n", cs); - - /* IO Coprocessor communication */ - cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE); - if (!cop_port) { - printf("Error: Can't open IO Coprocessor port.\n"); - return -1; - } - - debug("%s: cmd: %s", __func__, cmd_buf); - write_port(cop_port, cmd_buf); - /* - * Wait for transmission and maybe response data - * before closing the port. - */ - udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY); - memset(cmd_buf, 0, sizeof(cmd_buf)); - len = read_port(cop_port, cmd_buf, sizeof(cmd_buf)); - if (len) - printf("Error: %s\n", cmd_buf); - - close_port(4); - - return 0; -} - -static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - return set_lcd_brightness(argv[1]); -} - -U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness, - "set LCD brightness", - " - set LCD backlight level to .\n" -); diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig deleted file mode 100644 index 3a3eab8..0000000 --- a/board/phytec/pcm030/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PCM030 - -config SYS_BOARD - default "pcm030" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "pcm030" - -endif diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS deleted file mode 100644 index 4e2ab0d..0000000 --- a/board/phytec/pcm030/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PCM030 BOARD -M: Jon Smirl -S: Maintained -F: board/phytec/pcm030/ -F: include/configs/pcm030.h -F: configs/pcm030_defconfig -F: configs/pcm030_LOWBOOT_defconfig diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile deleted file mode 100644 index 2bb49dc..0000000 --- a/board/phytec/pcm030/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pcm030.o diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README deleted file mode 100644 index 05faab6..0000000 --- a/board/phytec/pcm030/README +++ /dev/null @@ -1,42 +0,0 @@ -To build RAMBOOT, replace this section the main Makefile - -pcm030_config \ -pcm030_RAMBOOT_config \ -pcm030_LOWBOOT_config: unconfig - @ >include/config.h - @[ -z "$(findstring LOWBOOT_,$@)" ] || \ - { echo "CONFIG_SYS_TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ - echo "... with LOWBOOT configuration" ; \ - } - @[ -z "$(findstring RAMBOOT_,$@)" ] || \ - { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\ - config.tmp ; \ - echo "... with RAMBOOT configuration" ; \ - echo "... remember to make sure that MBAR is already \ - switched to 0xF0000000 !!!" ; \ - } - @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec - @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1" - -Alternative SDRAM settings: - -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 - -/* Settings for XLB = 99 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714b0f00 -#define SDRAM_CONFIG1 0x63611730 -#define SDRAM_CONFIG2 0x47670000 - -The board ships default with the environment in EEPROM -Moving the environment to flash can be more reliable - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h deleted file mode 100644 index 47fc7c0..0000000 --- a/board/phytec/pcm030/mt46v32m16-75.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * Eric Schumann, Phytec Messtechnik - * adapted for mt46v32m16-75 DDR-RAM - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x71500F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x47770000 - -#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c deleted file mode 100644 index bdd980d..0000000 --- a/board/phytec/pcm030/pcm030.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messtechnik GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include "mt46v32m16-75.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - -#ifdef SDRAM_DDR - /* set mode register: extended mode */ - out_be32 (&sdram->mode, (SDRAM_EMODE)); - - /* set mode register: reset DLL */ - out_be32 (&sdram->mode, - (SDRAM_MODE | 0x04000000)); -#endif - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - - /* auto refresh */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); - - /* set mode register */ - out_be32 (&sdram->mode, (SDRAM_MODE)); - - /* normal operation */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | hi_addr_bit)); - - /* set CDM clock enable register, set MPC5200B SDRAM bus */ - /* to reduced driver strength */ - out_be32 (&cdm->clock_enable, (0x00CFFFFF)); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make - * real use of CONFIG_SYS_SDRAM_BASE. The code does not - * work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - /* 256MB at 0x0 */ - out_be32 (&mm->sdram0, 0x0000001b); - /* disabled */ - out_be32 (&mm->sdram1, 0x10000000); - - /* setup config registers */ - out_be32 (&sdram->config1, SDRAM_CONFIG1); - out_be32 (&sdram->config2, SDRAM_CONFIG2); - -#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) - /* set tap delay */ - out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - sdram_start(1); - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32 (&mm->sdram0, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - /* disabled */ - out_be32 (&mm->sdram0, 0); - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32(&mm->sdram1) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard(void) -{ - puts("Board: phyCORE-MPC5200B-tiny\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) - -#define GPIO_PSC2_4 0x02000000UL - -void init_ide_reset(void) -{ - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - debug("init_ide_reset\n"); - - /* Configure PSC2_4 as GPIO output for ATA reset */ - setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); - setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); - /* Deassert reset */ - setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); -} - -void ide_set_reset(int idereset) -{ - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else - setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); -} -#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/board/rockchip/evb_px5/Kconfig b/board/rockchip/evb_px5/Kconfig new file mode 100644 index 0000000..9a04ee7 --- /dev/null +++ b/board/rockchip/evb_px5/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_PX5 + +config SYS_BOARD + default "evb_px5" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_px5" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_px5/MAINTAINERS b/board/rockchip/evb_px5/MAINTAINERS new file mode 100644 index 0000000..5d09fbf --- /dev/null +++ b/board/rockchip/evb_px5/MAINTAINERS @@ -0,0 +1,6 @@ +PX5 EVB +M: Andy Yan +S: Maintained +F: board/rockchip/evb_px5 +F: include/configs/evb_px5.h +F: configs/evb-px5_defconfig diff --git a/board/rockchip/evb_px5/Makefile b/board/rockchip/evb_px5/Makefile new file mode 100644 index 0000000..f5aa5a9 --- /dev/null +++ b/board/rockchip/evb_px5/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-px5.o diff --git a/board/rockchip/evb_px5/README b/board/rockchip/evb_px5/README new file mode 100644 index 0000000..de980f2 --- /dev/null +++ b/board/rockchip/evb_px5/README @@ -0,0 +1 @@ +see board/rockchip/sheep_rk3368/README diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c new file mode 100644 index 0000000..54e62db --- /dev/null +++ b/board/rockchip/evb_px5/evb-px5.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017 Andy Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + struct rk3368_pmu_grf *pmugrf; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rk3368-pmugrf"); + pmugrf = (struct rk3368_pmu_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + + rk_clrsetreg(&pmugrf->gpio0d_iomux, + GPIO0D0_MASK | GPIO0D1_MASK | + GPIO0D2_MASK | GPIO0D3_MASK, + GPIO0D0_GPIO << GPIO0D0_SHIFT | + GPIO0D1_GPIO << GPIO0D1_SHIFT | + GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT | + GPIO0D3_UART4_SIN << GPIO0D3_SHIFT); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x40000000; + + return 0; +} + +int dram_init_banksize(void) +{ + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x3fe00000; + + return 0; +} diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 9db604f..2ee6e46 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -1,5 +1,5 @@ EVB-RK3328 -M: William Zhang +M: Kever Yang S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index a7895cb..0a26ed5 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -31,11 +31,6 @@ int dram_init_banksize(void) return 0; } -int usb_gadget_handle_interrupts(void) -{ - return 0; -} - int board_usb_init(int index, enum usb_init_type init) { return 0; diff --git a/board/rockchip/evb_rv1108/Kconfig b/board/rockchip/evb_rv1108/Kconfig new file mode 100644 index 0000000..4a76e0b --- /dev/null +++ b/board/rockchip/evb_rv1108/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RV1108 + +config SYS_BOARD + default "evb_rv1108" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rv1108" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rv1108/MAINTAINERS b/board/rockchip/evb_rv1108/MAINTAINERS new file mode 100644 index 0000000..94def32 --- /dev/null +++ b/board/rockchip/evb_rv1108/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RV1108 +M: Andy Yan +S: Maintained +F: board/rockchip/evb_rv1108 +F: include/configs/evb_rv1108.h +F: configs/evb-rv1108_defconfig diff --git a/board/rockchip/evb_rv1108/Makefile b/board/rockchip/evb_rv1108/Makefile new file mode 100644 index 0000000..dd99054 --- /dev/null +++ b/board/rockchip/evb_rv1108/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rv1108.o diff --git a/board/rockchip/evb_rv1108/README b/board/rockchip/evb_rv1108/README new file mode 100644 index 0000000..5889596 --- /dev/null +++ b/board/rockchip/evb_rv1108/README @@ -0,0 +1,47 @@ +Here is the step-by-step to boot U-Boot on rv1108 evb. + +Get ddr init binary +============================================================================== + > git clone https://github.com/rockchip-linux/rkbin.git + > dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1 + +Compile U-Boot +=========================== + > make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all + > ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin + > cat spl.bin u-boot.bin > u-boot.img + +Flash the image by rkdeveloptool +================================ +rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git + +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin + > rkdeveloptool wl 0x40 u-boot.img + > rkdeveloptool RD + +You should be able to get U-Boot log message from boot console: + +DDR Version V1.02 20170220 +In +400MHz +DDR3 +Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB +mach:2 +OUT + + +U-Boot 2017.05-00693-g3a5b171 (Jun 01 2017 - 17:37:53 +0800) + +Model: Rockchip RV1108 Evaluation board +DRAM: 128 MiB +APLL: 600000000 DPLL:792000000 GPLL:384000000 +MMC: +Using default environment + +In: serial@10210000 +Out: serial@10210000 +Err: serial@10210000 +Net: No ethernet found. +Hit any key to stop autoboot: 0 +=> diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c new file mode 100644 index 0000000..fe37eac --- /dev/null +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -0,0 +1,52 @@ +/* + * (C)Copyright 2016 Rockchip Electronics Co., Ltd + * Authors: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + int node; + struct rv1108_grf *grf; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf"); + grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + + /*evb board use UART2 m0 for debug*/ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D2_MASK | GPIO2D1_MASK, + GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | + GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); + rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); + + return 0; +} + + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x8000000; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0x60000000; + gd->bd->bi_dram[0].size = 0x8000000; + + return 0; +} diff --git a/board/rockchip/sheep_rk3368/Kconfig b/board/rockchip/sheep_rk3368/Kconfig new file mode 100644 index 0000000..d39b5e8 --- /dev/null +++ b/board/rockchip/sheep_rk3368/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SHEEP + +config SYS_BOARD + default "sheep_rk3368" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "sheep_rk3368" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/sheep_rk3368/MAINTAINERS b/board/rockchip/sheep_rk3368/MAINTAINERS new file mode 100644 index 0000000..cd5de99 --- /dev/null +++ b/board/rockchip/sheep_rk3368/MAINTAINERS @@ -0,0 +1,6 @@ +RK3368 Sheep Board +M: Andy Yan +S: Maintained +F: board/rockchip/sheep_rk3368 +F: include/configs/sheep_rk3368.h +F: configs/sheep-rk3368_defconfig diff --git a/board/rockchip/sheep_rk3368/Makefile b/board/rockchip/sheep_rk3368/Makefile new file mode 100644 index 0000000..a38b9ce --- /dev/null +++ b/board/rockchip/sheep_rk3368/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sheep_rk3368.o diff --git a/board/rockchip/sheep_rk3368/README b/board/rockchip/sheep_rk3368/README new file mode 100644 index 0000000..2d078cb --- /dev/null +++ b/board/rockchip/sheep_rk3368/README @@ -0,0 +1,44 @@ +Here is the step-by-step to boot to U-Boot on rk3368. + +Get miniloader and trust.img form rockchip vendor u-boot source code +============================================================================== + > git clone https://github.com/rockchip-linux/u-boot.git rockchip-uboot + > cd rockchip-uboot + > make rk3368_defconfig /*chose px5_defconfig if you run a px5 platform here*/ + > ./mkv8.sh + +Compile the upstream U-Boot +=========================== + > cd u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- sheep-rk3368_defconfig all + +Package u-boot for miniloader +================================ + > ../rockchip-uboot/tools/loaderimage --pack --uboot u-boot.bin u-boot.img + +Flash the image by rkdeveloptool +================================ +rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git + +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db ./rockchip-uboot/rk3368_loader_v2.00.256.bin + > rkdeveloptool wl 0x6000 ./rockchip-uboot/trust.img + > rkdeveloptool wl 0x4000 ./u-boot/u-boot.img + > rkdeveloptool RD + +You should be able to get U-Boot log message from boot console: + +U-Boot 2017.05-rc3-01094-g9ddd1e8-dirty (May 15 2017 - 15:57:23 +0800) + +Model: Rockchip sheep board +DRAM: 2 GiB +MMC: dwmmc@ff0f0000: 0 +Using default environment + +In: serial@ff690000 +Out: serial@ff690000 +Err: serial@ff690000 +Net: Net Initialization Skipped +No ethernet found. +Hit any key to stop autoboot: 0 +=> diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c new file mode 100644 index 0000000..df1fd9d --- /dev/null +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017 Andy Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x7fe00000; + + return 0; +} diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 79073d8..f60ddda 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -26,6 +26,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index accf16f..1469136 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -25,6 +25,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index c122580..e2620e3 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -25,6 +25,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 1259383..d0247ac 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -17,6 +17,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 79e127d..5d23844 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index feb8a34..cc6eaf7 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -23,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 9cafcea..b967227 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "../common/factoryset.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 396b5bd..8f8132a 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 6f39ef1..d07dda3 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 52196af..66073f3 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index 858a9ca..2a54b8b 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index f8e9fdd..2c34ea1 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 7a6d93c..fc4c60c 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -36,16 +37,18 @@ int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) } int dram_init(void) { - struct udevice *dev; int rv; fdt_addr_t mr_base, mr_size; +#ifndef CONFIG_SUPPORT_SPL + struct udevice *dev; rv = uclass_get_device(UCLASS_RAM, 0, &dev); if (rv) { debug("DRAM init failed: %d\n", rv); return rv; } +#endif rv = get_memory_base_size(&mr_base, &mr_size); if (rv) return rv; @@ -87,6 +90,37 @@ int board_early_init_f(void) } #endif +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + debug("SPL: booting kernel\n"); + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +int spl_dram_init(void) +{ + struct udevice *dev; + int rv; + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) + debug("DRAM init failed: %d\n", rv); + return rv; +} +void spl_board_init(void) +{ + spl_dram_init(); + preloader_console_init(); + arch_cpu_init(); /* to configure mpu for sdram rw permissions */ +} +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_XIP; +} + +#endif u32 get_board_rev(void) { return 0; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 0f1290a..e9f3e35 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -247,11 +247,21 @@ M: Mylène Josserand S: Maintained F: configs/nanopi_m1_defconfig +NANOPI-M1 PLUS BOARD +M: Jagan Teki +S: Maintained +F: configs/nanopi_m1_plus_defconfig + NANOPI-NEO BOARD M: Jelle van der Waa S: Maintained F: configs/nanopi_neo_defconfig +NANOPI-NEO2 BOARD +M: Jagan Teki +S: Maintained +F: configs/nanopi_neo2_defconfig + NANOPI-NEO-AIR BOARD M: Jelle van der Waa S: Maintained @@ -262,11 +272,21 @@ M: FUKAUMI Naoki S: Maintained F: configs/Nintendo_NES_Classic_Edition_defconfig +ORANGEPI WIN/WIN PLUS BOARD +M: Jagan Teki +S: Maintained +F: configs/orangepi_win_defconfig + ORANGEPI ZERO BOARD M: Icenowy Zheng S: Maintained F: configs/orangepi_zero_defconfig +ORANGEPI ZERO PLUS 2 BOARD +M: Jagan Teki +S: Maintained +F: configs/orangepi_zero_plus2_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara S: Maintained @@ -309,6 +329,11 @@ M: VishnuPatekar S: Maintained F: configs/Sinovoip_BPI_M3_defconfig +SOPINE BOARD +M: Icenowy Zheng +S: Maintained +F: configs/sopine_baseboard_defconfig + SUNCHIP CX-A99 BOARD M: Rask Ingemann Lambertsen S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index f79bd5c..800f412 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -33,6 +33,7 @@ #include #include #include +#include #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index 1a8d02b..250e345 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -56,8 +56,7 @@ Package the image ================= > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img - > tools/mkimage -f board/theobroma/puma_rk3399/fit_spl_atf.its \ - -E rk3399_bl3x.itb + > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb Flash the image =============== @@ -67,7 +66,7 @@ Copy the SPL to offset 32k and the FIT image containing the payloads card. > dd if=spl.img of=/dev/sdb seek=64 - > dd if=rk3399_bl3x.itb of=/dev/sdb seek=512 + > dd if=u-boot.itb of=/dev/sdb seek=512 After powering up the board (with the inserted SD card), you should see a U-Boot console on UART0 (115200n8). diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 0a8861a..6fff3e1 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -9,10 +9,15 @@ #include #include #include +#include +#include #include #include #include +#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + DECLARE_GLOBAL_DATA_PTR; #define RK3399_CPUID_OFF 0x7 @@ -63,6 +68,119 @@ out: return 0; } +static void setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(CMD_NET) + int ret; + const char *cpuid = getenv("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (getenv("ethaddr")) + return; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_setenv_enetaddr("ethaddr", mac_addr); +#endif + + return; +} + +static void setup_serial(void) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret, i; + u8 cpuid[RK3399_CPUID_LEN]; + u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; + char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u64 serialno; + char serialno_str[16]; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return; + } + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); + + setenv("cpuid#", cpuid_str); + setenv("serial#", serialno_str); +#endif + + return; +} + +int misc_init_r(void) +{ + setup_serial(); + setup_macaddr(); + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + u64 serial = 0; + + serial_string = getenv("serial#"); + + if (serial_string) + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (u32)(serial >> 32); + serialnr->low = (u32)(serial & 0xffffffff); +} +#endif + int dram_init(void) { struct ram_info ram; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 517965c..0a16529 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -343,14 +344,6 @@ static void scale_vcores_bone(int freq) if (board_is_bone_lt()) freq = MPUPLL_M_1000; - if (freq == MPUPLL_M_1000) { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; - } else { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - } - switch (freq) { case MPUPLL_M_1000: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; @@ -358,15 +351,16 @@ static void scale_vcores_bone(int freq) break; case MPUPLL_M_800: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; break; case MPUPLL_M_720: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; break; case MPUPLL_M_600: case MPUPLL_M_500: case MPUPLL_M_300: + default: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; break; @@ -469,7 +463,7 @@ void scale_vcores(void) gpi2c_init(); freq = am335x_get_efuse_mpu_max_freq(cdev); - if (board_is_bone()) + if (board_is_beaglebonex()) scale_vcores_bone(freq); else scale_vcores_generic(freq); diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 48c139a..e13fcff 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -39,6 +39,11 @@ static inline int board_is_bbg1(void) return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4); } +static inline int board_is_beaglebonex(void) +{ + return board_is_bone() || board_is_bone_lt() || board_is_bbg1(); +} + static inline int board_is_evm_sk(void) { return board_ti_is("A335X_SK"); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index f44103d..54f40e6 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "../common/board_detect.h" #include "board.h" #include @@ -421,6 +422,13 @@ void scale_vcores_generic(u32 m) printf("%s failure\n", __func__); return; } + + /* Set DCDC3 (DDR) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC3, + TPS65218_DCDC3_VOLT_SEL_1350MV)) { + printf("%s failure\n", __func__); + return; + } } void scale_vcores_idk(u32 m) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 3be697a..bf8c8e1 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -343,6 +343,54 @@ struct vcores_data am572x_idk_volts = { .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, }; +struct vcores_data am571x_idk_volts = { + .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, + .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, + .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, + .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, + .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, + .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, + .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, + .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, + .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, + .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7, + .core.pmic = &tps659038, + + .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, + .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, + .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, + .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + int get_voltrail_opp(int rail_offset) { int opp; @@ -452,6 +500,8 @@ void vcores_init(void) { if (board_is_am572x_idk()) *omap_vcores = &am572x_idk_volts; + else if (board_is_am571x_idk()) + *omap_vcores = &am571x_idk_volts; else *omap_vcores = &beagle_x15_volts; } @@ -573,6 +623,7 @@ int board_late_init(void) val); omap_die_id_serial(); + omap_set_fastboot_vars(); am57x_idk_lcd_detect(); @@ -593,8 +644,8 @@ void set_muxconf_regs(void) void recalibrate_iodelay(void) { const struct pad_conf_entry *pconf; - const struct iodelay_cfg_entry *iod; - int pconf_sz, iod_sz; + const struct iodelay_cfg_entry *iod, *delta_iod; + int pconf_sz, iod_sz, delta_iod_sz = 0; int ret; if (board_is_am572x_idk()) { @@ -646,6 +697,9 @@ void recalibrate_iodelay(void) if (am571x_idk_needs_lcd()) { pconf = core_padconf_array_vout_am571x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk); + delta_iod = iodelay_cfg_array_am571x_idk_4port; + delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port); + } else { pconf = core_padconf_array_icss1eth_am571x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk); @@ -655,6 +709,10 @@ void recalibrate_iodelay(void) /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); + if (delta_iod_sz) + ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod, + delta_iod_sz); + err: /* Closeup.. remove isolation */ __recalibrate_iodelay_end(ret); diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index aff274c..b4a71bd 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -67,8 +67,8 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ - {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ - {VIN1B_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1b_clk1.gpio2_31 */ + {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */ + {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ @@ -87,14 +87,14 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ - {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ + {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.pr1_uart0_cts_n */ {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ - {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ - {VIN2A_D1, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ - {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ - {VIN2A_D3, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ - {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ - {VIN2A_D5, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ + {VIN2A_D0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d2.uart10_rxd */ + {VIN2A_D3, (M8 | PIN_OUTPUT)}, /* vin2a_d3.uart10_txd */ + {VIN2A_D4, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d4.uart10_ctsn */ + {VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.uart10_rtsn */ {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ @@ -113,40 +113,12 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ - {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ - {MDIO_MCLK, (M0 | PIN_OUTPUT)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */ + {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ - {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ - {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ + {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ @@ -159,8 +131,8 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN)}, /* usb2_drvvbus.usb2_drvvbus */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ @@ -169,48 +141,36 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ - {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ + {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_fsx.i2c3_scl */ {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ - {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.i2c5_sda */ - {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M14 | PIN_INPUT)}, /* mcasp1_axr8.gpio5_10 */ - {MCASP1_AXR9, (M14 | PIN_INPUT)}, /* mcasp1_axr9.gpio5_11 */ - {MCASP1_AXR10, (M14 | PIN_INPUT)}, /* mcasp1_axr10.gpio5_12 */ - {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr11.gpio4_17 */ - {MCASP1_AXR12, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ - {MCASP1_AXR13, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */ - {MCASP1_AXR14, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ - {MCASP1_AXR15, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ - {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ - {MCASP2_FSX, (M0 | PIN_INPUT)}, /* mcasp2_fsx.mcasp2_fsx */ - {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ - {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ - {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ - {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ - {MCASP2_AXR2, (M0 | PIN_INPUT)}, /* mcasp2_axr2.mcasp2_axr2 */ - {MCASP2_AXR3, (M0 | PIN_INPUT)}, /* mcasp2_axr3.mcasp2_axr3 */ - {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ - {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ - {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ - {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ + {MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr8.gpio5_10 */ + {MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr9.gpio5_11 */ + {MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr10.gpio5_12 */ + {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ - {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ - {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ - {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */ {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */ - {MCASP4_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ - {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ + {MCASP4_FSX, (M3 | PIN_OUTPUT)}, /* mcasp4_fsx.uart8_txd */ + {MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr0.uart8_ctsn */ {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */ - {MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ - {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ + {MCASP5_FSX, (M3 | PIN_OUTPUT)}, /* mcasp5_fsx.uart9_txd */ + {MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr0.uart9_ctsn */ {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ @@ -218,7 +178,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ {GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ {MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */ @@ -227,31 +187,31 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */ {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */ {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */ - {MMC3_DAT4, (M1 | PIN_OUTPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ - {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ - {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ - {MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ + {MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat4.mmc3_dat4 */ + {MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat5.mmc3_dat5 */ + {MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat6.mmc3_dat6 */ + {MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat7.mmc3_dat7 */ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ - {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ - {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ - {SPI2_CS0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_cs0.gpio7_17 */ - {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ - {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {UART1_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart1_rxd.uart1_rxd */ - {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN)}, /* uart1_txd.uart1_txd */ + {SPI2_D1, (M14 | PIN_INPUT_SLEW)}, /* spi2_d1.gpio7_15 */ + {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_d0.gpio7_16 */ + {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ + {DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */ {UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */ {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */ {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */ {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (M1 | PIN_OUTPUT_PULLDOWN)}, /* uart2_rtsn.uart3_txd */ + {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */ {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */ {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */ @@ -263,7 +223,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ - {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */ + {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ {TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */ {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */ {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */ @@ -275,11 +235,67 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { }; const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = { - {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */ }; const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = { {VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ }; const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { @@ -302,16 +318,16 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ - {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */ - {GPMC_A20, (M1 | PIN_INPUT)}, /* gpmc_a20.mmc2_dat5 */ - {GPMC_A21, (M1 | PIN_INPUT)}, /* gpmc_a21.mmc2_dat6 */ - {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ - {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */ - {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */ - {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */ - {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */ - {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */ {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */ @@ -351,37 +367,37 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */ - {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ - {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ @@ -394,8 +410,8 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb2_drvvbus.usb2_drvvbus */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ @@ -404,50 +420,50 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ - {MCASP1_FSX, (M11 | PIN_INPUT)}, /* mcasp1_fsx.pr2_mdio_data */ + {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */ - {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */ - {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */ {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr8.pr2_mii0_txen */ - {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr9.pr2_mii0_txd3 */ - {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr10.pr2_mii0_txd2 */ - {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr11.pr2_mii0_txd1 */ - {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr12.pr2_mii0_txd0 */ - {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ - {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */ - {MCASP1_AXR15, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ - {MCASP2_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ - {MCASP2_AXR2, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ - {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */ {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */ {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ - {MCASP3_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.pr2_mii0_col */ - {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */ - {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */ - {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ + {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ - {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */ - {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */ - {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */ - {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */ - {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M14 | PIN_INPUT)}, /* mmc1_sdcd.gpio6_27 */ - {MMC1_SDWP, (M14 | PIN_INPUT)}, /* mmc1_sdwp.gpio6_28 */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ @@ -465,16 +481,16 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ + {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ + {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ + {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ - {SPI2_D1, (M0 | PIN_OUTPUT)}, /* spi2_d1.spi2_d1 */ - {SPI2_D0, (M0 | PIN_INPUT)}, /* spi2_d0.spi2_d0 */ - {SPI2_CS0, (M0 | PIN_OUTPUT)}, /* spi2_cs0.spi2_cs0 */ - {UART1_RXD, (M14 | PIN_OUTPUT)}, /* uart1_rxd.gpio7_22 */ - {UART1_TXD, (M14 | PIN_OUTPUT)}, /* uart1_txd.gpio7_23 */ + {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ + {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */ {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */ {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */ @@ -490,7 +506,7 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ - {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */ + {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */ @@ -498,29 +514,30 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */ + {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */ }; const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { - {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a0.vin1b_d0 */ - {GPMC_A1, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a1.vin1b_d1 */ - {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a2.vin1b_d2 */ - {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a3.vin1b_d3 */ - {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a4.vin1b_d4 */ - {GPMC_A5, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a5.vin1b_d5 */ - {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a6.vin1b_d6 */ - {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a7.vin1b_d7 */ - {GPMC_A8, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a8.vin1b_hsync1 */ - {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a9.vin1b_vsync1 */ - {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a10.vin1b_clk1 */ - {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a11.vin1b_de1 */ - {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a12.vin1b_fld1 */ - {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ - {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ - {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ - {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ - {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN) | MANUAL_MODE}, /* gpmc_a17.qspi1_d1 */ - {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin1b_d0 */ + {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin1b_d1 */ + {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin1b_d2 */ + {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin1b_d3 */ + {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin1b_d4 */ + {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin1b_d5 */ + {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin1b_d6 */ + {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin1b_d7 */ + {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin1b_hsync1 */ + {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin1b_vsync1 */ + {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin1b_clk1 */ + {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin1b_de1 */ + {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin1b_fld1 */ + {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ @@ -531,234 +548,230 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ - {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ - {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ - {GPMC_CS3, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.gpio2_21 */ - {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */ - {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ - {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ - {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ - {GPMC_BEN0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpio2_26 */ - {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */ - {GPMC_WAIT0, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */ + {GPMC_CS0, (M14 | PIN_OUTPUT)}, /* gpmc_cs0.gpio2_19 */ + {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M14 | PIN_OUTPUT)}, /* gpmc_cs3.gpio2_21 */ + {GPMC_CLK, (M14 | PIN_INPUT)}, /* gpmc_clk.gpio2_22 */ + {GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)}, /* gpmc_advn_ale.gpio2_23 */ + {GPMC_OEN_REN, (M14 | PIN_OUTPUT)}, /* gpmc_oen_ren.gpio2_24 */ + {GPMC_WEN, (M14 | PIN_OUTPUT)}, /* gpmc_wen.gpio2_25 */ + {GPMC_BEN0, (M14 | PIN_OUTPUT)}, /* gpmc_ben0.gpio2_26 */ + {GPMC_BEN1, (M14 | PIN_OUTPUT)}, /* gpmc_ben1.gpio2_27 */ + {GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */ - {VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */ - {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ - {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ - {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */ - {VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ - {VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */ - {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ - {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ - {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ - {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ - {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ - {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_VSYNC0, (M14 | PIN_OUTPUT)}, /* vin2a_vsync0.gpio4_0 */ + {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */ + {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ + {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */ + {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ - {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */ - {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ - {RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */ - {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */ - {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */ - {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ - {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ - {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ - {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ - {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ - {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */ + {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart3_txd.gpio5_19 */ + {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ - {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_rxctl.rgmii0_rxctl */ - {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ - {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ - {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ - {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ - {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */ - {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */ - {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */ - {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */ - {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)}, /* xref_clk1.pr2_mii1_crs */ - {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ - {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */ - {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ - {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */ - {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */ - {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */ - {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */ - {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ - {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ - {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */ + {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */ + {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */ + {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */ + {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M7 | PIN_INPUT)}, /* xref_clk3.hdq0 */ + {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ + {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */ + {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */ + {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ - {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ - {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */ - {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M11 | PIN_OUTPUT)}, /* mcasp1_axr8.pr2_mii0_txen */ - {MCASP1_AXR9, (M11 | PIN_OUTPUT)}, /* mcasp1_axr9.pr2_mii0_txd3 */ - {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */ - {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */ - {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */ - {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ - {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */ - {MCASP1_AXR15, (M11 | PIN_INPUT)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ - {MCASP2_ACLKX, (M11 | PIN_INPUT)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ - {MCASP2_FSX, (M11 | PIN_INPUT)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ - {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */ - {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */ - {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */ - {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */ - {MCASP2_AXR2, (M11 | PIN_INPUT)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ - {MCASP2_AXR3, (M11 | PIN_INPUT)}, /* mcasp2_axr3.pr2_mii0_rxlink */ - {MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */ - {MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */ - {MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */ - {MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */ - {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_aclkx.pr2_mii0_crs */ - {MCASP3_FSX, (M11 | PIN_INPUT)}, /* mcasp3_fsx.pr2_mii0_col */ - {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */ - {MCASP3_AXR1, (M11 | PIN_INPUT)}, /* mcasp3_axr1.pr2_mii1_rxlink */ - {MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */ - {MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */ - {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */ - {MCASP4_AXR1, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.spi3_cs0 */ - {MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */ - {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ - {MCASP5_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.Driveroff */ - {MCASP5_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.Driveroff */ + {MCASP1_AXR5, (M14 | PIN_INPUT)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ + {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */ + {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */ + {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */ + {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */ + {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ + {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP4_ACLKX, (M2 | PIN_OUTPUT)}, /* mcasp4_aclkx.spi3_sclk */ + {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */ + {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ + {MCASP5_AXR0, (M4 | PIN_INPUT)}, /* mcasp5_axr0.uart3_rxd */ + {MCASP5_AXR1, (M4 | PIN_OUTPUT)}, /* mcasp5_axr1.uart3_txd */ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ - {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */ - {GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.pr2_mii_mt1_clk */ - {GPIO6_11, (M11 | PIN_OUTPUT)}, /* gpio6_11.pr2_mii1_txen */ - {MMC3_CLK, (M11 | PIN_OUTPUT)}, /* mmc3_clk.pr2_mii1_txd3 */ - {MMC3_CMD, (M11 | PIN_OUTPUT)}, /* mmc3_cmd.pr2_mii1_txd2 */ - {MMC3_DAT0, (M11 | PIN_OUTPUT)}, /* mmc3_dat0.pr2_mii1_txd1 */ - {MMC3_DAT1, (M11 | PIN_OUTPUT)}, /* mmc3_dat1.pr2_mii1_txd0 */ - {MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat2.pr2_mii_mr1_clk */ + {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ + {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ + {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ + {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */ + {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */ + {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */ + {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */ - {MMC3_DAT4, (M11 | PIN_INPUT)}, /* mmc3_dat4.pr2_mii1_rxd3 */ - {MMC3_DAT5, (M11 | PIN_INPUT)}, /* mmc3_dat5.pr2_mii1_rxd2 */ - {MMC3_DAT6, (M11 | PIN_INPUT)}, /* mmc3_dat6.pr2_mii1_rxd1 */ - {MMC3_DAT7, (M11 | PIN_INPUT)}, /* mmc3_dat7.pr2_mii1_rxd0 */ - {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ - {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ - {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ - {SPI1_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs0.gpio7_10 */ - {SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ - {SPI2_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.spi2_sclk */ - {SPI2_D1, (M0 | PIN_INPUT_SLEW)}, /* spi2_d1.spi2_d1 */ - {SPI2_D0, (M0 | PIN_INPUT_SLEW)}, /* spi2_d0.spi2_d0 */ - {SPI2_CS0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ + {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */ + {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */ + {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */ + {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */ + {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ + {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ + {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ + {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {UART1_RXD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ - {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */ - {UART1_RTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rtsn.gpio7_25 */ - {UART2_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_rxd.uart2_rxd */ - {UART2_TXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_txd.uart2_txd */ - {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */ - {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */ - {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ - {WAKEUP0, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup0.Wakeup0 */ - {WAKEUP3, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup3.Wakeup3 */ - {ON_OFF, (M0 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ - {RTC_PORZ, (M0 | PIN_OUTPUT)}, /* rtc_porz.rtc_porz */ + {UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ + {UART1_CTSN, (M14 | PIN_OUTPUT)}, /* uart1_ctsn.gpio7_24 */ + {UART1_RTSN, (M14 | PIN_OUTPUT)}, /* uart1_rtsn.gpio7_25 */ + {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */ + {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */ + {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ - {TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */ + {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */ - {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */ - {RTCK, (M0 | PIN_INPUT)}, /* rtck.rtck */ - {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */ - {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */ - {RESETN, (M0 | PIN_OUTPUT_PULLUP)}, /* resetn.resetn */ - {RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */ + {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */ + {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */ + {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */ + {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */ + {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */ + {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */ }; const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = { /* PR1 MII0 */ - {VOUT1_D8, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.pr1_mii_mt0_clk */ - {VOUT1_D9, (M13 | PIN_OUTPUT)}, /* vout1_d9.pr1_mii0_txd3 */ - {VOUT1_D10, (M13 | PIN_OUTPUT)}, /* vout1_d10.pr1_mii0_txd2 */ - {VOUT1_D11, (M13 | PIN_OUTPUT)}, /* vout1_d11.pr1_mii0_txen */ - {VOUT1_D12, (M13 | PIN_OUTPUT)}, /* vout1_d12.pr1_mii0_txd1 */ - {VOUT1_D13, (M13 | PIN_OUTPUT)}, /* vout1_d13.pr1_mii0_txd0 */ - {VOUT1_D14, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.pr1_mii_mr0_clk */ + {VOUT1_D8, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d8.pr1_mii_mt0_clk */ + {VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d9.pr1_mii0_txd3 */ + {VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d10.pr1_mii0_txd2 */ + {VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d11.pr1_mii0_txen */ + {VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d12.pr1_mii0_txd1 */ + {VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d13.pr1_mii0_txd0 */ + {VOUT1_D14, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d14.pr1_mii_mr0_clk */ {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */ - {VOUT1_D16, (M12 | PIN_INPUT)}, /* vout1_d16.pr1_mii0_rxd3 */ - {VOUT1_D17, (M12 | PIN_INPUT)}, /* vout1_d17.pr1_mii0_rxd2 */ - {VOUT1_D18, (M12 | PIN_INPUT)}, /* vout1_d18.pr1_mii0_rxd1 */ - {VOUT1_D19, (M12 | PIN_INPUT)}, /* vout1_d19.pr1_mii0_rxd0 */ + {VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.pr1_mii0_rxd3 */ + {VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.pr1_mii0_rxd2 */ + {VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.pr1_mii0_rxd1 */ + {VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.pr1_mii0_rxd0 */ {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */ - {VOUT1_D21, (M12 | PIN_INPUT)}, /* vout1_d21.pr1_mii0_rxlink */ - {VOUT1_D22, (M12 | PIN_INPUT)}, /* vout1_d22.pr1_mii0_col */ - {VOUT1_D23, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d23.pr1_mii0_crs */ + {VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.pr1_mii0_rxlink */ + {VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.pr1_mii0_col */ + {VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.pr1_mii0_crs */ /* PR1 MII1 */ - {VIN2A_D3, (M12 | PIN_INPUT)}, /* vin2a_d3.pr1_mi1_col */ - {VIN2A_D4, (M13 | PIN_OUTPUT)}, /* vin2a_d4.pr1_mii1_txd1 */ - {VIN2A_D5, (M13 | PIN_OUTPUT)}, /* vin2a_d5.pr1_mii1_txd0 */ - {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */ - {VIN2A_D7, (M11 | PIN_OUTPUT)}, /* vin2a_d7.pr1_mii1_txen */ - {VIN2A_D8, (M11 | PIN_OUTPUT)}, /* vin2a_d8.pr1_mii1_txd3 */ - {VIN2A_D9, (M11 | PIN_OUTPUT)}, /* vin2a_d9.pr1_mii1_txd2 */ + {VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mii1_col */ + {VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d4.pr1_mii1_txd1 */ + {VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.pr1_mii1_txd0 */ + {VIN2A_D6, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d6.pr1_mii_mt1_clk */ + {VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d7.pr1_mii1_txen */ + {VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d8.pr1_mii1_txd3 */ + {VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d9.pr1_mii1_txd2 */ {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */ - {VOUT1_D0, (M12 | PIN_INPUT)}, /* vout1_d0.pr1_mii1_rxlink */ - {VOUT1_D1, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d1.pr1_mii1_crs */ - {VOUT1_D2, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.pr1_mii_mr1_clk */ + {VOUT1_D0, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d0.pr1_mii1_rxlink */ + {VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.pr1_mii1_crs */ + {VOUT1_D2, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d2.pr1_mii_mr1_clk */ {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */ - {VOUT1_D4, (M12 | PIN_INPUT)}, /* vout1_d4.pr1_mii1_rxd3 */ - {VOUT1_D5, (M12 | PIN_INPUT)}, /* vout1_d5.pr1_mii1_rxd2 */ - {VOUT1_D6, (M12 | PIN_INPUT)}, /* vout1_d6.pr1_mii1_rxd1 */ - {VOUT1_D7, (M12 | PIN_INPUT)}, /* vout1_d7.pr1_mii1_rxd0 */ + {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.pr1_mii1_rxd3 */ + {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.pr1_mii1_rxd2 */ + {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.pr1_mii1_rxd1 */ + {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.pr1_mii1_rxd0 */ }; const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = { - {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ - {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */ + + {MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpi1 */ + {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ + {UART2_RXD, (M0 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */ + {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */ + {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */ }; const struct pad_conf_entry early_padconf[] = { @@ -798,6 +811,36 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = { {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ + {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */ + {0x0678, 406, 0}, /* CFG_MMC3_CLK_IN */ + {0x0680, 659, 0}, /* CFG_MMC3_CLK_OUT */ + {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */ + {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */ + {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */ + {0x0690, 130, 0}, /* CFG_MMC3_DAT0_IN */ + {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */ + {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */ + {0x069C, 169, 0}, /* CFG_MMC3_DAT1_IN */ + {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */ + {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */ + {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */ + {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */ + {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */ + {0x06B4, 457, 0}, /* CFG_MMC3_DAT3_IN */ + {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */ + {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */ + {0x06C0, 702, 0}, /* CFG_MMC3_DAT4_IN */ + {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */ + {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */ + {0x06CC, 738, 0}, /* CFG_MMC3_DAT5_IN */ + {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */ + {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */ + {0x06D8, 856, 0}, /* CFG_MMC3_DAT6_IN */ + {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */ + {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */ + {0x06E4, 610, 0}, /* CFG_MMC3_DAT7_IN */ + {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */ + {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ @@ -815,7 +858,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = { {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ @@ -871,6 +914,18 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = { {0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */ {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */ {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */ + {0x06C0, 792, 0}, /* CFG_MMC3_DAT4_IN */ + {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */ + {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */ + {0x06CC, 782, 0}, /* CFG_MMC3_DAT5_IN */ + {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */ + {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */ + {0x06D8, 942, 0}, /* CFG_MMC3_DAT6_IN */ + {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */ + {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */ + {0x06E4, 636, 0}, /* CFG_MMC3_DAT7_IN */ + {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */ + {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */ {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */ {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */ {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */ @@ -895,6 +950,34 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = { {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */ {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */ + {0x0B9C, 0, 706}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 2313, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 2199, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 2266, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 3159, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 2100, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 2229, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 2202, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 2084, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 2195, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 2342, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 2463, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 2439, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 2304, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 2103, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 2145, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 1932, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 2200, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 2355, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 3215, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 2314, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 2238, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 2381, 0}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 2138, 0}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 2383, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 1984, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 1947, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */ }; const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = { @@ -921,68 +1004,113 @@ const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = { {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ {0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */ {0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */ - {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */ - {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */ - {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */ - {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */ - {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */ - {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */ - {0x0740, 90, 70}, /* CFG_RGMII0_TXC_OUT */ - {0x074C, 70, 70}, /* CFG_RGMII0_TXCTL_OUT */ - {0x0758, 180, 70}, /* CFG_RGMII0_TXD0_OUT */ - {0x0764, 35, 70}, /* CFG_RGMII0_TXD1_OUT */ - {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ - {0x077C, 180, 70}, /* CFG_RGMII0_TXD3_OUT */ - {0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */ - {0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */ - {0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */ - {0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */ - {0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ - {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */ - {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */ - {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */ - {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ - {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ - {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ + {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */ {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */ + {0x0B9C, 1126, 751}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 395, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 282, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 348, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 1240, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 182, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 311, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 285, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 166, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 278, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 425, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 516, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 521, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 386, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 111, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 227, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 0, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 282, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 438, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 1298, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 397, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 321, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 155, 309}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 212, 0}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 466, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 139, 701}, /* CFG_VOUT1_VSYNC_OUT */ }; const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = { - {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ - {0x0150, 2062, 2277}, /* CFG_GPMC_A14_IN */ - {0x015C, 1960, 2289}, /* CFG_GPMC_A15_IN */ - {0x0168, 2058, 2386}, /* CFG_GPMC_A16_IN */ - {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ - {0x0174, 2062, 2350}, /* CFG_GPMC_A17_IN */ - {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ - {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */ - {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */ - {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */ - {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */ - {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */ - {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */ - {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */ - {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */ - {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */ - {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */ - {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ - {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */ - {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */ - {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */ - {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */ - {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */ - {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ - {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */ - {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */ - {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */ - {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */ - {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */ - {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */ - {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */ - {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */ + {0x0114, 1873, 702}, /* CFG_GPMC_A0_IN */ + {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 1851, 1011}, /* CFG_GPMC_A11_IN */ + {0x0138, 2009, 601}, /* CFG_GPMC_A12_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */ + {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */ + {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x0198, 1629, 772}, /* CFG_GPMC_A1_IN */ + {0x0204, 1734, 898}, /* CFG_GPMC_A2_IN */ + {0x0210, 1757, 1076}, /* CFG_GPMC_A3_IN */ + {0x021C, 1794, 893}, /* CFG_GPMC_A4_IN */ + {0x0228, 1726, 853}, /* CFG_GPMC_A5_IN */ + {0x0234, 1792, 612}, /* CFG_GPMC_A6_IN */ + {0x0240, 2117, 610}, /* CFG_GPMC_A7_IN */ + {0x024C, 1758, 653}, /* CFG_GPMC_A8_IN */ + {0x0258, 1705, 899}, /* CFG_GPMC_A9_IN */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ + {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */ }; +const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = { + {0x0588, 2100, 1959}, /* CFG_MCASP5_ACLKX_IN */ + {0x05AC, 2100, 1780}, /* CFG_MCASP5_FSX_IN */ + {0x0B30, 0, 400}, /* CFG_VIN2A_D5_OUT */ +}; #endif #endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 00d127e..887b577 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -443,13 +443,13 @@ int misc_init_r(void) printf("Recognized BeagleBoardToys WiFi board\n"); MUX_BBTOYS_WIFI() setenv("buddy", "bbtoys-wifi"); - break;; + break; case BBTOYS_VGA: printf("Recognized BeagleBoardToys VGA board\n"); - break;; + break; case BBTOYS_LCD: printf("Recognized BeagleBoardToys LCD board\n"); - break;; + break; case BCT_BRETTL3: printf("Recognized bct electronic GmbH brettl3 board\n"); break; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 8c02add..7d36f03 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -561,6 +561,7 @@ int board_late_init(void) setenv("boot_fit", "1"); omap_die_id_serial(); + omap_set_fastboot_vars(); #endif return 0; } diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 21aec8f..f0bd31d 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -79,29 +79,29 @@ static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { [SPD400] = {MAIN_PLL, 125, 3, 2}, [SPD600] = {MAIN_PLL, 125, 2, 2}, [SPD800] = {MAIN_PLL, 250, 3, 2}, - [SPD900] = {TETRIS_PLL, 187, 2, 2}, - [SPD1000] = {TETRIS_PLL, 104, 1, 2}, + [SPD900] = {MAIN_PLL, 187, 2, 2}, + [SPD1000] = {MAIN_PLL, 104, 1, 2}, }, [SYSCLK_24MHz] = { [SPD400] = {MAIN_PLL, 100, 3, 2}, [SPD600] = {MAIN_PLL, 300, 6, 2}, [SPD800] = {MAIN_PLL, 200, 3, 2}, - [SPD900] = {TETRIS_PLL, 75, 1, 2}, - [SPD1000] = {TETRIS_PLL, 250, 3, 2}, + [SPD900] = {MAIN_PLL, 75, 1, 2}, + [SPD1000] = {MAIN_PLL, 250, 3, 2}, }, [SYSCLK_25MHz] = { [SPD400] = {MAIN_PLL, 32, 1, 2}, [SPD600] = {MAIN_PLL, 48, 1, 2}, [SPD800] = {MAIN_PLL, 64, 1, 2}, - [SPD900] = {TETRIS_PLL, 72, 1, 2}, - [SPD1000] = {TETRIS_PLL, 80, 1, 2}, + [SPD900] = {MAIN_PLL, 72, 1, 2}, + [SPD1000] = {MAIN_PLL, 80, 1, 2}, }, [SYSCLK_26MHz] = { [SPD400] = {MAIN_PLL, 400, 13, 2}, [SPD600] = {MAIN_PLL, 230, 5, 2}, [SPD800] = {MAIN_PLL, 123, 2, 2}, - [SPD900] = {TETRIS_PLL, 69, 1, 2}, - [SPD1000] = {TETRIS_PLL, 384, 5, 2}, + [SPD900] = {MAIN_PLL, 69, 1, 2}, + [SPD1000] = {MAIN_PLL, 384, 5, 2}, }, }; diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index b6cc417..4b25cc2 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 72aabb2..6ffb53c 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index b6bf162..577e60f 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -24,12 +24,14 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NAND) + gpmc_init(); +#endif return 0; } #ifdef CONFIG_SPL_BUILD - static struct module_pin_mux mmc_pin_mux[] = { { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, @@ -41,176 +43,68 @@ static struct module_pin_mux mmc_pin_mux[] = { { -1 }, }; -const struct dmm_lisa_map_regs evm_lisa_map_regs = { - .dmm_lisa_map_0 = 0x00000000, - .dmm_lisa_map_1 = 0x00000000, - .dmm_lisa_map_2 = 0x80640300, - .dmm_lisa_map_3 = 0xC0640320, -}; - -/* - * DDR2 related definitions - */ -#ifdef CONFIG_TI816X_EVM_DDR2 -static struct ddr_data ddr2_data = { - .datardsratio0 = ((0x40<<10) | (0x40<<0)), - .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)), - .datawiratio0 = ((0x0<<10) | (0x0<<0)), - .datagiratio0 = ((0x0<<10) | (0x0<<0)), - .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), - .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), -}; - -static struct cmd_control ddr2_ctrl = { - .cmd0csratio = 0x80, - .cmd0iclkout = 0x00, - - .cmd1csratio = 0x80, - .cmd1iclkout = 0x00, - - .cmd2csratio = 0x80, - .cmd2iclkout = 0x00, - -}; - -static struct emif_regs ddr2_emif0_regs = { - .sdram_config = 0x43801A3A, - .ref_ctrl = 0x10000C30, - .sdram_tim1 = 0x0AAB15E2, - .sdram_tim2 = 0x423631D2, - .sdram_tim3 = 0x0080032F, - .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ -}; +void set_uart_mux_conf(void) {} -static struct emif_regs ddr2_emif1_regs = { - .sdram_config = 0x43801A3A, - .ref_ctrl = 0x10000C30, - .sdram_tim1 = 0x0AAB15E2, - .sdram_tim2 = 0x423631D2, - .sdram_tim3 = 0x0080032F, - .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ -}; -#endif +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc_pin_mux); +} /* - * DDR3 related definitions + * EMIF Paramters. Refer the EMIF register documentation and the + * memory datasheet for details. This is for 796 MHz. */ - -#if defined(CONFIG_TI816X_DDR_PLL_400) -#define RD_DQS 0x03B -#define WR_DQS 0x0A6 -#define RD_DQS_GATE 0x12A -#define EMIF_SDCFG 0x62A41032 -#define EMIF_SDREF 0x10000C30 -#define EMIF_TIM1 0x0CCCE524 -#define EMIF_TIM2 0x30308023 -#define EMIF_TIM3 0x009F82CF -#define EMIF_PHYCFG 0x0000010B -#elif defined(CONFIG_TI816X_DDR_PLL_531) -#define RD_DQS 0x039 -#define WR_DQS 0x0B4 -#define RD_DQS_GATE 0x13D -#define EMIF_SDCFG 0x62A51832 -#define EMIF_SDREF 0x1000102E -#define EMIF_TIM1 0x0EF136AC -#define EMIF_TIM2 0x30408063 -#define EMIF_TIM3 0x009F83AF -#define EMIF_PHYCFG 0x0000010C -#elif defined(CONFIG_TI816X_DDR_PLL_675) -#define RD_DQS 0x039 -#define WR_DQS 0x091 -#define RD_DQS_GATE 0x196 -#define EMIF_SDCFG 0x62A63032 -#define EMIF_SDREF 0x10001491 -#define EMIF_TIM1 0x13358875 -#define EMIF_TIM2 0x5051806C -#define EMIF_TIM3 0x009F84AF -#define EMIF_PHYCFG 0x0000010F -#elif defined(CONFIG_TI816X_DDR_PLL_796) -#define RD_DQS 0x035 -#define WR_DQS 0x093 -#define RD_DQS_GATE 0x1B3 -#define EMIF_SDCFG 0x62A73832 -#define EMIF_SDREF 0x10001841 -#define EMIF_TIM1 0x1779C9FE -#define EMIF_TIM2 0x50608074 -#define EMIF_TIM3 0x009F857F -#define EMIF_PHYCFG 0x00000110 -#endif - -static struct ddr_data ddr3_data = { - .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), - .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), - .datawiratio0 = ((0x20<<10) | 0x20<<0), - .datagiratio0 = ((0x20<<10) | 0x20<<0), - .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), - .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_SDREF 0x10001841 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_PHYCFG 0x00000110 +static const struct emif_regs ddr3_emif_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, }; static const struct cmd_control ddr3_ctrl = { .cmd0csratio = 0x100, .cmd0iclkout = 0x001, - .cmd1csratio = 0x100, .cmd1iclkout = 0x001, - .cmd2csratio = 0x100, .cmd2iclkout = 0x001, }; -static const struct emif_regs ddr3_emif0_regs = { - .sdram_config = EMIF_SDCFG, - .ref_ctrl = EMIF_SDREF, - .sdram_tim1 = EMIF_TIM1, - .sdram_tim2 = EMIF_TIM2, - .sdram_tim3 = EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +/* These values are obtained from the CCS app */ +#define RD_DQS_GATE (0x1B3) +#define RD_DQS (0x35) +#define WR_DQS (0x93) +static struct ddr_data ddr3_data = { + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), + .datawiratio0 = ((0x20<<10) | 0x20<<0), + .datagiratio0 = ((0x20<<10) | 0x20<<0), + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), }; -static const struct emif_regs ddr3_emif1_regs = { - .sdram_config = EMIF_SDCFG, - .ref_ctrl = EMIF_SDREF, - .sdram_tim1 = EMIF_TIM1, - .sdram_tim2 = EMIF_TIM2, - .sdram_tim3 = EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +static const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, }; -void set_uart_mux_conf(void) {} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(mmc_pin_mux); -} - void sdram_init(void) { - config_dmm(&evm_lisa_map_regs); - -#ifdef CONFIG_TI816X_EVM_DDR2 - if (CONFIG_TI816X_USE_EMIF0) { - ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = - (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, - 0); - } - - if (CONFIG_TI816X_USE_EMIF1) { - ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = - (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, - 1); - } -#endif - -#ifdef CONFIG_TI816X_EVM_DDR3 - if (CONFIG_TI816X_USE_EMIF0) - config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, - 0); - - if (CONFIG_TI816X_USE_EMIF1) - config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, - 1); -#endif + /* + * Pass in our DDR3 config information and that we have 2 EMIFs to + * configure. + */ + config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs, + &evm_lisa_map_regs, 2); } #endif /* CONFIG_SPL_BUILD */ diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c new file mode 100644 index 0000000..ec0cc7d --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -0,0 +1,227 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../ps7_init_gpl.h" + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U), + EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU), + EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt new file mode 100644 index 0000000..db6e642 --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt @@ -0,0 +1,61 @@ +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) +0xf8000700 0x202 +0xf8000704 0x202 +0xf8000708 0x202 +0xf800070c 0x202 +0xf8000710 0x202 +0xf8000714 0x202 +0xf8000718 0x202 +0xf800071c 0x200 +0xf8000720 0x202 +0xf8000724 0x202 +0xf8000728 0x202 +0xf800072c 0x202 +0xf8000730 0x202 +0xf8000734 0x202 +0xf8000738 0x12e1 +0xf800073c 0x12e0 +0xf8000740 0x1200 +0xf8000744 0x1200 +0xf8000748 0x1200 +0xf800074c 0x1200 +0xf8000750 0x1200 +0xf8000754 0x1200 +0xf8000758 0x1200 +0xf800075c 0x1200 +0xf8000760 0x1200 +0xf8000764 0x200 +0xf8000768 0x1200 +0xf800076c 0x200 +0xf8000770 0x304 +0xf8000774 0x305 +0xf8000778 0x304 +0xf800077c 0x305 +0xf8000780 0x304 +0xf8000784 0x304 +0xf8000788 0x304 +0xf800078c 0x304 +0xf8000790 0x305 +0xf8000794 0x304 +0xf8000798 0x304 +0xf800079c 0x304 +0xf80007a0 0x380 +0xf80007a4 0x380 +0xf80007a8 0x380 +0xf80007ac 0x380 +0xf80007b0 0x380 +0xf80007b4 0x380 +0xf80007b8 0x1200 +0xf80007bc 0x1200 +0xf80007c0 0x1240 +0xf80007c4 0x1240 +0xf80007c8 0x1240 +0xf80007cc 0x1240 +0xf80007d0 0x1200 +0xf80007d4 0x1200 +0xf8000830 0x380037 +0xf8000834 0x3a0039 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) +0xE000D000 0x800238C1 // QSPI config - divide-by-2 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay +0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 5d62e66..85afecf 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 2a810c8..68ec436 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -23,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 2c6fc40..0d26787 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -9,6 +9,7 @@ #include #include "tdx-cfg-block.h" +#include #include "tdx-common.h" #ifdef CONFIG_TDX_CFG_BLOCK diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig deleted file mode 100644 index 738dc80..0000000 --- a/board/tqc/tqm5200/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_CHARON - -config SYS_BOARD - default "tqm5200" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "charon" - -endif - -if TARGET_TQM5200 - -config SYS_BOARD - default "tqm5200" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM5200" - -endif diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS deleted file mode 100644 index 12d143d..0000000 --- a/board/tqc/tqm5200/MAINTAINERS +++ /dev/null @@ -1,23 +0,0 @@ -TQM5200 BOARD -#M: - -S: Maintained -F: board/tqc/tqm5200/ -F: include/configs/aev.h -F: configs/aev_defconfig -F: include/configs/TQM5200.h -F: configs/cam5200_defconfig -F: configs/cam5200_niosflash_defconfig -F: configs/fo300_defconfig -F: configs/MiniFAP_defconfig -F: configs/TQM5200_defconfig -F: configs/TQM5200_B_defconfig -F: configs/TQM5200_B_HIGHBOOT_defconfig -F: configs/TQM5200_STK100_defconfig -F: configs/TQM5200S_defconfig -F: configs/TQM5200S_HIGHBOOT_defconfig - -CHARON BOARD -M: Heiko Schocher -S: Maintained -F: include/configs/charon.h -F: configs/charon_defconfig diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile deleted file mode 100644 index f7c97b7..0000000 --- a/board/tqc/tqm5200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := tqm5200.o cmd_stk52xx.o cam5200_flash.o diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c deleted file mode 100644 index c3ae5c0..0000000 --- a/board/tqc/tqm5200/cam5200_flash.c +++ /dev/null @@ -1,768 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) - -#if 0 -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif - -#define swap16(x) __swab16(x) - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CAM5200 is a TQM5200B based board. Additionally it also features - * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx - * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as - * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes - * access to flash chip slightly more complicated as additional byte - * swapping is necessary within each 16 bit wide flash 'word'. - * - * This driver's task is to handle both flash devices: 32 bit TQM5200B - * flash chip and 16 bit NIOS cpu flash chip. In the below - * flash_addr_table table we use least significant address bit to mark - * 16 bit flash bank and two sets of routines *_32 and *_16 to handle - * specifics of both flashes. - */ -static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { - {CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1} -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word_32(flash_info_t * info, ulong dest, ulong data); -static int write_word_16(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_32(flash_info_t * info, int s_first, int s_last); -static int flash_erase_16(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_32(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_16(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i, k; - int size, erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_S29GL128N: - printf ("S29GL128N (256 Mbit, uniform sector size)\n"); - break; - case FLASH_AM320B: - printf ("29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("29LV320T (32 Mbit, top boot sect)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - - printf(" %08lX%s%s", info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - - DEBUGF("get_size: FLASH ADDR %08lx\n", addr); - - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) - return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info); - else - return flash_get_size_32(addr, info); -} - -static ulong flash_get_size_32(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case AMD_ID_MIRROR: - DEBUGF("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - switch(addr[14]) { - case AMD_ID_GL128N_2: - if (addr[15] != AMD_ID_GL128N_3) { - DEBUGF("Chip: S29GL128N -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - DEBUGF("Chip: S29GL128N\n"); - info->flash_id += FLASH_S29GL128N; - info->sector_count = 128; - info->size = 0x02000000; - } - break; - default: - info->flash_id = FLASH_UNKNOWN; - return(0); - } - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00040000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_32(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { - return flash_erase_16(info, s_first, s_last); - } else { - return flash_erase_32(info, s_first, s_last); - } -} - -static int flash_erase_32(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_32(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { - return write_word_16(info, dest, data); - } else { - return write_word_32(info, dest, data); - } -} - -static int write_word_32(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - ulong *datap = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = - (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap; - ulong start; - int i, flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV - -#undef CONFIG_SYS_FLASH_WORD_SIZE -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr); - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000; - udelay(1000); - - value = swap16(addr2[0]); - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = swap16(addr2[1]); /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000a000; - info->start[6] = base + 0x0000c000; - info->start[7] = base + 0x0000e000; - - for (i = 8; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; - - return (info->size); -} - -static int wait_for_DQ7_16(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_16(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ - - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_16(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_16(flash_info_t * info, ulong dest, ulong data) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - ulong *datap = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = - (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - if ((dest2[i] & swap16(data2[i])) != swap16(data2[i])) - return (2); - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000; - - dest2[i] = swap16(data2[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != - (swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) - continue; - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - - flash_info[i].size = size_b[i]; - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i+1, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - total_b += flash_info[i].size; - } - - return total_b; -} -#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */ diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c deleted file mode 100644 index dc22ee4..0000000 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ /dev/null @@ -1,1228 +0,0 @@ -/* - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * STK52XX specific functions - */ -/*#define DEBUG*/ - -#include -#include -#include - -#if defined(CONFIG_CMD_BSP) - -#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) -#define DEFAULT_VOL 45 -#define DEFAULT_FREQ 500 -#define DEFAULT_DURATION 200 -#define LEFT 1 -#define RIGHT 2 -#define LEFT_RIGHT 3 -#define BL_OFF 0 -#define BL_ON 1 - -#define SM501_GPIO_CTRL_LOW 0x00000008UL -#define SM501_GPIO_CTRL_HIGH 0x0000000CUL -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_LOW 0x00010000UL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL - -static int i2s_squarewave(unsigned long duration, unsigned int freq, - unsigned int channel); -static int i2s_sawtooth(unsigned long duration, unsigned int freq, - unsigned int channel); -static void spi_init(void); -static int spi_transmit(unsigned char data); -static void pcm1772_write_reg(unsigned char addr, unsigned char data); -static void set_attenuation(unsigned char attenuation); - -static void spi_init(void) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - /* PSC3 as SPI and GPIOs */ - gpio->port_config &= 0xFFFFF0FF; - gpio->port_config |= 0x00000800; - /* - * Its important to use the correct order when initializing the - * registers - */ - spi->ddr = 0x0F; /* set all SPI pins as output */ - spi->pdr = 0x08; /* set SS high */ - spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */ - spi->cr2 = 0x00; /* normal operation */ - spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */ -} - -static int spi_transmit(unsigned char data) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - - spi->dr = data; - /* wait for SPI transmission completed */ - while (!(spi->sr & 0x80)) { - if (spi->sr & 0x40) { /* if write collision occurred */ - int dummy; - - /* do dummy read to clear status register */ - dummy = spi->dr; - printf("SPI write collision: dr=0x%x\n", dummy); - return -1; - } - } - return (spi->dr); -} - -static void pcm1772_write_reg(unsigned char addr, unsigned char data) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - - spi->pdr = 0x00; /* Set SS low */ - spi_transmit(addr); - spi_transmit(data); - /* wait some time to meet MS# hold time of PCM1772 */ - udelay (1); - spi->pdr = 0x08; /* set SS high */ -} - -static void set_attenuation(unsigned char attenuation) -{ - pcm1772_write_reg(0x01, attenuation); /* left channel */ - debug ("PCM1772 attenuation left set to %d.\n", attenuation); - pcm1772_write_reg(0x02, attenuation); /* right channel */ - debug ("PCM1772 attenuation right set to %d.\n", attenuation); -} - -void amplifier_init(void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - /* Do this only once, because of the long time delay */ - if (!init_done) { - /* configure PCM1772 audio format as I2S */ - pcm1772_write_reg(0x03, 0x01); - /* enable audio amplifier */ - gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */ - gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */ - gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */ - gpio->sint_ddr |= 0x02; /* PSC3_5 as output */ - /* - * wait some time to allow amplifier to recover from shutdown - * mode. - */ - for(i = 0; i < 350; i++) - udelay(1000); - /* - * The used amplifier (LM4867) has a so called "pop and click" - * elmination filter. The input signal of the amplifier must - * exceed a certain level once after power up to activate the - * generation of the output signal. This is achieved by - * sending a low frequent (nearly inaudible) sawtooth with a - * sufficient signal level. - */ - set_attenuation(50); - i2s_sawtooth (200, 5, LEFT_RIGHT); - init_done = 1; - } -} - -static void i2s_init(void) -{ - unsigned long i; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */ - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - psc->sicr = 0x22E00000; /* 16 bit data; I2S */ - - *(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK - * 5.617 MHz */ - *(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable - * register */ - psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ - psc->ctur = 0x0F; /* 16 bit frame width */ - - for (i = 0; i < 128; i++) - psc->psc_buffer_32 = 0; /* clear tx fifo */ -} - -static int i2s_play_wave(unsigned long addr, unsigned long len) -{ - unsigned long i; - unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip - * wav header*/ - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - /* - * play wave file in memory; bytes/words are be swapped - */ - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - for(i = 0;i < (len / 4); i++) { - unsigned char swapped[4]; - unsigned long *p = (unsigned long*)swapped; - - swapped[3] = *wave_file++; - swapped[2] = *wave_file++; - swapped[1] = *wave_file++; - swapped[0] = *wave_file++; - - psc->psc_buffer_32 = *p; - - while (psc->tfnum > 400) { - if(ctrlc()) - return 0; - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - return 0; -} - -static int i2s_sawtooth(unsigned long duration, unsigned int freq, - unsigned int channel) -{ - long i,j; - unsigned long data; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - /* - * Generate sawtooth. Start with middle level up to highest level. Then - * go to lowest level and back to middle level. - */ - for(j = 0; j < ((duration * freq) / 1000); j++) { - for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - - return 0; -} - -static int i2s_squarewave(unsigned long duration, unsigned int freq, - unsigned int channel) -{ - long i,j; - unsigned long data; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - /* - * Generate sqarewave. Start with high level, duty cycle 1:1. - */ - for(j = 0; j < ((duration * freq) / 1000); j++) { - for(i = 0; i < (44100/(freq*2)); i ++) { - data = 0x7FFF; - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = 0; i < (44100/(freq*2)); i ++) { - data = 0x8000; - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - - return 0; -} - -static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned long reg, val, duration; - char *tmp; - unsigned int freq, channel; - unsigned char volume; - int rcode = 1; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - if ((tmp = getenv ("volume")) != NULL) { - volume = simple_strtoul (tmp, NULL, 10); - } else { - volume = DEFAULT_VOL; - } - set_attenuation(volume); - - switch (argc) { - case 0: - case 1: - return cmd_usage(cmdtp); - case 2: - if (strncmp(argv[1],"saw",3) == 0) { - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - printf ("Play squarewave\n"); - rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } - - return cmd_usage(cmdtp); - case 3: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (duration, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } - return cmd_usage(cmdtp); - case 4: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (duration, freq, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, freq, - LEFT_RIGHT); - return rcode; - } else if (strcmp(argv[1],"pcm1772") == 0) { - reg = simple_strtoul(argv[2], NULL, 10); - val = simple_strtoul(argv[3], NULL, 10); - printf("Set PCM1772 %lu. %lu\n", reg, val); - pcm1772_write_reg((uchar)reg, (uchar)val); - return 0; - } - return cmd_usage(cmdtp); - case 5: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - if (strncmp(argv[4],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[4],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - printf ("Play squarewave\n"); - rcode = i2s_sawtooth (duration, freq, - channel); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - if (strncmp(argv[4],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[4],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, freq, - channel); - return rcode; - } - return cmd_usage(cmdtp); - } - printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); - return 1; -} - -static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned long length, addr; - unsigned char volume; - int rcode = 1; - char *tmp; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - switch (argc) { - - case 3: - length = simple_strtoul(argv[2], NULL, 16); - addr = simple_strtoul(argv[1], NULL, 16); - break; - - case 2: - if ((tmp = getenv ("filesize")) != NULL) { - length = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No filesize provided\n"); - return 1; - } - addr = simple_strtoul(argv[1], NULL, 16); - - case 1: - if ((tmp = getenv ("filesize")) != NULL) { - length = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No filesize provided\n"); - return 1; - } - if ((tmp = getenv ("loadaddr")) != NULL) { - addr = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No loadaddr provided\n"); - return 1; - } - break; - - default: - printf("Usage:\nwav port_config &= ~(0x00000F00); - gpio->port_config |= 0x00000800; - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000F00; - - /* configure timer 4-7 for simple GPIO output */ - gpt->gpt4.emsr |= 0x00000024; - gpt->gpt5.emsr |= 0x00000024; - gpt->gpt6.emsr |= 0x00000024; - gpt->gpt7.emsr |= 0x00000024; - -#ifndef CONFIG_TQM5200S - /* enable SM501 GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - - /* configure SM501 gpio pins 24-27 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24); - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24); - - /* configure SM501 gpio pins 48-51 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); -#endif /* !CONFIG_TQM5200S */ -} - -/* - * return 1 if led number unknown - * return 0 else - */ -int do_led(char * const argv[]) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 0: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 8); - } else { - gpio->simple_dvo &= ~(1 << 8); - } - break; - - case 1: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 9); - } else { - gpio->simple_dvo &= ~(1 << 9); - } - break; - - case 2: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 10); - } else { - gpio->simple_dvo &= ~(1 << 10); - } - break; - - case 3: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 11); - } else { - gpio->simple_dvo &= ~(1 << 11); - } - break; - - case 4: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt4.emsr |= (1 << 4); - } else { - gpt->gpt4.emsr &= ~(1 << 4); - } - break; - - case 5: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt5.emsr |= (1 << 4); - } else { - gpt->gpt5.emsr &= ~(1 << 4); - } - break; - - case 6: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt6.emsr |= (1 << 4); - } else { - gpt->gpt6.emsr &= ~(1 << 4); - } - break; - - case 7: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt7.emsr |= (1 << 4); - } else { - gpt->gpt7.emsr &= ~(1 << 4); - } - break; -#ifndef CONFIG_TQM5200S - case 24: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 24); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 24); - } - break; - - case 25: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 25); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 25); - } - break; - - case 26: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 26); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 26); - } - break; - - case 27: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 27); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 27); - } - break; - - case 48: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 16); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 16); - } - break; - - case 49: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 17); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 17); - } - break; - - case 50: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 18); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 18); - } - break; - - case 51: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 19); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 19); - } - break; -#endif /* !CONFIG_TQM5200S */ - default: - printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); - return 1; - } - - return 0; -} -#endif - -#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) -/* - * return 1 on CAN initialization failure - * return 0 if no failure - */ -int can_init(void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); - - /* GPIO configuration of the CAN pins is done in TQM5200.h */ - - if (!init_done) { - /* init CAN 1 */ - can1->canctl1 |= 0x80; /* CAN enable */ - udelay(100); - - i = 0; - can1->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can1->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can1->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can1->canctl1 & 0x01)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can1->canctl1 = 0x80; - can1->canctl1 |= 0x40; - can1->canbtr0 = 0x0F; - can1->canbtr1 = 0x7F; - can1->canidac &= ~(0x30); - can1->canidar1 = 0x00; - can1->canidar3 = 0x00; - can1->canidar5 = 0x00; - can1->canidar7 = 0x00; - can1->canidmr0 = 0xFF; - can1->canidmr1 = 0xFF; - can1->canidmr2 = 0xFF; - can1->canidmr3 = 0xFF; - can1->canidmr4 = 0xFF; - can1->canidmr5 = 0xFF; - can1->canidmr6 = 0xFF; - can1->canidmr7 = 0xFF; - - i = 0; - can1->canctl0 &= ~(0x01); /* leave init mode */ - can1->canctl0 &= ~(0x02); - /* wait until init and sleep mode left */ - while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - - /* init CAN 2 */ - can2->canctl1 |= 0x80; /* CAN enable */ - udelay(100); - - i = 0; - can2->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can2->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can2->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can2->canctl1 & 0x01)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can2->canctl1 = 0x80; - can2->canctl1 |= 0x40; - can2->canbtr0 = 0x0F; - can2->canbtr1 = 0x7F; - can2->canidac &= ~(0x30); - can2->canidar1 = 0x00; - can2->canidar3 = 0x00; - can2->canidar5 = 0x00; - can2->canidar7 = 0x00; - can2->canidmr0 = 0xFF; - can2->canidmr1 = 0xFF; - can2->canidmr2 = 0xFF; - can2->canidmr3 = 0xFF; - can2->canidmr4 = 0xFF; - can2->canidmr5 = 0xFF; - can2->canidmr6 = 0xFF; - can2->canidmr7 = 0xFF; - can2->canctl0 &= ~(0x01); /* leave init mode */ - can2->canctl0 &= ~(0x02); - - i = 0; - /* wait until init mode left */ - while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - init_done = 1; - } - return 0; -} - -/* - * return 1 on CAN failure - * return 0 if no failure - */ -int do_can(char * const argv[]) -{ - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); - - /* send a message on CAN1 */ - can1->cantbsel = 0x01; - can1->cantxfg.idr[0] = 0x55; - can1->cantxfg.idr[1] = 0x00; - can1->cantxfg.idr[1] &= ~0x8; - can1->cantxfg.idr[1] &= ~0x10; - can1->cantxfg.dsr[0] = 0xCC; - can1->cantxfg.dlr = 1; - can1->cantxfg.tbpr = 0; - can1->cantflg = 0x01; - - i = 0; - while ((can1->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN1 send timeout, " - "can not send message!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - udelay(1000); - - i = 0; - while (!(can2->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN2 receive timeout, " - "no message received!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - - if (can2->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN2 receive error, " - "data mismatch!\n", - __FUNCTION__); - return 1; - } - - /* send a message on CAN2 */ - can2->cantbsel = 0x01; - can2->cantxfg.idr[0] = 0x55; - can2->cantxfg.idr[1] = 0x00; - can2->cantxfg.idr[1] &= ~0x8; - can2->cantxfg.idr[1] &= ~0x10; - can2->cantxfg.dsr[0] = 0xCC; - can2->cantxfg.dlr = 1; - can2->cantxfg.tbpr = 0; - can2->cantflg = 0x01; - - i = 0; - while ((can2->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN2 send error, " - "can not send message!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - udelay(1000); - - i = 0; - while (!(can1->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN1 receive timeout, " - "no message received!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - - if (can1->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN1 receive error 0x%02x\n", - __FUNCTION__, (can1->canrxfg.dsr[0])); - return 1; - } - - return 0; -} - -/* - * return 1 if rs232 port unknown - * return 2 on txd/rxd failure (only rs232 2) - * return 3 on rts/cts failure - * return 0 if no failure - */ -int do_rs232(char * const argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf ("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf ("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - break; - - case 2: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf ("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf ("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf ("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf ("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */ - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000F00; - break; - - default: - printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - - return error_status; -} - -#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) -static void sm501_backlight (unsigned int state) -{ - if (state == BL_ON) { - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= - (1 << 26) | (1 << 27); - } else if (state == BL_OFF) - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= - ~((1 << 26) | (1 << 27)); -} -#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ - -int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif -#if defined(CONFIG_STK52XX) - led_init(); -#endif - can_init(); - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strncmp (argv[1], "can", 3) == 0) { - rcode = do_can (argv); - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - return rcode; - } - break; - - case 3: - if (strncmp (argv[1], "rs232", 3) == 0) { - rcode = do_rs232 (argv); - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - return rcode; -#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) - } else if (strncmp (argv[1], "backlight", 4) == 0) { - if (strncmp (argv[2], "on", 2) == 0) { - sm501_backlight (BL_ON); - return 0; - } - else if (strncmp (argv[2], "off", 3) == 0) { - sm501_backlight (BL_OFF); - return 0; - } -#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ - } - break; - -#if defined(CONFIG_STK52XX) - case 4: - if (strcmp (argv[1], "led") == 0) { - return (do_led (argv)); - } - break; -#endif - - default: - break; - } - - printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n"); - return 1; -} - - -U_BOOT_CMD( - sound , 5, 1, cmd_sound, - "Sound sub-system", - "saw [duration] [freq] [channel]\n" - " - generate sawtooth for 'duration' ms with frequency 'freq'\n" - " on left \"l\" or right \"r\" channel\n" - "sound square [duration] [freq] [channel]\n" - " - generate squarewave for 'duration' ms with frequency 'freq'\n" - " on left \"l\" or right \"r\" channel\n" - "pcm1772 reg val" -); - -U_BOOT_CMD( - wav , 3, 1, cmd_wav, - "play wav file", - "[addr] [bytes]\n" - " - play wav file at address 'addr' with length 'bytes'" -); - -U_BOOT_CMD( - beep , 2, 1, cmd_beep, - "play short beep", - "[channel]\n" - " - play short beep on \"l\"eft or \"r\"ight channel" -); -#endif /* CONFIG_STK52XX || CONFIG_FO300 */ - -#if defined(CONFIG_STK52XX) -U_BOOT_CMD( - fkt , 4, 1, cmd_fkt, - "Function test routines", - "led number on/off\n" - " - 'number's like printed on STK52XX board\n" - "fkt can\n" - " - loopback plug for X83 required\n" - "fkt rs232 number\n" - " - loopback plug(s) for X2 required" -#ifndef CONFIG_TQM5200S - "\n" - "fkt backlight on/off\n" - " - switch backlight on or off" -#endif /* !CONFIG_TQM5200S */ -); -#elif defined(CONFIG_FO300) -U_BOOT_CMD( - fkt , 3, 1, cmd_fkt, - "Function test routines", - "fkt can\n" - " - loopback plug for X16/X29 required\n" - "fkt rs232 number\n" - " - loopback plug(s) for X21/X22 required" -); -#endif -#endif diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h deleted file mode 100644 index 3d99796..0000000 --- a/board/tqc/tqm5200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ -#define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c deleted file mode 100644 index cb99afd..0000000 --- a/board/tqc/tqm5200/tqm5200.c +++ /dev/null @@ -1,875 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_VIDEO_SM501 -#include -#endif - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifdef CONFIG_OF_LIBFDT -#include -#endif /* CONFIG_OF_LIBFDT */ - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \ - defined(CONFIG_VIDEO) -/* - * EDID block has been generated using Phoenix EDID Designer 1.3. - * This tool creates a text file containing: - * - * EDID BYTES: - * - * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F - * ------------------------------------------------ - * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00 - * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00 - * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01 - * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00 - * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 - * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 - * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 - * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17 - * - * Then this data has been manually converted to the char - * array below. - */ -static unsigned char edid_buf[128] = { - 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, - 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, -}; -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - -#if defined(CONFIG_TQM5200_B) - gd->ram_size = dramsize + dramsize2; -#else - gd->ram_size = dramsize; -#endif /* CONFIG_TQM5200_B */ - - return 0; -} - -int checkboard (void) -{ -#if defined(CONFIG_TQM5200S) -# define MODULE_NAME "TQM5200S" -#else -# define MODULE_NAME "TQM5200" -#endif - -#if defined(CONFIG_STK52XX) -# define CARRIER_NAME "STK52xx" -#elif defined(CONFIG_CAM5200) -# define CARRIER_NAME "CAM5200" -#elif defined(CONFIG_FO300) -# define CARRIER_NAME "FO300" -#elif defined(CONFIG_CHARON) -# define CARRIER_NAME "CHARON" -#else -# error "UNKNOWN" -#endif - - puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" - " on a " CARRIER_NAME " carrier board\n"); - - return 0; -} - -#undef MODULE_NAME -#undef CARRIER_NAME - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) - -#if defined (CONFIG_MINIFAP) -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_51 0x00080000UL -#endif /* CONFIG MINIFAP */ - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -#if defined (CONFIG_MINIFAP) - /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ - - /* enable GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - /* configure GPIO51 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= - SM501_GPIO_51; -#else - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - - /* by default the ATA reset is de-asserted */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -#endif -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -#if defined (CONFIG_MINIFAP) - if (idereset) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~SM501_GPIO_51; - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - SM501_GPIO_51; - } -#else - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -#endif -} -#endif - -#ifdef CONFIG_POST -/* - * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 - * is left open, no keypress is detected. - */ -int post_hotkeys_pressed(void) -{ -#ifdef CONFIG_STK52XX - struct mpc5xxx_gpio *gpio; - - gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; - - /* - * Configure PSC6_0 through PSC6_3 as GPIO. - */ - gpio->port_config &= ~(0x00700000); - - /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ - gpio->simple_gpioe |= 0x20000000; - - /* Configure GPIO_IRDA_1 as input */ - gpio->simple_ddr &= ~(0x20000000); - - return ((gpio->simple_ival & 0x20000000) ? 0 : 1); -#else - return 0; -#endif -} -#endif - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - - extern int usb_cpu_init(void); - -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - /* Low level USB init, required for proper kernel operation */ - usb_cpu_init(); -#endif - - return (0); -} -#endif - -#ifdef CONFIG_FO300 -int silent_boot (void) -{ - vu_long timer3_status; - - /* Configure GPT3 as GPIO input */ - *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004; - - /* Read in TIMER_3 pin status */ - timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; - -#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED - /* Force silent console mode if S1 switch - * is in closed position (TIMER_3 pin status is LOW). */ - if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0) - return 1; -#else - /* Force silent console mode if S1 switch - * is in open position (TIMER_3 pin status is HIGH). */ - if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1) - return 1; -#endif - - return 0; -} - -int board_early_init_f (void) -{ - if (silent_boot()) - gd->flags |= GD_FLG_SILENT; - - return 0; -} -#endif /* CONFIG_FO300 */ - -#if defined(CONFIG_CHARON) -#include -#include - -/* The TFP410 registers */ -#define TFP410_REG_VEN_ID_L 0x00 -#define TFP410_REG_VEN_ID_H 0x01 -#define TFP410_REG_DEV_ID_L 0x02 -#define TFP410_REG_DEV_ID_H 0x03 -#define TFP410_REG_REV_ID 0x04 - -#define TFP410_REG_CTL_1_MODE 0x08 -#define TFP410_REG_CTL_2_MODE 0x09 -#define TFP410_REG_CTL_3_MODE 0x0A - -#define TFP410_REG_CFG 0x0B - -#define TFP410_REG_DE_DLY 0x32 -#define TFP410_REG_DE_CTL 0x33 -#define TFP410_REG_DE_TOP 0x34 -#define TFP410_REG_DE_CNT_L 0x36 -#define TFP410_REG_DE_CNT_H 0x37 -#define TFP410_REG_DE_LIN_L 0x38 -#define TFP410_REG_DE_LIN_H 0x39 - -#define TFP410_REG_H_RES_L 0x3A -#define TFP410_REG_H_RES_H 0x3B -#define TFP410_REG_V_RES_L 0x3C -#define TFP410_REG_V_RES_H 0x3D - -static int tfp410_read_reg(int reg, uchar *buf) -{ - puts("Error reading the chip.\n"); - return -ENOSYS; -} - -static int tfp410_write_reg(int reg, uchar buf) -{ - puts("Error writing the chip.\n"); - return -ENOSYS; -} - -typedef struct _tfp410_config { - int reg; - uchar val; -}TFP410_CONFIG; - -static TFP410_CONFIG tfp410_configtbl[] = { - {TFP410_REG_CTL_1_MODE, 0x37}, - {TFP410_REG_CTL_2_MODE, 0x20}, - {TFP410_REG_CTL_3_MODE, 0x80}, - {TFP410_REG_DE_DLY, 0x90}, - {TFP410_REG_DE_CTL, 0x00}, - {TFP410_REG_DE_TOP, 0x23}, - {TFP410_REG_DE_CNT_H, 0x02}, - {TFP410_REG_DE_CNT_L, 0x80}, - {TFP410_REG_DE_LIN_H, 0x01}, - {TFP410_REG_DE_LIN_L, 0xe0}, - {-1, 0}, -}; - -static int charon_last_stage_init(void) -{ - volatile struct mpc5xxx_lpb *lpb = - (struct mpc5xxx_lpb *) MPC5XXX_LPB; - uchar buf; - int i = 0; - - /* check version */ - if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0) - return -1; - if (!(buf & 0x04)) - return -1; - if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0) - return -1; - if (!(buf & 0x10)) - return -1; - /* OK, now init the chip */ - while (tfp410_configtbl[i].reg != -1) { - int ret; - - ret = tfp410_write_reg(tfp410_configtbl[i].reg, - tfp410_configtbl[i].val); - if (ret != 0) - return -1; - i++; - } - printf("TFP410 initialized.\n"); - - /* set deadcycle for cs3 to 0 */ - setbits_be32(&lpb->cs_deadcycle, 0xffffcfff); - return 0; -} -#endif - -int last_stage_init (void) -{ - /* - * auto scan for really existing devices and re-set chip select - * configuration. - */ - u16 save, tmp; - int restore; - - /* - * Check for SRAM and SRAM size - */ - - /* save original SRAM content */ - save = *(volatile u16 *)CONFIG_SYS_CS2_START; - restore = 1; - - /* write test pattern to SRAM */ - *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in SRAM detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { - /* no SRAM at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); - *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { - /* make sure that we access a mirrored address */ - *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; - __asm__ volatile ("sync"); - if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { - /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, - 0x80000); - __asm__ volatile ("sync"); - puts ("SRAM: 512 kB\n"); - } - else - puts ("!! possible error in SRAM detection\n"); - } else { - puts ("SRAM: 1 MB\n"); - } - /* restore origianl SRAM content */ - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS2_START = save; - __asm__ volatile ("sync"); - } - -#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */ - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CONFIG_SYS_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { - /* no grafic controller at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); - *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else { - puts ("VGA: SMI501 (Voyager) with 8 MB\n"); - } - /* restore origianl FB content */ - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS1_START = save; - __asm__ volatile ("sync"); - } - -#ifdef CONFIG_FO300 - if (silent_boot()) { - setenv("bootdelay", "0"); - disable_ctrlc(1); - } -#endif -#endif /* !CONFIG_TQM5200S */ - -#if defined(CONFIG_CHARON) - charon_last_stage_init(); -#endif - return 0; -} - -#ifdef CONFIG_VIDEO_SM501 - -#ifdef CONFIG_FO300 -#define DISPLAY_WIDTH 800 -#else -#define DISPLAY_WIDTH 640 -#endif -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#error CONFIG_VIDEO_SM501_16BPP not supported. -#endif /* CONFIG_VIDEO_SM501_16BPP */ -#ifdef CONFIG_VIDEO_SM501_32BPP -static const SMI_REGS init_regs [] = -{ -#if 0 /* CRT only */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x10090a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x10090a01}, - {0x00054, 0x0}, - {0x80200, 0x00010000}, - {0x80204, 0x0}, - {0x80208, 0x0A000A00}, - {0x8020C, 0x02fa027f}, - {0x80210, 0x004a028b}, - {0x80214, 0x020c01df}, - {0x80218, 0x000201e9}, - {0x80200, 0x00013306}, -#else /* panel + CRT */ -#ifdef CONFIG_FO300 - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x301a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x0f013106}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0C800C80}, - {0x80014, 0x03200000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00320}, - {0x80024, 0x042a031f}, - {0x80028, 0x0086034a}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201ea}, - {0x80200, 0x00010000}, -#else - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x091a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x0f013106}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0a000a00}, - {0x80014, 0x02800000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00280}, - {0x80024, 0x02fa027f}, - {0x80028, 0x004a028b}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00010000}, -#endif /* #ifdef CONFIG_FO300 */ -#endif - {0, 0} -}; -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \ - defined(CONFIG_STK52XX) - } else if (line_number == 2) { -#if defined (CONFIG_CHARON) - strcpy (info, " on a CHARON carrier board"); -#endif -#if defined (CONFIG_STK52XX) - strcpy (info, " on a STK52xx carrier board"); -#endif -#if defined (CONFIG_FO300) - strcpy (info, " on a FO300 carrier board"); -#endif -#endif - } - else { - info [0] = '\0'; - } -} -#endif - -/* - * Returns SM501 register base address. First thing called in the - * driver. Checks if SM501 is physically present. - */ -unsigned int board_video_init (void) -{ - u16 save, tmp; - int restore, ret; - - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CONFIG_SYS_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { - /* no grafic controller found */ - restore = 0; - ret = 0; - } else { - ret = SM501_MMIO_BASE; - } - - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS1_START = save; - __asm__ volatile ("sync"); - } - return ret; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - return SM501_FB_BASE; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - return init_regs; -} - -int board_get_width (void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height (void) -{ - return DISPLAY_HEIGHT; -} - -#endif /* CONFIG_VIDEO_SM501 */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#if defined(CONFIG_VIDEO) - fdt_add_edid(blob, "smi,sm501", edid_buf); -#endif - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#if defined(CONFIG_RESET_PHY_R) -#include - -void reset_phy(void) -{ - /* init Micrel KSZ8993 PHY */ - miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09); -} -#endif - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig deleted file mode 100644 index 857fedb..0000000 --- a/board/tqc/tqm8xx/Kconfig +++ /dev/null @@ -1,155 +0,0 @@ -if TARGET_TQM823L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM823L" - -endif - -if TARGET_TQM823M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM823M" - -endif - -if TARGET_TQM850L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM850L" - -endif - -if TARGET_TQM850M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM850M" - -endif - -if TARGET_TQM855L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM855L" - -endif - -if TARGET_TQM855M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM855M" - -endif - -if TARGET_TQM860L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM860L" - -endif - -if TARGET_TQM860M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM860M" - -endif - -if TARGET_TQM862L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM862L" - -endif - -if TARGET_TQM862M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM862M" - -endif - -if TARGET_TQM866M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM866M" - -endif - -if TARGET_TQM885D - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM885D" - -endif diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS deleted file mode 100644 index f3ddc6a..0000000 --- a/board/tqc/tqm8xx/MAINTAINERS +++ /dev/null @@ -1,31 +0,0 @@ -TQM8XX BOARD -M: Wolfgang Denk -S: Maintained -F: board/tqc/tqm8xx/ -F: include/configs/TQM823L.h -F: configs/TQM823L_defconfig -F: configs/TQM823L_LCD_defconfig -F: include/configs/TQM823M.h -F: configs/TQM823M_defconfig -F: include/configs/TQM850L.h -F: configs/TQM850L_defconfig -F: include/configs/TQM850M.h -F: configs/TQM850M_defconfig -F: include/configs/TQM855L.h -F: configs/TQM855L_defconfig -F: include/configs/TQM855M.h -F: configs/TQM855M_defconfig -F: include/configs/TQM860L.h -F: configs/TQM860L_defconfig -F: include/configs/TQM860M.h -F: configs/TQM860M_defconfig -F: include/configs/TQM862L.h -F: configs/TQM862L_defconfig -F: include/configs/TQM862M.h -F: configs/TQM862M_defconfig -F: include/configs/TQM866M.h -F: configs/TQM866M_defconfig -F: include/configs/TQM885D.h -F: configs/TQM885D_defconfig -F: configs/TTTech_defconfig -F: configs/wtk_defconfig diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile deleted file mode 100644 index 2651a2f..0000000 --- a/board/tqc/tqm8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8xx.o load_sernum_ethaddr.o diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c deleted file mode 100644 index 0070da1..0000000 --- a/board/tqc/tqm8xx/load_sernum_ethaddr.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/*----------------------------------------------------------------------- - * Process Hardware Information Block: - * - * If we boot on a system fresh from factory, check if the Hardware - * Information Block exists and save the information it contains. - * - * The TQM8xxL / TQM82xx Hardware Information Block is defined as - * follows: - * - located in first flash bank - * - starts at offset 0x0003FFC0 - * - size 0x00000040 - * - * Internal structure: - * - sequence of ASCII character strings - * - fields separated by a single space character (0x20) - * - last field terminated by NUL character (0x00) - * - remaining space filled with NUL characters (0x00) - * - * Fields in Hardware Information Block: - * 1) Module Type - * 2) Serial Number - * 3) First MAC Address - * 4) Number of additional MAC addresses - */ - -void load_sernum_ethaddr (void) -{ - unsigned char *hwi; - unsigned char serial [CONFIG_SYS_HWINFO_SIZE]; - unsigned char ethaddr[CONFIG_SYS_HWINFO_SIZE]; - unsigned short ih, is, ie, part; - - hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); - ih = is = ie = 0; - - if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - return; - } - - part = 1; - - /* copy serial # / MAC address */ - while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) { - if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ - return; - } - switch (part) { - default: /* Copy serial # */ - if (hwi[ih] == ' ') { - ++part; - } - serial[is++] = hwi[ih]; - break; - case 3: /* Copy MAC address */ - if (hwi[ih] == ' ') { - ++part; - break; - } - ethaddr[ie++] = hwi[ih]; - if ((ie % 3) == 2) - ethaddr[ie++] = ':'; - break; - } - ++ih; - } - serial[is] = '\0'; - if (ie && ethaddr[ie-1] == ':') - --ie; - ethaddr[ie] = '\0'; - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ((char *)"serial#", (char *)serial); - } - - if (getenv("ethaddr") == NULL) { - setenv ((char *)"ethaddr", (char *)ethaddr); - } -} diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c deleted file mode 100644 index 58bd7fa..0000000 --- a/board/tqc/tqm8xx/tqm8xx.c +++ /dev/null @@ -1,677 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#ifdef CONFIG_PS2MULT -#include -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#include -#endif - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -DECLARE_GLOBAL_DATA_PTR; - -static long int dram_size (long int, long int *, long int); - -#define _NOT_USED_ 0xFFFFFFFF - -/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */ -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44, - 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else. - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (l < 0 || strncmp(buf, "TQM8", 4)) { - puts ("### No HW ID - assuming TQM8xxL\n"); - return (0); - } - - if ((buf[6] == 'L')) { /* a TQM8xxL type */ - gd->board_type = 'L'; - } - - if ((buf[6] == 'M')) { /* a TQM8xxM type */ - gd->board_type = 'M'; - } - - if ((buf[6] == 'D')) { /* a TQM885D type */ - gd->board_type = 'D'; - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int dram_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9, size10; - long int size_b0 = 0; - long int size_b1 = 0; - int board_type = gd->board_type; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - /* - * The following value is used as an address (i.e. opcode) for - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If - * the port size is 32bit the SDRAM does NOT "see" the lower two - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for - * MICRON SDRAMs: - * -> 0 00 010 0 010 - * | | | | +- Burst Length = 4 - * | | | +----- Burst Type = Sequential - * | | +------- CAS Latency = 2 - * | +----------- Operating Mode = Standard - * +-------------- Write Burst Mode = Programmed Burst Length - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ - udelay (1); - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); - - udelay(1000); - -#if defined(CONFIG_SYS_MAMR_10COL) - /* - * try 10 column mode - */ - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); -#else - size10 = 0; -#endif /* CONFIG_SYS_MAMR_10COL */ - - if ((size8 < size10) && (size9 < size10)) { - size_b0 = size10; - } else if ((size8 < size9) && (size10 < size9)) { - size_b0 = size9; - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; - udelay (500); - } else { - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); - } - debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20); - } else { - size_b1 = 0; - } -#endif /* CONFIG_CAN_DRIVER */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - -#ifndef CONFIG_CAN_DRIVER - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; -#endif /* CONFIG_CAN_DRIVER */ - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - -#ifdef CONFIG_CAN_DRIVER - /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ - - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFCC04; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC07; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCCC04; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCDC04; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x3FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDC405; - memctl->memc_mcr = 0x011C | UPMB; -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB - /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362; - memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362; -#endif /* CONFIG_ISP1362_USB */ - gd->ram_size = size_b0 + size_b1; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_MISC_INIT_R -extern void load_sernum_ethaddr(void); -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - load_sernum_ethaddr(); - -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else { - trlx = 0; - } - - /* - * We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* - * We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* - * For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); - - memctl->memc_or0 = - flash_or_timing | (-flash_info[0].size & OR_AM_MSK); -#else - memctl->memc_or0 = - CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); -#endif - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - if (flash_info[1].size) { -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or1 = flash_or_timing | - (-flash_info[1].size & 0xFFFF8000); -#else - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | - (-flash_info[1].size & 0xFFFF8000); -#endif - memctl->memc_br1 = - ((CONFIG_SYS_FLASH_BASE + - flash_info[0]. - size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } - -# ifdef CONFIG_IDE_LED - /* Configure PA15 as output port */ - immap->im_ioport.iop_padir |= 0x0001; - immap->im_ioport.iop_paodr |= 0x0001; - immap->im_ioport.iop_papar &= ~0x0001; - immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ -# endif - - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ - - -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat |= 0x0001; - } else { - immap->im_ioport.iop_padat &= ~0x0001; - } -} -# endif - -#ifdef CONFIG_LCD_INFO -#include -#include -#include - -void lcd_show_board_info(void) -{ - char temp[32]; - - lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); - lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); - lcd_printf (" Wolfgang DENK, wd@denx.de\n"); -#ifdef CONFIG_LCD_INFO_BELOW_LOGO - lcd_printf ("MPC823 CPU at %s MHz\n", - strmhz(temp, gd->cpu_clk)); - lcd_printf (" %ld MB RAM, %ld MB Flash\n", - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#else - /* leave one blank line */ - lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ -} -#endif /* CONFIG_LCD_INFO */ - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -int fdt_set_node_and_value (void *blob, - char *nodename, - char *regname, - void *var, - int size) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_setprop (blob, nodeoffset, regname, var, - size); - if (ret < 0) { - printf("ft_blob_update(): " - "cannot set %s/%s property; err: %s\n", - nodename, regname, fdt_strerror (ret)); - } - } else { - printf("ft_blob_update(): " - "cannot find %s node err:%s\n", - nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -int fdt_del_node_name (void *blob, char *nodename) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_del_node (blob, nodeoffset); - if (ret < 0) { - printf("%s: cannot delete %s; err: %s\n", - __func__, nodename, fdt_strerror (ret)); - } - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -int fdt_del_prop_name (void *blob, char *nodename, char *propname) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_delprop (blob, nodeoffset, propname); - if (ret < 0) { - printf("%s: cannot delete %s %s; err: %s\n", - __func__, nodename, propname, - fdt_strerror (ret)); - } - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -/* - * update "brg" property in the blob - */ -void ft_blob_update (void *blob, bd_t *bd) -{ - uchar enetaddr[6]; - ulong brg_data = 0; - - /* BRG */ - brg_data = cpu_to_be32(bd->bi_busfreq); - fdt_set_node_and_value(blob, - "/soc/cpm", "brg-frequency", - &brg_data, sizeof(brg_data)); - - /* MAC addr */ - if (eth_getenv_enetaddr("ethaddr", enetaddr)) { - fdt_set_node_and_value(blob, - "ethernet0", "local-mac-address", - enetaddr, sizeof(u8) * 6); - } - - if (hwconfig_arg_cmp("fec", "off")) { - /* no FEC on this plattform, delete DTS nodes */ - fdt_del_node_name (blob, "ethernet1"); - fdt_del_node_name (blob, "mdio1"); - /* also the aliases entries */ - fdt_del_prop_name (blob, "/aliases", "ethernet1"); - fdt_del_prop_name (blob, "/aliases", "mdio1"); - } else { - /* adjust local-mac-address for FEC ethernet */ - if (eth_getenv_enetaddr("eth1addr", enetaddr)) { - fdt_set_node_and_value(blob, - "ethernet1", "local-mac-address", - enetaddr, sizeof(u8) * 6); - } - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_blob_update(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds deleted file mode 100644 index 44dfafa..0000000 --- a/board/tqc/tqm8xx/u-boot.lds +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2000-2012 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - board/tqc/tqm8xx/built-in.o (.text*) - disk/built-in.o (.text*) - drivers/net/built-in.o (.text*) - drivers/built-in.o (.text.pcmcia_on) - drivers/built-in.o (.text.pcmcia_hardware_enable) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig deleted file mode 100644 index 653bfc1..0000000 --- a/board/v38b/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_V38B - -config SYS_BOARD - default "v38b" - -config SYS_CONFIG_NAME - default "v38b" - -endif diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS deleted file mode 100644 index d1a6ae6..0000000 --- a/board/v38b/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -V38B BOARD -#M: - -S: Maintained -F: board/v38b/ -F: include/configs/v38b.h -F: configs/v38b_defconfig diff --git a/board/v38b/Makefile b/board/v38b/Makefile deleted file mode 100644 index a20a5ef..0000000 --- a/board/v38b/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := v38b.o ethaddr.o diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c deleted file mode 100644 index 982998f..0000000 --- a/board/v38b/ethaddr.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* For the V38B board the pin is GPIO_PSC_6 */ -#define GPIO_PIN GPIO_PSC6_0 - -#define NO_ERROR 0 -#define ERR_NO_NUMBER 1 -#define ERR_BAD_NUMBER 2 - -static int is_high(void); -static int check_device(void); -static void io_out(int value); -static void io_input(void); -static void io_output(void); -static void init_gpio(void); -static void read_byte(unsigned char *data); -static void write_byte(unsigned char command); - -void read_2501_memory(unsigned char *psernum, unsigned char *perr); -void board_get_enetaddr(uchar *enetaddr); - - -static int is_high() -{ - return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN); -} - -static void io_out(int value) -{ - if (value) - *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN; - else - *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN; -} - -static void io_input() -{ - *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN; - udelay(3); /* allow input to settle */ -} - -static void io_output() -{ - *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN; -} - -static void init_gpio() -{ - *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ -} - -void read_2501_memory(unsigned char *psernum, unsigned char *perr) -{ -#define NBYTES 28 - unsigned char crcval, i; - unsigned char buf[NBYTES]; - - *perr = 0; - crcval = 0; - - for (i = 0; i < NBYTES; i++) - buf[i] = 0; - - if (!check_device()) - *perr = ERR_NO_NUMBER; - else { - *perr = NO_ERROR; - write_byte(0xCC); /* skip ROM (0xCC) */ - write_byte(0xF0); /* Read memory command 0xF0 */ - write_byte(0x00); /* Address TA1=0, TA2=0 */ - write_byte(0x00); - read_byte(&crcval); /* Read CRC of address and command */ - - for (i = 0; i < NBYTES; i++) - read_byte(&buf[i]); - } - if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) { - *perr = ERR_BAD_NUMBER; - psernum[0] = 0x00; - psernum[1] = 0xE0; - psernum[2] = 0xEE; - psernum[3] = 0xFF; - psernum[4] = 0xFF; - psernum[5] = 0xFF; - } else { - psernum[0] = 0x00; - psernum[1] = 0xE0; - psernum[2] = 0xEE; - psernum[3] = buf[7]; - psernum[4] = buf[6]; - psernum[5] = buf[5]; - } -} - -static int check_device() -{ - int found; - - io_output(); - io_out(0); - udelay(500); /* must be at least 480 us low pulse */ - - io_input(); - udelay(60); - - found = (is_high() == 0) ? 1 : 0; - udelay(500); /* must be at least 480 us low pulse */ - - return found; -} - -static void write_byte(unsigned char command) -{ - char i; - - for (i = 0; i < 8; i++) { - /* 1 us to 15 us low pulse starts bit slot */ - /* Start with high pulse for 3 us */ - io_input(); - udelay(3); - - io_out(0); - io_output(); - udelay(3); - - if (command & 0x01) { - /* 60 us high for 1-bit */ - io_input(); - udelay(60); - } else - /* 60 us low for 0-bit */ - udelay(60); - /* Leave pin as input */ - io_input(); - - command = command >> 1; - } -} - -static void read_byte(unsigned char *data) -{ - unsigned char i, rdat = 0; - - for (i = 0; i < 8; i++) { - /* read one bit from one-wire device */ - - /* 1 - 15 us low starts bit slot */ - io_out(0); - io_output(); - udelay(0); - - /* allow line to be pulled high */ - io_input(); - - /* delay 10 us */ - udelay(10); - - /* now sample input status */ - if (is_high()) - rdat = (rdat >> 1) | 0x80; - else - rdat = rdat >> 1; - - udelay(60); /* at least 60 us */ - } - /* copy the return value */ - *data = rdat; -} - -void board_get_enetaddr(uchar *enetaddr) -{ - unsigned char sn[6], err = NO_ERROR; - - init_gpio(); - - read_2501_memory(sn, &err); - - if (err == NO_ERROR) { - sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x", - sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); - printf("MAC address: %s\n", enetaddr); - setenv("ethaddr", (char *)enetaddr); - } else { - sprintf((char *)enetaddr, "00:01:02:03:04:05"); - printf("Error reading MAC address.\n"); - printf("Setting default to %s\n", enetaddr); - setenv("ethaddr", (char *)enetaddr); - } -} diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c deleted file mode 100644 index e680b7b..0000000 --- a/board/v38b/v38b.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif /* SDRAM_DDR */ - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif /* !CONFIG_SYS_RAMBOOT */ - - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif /* SDRAM_DDR */ - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else - dramsize2 = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - else - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - - -int checkboard (void) -{ - puts("Board: MarelV38B\n"); - return 0; -} - -int board_early_init_f(void) -{ -#ifdef CONFIG_HW_WATCHDOG - /* - * Enable and configure the direction (output) of PSC3_9 - watchdog - * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's - * Manual. - */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; -#endif /* CONFIG_HW_WATCHDOG */ - return 0; -} - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for the - * detection process. Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - - /* - * Enable GPIO_WKUP_7 to "read the status of the actual power - * situation". Default direction is input, so no need to set it - * explicitly. - */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7; - return 0; -} - -extern void board_get_enetaddr(uchar *enetaddr); -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} - - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} -#endif - - -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - /* - * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog - * we need a positive or negative transition on WDI i.e., our PSC3_9. - */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9; -} -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/xilinx/zynqmp/sleep.h b/board/xilinx/zynqmp/sleep.h new file mode 100644 index 0000000..a962319 --- /dev/null +++ b/board/xilinx/zynqmp/sleep.h @@ -0,0 +1 @@ +/* Intentionally empty file for psu_init* */ diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h index 6bbc000..679d234 100644 --- a/board/xilinx/zynqmp/xil_io.h +++ b/board/xilinx/zynqmp/xil_io.h @@ -33,12 +33,9 @@ int Xil_In32(unsigned long addr) return readl(addr); } -void mask_delay(u32 delay); void usleep(u32 sleep) { udelay(sleep); } -int mask_poll(u32 add, u32 mask); -int mask_pollOnValue(u32 add, u32 mask, u32 value); #endif /* XIL_IO_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 3849b58..51a3d9f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -113,6 +113,14 @@ static char *zynqmp_get_silicon_idcode_name(void) } #endif +int board_early_init_f(void) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) + zynqmp_pmufw_version(); +#endif + return 0; +} + #define ZYNQMP_VERSION_SIZE 9 int board_init(void) diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index e81d6ff..8a15c30 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -16,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/cmd/Kconfig b/cmd/Kconfig index 270cff6..07b0e3b 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -266,7 +266,9 @@ config CMD_XIMG Extract a part of a multi-image. config CMD_POWEROFF - bool + bool "poweroff" + help + Poweroff/Shutdown the system endmenu @@ -1230,7 +1232,7 @@ config CMD_DIAG config CMD_IRQ bool "irq - Show information about interrupts" - depends on !ARM && !MIPS && !SH && !MPC512X + depends on !ARM && !MIPS && !SH help This enables two commands: diff --git a/cmd/Makefile b/cmd/Makefile index 9ea56e9..b92e42d 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -192,3 +192,5 @@ $(obj)/license_data_gz.h: $(obj)/license_data.gz FORCE targets += license_data_size.h $(obj)/license_data_size.h: $(srctree)/Licenses/gpl-2.0.txt FORCE $(call filechk,data_size) + +CFLAGS_ethsw.o := -Wno-enum-conversion diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 41ab8e8..48dba20 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -183,8 +183,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_flash(bd); print_num("sramstart", bd->bi_sramstart); print_num("sramsize", bd->bi_sramsize); -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \ - defined(CONFIG_MPC8260) || defined(CONFIG_E500) +#if defined(CONFIG_E500) print_num("immr_base", bd->bi_immr_base); #endif print_num("bootflags", bd->bi_bootflags); diff --git a/cmd/bedbug.c b/cmd/bedbug.c index 69afeaf..3206757 100644 --- a/cmd/bedbug.c +++ b/cmd/bedbug.c @@ -52,17 +52,6 @@ void bedbug_init (void) void bedbug405_init (void); bedbug405_init (); -#elif defined(CONFIG_8xx) - void bedbug860_init (void); - - bedbug860_init (); -#endif - -#if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260) - /* Processors that are 603e core based */ - void bedbug603e_init (void); - - bedbug603e_init (); #endif return; diff --git a/cmd/elf.c b/cmd/elf.c index e4c6535..ed9625b 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -147,25 +147,25 @@ int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long addr; /* Address of the ELF image */ unsigned long rc; /* Return value from user code */ - char *sload, *saddr; + char *sload = NULL; const char *ep = getenv("autostart"); - int rcode = 0; - sload = saddr = NULL; - if (argc == 3) { - sload = argv[1]; - saddr = argv[2]; - } else if (argc == 2) { - if (argv[1][0] == '-') - sload = argv[1]; - else - saddr = argv[1]; - } + /* Consume 'bootelf' */ + argc--; argv++; - if (saddr) - addr = simple_strtoul(saddr, NULL, 16); - else + /* Check for flag. */ + if (argc >= 1 && (argv[0][0] == '-' && \ + (argv[0][1] == 'p' || argv[0][1] == 's'))) { + sload = argv[0]; + /* Consume flag. */ + argc--; argv++; + } + /* Check for address. */ + if (argc >= 1 && strict_strtoul(argv[0], 16, &addr) != -EINVAL) { + /* Consume address */ + argc--; argv++; + } else addr = load_addr; if (!valid_elf_image(addr)) @@ -185,7 +185,7 @@ int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * pass address parameter as argv[0] (aka command name), * and all remaining args */ - rc = do_bootelf_exec((void *)addr, argc - 1, argv + 1); + rc = do_bootelf_exec((void *)addr, argc, argv); if (rc != 0) rcode = 1; @@ -385,7 +385,7 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - bootelf, 3, 0, do_bootelf, + bootelf, CONFIG_SYS_MAXARGS, 0, do_bootelf, "Boot from an ELF image in memory", "[-p|-s] [address]\n" "\t- load ELF image at [address] via program headers (-p)\n" diff --git a/cmd/ethsw.c b/cmd/ethsw.c index 491cb8e..b600965 100644 --- a/cmd/ethsw.c +++ b/cmd/ethsw.c @@ -915,7 +915,7 @@ static void cmd_keywords_opt_check(const struct ethsw_command_def *parsed_cmd, * check if our command's optional keywords match the optional * keywords of an available command */ - for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) { + for (i = 0; i < ARRAY_SIZE(cmd_opt_def); i++) { keyw_opt_matched = 0; cmd_keyw_p = &parsed_cmd->cmd_to_keywords[keyw_opt_matched]; cmd_keyw_opt_p = &cmd_opt_def[i].cmd_keyword[keyw_opt_matched]; diff --git a/cmd/fdt.c b/cmd/fdt.c index a21415d..31a5361 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -257,6 +257,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *prop; /* property */ int nodeoffset; /* node offset from libfdt */ static char data[SCRATCHPAD]; /* storage for the property */ + const void *ptmp; int len; /* new length of the property */ int ret; /* return value */ @@ -268,13 +269,6 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) pathp = argv[2]; prop = argv[3]; - if (argc == 4) { - len = 0; - } else { - ret = fdt_parse_prop(&argv[4], argc - 4, data, &len); - if (ret != 0) - return ret; - } nodeoffset = fdt_path_offset (working_fdt, pathp); if (nodeoffset < 0) { @@ -286,6 +280,21 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } + if (argc == 4) { + len = 0; + } else { + ptmp = fdt_getprop(working_fdt, nodeoffset, prop, &len); + if (len > SCRATCHPAD) { + printf("prop (%d) doesn't fit in scratchpad!\n", + len); + return 1; + } + memcpy(data, ptmp, len); + ret = fdt_parse_prop(&argv[4], argc - 4, data, &len); + if (ret != 0) + return ret; + } + ret = fdt_setprop(working_fdt, nodeoffset, prop, data, len); if (ret < 0) { printf ("libfdt fdt_setprop(): %s\n", fdt_strerror(ret)); @@ -371,7 +380,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* no property value */ setenv(var, ""); return 0; - } else if (len > 0) { + } else if (nodep && len > 0) { if (subcmd[0] == 'v') { int ret; @@ -766,7 +775,11 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) cp = newp; tmp = simple_strtoul(cp, &newp, 0); - *(fdt32_t *)data = cpu_to_fdt32(tmp); + if (*cp != '?') + *(fdt32_t *)data = cpu_to_fdt32(tmp); + else + newp++; + data += 4; *len += 4; @@ -962,7 +975,7 @@ static int fdt_print(const char *pathp, char *prop, int depth) /* no property value */ printf("%s %s\n", pathp, prop); return 0; - } else if (len > 0) { + } else if (nodep && len > 0) { printf("%s = ", prop); print_data (nodep, len); printf("\n"); diff --git a/cmd/ide.c b/cmd/ide.c index 0fd401b..10fb2f9 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -18,7 +18,7 @@ #include #include -#if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) +#if defined(CONFIG_IDE_PCMCIA) # include #endif @@ -42,12 +42,7 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_USAGE; case 2: if (strncmp(argv[1], "res", 3) == 0) { - puts("\nReset IDE" -#ifdef CONFIG_IDE_8xx_DIRECT - " on PCMCIA " PCMCIA_SLOT_MSG -#endif - ": "); - + puts("\nReset IDE: "); ide_init(); return 0; } else if (strncmp(argv[1], "inf", 3) == 0) { diff --git a/cmd/jffs2.c b/cmd/jffs2.c index f00d53a..9be198e 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -606,7 +606,7 @@ U_BOOT_CMD( " with offset 'off'" ); U_BOOT_CMD( - ls, 2, 1, do_jffs2_ls, + fsls, 2, 1, do_jffs2_ls, "list files in a directory (default /)", "[ directory ]" ); diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index 112bf1f..683c48b 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -1556,7 +1556,7 @@ static int parse_mtdparts(const char *const mtdparts) int err = 1; char tmp_parts[MTDPARTS_MAXLEN]; - debug("\n---parse_mtdparts---\nmtdparts = %s\n\n", p); + debug("\n---parse_mtdparts---\nmtdparts = %s\n\n", mtdparts); /* delete all devices and partitions */ if (mtd_devices_init() != 0) { diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 8f4e6bb..cd17db6 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -54,8 +54,8 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CONFIG_ENV_IS_IN_REMOTE) && \ !defined(CONFIG_ENV_IS_IN_UBI) && \ !defined(CONFIG_ENV_IS_NOWHERE) -# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\ -SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE +# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|MMC|FAT|EXT4|\ +NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE #endif /* diff --git a/cmd/pci.c b/cmd/pci.c index 41b4fff..fe27b4f 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -150,7 +150,8 @@ int pci_bar_show(struct udevice *dev) if ((!is_64 && size_low) || (is_64 && size)) { size = ~size + 1; printf(" %d %#016llx %#016llx %d %s %s\n", - bar_id, base, size, is_64 ? 64 : 32, + bar_id, (unsigned long long)base, + (unsigned long long)size, is_64 ? 64 : 32, is_io ? "I/O" : "MEM", prefetchable ? "Prefetchable" : ""); } diff --git a/cmd/pcmcia.c b/cmd/pcmcia.c index 044fb9e..0bf2bd6 100644 --- a/cmd/pcmcia.c +++ b/cmd/pcmcia.c @@ -83,10 +83,6 @@ U_BOOT_CMD( #undef CHECK_IDE_DEVICE -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CHECK_IDE_DEVICE -#endif - #if defined(CONFIG_PXA_PCMCIA) #define CHECK_IDE_DEVICE #endif diff --git a/cmd/reginfo.c b/cmd/reginfo.c index a3696d1..babea84 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -7,14 +7,8 @@ #include #include -#if defined(CONFIG_8xx) -#include -#elif defined (CONFIG_4xx) +#if defined (CONFIG_4xx) extern void ppc4xx_reginfo(void); -#elif defined (CONFIG_5xx) -#include -#elif defined (CONFIG_MPC5200) -#include #elif defined (CONFIG_MPC86xx) extern void mpc86xx_reginfo(void); #elif defined(CONFIG_MPC85xx) @@ -24,149 +18,8 @@ extern void mpc85xx_reginfo(void); static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { -#if defined(CONFIG_8xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; - volatile sit8xx_t *timers = &immap->im_sit; - - /* Hopefully more PowerPC knowledgable people will add code to display - * other useful registers - */ - - printf ("\nSystem Configuration registers\n" - - "\tIMMR\t0x%08X\n", get_immr(0)); - - printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); - printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); - - printf("\tSWT\t0x%08X", sysconf->sc_swt); - printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); - - printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", - sysconf->sc_sipend, sysconf->sc_simask); - printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", - sysconf->sc_siel, sysconf->sc_sivec); - printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", - sysconf->sc_tesr, sysconf->sc_sdcr); - - printf ("Memory Controller Registers\n" - - "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); - printf ("\n" - "\tmamr\t0x%08X\tmbmr\t0x%08X \n", - memctl->memc_mamr, memctl->memc_mbmr ); - printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", - memctl->memc_mstat, memctl->memc_mptpr ); - printf("\tmdr\t0x%08X \n", memctl->memc_mdr); - - printf ("\nSystem Integration Timers\n" - "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", - timers->sit_tbscr, timers->sit_rtcsc); - printf("\tPISCR\t0x%08X \n", timers->sit_piscr); - - /* - * May be some CPM info here? - */ - -#elif defined (CONFIG_4xx) +#if defined (CONFIG_4xx) ppc4xx_reginfo(); -#elif defined(CONFIG_5xx) - - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl5xx_t *memctl = &immap->im_memctl; - volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; - volatile sit5xx_t *timers = &immap->im_sit; - volatile car5xx_t *car = &immap->im_clkrst; - volatile uimb5xx_t *uimb = &immap->im_uimb; - - puts ("\nSystem Configuration registers\n"); - printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr); - printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr); - printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask); - printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec); - printf("\tTESR\t0x%08X\n", sysconf->sc_tesr); - - puts ("\nMemory Controller Registers\n"); - printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); - printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor ); - printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat); - - puts ("\nSystem Integration Timers\n"); - printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); - printf("\tPISCR\t0x%08X \n", timers->sit_piscr); - - puts ("\nClocks and Reset\n"); - printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr); - - puts ("\nU-Bus to IMB3 Bus Interface\n"); - printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend); - puts ("\n\n"); - -#elif defined(CONFIG_MPC5200) - puts ("\nMPC5200 registers\n"); - printf ("MBAR=%08x\n", CONFIG_SYS_MBAR); - puts ("Memory map registers\n"); - printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS0_START, - *(volatile ulong*)MPC5XXX_CS0_STOP, - *(volatile ulong*)MPC5XXX_CS0_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); - printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS1_START, - *(volatile ulong*)MPC5XXX_CS1_STOP, - *(volatile ulong*)MPC5XXX_CS1_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); - printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS2_START, - *(volatile ulong*)MPC5XXX_CS2_STOP, - *(volatile ulong*)MPC5XXX_CS2_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); - printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS3_START, - *(volatile ulong*)MPC5XXX_CS3_STOP, - *(volatile ulong*)MPC5XXX_CS3_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); - printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS4_START, - *(volatile ulong*)MPC5XXX_CS4_STOP, - *(volatile ulong*)MPC5XXX_CS4_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); - printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS5_START, - *(volatile ulong*)MPC5XXX_CS5_STOP, - *(volatile ulong*)MPC5XXX_CS5_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); - printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS6_START, - *(volatile ulong*)MPC5XXX_CS6_STOP, - *(volatile ulong*)MPC5XXX_CS6_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); - printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_CS7_START, - *(volatile ulong*)MPC5XXX_CS7_STOP, - *(volatile ulong*)MPC5XXX_CS7_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); - printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", - *(volatile ulong*)MPC5XXX_BOOTCS_START, - *(volatile ulong*)MPC5XXX_BOOTCS_STOP, - *(volatile ulong*)MPC5XXX_BOOTCS_CFG, - (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); - printf ("\tSDRAMCS0: %08lX\n", - *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); - printf ("\tSDRAMCS1: %08lX\n", - *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); #elif defined(CONFIG_MPC86xx) mpc86xx_reginfo(); diff --git a/cmd/source.c b/cmd/source.c index db7ab7e..177f86b 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -22,9 +22,6 @@ #include #include #include -#if defined(CONFIG_8xx) -#include -#endif int source (ulong addr, const char *fit_uname) diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c index 86398fc..3353f95 100644 --- a/cmd/usb_mass_storage.c +++ b/cmd/usb_mass_storage.c @@ -44,7 +44,7 @@ static void ums_fini(void) for (i = 0; i < ums_count; i++) free((void *)ums[i].name); free(ums); - ums = 0; + ums = NULL; ums_count = 0; } @@ -133,7 +133,7 @@ cleanup: return ret; } -int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, +static int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { const char *usb_controller; diff --git a/common/Kconfig b/common/Kconfig index 5c39663..27dde11 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -18,6 +18,15 @@ config BOOTSTAGE Calls to show_boot_progress() will also result in log entries but these will not have names. +config SPL_BOOTSTAGE + bool "Boot timing and reported in SPL" + depends on BOOTSTAGE + help + Enable recording of boot time in SPL. To make this visible to U-Boot + proper, enable BOOTSTAGE_STASH as well. This will stash the timing + information when SPL finishes and load it when U-Boot proper starts + up. + config BOOTSTAGE_REPORT bool "Display a detailed boot timing report before booting the OS" depends on BOOTSTAGE @@ -38,7 +47,7 @@ config BOOTSTAGE_REPORT 30,361,327 445,160 start_kernel config BOOTSTAGE_USER_COUNT - hex "Number of boot ID numbers available for user use" + int "Number of boot ID numbers available for user use" default 20 help This is the number of available user bootstage records. @@ -46,6 +55,13 @@ config BOOTSTAGE_USER_COUNT a new ID will be allocated from this stash. If you exceed the limit, recording will stop. +config BOOTSTAGE_RECORD_COUNT + int "Number of boot stage records to store" + default 30 + help + This is the size of the bootstage record list and is the maximum + number of bootstage records that can be recorded. + config BOOTSTAGE_FDT bool "Store boot timing information in the OS device tree" depends on BOOTSTAGE @@ -448,7 +464,7 @@ config BOARD_LATE_INIT config DISPLAY_CPUINFO bool "Display information about the CPU during start up" - default y if ARM || NIOS2 || X86 || XTENSA || MPC5xxx + default y if ARM || NIOS2 || X86 || XTENSA help Display information about the CPU that U-Boot is running on when U-Boot starts up. The function print_cpuinfo() is called diff --git a/common/Makefile b/common/Makefile index c7c8ea4..539cf98 100644 --- a/common/Makefile +++ b/common/Makefile @@ -65,7 +65,6 @@ obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif # others -obj-$(CONFIG_BOOTSTAGE) += bootstage.o obj-$(CONFIG_CONSOLE_MUX) += iomux.o obj-$(CONFIG_MTD_NOR_FLASH) += flash.o obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o @@ -89,6 +88,8 @@ obj-$(CONFIG_CMDLINE) += cli_readline.o cli_simple.o endif # !CONFIG_SPL_BUILD +obj-$(CONFIG_$(SPL_)BOOTSTAGE) += bootstage.o + ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o diff --git a/common/board_f.c b/common/board_f.c index a212f2b..850d19d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -31,6 +31,9 @@ #include #include #include +#ifdef CONFIG_MACH_TYPE +#include +#endif #if defined(CONFIG_MP) && defined(CONFIG_PPC) #include #endif @@ -384,7 +387,7 @@ static int reserve_video(void) gd->fb_base = gd->relocaddr; # endif /* CONFIG_FB_ADDR */ #elif defined(CONFIG_VIDEO) && \ - (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ + (!defined(CONFIG_PPC)) && \ !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ !defined(CONFIG_M68K) /* reserve memory for video display (always full pages) */ @@ -488,6 +491,20 @@ static int reserve_fdt(void) return 0; } +static int reserve_bootstage(void) +{ +#ifdef CONFIG_BOOTSTAGE + int size = bootstage_get_size(); + + gd->start_addr_sp -= size; + gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); + debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, + gd->start_addr_sp); +#endif + + return 0; +} + int arch_reserve_stacks(void) { return 0; @@ -530,11 +547,10 @@ static int setup_board_part1(void) bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif -#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ - defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) +#if defined(CONFIG_M68K) bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ #endif #if defined(CONFIG_MPC83xx) @@ -558,13 +574,6 @@ static int setup_board_part2(void) bd->bi_sccfreq = gd->arch.scc_clk; bd->bi_vco = gd->arch.vco_out; #endif /* CONFIG_CPM2 */ -#if defined(CONFIG_MPC512X) - bd->bi_ipsfreq = gd->arch.ips_clk; -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) - bd->bi_ipbfreq = gd->arch.ipb_clk; - bd->bi_pcifreq = gd->pci_clk; -#endif /* CONFIG_MPC5xxx */ #if defined(CONFIG_M68K) && defined(CONFIG_PCI) bd->bi_pcifreq = gd->pci_clk; #endif @@ -602,6 +611,24 @@ static int reloc_fdt(void) return 0; } +static int reloc_bootstage(void) +{ +#ifdef CONFIG_BOOTSTAGE + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; + if (gd->new_bootstage) { + int size = bootstage_get_size(); + + debug("Copying bootstage from %p to %p, size %x\n", + gd->bootstage, gd->new_bootstage, size); + memcpy(gd->new_bootstage, gd->bootstage, size); + gd->bootstage = gd->new_bootstage; + } +#endif + + return 0; +} + static int setup_reloc(void) { if (gd->flags & GD_FLG_SKIP_RELOC) { @@ -610,13 +637,16 @@ static int setup_reloc(void) } #ifdef CONFIG_SYS_TEXT_BASE - gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; -#ifdef CONFIG_M68K +#ifdef ARM + gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; +#elif defined(CONFIG_M68K) /* * On all ColdFire arch cpu, monitor code starts always * just after the default vector table location, so at 0x400 */ gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); +#else + gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; #endif #endif memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); @@ -670,8 +700,26 @@ static int jump_to_copy(void) #endif /* Record the board_init_f() bootstage (after arch_cpu_init()) */ -static int mark_bootstage(void) +static int initf_bootstage(void) { + bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && + IS_ENABLED(CONFIG_BOOTSTAGE_STASH); + int ret; + + ret = bootstage_init(!from_spl); + if (ret) + return ret; + if (from_spl) { + const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, + CONFIG_BOOTSTAGE_STASH_SIZE); + + ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); + if (ret && ret != -ENOENT) { + debug("Failed to unstash bootstage: err=%d\n", ret); + return ret; + } + } + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); return 0; @@ -691,7 +739,9 @@ static int initf_dm(void) #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) int ret; + bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); ret = dm_init_and_scan(true); + bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); if (ret) return ret; #endif @@ -724,6 +774,7 @@ static const init_fnc_t init_sequence_f[] = { trace_early_init, #endif initf_malloc, + initf_bootstage, /* uses its own timer, so does not need DM */ initf_console_record, #if defined(CONFIG_HAVE_FSP) arch_fsp_init, @@ -732,7 +783,6 @@ static const init_fnc_t init_sequence_f[] = { mach_cpu_init, /* SoC/machine dependent CPU setup */ initf_dm, arch_cpu_init_dm, - mark_bootstage, /* need timer, go after init dm */ #if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f, #endif @@ -819,6 +869,7 @@ static const init_fnc_t init_sequence_f[] = { setup_machine, reserve_global_data, reserve_fdt, + reserve_bootstage, reserve_arch, reserve_stacks, dram_init_banksize, @@ -840,6 +891,7 @@ static const init_fnc_t init_sequence_f[] = { #endif INIT_FUNC_WATCHDOG_RESET reloc_fdt, + reloc_bootstage, setup_reloc, #if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, diff --git a/common/board_r.c b/common/board_r.c index 00ba319..adc1f19 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -11,6 +11,7 @@ */ #include +#include /* TODO: can we just include all these headers whether needed or not? */ #if defined(CONFIG_CMD_BEDBUG) #include @@ -226,13 +227,6 @@ static int initr_post_backlog(void) } #endif -#ifdef CONFIG_SYS_DELAYED_ICACHE -static int initr_icache_enable(void) -{ - return 0; -} -#endif - #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) static int initr_unlock_ram_in_cache(void) { @@ -296,8 +290,15 @@ static int initr_noncached(void) #ifdef CONFIG_OF_LIVE static int initr_of_live(void) { - return of_live_build(gd->fdt_blob, - (struct device_node **)&gd->of_root); + int ret; + + bootstage_start(BOOTSTAGE_ID_ACCUM_OF_LIVE, "of_live"); + ret = of_live_build(gd->fdt_blob, (struct device_node **)&gd->of_root); + bootstage_accum(BOOTSTAGE_ID_ACCUM_OF_LIVE); + if (ret) + return ret; + + return 0; } #endif @@ -312,7 +313,9 @@ static int initr_dm(void) #ifdef CONFIG_TIMER gd->timer = NULL; #endif + bootstage_start(BOOTSTATE_ID_ACCUM_DM_R, "dm_r"); ret = dm_init_and_scan(false); + bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R); if (ret) return ret; #ifdef CONFIG_TIMER_EARLY @@ -327,7 +330,6 @@ static int initr_dm(void) static int initr_bootstage(void) { - /* We cannot do this before initr_dm() */ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); return 0; @@ -630,11 +632,7 @@ static int initr_pcmcia(void) #if defined(CONFIG_IDE) static int initr_ide(void) { -#ifdef CONFIG_IDE_8xx_PCCARD - puts("PCMCIA:"); -#else puts("IDE: "); -#endif #if defined(CONFIG_START_IDE) if (board_start_ide()) ide_init(); @@ -726,6 +724,7 @@ static init_fnc_t init_sequence_r[] = { #endif initr_barrier, initr_malloc, + initr_bootstage, /* Needs malloc() but has its own timer */ initr_console_record, #ifdef CONFIG_SYS_NONCACHED_MEMORY initr_noncached, @@ -737,7 +736,6 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_DM initr_dm, #endif - initr_bootstage, #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) board_init, /* Setup chipselects */ #endif @@ -777,9 +775,6 @@ static init_fnc_t init_sequence_r[] = { initr_post_backlog, #endif INIT_FUNC_WATCHDOG_RESET -#ifdef CONFIG_SYS_DELAYED_ICACHE - initr_icache_enable, -#endif #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, diff --git a/common/bootm_os.c b/common/bootm_os.c index e102406..d9e6e93 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -56,7 +56,6 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], void (*loader)(bd_t *, image_header_t *, char *, char *); image_header_t *os_hdr, *hdr; ulong kernel_data, kernel_len; - char *consdev; char *cmdline; if (flag != BOOTM_STATE_OS_GO) @@ -88,17 +87,6 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], os_hdr = hdr; } - consdev = ""; -#if defined(CONFIG_8xx_CONS_SMC1) - consdev = "smc1"; -#elif defined(CONFIG_8xx_CONS_SMC2) - consdev = "smc2"; -#elif defined(CONFIG_8xx_CONS_SCC2) - consdev = "scc2"; -#elif defined(CONFIG_8xx_CONS_SCC3) - consdev = "scc3"; -#endif - if (argc > 0) { ulong len; int i; @@ -127,7 +115,7 @@ static int do_bootm_netbsd(int flag, int argc, char * const argv[], * arg[2]: char pointer to the console device to use * arg[3]: char pointer to the boot arguments */ - (*loader)(gd->bd, os_hdr, consdev, cmdline); + (*loader)(gd->bd, os_hdr, "", cmdline); return 1; } diff --git a/common/bootstage.c b/common/bootstage.c index 35bce3d..61479d7 100644 --- a/common/bootstage.c +++ b/common/bootstage.c @@ -8,8 +8,6 @@ /* * This module records the progress of boot and arbitrary commands, and * permits accurate timestamping of each. - * - * TBD: Pass timings to kernel in the FDT */ #include @@ -19,6 +17,10 @@ DECLARE_GLOBAL_DATA_PTR; +enum { + RECORD_COUNT = CONFIG_BOOTSTAGE_RECORD_COUNT, +}; + struct bootstage_record { ulong time_us; uint32_t start_us; @@ -27,8 +29,11 @@ struct bootstage_record { enum bootstage_id id; }; -static struct bootstage_record record[BOOTSTAGE_ID_COUNT] = { {1} }; -static int next_id = BOOTSTAGE_ID_USER; +struct bootstage_data { + uint rec_count; + uint next_id; + struct bootstage_record record[RECORD_COUNT]; +}; enum { BOOTSTAGE_VERSION = 0, @@ -45,41 +50,72 @@ struct bootstage_hdr { int bootstage_relocate(void) { + struct bootstage_data *data = gd->bootstage; int i; /* * Duplicate all strings. They may point to an old location in the * program .text section that can eventually get trashed. */ - for (i = 0; i < BOOTSTAGE_ID_COUNT; i++) - if (record[i].name) - record[i].name = strdup(record[i].name); + debug("Relocating %d records\n", data->rec_count); + for (i = 0; i < data->rec_count; i++) + data->record[i].name = strdup(data->record[i].name); return 0; } +struct bootstage_record *find_id(struct bootstage_data *data, + enum bootstage_id id) +{ + struct bootstage_record *rec; + struct bootstage_record *end; + + for (rec = data->record, end = rec + data->rec_count; rec < end; + rec++) { + if (rec->id == id) + return rec; + } + + return NULL; +} + +struct bootstage_record *ensure_id(struct bootstage_data *data, + enum bootstage_id id) +{ + struct bootstage_record *rec; + + rec = find_id(data, id); + if (!rec && data->rec_count < RECORD_COUNT) { + rec = &data->record[data->rec_count++]; + rec->id = id; + return rec; + } + + return rec; +} + ulong bootstage_add_record(enum bootstage_id id, const char *name, int flags, ulong mark) { + struct bootstage_data *data = gd->bootstage; struct bootstage_record *rec; if (flags & BOOTSTAGEF_ALLOC) - id = next_id++; - - if (id < BOOTSTAGE_ID_COUNT) { - rec = &record[id]; - - /* Only record the first event for each */ - if (!rec->time_us) { - rec->time_us = mark; - rec->name = name; - rec->flags = flags; - rec->id = id; - } + id = data->next_id++; + + /* Only record the first event for each */ + rec = find_id(data, id); + if (!rec && data->rec_count < RECORD_COUNT) { + rec = &data->record[data->rec_count++]; + rec->time_us = mark; + rec->name = name; + rec->flags = flags; + rec->id = id; } /* Tell the board about this progress */ show_boot_progress(flags & BOOTSTAGEF_ERROR ? -id : id); + return mark; } @@ -101,6 +137,7 @@ ulong bootstage_mark_name(enum bootstage_id id, const char *name) if (id == BOOTSTAGE_ID_ALLOC) flags = BOOTSTAGEF_ALLOC; + return bootstage_add_record(id, name, flags, timer_get_boot_us()); } @@ -133,20 +170,29 @@ ulong bootstage_mark_code(const char *file, const char *func, int linenum) uint32_t bootstage_start(enum bootstage_id id, const char *name) { - struct bootstage_record *rec = &record[id]; + struct bootstage_data *data = gd->bootstage; + struct bootstage_record *rec = ensure_id(data, id); + ulong start_us = timer_get_boot_us(); + + if (rec) { + rec->start_us = start_us; + rec->name = name; + } - rec->start_us = timer_get_boot_us(); - rec->name = name; - return rec->start_us; + return start_us; } uint32_t bootstage_accum(enum bootstage_id id) { - struct bootstage_record *rec = &record[id]; + struct bootstage_data *data = gd->bootstage; + struct bootstage_record *rec = ensure_id(data, id); uint32_t duration; + if (!rec) + return 0; duration = (uint32_t)timer_get_boot_us() - rec->start_us; rec->time_us += duration; + return duration; } @@ -159,7 +205,7 @@ uint32_t bootstage_accum(enum bootstage_id id) * @return pointer to name, either from the record or pointing to buf. */ static const char *get_record_name(char *buf, int len, - struct bootstage_record *rec) + const struct bootstage_record *rec) { if (rec->name) return rec->name; @@ -171,8 +217,7 @@ static const char *get_record_name(char *buf, int len, return buf; } -static uint32_t print_time_record(enum bootstage_id id, - struct bootstage_record *rec, uint32_t prev) +static uint32_t print_time_record(struct bootstage_record *rec, uint32_t prev) { char buf[20]; @@ -204,9 +249,10 @@ static int h_compare_record(const void *r1, const void *r2) */ static int add_bootstages_devicetree(struct fdt_header *blob) { + struct bootstage_data *data = gd->bootstage; int bootstage; char buf[20]; - int id; + int recnum; int i; if (!blob) @@ -218,17 +264,17 @@ static int add_bootstages_devicetree(struct fdt_header *blob) */ bootstage = fdt_add_subnode(blob, 0, "bootstage"); if (bootstage < 0) - return -1; + return -EINVAL; /* * Insert the timings to the device tree in the reverse order so * that they can be printed in the Linux kernel in the right order. */ - for (id = BOOTSTAGE_ID_COUNT - 1, i = 0; id >= 0; id--, i++) { - struct bootstage_record *rec = &record[id]; + for (recnum = data->rec_count - 1, i = 0; recnum >= 0; recnum--, i++) { + struct bootstage_record *rec = &data->record[recnum]; int node; - if (id != BOOTSTAGE_ID_AWAKE && rec->time_us == 0) + if (rec->id != BOOTSTAGE_ID_AWAKE && rec->time_us == 0) continue; node = fdt_add_subnode(blob, bootstage, simple_itoa(i)); @@ -237,14 +283,14 @@ static int add_bootstages_devicetree(struct fdt_header *blob) /* add properties to the node. */ if (fdt_setprop_string(blob, node, "name", - get_record_name(buf, sizeof(buf), rec))) - return -1; + get_record_name(buf, sizeof(buf), rec))) + return -EINVAL; /* Check if this is a 'mark' or 'accum' record */ if (fdt_setprop_cell(blob, node, rec->start_us ? "accum" : "mark", rec->time_us)) - return -1; + return -EINVAL; } return 0; @@ -261,54 +307,36 @@ int bootstage_fdt_add_report(void) void bootstage_report(void) { - struct bootstage_record *rec = record; - int id; + struct bootstage_data *data = gd->bootstage; + struct bootstage_record *rec = data->record; uint32_t prev; + int i; - puts("Timer summary in microseconds:\n"); + printf("Timer summary in microseconds (%d records):\n", + data->rec_count); printf("%11s%11s %s\n", "Mark", "Elapsed", "Stage"); - /* Fake the first record - we could get it from early boot */ - rec->name = "reset"; - rec->time_us = 0; - prev = print_time_record(BOOTSTAGE_ID_AWAKE, rec, 0); + prev = print_time_record(rec, 0); /* Sort records by increasing time */ - qsort(record, ARRAY_SIZE(record), sizeof(*rec), h_compare_record); + qsort(data->record, data->rec_count, sizeof(*rec), h_compare_record); - for (id = 0; id < BOOTSTAGE_ID_COUNT; id++, rec++) { - if (rec->time_us != 0 && !rec->start_us) - prev = print_time_record(rec->id, rec, prev); + for (i = 1, rec++; i < data->rec_count; i++, rec++) { + if (rec->id && !rec->start_us) + prev = print_time_record(rec, prev); } - if (next_id > BOOTSTAGE_ID_COUNT) - printf("(Overflowed internal boot id table by %d entries\n" - "- please increase CONFIG_BOOTSTAGE_USER_COUNT\n", - next_id - BOOTSTAGE_ID_COUNT); + if (data->rec_count > RECORD_COUNT) + printf("Overflowed internal boot id table by %d entries\n" + "- please increase CONFIG_BOOTSTAGE_RECORD_COUNT\n", + data->rec_count - RECORD_COUNT); puts("\nAccumulated time:\n"); - for (id = 0, rec = record; id < BOOTSTAGE_ID_COUNT; id++, rec++) { + for (i = 0, rec = data->record; i < data->rec_count; i++, rec++) { if (rec->start_us) - prev = print_time_record(id, rec, -1); + prev = print_time_record(rec, -1); } } -ulong __timer_get_boot_us(void) -{ - static ulong base_time; - - /* - * We can't implement this properly. Return 0 on the first call and - * larger values after that. - */ - if (base_time) - return get_timer(base_time) * 1000; - base_time = get_timer(0); - return 0; -} - -ulong timer_get_boot_us(void) - __attribute__((weak, alias("__timer_get_boot_us"))); - /** * Append data to a memory buffer * @@ -333,25 +361,26 @@ static void append_data(char **ptrp, char *end, const void *data, int size) int bootstage_stash(void *base, int size) { + const struct bootstage_data *data = gd->bootstage; struct bootstage_hdr *hdr = (struct bootstage_hdr *)base; - struct bootstage_record *rec; + const struct bootstage_record *rec; char buf[20]; char *ptr = base, *end = ptr + size; uint32_t count; - int id; + int i; if (hdr + 1 > (struct bootstage_hdr *)end) { debug("%s: Not enough space for bootstage hdr\n", __func__); - return -1; + return -ENOSPC; } /* Write an arbitrary version number */ hdr->version = BOOTSTAGE_VERSION; /* Count the number of records, and write that value first */ - for (rec = record, id = count = 0; id < BOOTSTAGE_ID_COUNT; - id++, rec++) { - if (rec->time_us != 0) + for (rec = data->record, i = count = 0; i < data->rec_count; + i++, rec++) { + if (rec->id != 0) count++; } hdr->count = count; @@ -360,89 +389,88 @@ int bootstage_stash(void *base, int size) ptr += sizeof(*hdr); /* Write the records, silently stopping when we run out of space */ - for (rec = record, id = 0; id < BOOTSTAGE_ID_COUNT; id++, rec++) { - if (rec->time_us != 0) - append_data(&ptr, end, rec, sizeof(*rec)); + for (rec = data->record, i = 0; i < data->rec_count; i++, rec++) { + append_data(&ptr, end, rec, sizeof(*rec)); } /* Write the name strings */ - for (rec = record, id = 0; id < BOOTSTAGE_ID_COUNT; id++, rec++) { - if (rec->time_us != 0) { - const char *name; + for (rec = data->record, i = 0; i < data->rec_count; i++, rec++) { + const char *name; - name = get_record_name(buf, sizeof(buf), rec); - append_data(&ptr, end, name, strlen(name) + 1); - } + name = get_record_name(buf, sizeof(buf), rec); + append_data(&ptr, end, name, strlen(name) + 1); } /* Check for buffer overflow */ if (ptr > end) { debug("%s: Not enough space for bootstage stash\n", __func__); - return -1; + return -ENOSPC; } /* Update total data size */ hdr->size = ptr - (char *)base; - printf("Stashed %d records\n", hdr->count); + debug("Stashed %d records\n", hdr->count); return 0; } -int bootstage_unstash(void *base, int size) +int bootstage_unstash(const void *base, int size) { - struct bootstage_hdr *hdr = (struct bootstage_hdr *)base; + const struct bootstage_hdr *hdr = (struct bootstage_hdr *)base; + struct bootstage_data *data = gd->bootstage; + const char *ptr = base, *end = ptr + size; struct bootstage_record *rec; - char *ptr = base, *end = ptr + size; uint rec_size; - int id; + int i; if (size == -1) end = (char *)(~(uintptr_t)0); if (hdr + 1 > (struct bootstage_hdr *)end) { debug("%s: Not enough space for bootstage hdr\n", __func__); - return -1; + return -EPERM; } if (hdr->magic != BOOTSTAGE_MAGIC) { debug("%s: Invalid bootstage magic\n", __func__); - return -1; + return -ENOENT; } if (ptr + hdr->size > end) { debug("%s: Bootstage data runs past buffer end\n", __func__); - return -1; + return -ENOSPC; } if (hdr->count * sizeof(*rec) > hdr->size) { debug("%s: Bootstage has %d records needing %lu bytes, but " "only %d bytes is available\n", __func__, hdr->count, (ulong)hdr->count * sizeof(*rec), hdr->size); - return -1; + return -ENOSPC; } if (hdr->version != BOOTSTAGE_VERSION) { debug("%s: Bootstage data version %#0x unrecognised\n", __func__, hdr->version); - return -1; + return -EINVAL; } - if (next_id + hdr->count > BOOTSTAGE_ID_COUNT) { + if (data->rec_count + hdr->count > RECORD_COUNT) { debug("%s: Bootstage has %d records, we have space for %d\n" "- please increase CONFIG_BOOTSTAGE_USER_COUNT\n", - __func__, hdr->count, BOOTSTAGE_ID_COUNT - next_id); - return -1; + __func__, hdr->count, RECORD_COUNT - data->rec_count); + return -ENOSPC; } ptr += sizeof(*hdr); /* Read the records */ - rec_size = hdr->count * sizeof(*record); - memcpy(record + next_id, ptr, rec_size); + rec_size = hdr->count * sizeof(*data->record); + memcpy(data->record + data->rec_count, ptr, rec_size); /* Read the name strings */ ptr += rec_size; - for (rec = record + next_id, id = 0; id < hdr->count; id++, rec++) { + for (rec = data->record + data->next_id, i = 0; i < hdr->count; + i++, rec++) { rec->name = ptr; /* Assume no data corruption here */ @@ -450,8 +478,31 @@ int bootstage_unstash(void *base, int size) } /* Mark the records as read */ - next_id += hdr->count; - printf("Unstashed %d records\n", hdr->count); + data->rec_count += hdr->count; + debug("Unstashed %d records\n", hdr->count); + + return 0; +} + +int bootstage_get_size(void) +{ + return sizeof(struct bootstage_data); +} + +int bootstage_init(bool first) +{ + struct bootstage_data *data; + int size = sizeof(struct bootstage_data); + + gd->bootstage = (struct bootstage_data *)malloc(size); + if (!gd->bootstage) + return -ENOMEM; + data = gd->bootstage; + memset(data, '\0', size); + if (first) { + data->next_id = BOOTSTAGE_ID_USER; + bootstage_add_record(BOOTSTAGE_ID_AWAKE, "reset", 0, 0); + } return 0; } diff --git a/common/dlmalloc.c b/common/dlmalloc.c index adc680e..fc1e8b3 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1,6 +1,6 @@ #include -#ifdef CONFIG_SANDBOX +#if defined(CONFIG_UNIT_TEST) #define DEBUG #endif diff --git a/common/edid.c b/common/edid.c index 19410aa..3d0809a 100644 --- a/common/edid.c +++ b/common/edid.c @@ -148,8 +148,8 @@ static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) /* check for end of data block */ end = info->dtd_offset; if (end == 0) - end = 127; - if (end < 4 || end > 127) + end = sizeof(info->data); + if (end < 4 || end > sizeof(info->data)) return false; end -= 4; @@ -295,7 +295,7 @@ static void edid_print_dtd(struct edid_monitor_descriptor *monitor, h_total = h_active + h_blanking; v_total = v_active + v_blanking; - if (v_total * h_total) + if (v_total > 0 && h_total > 0) vfreq = pixclock / (v_total * h_total); else vfreq = 1; /* Error case */ diff --git a/common/env_mmc.c b/common/env_mmc.c index 404de85..88b043e 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -121,7 +121,12 @@ static const char *init_mmc_for_env(struct mmc *mmc) if (!mmc) return "!No MMC card found"; -#ifndef CONFIG_BLK +#ifdef CONFIG_BLK + struct udevice *dev; + + if (blk_get_from_parent(mmc->dev, &dev)) + return "!No block device"; +#else if (mmc_init(mmc)) return "!MMC init failed"; #endif diff --git a/common/fb_mmc.c b/common/fb_mmc.c index 866982e..2113b6c 100644 --- a/common/fb_mmc.c +++ b/common/fb_mmc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include /* * FIXME: Ensure we always set these names via Kconfig once xxx_PARTITION is @@ -27,6 +29,8 @@ #define CONFIG_FASTBOOT_MBR_NAME "mbr" #endif +#define BOOT_PARTITION_NAME "boot" + struct fb_mmc_sparse { struct blk_desc *dev_desc; }; @@ -99,6 +103,163 @@ static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info, fastboot_okay(""); } +#ifdef CONFIG_ANDROID_BOOT_IMAGE +/** + * Read Android boot image header from boot partition. + * + * @param[in] dev_desc MMC device descriptor + * @param[in] info Boot partition info + * @param[out] hdr Where to store read boot image header + * + * @return Boot image header sectors count or 0 on error + */ +static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc, + disk_partition_t *info, + struct andr_img_hdr *hdr) +{ + ulong sector_size; /* boot partition sector size */ + lbaint_t hdr_sectors; /* boot image header sectors count */ + int res; + + /* Calculate boot image sectors count */ + sector_size = info->blksz; + hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_img_hdr), sector_size); + if (hdr_sectors == 0) { + error("invalid number of boot sectors: 0"); + fastboot_fail("invalid number of boot sectors: 0"); + return 0; + } + + /* Read the boot image header */ + res = blk_dread(dev_desc, info->start, hdr_sectors, (void *)hdr); + if (res == 0) { + error("cannot read header from boot partition"); + fastboot_fail("cannot read header from boot partition"); + return 0; + } + + /* Check boot header magic string */ + res = android_image_check_header(hdr); + if (res != 0) { + error("bad boot image magic"); + fastboot_fail("boot partition not initialized"); + return 0; + } + + return hdr_sectors; +} + +/** + * Write downloaded zImage to boot partition and repack it properly. + * + * @param dev_desc MMC device descriptor + * @param download_buffer Address to fastboot buffer with zImage in it + * @param download_bytes Size of fastboot buffer, in bytes + * + * @return 0 on success or -1 on error + */ +static int fb_mmc_update_zimage(struct blk_desc *dev_desc, + void *download_buffer, + unsigned int download_bytes) +{ + u32 hdr_addr; /* boot image header address */ + struct andr_img_hdr *hdr; /* boot image header */ + lbaint_t hdr_sectors; /* boot image header sectors */ + u8 *ramdisk_buffer; + u32 ramdisk_sector_start; + u32 ramdisk_sectors; + u32 kernel_sector_start; + u32 kernel_sectors; + u32 sectors_per_page; + disk_partition_t info; + int res; + + puts("Flashing zImage\n"); + + /* Get boot partition info */ + res = part_get_info_by_name(dev_desc, BOOT_PARTITION_NAME, &info); + if (res < 0) { + error("cannot find boot partition"); + fastboot_fail("cannot find boot partition"); + return -1; + } + + /* Put boot image header in fastboot buffer after downloaded zImage */ + hdr_addr = (u32)download_buffer + ALIGN(download_bytes, PAGE_SIZE); + hdr = (struct andr_img_hdr *)hdr_addr; + + /* Read boot image header */ + hdr_sectors = fb_mmc_get_boot_header(dev_desc, &info, hdr); + if (hdr_sectors == 0) { + error("unable to read boot image header"); + fastboot_fail("unable to read boot image header"); + return -1; + } + + /* Check if boot image has second stage in it (we don't support it) */ + if (hdr->second_size > 0) { + error("moving second stage is not supported yet"); + fastboot_fail("moving second stage is not supported yet"); + return -1; + } + + /* Extract ramdisk location */ + sectors_per_page = hdr->page_size / info.blksz; + ramdisk_sector_start = info.start + sectors_per_page; + ramdisk_sector_start += DIV_ROUND_UP(hdr->kernel_size, hdr->page_size) * + sectors_per_page; + ramdisk_sectors = DIV_ROUND_UP(hdr->ramdisk_size, hdr->page_size) * + sectors_per_page; + + /* Read ramdisk and put it in fastboot buffer after boot image header */ + ramdisk_buffer = (u8 *)hdr + (hdr_sectors * info.blksz); + res = blk_dread(dev_desc, ramdisk_sector_start, ramdisk_sectors, + ramdisk_buffer); + if (res == 0) { + error("cannot read ramdisk from boot partition"); + fastboot_fail("cannot read ramdisk from boot partition"); + return -1; + } + + /* Write new kernel size to boot image header */ + hdr->kernel_size = download_bytes; + res = blk_dwrite(dev_desc, info.start, hdr_sectors, (void *)hdr); + if (res == 0) { + error("cannot writeback boot image header"); + fastboot_fail("cannot write back boot image header"); + return -1; + } + + /* Write the new downloaded kernel */ + kernel_sector_start = info.start + sectors_per_page; + kernel_sectors = DIV_ROUND_UP(hdr->kernel_size, hdr->page_size) * + sectors_per_page; + res = blk_dwrite(dev_desc, kernel_sector_start, kernel_sectors, + download_buffer); + if (res == 0) { + error("cannot write new kernel"); + fastboot_fail("cannot write new kernel"); + return -1; + } + + /* Write the saved ramdisk back */ + ramdisk_sector_start = info.start + sectors_per_page; + ramdisk_sector_start += DIV_ROUND_UP(hdr->kernel_size, hdr->page_size) * + sectors_per_page; + res = blk_dwrite(dev_desc, ramdisk_sector_start, ramdisk_sectors, + ramdisk_buffer); + if (res == 0) { + error("cannot write back original ramdisk"); + fastboot_fail("cannot write back original ramdisk"); + return -1; + } + + puts("........ zImage was updated in boot partition\n"); + fastboot_okay(""); + return 0; +} +#endif + void fb_mmc_flash_write(const char *cmd, void *download_buffer, unsigned int download_bytes) { @@ -153,6 +314,13 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, } #endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + if (strncasecmp(cmd, "zimage", 6) == 0) { + fb_mmc_update_zimage(dev_desc, download_buffer, download_bytes); + return; + } +#endif + if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) { error("cannot find partition: '%s'\n", cmd); fastboot_fail("cannot find partition"); diff --git a/common/lcd.c b/common/lcd.c index 2405146..7e399ce 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -562,11 +562,7 @@ __weak void lcd_set_cmap(struct bmp_image *bmp, unsigned colors) *cmap = (((cte.red) << 8) & 0xf800) | (((cte.green) << 3) & 0x07e0) | (((cte.blue) >> 3) & 0x001f); -#if defined(CONFIG_MPC823) - cmap--; -#else cmap++; -#endif } } diff --git a/common/lynxkdi.c b/common/lynxkdi.c index 22ad384..9856015 100644 --- a/common/lynxkdi.c +++ b/common/lynxkdi.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) void lynxkdi_boot(image_header_t *hdr) { void (*lynxkdi)(void) = (void(*)(void))image_get_ep(hdr); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 48a0fad..4de8139 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -16,8 +16,9 @@ config SPL help If you want to build SPL as well as the normal image, say Y. +if SPL + config SPL_BOARD_INIT - depends on SPL bool "Call board-specific initialization in SPL" help If this option is enabled, U-Boot will call the function @@ -26,7 +27,6 @@ config SPL_BOARD_INIT config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" - depends on SPL default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) default y if !TI_SECURE_DEVICE help @@ -44,7 +44,6 @@ config SPL_LEGACY_IMAGE_SUPPORT config SPL_SYS_MALLOC_SIMPLE bool - depends on SPL prompt "Only use malloc_simple functions in the SPL" help Say Y here to only use the *_simple malloc functions from @@ -53,7 +52,6 @@ config SPL_SYS_MALLOC_SIMPLE usage as the *_simple malloc functions do not re-use free-ed mem. config SPL_STACK_R - depends on SPL bool "Enable SDRAM location for SPL stack" help SPL starts off execution in SRAM and thus typically has only a small @@ -81,7 +79,6 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN SRAM which is limited to SYS_MALLOC_F_LEN bytes. config SPL_SEPARATE_BSS - depends on SPL bool "BSS section is in a different memory region from text" help Some platforms need a large BSS region in SPL and can provide this @@ -91,7 +88,6 @@ config SPL_SEPARATE_BSS but with this option enabled, it goes at _image_binary_end. config SPL_DISPLAY_PRINT - depends on SPL bool "Display a board-specific message in SPL" help If this option is enabled, U-Boot will call the function @@ -101,7 +97,6 @@ config SPL_DISPLAY_PRINT config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool "MMC raw mode: by sector" - depends on SPL default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_MX6 || \ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ @@ -112,7 +107,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR hex "Address on the MMC to load U-Boot from" - depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR default 0x50 if ARCH_SUNXI default 0x75 if ARCH_DAVINCI default 0x8a if ARCH_MX6 @@ -127,13 +122,12 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION bool "MMC Raw mode: by partition" - depends on SPL help Use a partition for loading U-Boot when using MMC/SD in raw mode. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION hex "Partition to use to load U-Boot from" - depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION default 1 help Partition on the MMC to load U-Boot from when the MMC is being @@ -141,8 +135,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE bool "MMC raw mode: by partition type" - depends on SPL && DOS_PARTITION && \ - SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + depends on DOS_PARTITION && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION help Use partition type for specifying U-Boot partition on MMC/SD in raw mode. U-Boot will be loaded from the first partition of this @@ -150,18 +143,11 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE hex "Partition Type on the MMC to load U-Boot from" - depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE help Partition Type on the MMC to load U-Boot from, when the MMC is being used in raw mode. -config TPL - bool - depends on SPL && SUPPORT_TPL - prompt "Enable TPL" - help - If you want to build TPL as well as the normal image and SPL, say Y. - config SPL_CRC32_SUPPORT bool "Support CRC32" depends on SPL_FIT @@ -212,7 +198,6 @@ config SPL_SHA256_SUPPORT config SPL_CPU_SUPPORT bool "Support CPU drivers" - depends on SPL help Enable this to support CPU drivers in SPL. These drivers can set up CPUs and provide information about them such as the model and @@ -222,7 +207,6 @@ config SPL_CPU_SUPPORT config SPL_CRYPTO_SUPPORT bool "Support crypto drivers" - depends on SPL help Enable crypto drivers in SPL. These drivers can be used to accelerate secure boot processing in secure applications. Enable @@ -233,7 +217,6 @@ config SPL_HASH_SUPPORT bool "Support hashing drivers" select SHA1 select SHA256 - depends on SPL help Enable hashing drivers in SPL. These drivers can be used to accelerate secure boot processing in secure applications. Enable @@ -242,7 +225,6 @@ config SPL_HASH_SUPPORT config SPL_DMA_SUPPORT bool "Support DMA drivers" - depends on SPL help Enable DMA (direct-memory-access) drivers in SPL. These drivers can be used to handle memory-to-peripheral data transfer without @@ -251,7 +233,6 @@ config SPL_DMA_SUPPORT config SPL_DRIVERS_MISC_SUPPORT bool "Support misc drivers" - depends on SPL help Enable miscellaneous drivers in SPL. These drivers perform various tasks that don't fall nicely into other categories, Enable this @@ -260,7 +241,6 @@ config SPL_DRIVERS_MISC_SUPPORT config SPL_ENV_SUPPORT bool "Support an environment" - depends on SPL help Enable environment support in SPL. The U-Boot environment provides a number of settings (essentially name/value pairs) which can @@ -273,7 +253,7 @@ config SPL_ENV_SUPPORT config SPL_SAVEENV bool "Support save environment" - depends on SPL && SPL_ENV_SUPPORT + depends on SPL_ENV_SUPPORT help Enable save environment support in SPL after setenv. By default the saveenv option is not provided in SPL, but some boards need @@ -296,7 +276,6 @@ config SPL_ETH_SUPPORT config SPL_EXT_SUPPORT bool "Support EXT filesystems" - depends on SPL help Enable support for EXT2/3/4 filesystems with SPL. This permits U-Boot (or Linux in Falcon mode) to be loaded from an EXT @@ -305,7 +284,6 @@ config SPL_EXT_SUPPORT config SPL_FAT_SUPPORT bool "Support FAT filesystems" - depends on SPL select FS_FAT help Enable support for FAT and VFAT filesystems with SPL. This @@ -315,7 +293,6 @@ config SPL_FAT_SUPPORT config SPL_FPGA_SUPPORT bool "Support FPGAs" - depends on SPL help Enable support for FPGAs in SPL. Field-programmable Gate Arrays provide software-configurable hardware which is typically used to @@ -327,7 +304,6 @@ config SPL_FPGA_SUPPORT config SPL_GPIO_SUPPORT bool "Support GPIO" - depends on SPL help Enable support for GPIOs (General-purpose Input/Output) in SPL. GPIOs allow U-Boot to read the state of an input line (high or @@ -339,7 +315,6 @@ config SPL_GPIO_SUPPORT config SPL_I2C_SUPPORT bool "Support I2C" - depends on SPL help Enable support for the I2C (Inter-Integrated Circuit) bus in SPL. I2C works with a clock and data line which can be driven by a @@ -353,7 +328,6 @@ config SPL_I2C_SUPPORT config SPL_LIBCOMMON_SUPPORT bool "Support common libraries" - depends on SPL help Enable support for common U-Boot libraries within SPL. These libraries include common code to deal with U-Boot images, @@ -363,7 +337,6 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBDISK_SUPPORT bool "Support disk paritions" - depends on SPL help Enable support for disk partitions within SPL. 'Disk' is something of a misnomer as it includes non-spinning media such as flash (as @@ -377,7 +350,6 @@ config SPL_LIBDISK_SUPPORT config SPL_LIBGENERIC_SUPPORT bool "Support generic libraries" - depends on SPL help Enable support for generic U-Boot libraries within SPL. These libraries include generic code to deal with device tree, hashing, @@ -387,7 +359,7 @@ config SPL_LIBGENERIC_SUPPORT config SPL_MMC_SUPPORT bool "Support MMC" - depends on SPL && MMC + depends on MMC help Enable support for MMC (Multimedia Card) within SPL. This enables the MMC protocol implementation and allows any enabled drivers to @@ -398,7 +370,6 @@ config SPL_MMC_SUPPORT config SPL_MPC8XXX_INIT_DDR_SUPPORT bool "Support MPC8XXX DDR init" - depends on SPL help Enable support for DDR-SDRAM (double-data-rate synchronous dynamic random-access memory) on the MPC8XXX family within SPL. This @@ -407,7 +378,6 @@ config SPL_MPC8XXX_INIT_DDR_SUPPORT config SPL_MTD_SUPPORT bool "Support MTD drivers" - depends on SPL help Enable support for MTD (Memory Technology Device) within SPL. MTD provides a block interface over raw NAND and can also be used with @@ -417,7 +387,6 @@ config SPL_MTD_SUPPORT config SPL_MUSB_NEW_SUPPORT bool "Support new Mentor Graphics USB" - depends on SPL help Enable support for Mentor Graphics USB in SPL. This is a new driver used by some boards. Enable this option to build @@ -426,7 +395,6 @@ config SPL_MUSB_NEW_SUPPORT config SPL_NAND_SUPPORT bool "Support NAND flash" - depends on SPL help Enable support for NAND (Negative AND) flash in SPL. NAND flash can be used to allow SPL to load U-Boot from supported devices. @@ -435,7 +403,6 @@ config SPL_NAND_SUPPORT config SPL_NET_SUPPORT bool "Support networking" - depends on SPL help Enable support for network devices (such as Ethernet) in SPL. This permits SPL to load U-Boot over a network link rather than @@ -456,7 +423,6 @@ endif # if SPL_NET_SUPPORT config SPL_NO_CPU_SUPPORT bool "Drop CPU code in SPL" - depends on SPL help This is specific to the ARM926EJ-S CPU. It disables the standard start.S start-up code, presumably so that a replacement can be @@ -465,16 +431,23 @@ config SPL_NO_CPU_SUPPORT config SPL_NOR_SUPPORT bool "Support NOR flash" - depends on SPL help Enable support for loading U-Boot from memory-mapped NOR (Negative OR) flash in SPL. NOR flash is slow to write but fast to read, and a memory-mapped device makes it very easy to access. Loading from NOR is typically achieved with just a memcpy(). +config SPL_XIP_SUPPORT + bool "Support XIP" + depends on SPL + help + Enable support for execute in place of U-Boot or kernel image. There + is no need to copy image from flash to ram if flash supports execute + in place. Its very useful in systems having enough flash but not + enough ram to load the image. + config SPL_ONENAND_SUPPORT bool "Support OneNAND flash" - depends on SPL help Enable support for OneNAND (Negative AND) flash in SPL. OneNAND is a type of NAND flash and therefore can be used to allow SPL to @@ -483,7 +456,7 @@ config SPL_ONENAND_SUPPORT config SPL_OS_BOOT bool "Activate Falcon Mode" - depends on SPL && !TI_SECURE_DEVICE + depends on !TI_SECURE_DEVICE default n help Enable booting directly to an OS from SPL. @@ -492,7 +465,7 @@ config SPL_OS_BOOT if SPL_OS_BOOT config SYS_OS_BASE hex "addr, where OS is found" - depends on SPL && SPL_NOR_SUPPORT + depends on SPL_NOR_SUPPORT help Specify the address, where the OS image is found, which gets booted. @@ -501,7 +474,6 @@ endif # SPL_OS_BOOT config SPL_PCI_SUPPORT bool "Support PCI drivers" - depends on SPL help Enable support for PCI in SPL. For platforms that need PCI to boot, or must perform some init using PCI in SPL, this provides the @@ -510,7 +482,6 @@ config SPL_PCI_SUPPORT config SPL_PCH_SUPPORT bool "Support PCH drivers" - depends on SPL help Enable support for PCH (Platform Controller Hub) devices in SPL. These are used to set up GPIOs and the SPI peripheral early in @@ -519,7 +490,6 @@ config SPL_PCH_SUPPORT config SPL_POST_MEM_SUPPORT bool "Support POST drivers" - depends on SPL help Enable support for POST (Power-on Self Test) in SPL. POST is a procedure that checks that the hardware (CPU or board) appears to @@ -529,7 +499,6 @@ config SPL_POST_MEM_SUPPORT config SPL_POWER_SUPPORT bool "Support power drivers" - depends on SPL help Enable support for power control in SPL. This includes support for PMICs (Power-management Integrated Circuits) and some of the @@ -542,7 +511,6 @@ config SPL_POWER_SUPPORT config SPL_RAM_SUPPORT bool "Support booting from RAM" - depends on SPL default y if MICROBLAZE || ARCH_SOCFPGA || TEGRA || ARCH_ZYNQ help Enable booting of an image in RAM. The image can be preloaded or @@ -559,7 +527,6 @@ config SPL_RAM_DEVICE config SPL_RTC_SUPPORT bool "Support RTC drivers" - depends on SPL help Enable RTC (Real-time Clock) support in SPL. This includes support for reading and setting the time. Some RTC devices also have some @@ -569,7 +536,6 @@ config SPL_RTC_SUPPORT config SPL_SATA_SUPPORT bool "Support loading from SATA" - depends on SPL help Enable support for SATA (Serial AT attachment) in SPL. This allows use of SATA devices such as hard drives and flash drivers for @@ -580,7 +546,6 @@ config SPL_SATA_SUPPORT config SPL_SERIAL_SUPPORT bool "Support serial" - depends on SPL help Enable support for serial in SPL. This allows use of a serial UART for displaying messages while SPL is running. It also brings in @@ -590,7 +555,6 @@ config SPL_SERIAL_SUPPORT config SPL_SPI_FLASH_SUPPORT bool "Support SPI flash drivers" - depends on SPL help Enable support for using SPI flash in SPL, and loading U-Boot from SPI flash. SPI flash (Serial Peripheral Bus flash) is named after @@ -601,7 +565,6 @@ config SPL_SPI_FLASH_SUPPORT config SPL_SPI_SUPPORT bool "Support SPI drivers" - depends on SPL help Enable support for using SPI in SPL. This is used for connecting to SPI flash for loading U-Boot. See SPL_SPI_FLASH_SUPPORT for @@ -612,7 +575,6 @@ config SPL_SPI_SUPPORT config SPL_TIMER_SUPPORT bool "Support timer drivers" - depends on SPL help Enable support for timer drivers in SPL. These can be used to get a timer value when in SPL, or perhaps for implementing a delay @@ -621,7 +583,6 @@ config SPL_TIMER_SUPPORT config SPL_USB_HOST_SUPPORT bool "Support USB host drivers" - depends on SPL help Enable access to USB (Universal Serial Bus) host devices so that SPL can load U-Boot from a connected USB peripheral, such as a USB @@ -642,7 +603,6 @@ config SPL_USB_SUPPORT config SPL_USB_GADGET_SUPPORT bool "Suppport USB Gadget drivers" - depends on SPL help Enable USB Gadget API which allows to enable USB device functions in SPL. @@ -690,7 +650,6 @@ endif config SPL_WATCHDOG_SUPPORT bool "Support watchdog drivers" - depends on SPL help Enable support for watchdog drivers in SPL. A watchdog is typically a hardware peripheral which can reset the system when it @@ -699,7 +658,6 @@ config SPL_WATCHDOG_SUPPORT config SPL_YMODEM_SUPPORT bool "Support loading using Ymodem" - depends on SPL help While loading from serial is slow it can be a useful backup when there is no other option. The Ymodem protocol provides a reliable @@ -708,7 +666,7 @@ config SPL_YMODEM_SUPPORT config SPL_ATF_SUPPORT bool "Support ARM Trusted Firmware" - depends on SPL && ARM64 + depends on ARM64 help ATF(ARM Trusted Firmware) is a component for ARM arch64 which which is loaded by SPL(which is considered as BL2 in ATF terminology). @@ -720,71 +678,74 @@ config SPL_ATF_TEXT_BASE help This is the base address in memory for ATF BL31 text and entry point. +config TPL + bool + depends on SUPPORT_TPL + prompt "Enable TPL" + help + If you want to build TPL as well as the normal image and SPL, say Y. + +if TPL + config TPL_ENV_SUPPORT bool "Support an environment" - depends on TPL help Enable environment support in TPL. See SPL_ENV_SUPPORT for details. config TPL_I2C_SUPPORT bool "Support I2C" - depends on TPL help Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for details. config TPL_LIBCOMMON_SUPPORT bool "Support common libraries" - depends on TPL help Enable support for common U-Boot libraries within TPL. See SPL_LIBCOMMON_SUPPORT for details. config TPL_LIBGENERIC_SUPPORT bool "Support generic libraries" - depends on TPL help Enable support for generic U-Boot libraries within TPL. See SPL_LIBGENERIC_SUPPORT for details. config TPL_MPC8XXX_INIT_DDR_SUPPORT bool "Support MPC8XXX DDR init" - depends on TPL help Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See SPL_MPC8XXX_INIT_DDR_SUPPORT for details. config TPL_MMC_SUPPORT bool "Support MMC" - depends on TPL && MMC + depends on MMC help Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details. config TPL_NAND_SUPPORT bool "Support NAND flash" - depends on TPL help Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details. config TPL_SERIAL_SUPPORT bool "Support serial" - depends on TPL help Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for details. config TPL_SPI_FLASH_SUPPORT bool "Support SPI flash drivers" - depends on TPL help Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT for details. config TPL_SPI_SUPPORT bool "Support SPI drivers" - depends on TPL help Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for details. +endif # TPL + +endif # SPL endmenu diff --git a/common/spl/Makefile b/common/spl/Makefile index b3b34d6..47a64dd 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -12,6 +12,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o +obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o ifndef CONFIG_SPL_UBI obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o diff --git a/common/spl/spl.c b/common/spl/spl.c index 0a49766..7f3fd92 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -121,9 +121,6 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) { spl_image->size = CONFIG_SYS_MONITOR_LEN; spl_image->entry_point = CONFIG_SYS_UBOOT_START; -#ifdef CONFIG_CPU_V7M - spl_image->entry_point |= 0x1; -#endif spl_image->load_addr = CONFIG_SYS_TEXT_BASE; spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; @@ -232,6 +229,13 @@ static int spl_common_init(bool setup_malloc) gd->malloc_ptr = 0; } #endif + ret = bootstage_init(true); + if (ret) { + debug("%s: Failed to set up bootstage: ret=%d\n", __func__, + ret); + return ret; + } + bootstage_mark_name(BOOTSTAGE_ID_START_SPL, "spl"); if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = fdtdec_setup(); if (ret) { @@ -240,8 +244,10 @@ static int spl_common_init(bool setup_malloc) } } if (IS_ENABLED(CONFIG_SPL_DM)) { + bootstage_start(BOOTSTATE_ID_ACCUM_DM_SPL, "dm_spl"); /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA)); + bootstage_accum(BOOTSTATE_ID_ACCUM_DM_SPL); if (ret) { debug("dm_init_and_scan() returned error %d\n", ret); return ret; @@ -396,6 +402,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) hang(); } +#ifdef CONFIG_CPU_V7M + spl_image.entry_point |= 0x1; +#endif switch (spl_image.os) { case IH_OS_U_BOOT: debug("Jumping to U-Boot\n"); @@ -421,6 +430,15 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } debug("loaded - jumping to U-Boot...\n"); +#ifdef CONFIG_BOOTSTAGE_STASH + int ret; + + bootstage_mark_name(BOOTSTAGE_ID_END_SPL, "end_spl"); + ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, + CONFIG_BOOTSTAGE_STASH_SIZE); + if (ret) + debug("Failed to stash bootstage: err=%d\n", ret); +#endif spl_board_prepare_for_boot(); jump_to_image_no_args(&spl_image); } diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c new file mode 100644 index 0000000..18c7d11 --- /dev/null +++ b/common/spl/spl_xip.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2017 Vikas Manocha + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +static int spl_xip(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ +#ifdef CONFIG_SPL_OS_BOOT + if (!spl_start_uboot()) { + spl_image->arg = (void *)CONFIG_SYS_FDT_BASE; + spl_image->name = "Linux"; + spl_image->os = IH_OS_LINUX; + spl_image->load_addr = CONFIG_SYS_LOAD_ADDR; + spl_image->entry_point = CONFIG_SYS_LOAD_ADDR; + debug("spl: payload xipImage, load addr: 0x%lx\n", + spl_image->load_addr); + return 0; + } +#endif + return(spl_parse_image_header(spl_image, (const struct image_header *) + CONFIG_SYS_UBOOT_BASE)); +} +SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip); diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 6c3a044..5db680b 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig index 589ad9e..3c563d6 100644 --- a/configs/MPC8536DS_defconfig +++ b/configs/MPC8536DS_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig deleted file mode 100644 index cef9c11..0000000 --- a/configs/MPC8540ADS_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_MPC8540ADS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig index 1798622..aef9bac 100644 --- a/configs/MPC8544DS_defconfig +++ b/configs/MPC8544DS_defconfig @@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 277043e..fd3b8d6 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index a0c2f00..e090a5b 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -7,6 +7,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig deleted file mode 100644 index 2ceab0d..0000000 --- a/configs/MPC8560ADS_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_MPC8560ADS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y -CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig index c41712f..6e3cfa1 100644 --- a/configs/MPC8568MDS_defconfig +++ b/configs/MPC8568MDS_defconfig @@ -8,6 +8,7 @@ CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index cbbf4bc..6adb9cf 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig index 45c4f54..73cf6e3 100644 --- a/configs/MPC8569MDS_defconfig +++ b/configs/MPC8569MDS_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index 64fe8e4..aa2a464 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -10,6 +10,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig deleted file mode 100644 index b9cbafc..0000000 --- a/configs/MiniFAP_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MINIFAP" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig deleted file mode 100644 index c0e9541..0000000 --- a/configs/O2D300_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2D300=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig deleted file mode 100644 index 8cff44c..0000000 --- a/configs/O2DNT2_RAMBOOT_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2DNT2=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" -CONFIG_AUTOBOOT_STOP_STR="++++++++++" -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig deleted file mode 100644 index f29abb8..0000000 --- a/configs/O2DNT2_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2DNT2=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" -CONFIG_AUTOBOOT_STOP_STR="++++++++++" -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig deleted file mode 100644 index 534cfe1..0000000 --- a/configs/O2D_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2D=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig deleted file mode 100644 index acf42ab..0000000 --- a/configs/O2I_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2I=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig deleted file mode 100644 index de647c7..0000000 --- a/configs/O2MNT_O2M110_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2MNT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\"" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig deleted file mode 100644 index b243e9c..0000000 --- a/configs/O2MNT_O2M112_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2MNT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\"" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig deleted file mode 100644 index 1584058..0000000 --- a/configs/O2MNT_O2M113_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2MNT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\"" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig deleted file mode 100644 index 20bd314..0000000 --- a/configs/O2MNT_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O2MNT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig deleted file mode 100644 index ea769e7..0000000 --- a/configs/O3DNT_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_O3DNT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BSP=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig deleted file mode 100644 index cd78de7..0000000 --- a/configs/PATI_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10084-001 released" -CONFIG_5xx=y -CONFIG_TARGET_PATI=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="pati=> " -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_BSP=y -CONFIG_CMD_IRQ=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_BAUDRATE=9600 diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig b/configs/Sinovoip_BPI_M2_Plus_defconfig index e8cd4fb..651a2ff 100644 --- a/configs/Sinovoip_BPI_M2_Plus_defconfig +++ b/configs/Sinovoip_BPI_M2_Plus_defconfig @@ -8,7 +8,6 @@ CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig deleted file mode 100644 index 5e6f9c9..0000000 --- a/configs/TQM5200S_HIGHBOOT_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig deleted file mode 100644 index d0c352f..0000000 --- a/configs/TQM5200S_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig deleted file mode 100644 index ed74408..0000000 --- a/configs/TQM5200_B_HIGHBOOT_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig deleted file mode 100644 index cc9968c..0000000 --- a/configs/TQM5200_B_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig deleted file mode 100644 index 35d4860..0000000 --- a/configs/TQM5200_STK100_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig deleted file mode 100644 index 783c39a..0000000 --- a/configs/TQM5200_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig deleted file mode 100644 index ccb68b2..0000000 --- a/configs/TQM823L_LCD_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="NEC_NL6448BC20" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig deleted file mode 100644 index c588948..0000000 --- a/configs/TQM823L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig deleted file mode 100644 index 0490828..0000000 --- a/configs/TQM823M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig deleted file mode 100644 index 0e42d8c..0000000 --- a/configs/TQM850L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM850L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig deleted file mode 100644 index a464fe5..0000000 --- a/configs/TQM850M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM850M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig deleted file mode 100644 index aa37001..0000000 --- a/configs/TQM855L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM855L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig deleted file mode 100644 index faab826..0000000 --- a/configs/TQM855M_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM855M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig deleted file mode 100644 index b18cf31..0000000 --- a/configs/TQM860L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM860L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig deleted file mode 100644 index fe2fe6d..0000000 --- a/configs/TQM860M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM860M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig deleted file mode 100644 index 6f5f772..0000000 --- a/configs/TQM862L_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM862L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig deleted file mode 100644 index 4430776..0000000 --- a/configs/TQM862M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM862M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig deleted file mode 100644 index d892290..0000000 --- a/configs/TQM866M_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM866M=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig deleted file mode 100644 index 48421e3..0000000 --- a/configs/TQM885D_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM885D=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_LED_STATUS=y -# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=1 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig deleted file mode 100644 index 9d26e94..0000000 --- a/configs/TTTech_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SHARP_LQ104V7DS01" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig index 2fc8d86..29bf82a 100644 --- a/configs/UCP1020_SPIFLASH_defconfig +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -20,8 +20,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index 63f1a9d..dbf073d 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -20,8 +20,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig deleted file mode 100644 index a461b80..0000000 --- a/configs/a3m071_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_PPC=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_A3M071=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_OS_BASE=0xfc200000 -CONFIG_HUSH_PARSER=y -CONFIG_LOOPW=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_LINK_LOCAL=y -CONFIG_CMD_BSP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_UBI=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LIB_RAND=y -CONFIG_OF_LIBFDT=y diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig deleted file mode 100644 index 4fbffb6..0000000 --- a/configs/a4m072_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_A4M072=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SILENT_CONSOLE=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="asdfg" -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DISPLAY=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_BAUDRATE=9600 -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig deleted file mode 100644 index 3100da6..0000000 --- a/configs/a4m2k_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_PPC=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_A3M071=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="A4M2K" -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL=y -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_OS_BASE=0xfc200000 -CONFIG_HUSH_PARSER=y -CONFIG_LOOPW=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_LINK_LOCAL=y -CONFIG_CMD_BSP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_UBI=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LIB_RAND=y -CONFIG_OF_LIBFDT=y diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig deleted file mode 100644 index 6855331..0000000 --- a/configs/ac14xx_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC512X=y -CONFIG_TARGET_AC14XX=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_PROMPT="ac14xx> " -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index cbef412..d47ad86 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -12,16 +12,16 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_MMC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_BAUDRATE=38400 CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_MMC=y CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y CONFIG_DM_ETH=y CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_TIMER=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 22b1182..6ce9e80 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -12,14 +12,14 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_MMC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_BAUDRATE=38400 CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_MMC=y +CONFIG_MTD_NOR_FLASH=y CONFIG_DM_ETH=y CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_TIMER=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index f210cca..b69ba8f 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -10,9 +10,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FAT_SUPPORT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="NAND" @@ -24,6 +23,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index 487ece4..7bfdfa8 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 198efb4..ef5a3f1 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" @@ -30,7 +29,6 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 962bb65..ff1e43f 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_DISTRO_DEFAULTS=y @@ -28,7 +27,6 @@ CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 31019e3..6ff0aca 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y CONFIG_NOR=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index ef8cb0b..49f75b2 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -3,7 +3,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y CONFIG_NOR=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NOR_BOOT=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index ece79c2..64b44ff 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index ee3405c..a578322 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y -CONFIG_TARGET_AM335X_EVM=y +# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="NAND" @@ -11,10 +11,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USBETH_SUPPORT=y +# CONFIG_SPL_YMODEM_SUPPORT is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 73c9d01..b0c88a6 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_AM33XX=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_TARGET_AM335X_EVM=y CONFIG_ISW_ENTRY_ADDR=0x40300350 # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_STACK_R_ADDR=0x82000000 @@ -17,7 +16,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y @@ -35,7 +33,6 @@ CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y @@ -54,6 +51,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 -CONFIG_USE_TINY_PRINTF=y CONFIG_RSA=y -CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 651e194..df7d1c6 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -3,17 +3,16 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_AM33XX=y CONFIG_TARGET_AM335X_IGEP003X=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FAT_SUPPORT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -23,6 +22,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index ab912bb..4bd1b65 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -9,10 +9,9 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y CONFIG_SERIES=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -20,6 +19,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 7d75c5c..1025cd1 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -9,11 +9,10 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y CONFIG_SHC_ICT=y CONFIG_SERIES=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -21,6 +20,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 322a070..0011234 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -9,11 +9,10 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y CONFIG_SHC_NETBOOT=y CONFIG_SERIES=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -22,6 +21,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig index c5d8dca..a6c617f 100644 --- a/configs/am335x_shc_prompt_defconfig +++ b/configs/am335x_shc_prompt_defconfig @@ -9,10 +9,9 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y CONFIG_SERIES=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -20,6 +19,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n" diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 185258d..fa23154 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -9,11 +9,10 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y CONFIG_SHC_SDBOOT=y CONFIG_SERIES=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -21,6 +20,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig index 185258d..fa23154 100644 --- a/configs/am335x_shc_sdboot_prompt_defconfig +++ b/configs/am335x_shc_sdboot_prompt_defconfig @@ -9,11 +9,10 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y CONFIG_SHC_SDBOOT=y CONFIG_SERIES=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y @@ -21,6 +20,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 86035d2..02ce013 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -9,9 +9,8 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FAT_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -22,6 +21,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_AUTOBOOT is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index 2a0987e..c51313f 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y # CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_CRANE=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 04bade9..7e9ea0e 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y # CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_OMAP34XX=y CONFIG_TARGET_AM3517_EVM=y CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 4d9ec88..3878d27 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_AM43XX=y -CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_TARGET_AM43XX_EVM=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_SPL_LOAD_FIT=y @@ -28,7 +27,6 @@ CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 20874dd..6df60e8 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_AM43XX=y -CONFIG_TARGET_AM43XX_EVM=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index c0d0bcc..87d5ba7 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_AM43XX=y -CONFIG_TARGET_AM43XX_EVM=y CONFIG_ISW_ENTRY_ADDR=0x30000000 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT" CONFIG_QSPI_BOOT=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 870ed0f..2006957 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_AM43XX=y -CONFIG_TARGET_AM43XX_EVM=y CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" @@ -50,7 +49,6 @@ CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 6f3cb51..fb4bb03 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -1,10 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_AM43XX=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_TARGET_AM43XX_EVM=y CONFIG_ISW_ENTRY_ADDR=0x403018e0 CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" @@ -38,7 +37,6 @@ CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 5dc9f4f..658ab92 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -1,14 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OMAP54XX=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_AM57XX_EVM=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="am572x-idk" CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -46,7 +46,6 @@ CONFIG_DFU_RAM=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 517f750..b383330 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OMAP54XX=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TARGET_AM57XX_EVM=y CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 @@ -11,8 +11,8 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -50,7 +50,6 @@ CONFIG_DFU_RAM=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index 40055f0..3e1f058 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -2,6 +2,7 @@ CONFIG_MIPS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ARCH_ATH79=y CONFIG_DEFAULT_DEVICE_TREE="ap121" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y @@ -42,7 +43,6 @@ CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_AR933X=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_AR933X=y CONFIG_DEBUG_UART_BASE=0xb8020000 CONFIG_DEBUG_UART_CLOCK=25000000 diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 05f1699..58eb77b 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP143=y CONFIG_DEFAULT_DEVICE_TREE="ap143" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_DISPLAY_CPUINFO=y CONFIG_BOARD_EARLY_INIT_F=y @@ -38,7 +39,6 @@ CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_SPI_FLASH_MTD=y CONFIG_PINCTRL=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xb8020000 CONFIG_DEBUG_UART_CLOCK=25000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/aria_defconfig b/configs/aria_defconfig deleted file mode 100644 index 0613dd1..0000000 --- a/configs/aria_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC512X=y -CONFIG_TARGET_ARIA=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index cc3f0a8..7c43c50 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index cb621df..1f959ea 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 20d3565..7df2e06 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 02e9114..d1074fa 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -36,7 +37,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 02e9114..d1074fa 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -36,7 +37,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 2ddcf2b..aef21b8 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -36,7 +37,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 21480c5..66484a1 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -31,19 +32,18 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD_NOR_FLASH=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y -CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 824c366..1e17748 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -31,19 +32,18 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD_NOR_FLASH=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y -CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 18e88a7..2a696d4 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -33,7 +34,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index fb0d87a..55923ca 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -33,7 +34,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 27c1c10..3df66b6 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 1826e6c..f0a3a66 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 1ac8863..359ee54 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index d8ba087..46f082f 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -37,7 +38,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index eda54a4..ddc26be 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -37,7 +38,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index d13eed0..f323ce8 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -35,7 +36,6 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index e626805..08887c4 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -35,7 +36,6 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index a5abcd1..8b8229b 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -35,7 +36,6 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index d4abb2a..e2642b9 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -34,7 +35,6 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index edf9881..afe28d6 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -34,7 +35,6 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index d68b562..851867e 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -34,7 +35,6 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 64707db..f52d921 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -40,7 +41,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index fbe11ef..1aa1dd8 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -40,7 +41,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index a26b38f..e31b659 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -40,7 +41,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 75d25d8..f8d2ce3 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -40,7 +41,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 80673d2..5405939 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 8922065..a057702 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 9c28a59..e304fd6 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" +CONFIG_DEBUG_UART=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfffff200 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index 62e50b6..ffda22e 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -9,11 +9,11 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CRC32_VERIFY=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y -CONFIG_CRC32_VERIFY=y CONFIG_CMD_HASH=y CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index d866b60..073a58d 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_BAV_VERSION=1 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -21,6 +20,7 @@ CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index ef73fbf..5269c17 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_BAV_VERSION=2 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -21,6 +20,7 @@ CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -54,7 +54,6 @@ CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y -CONFIG_FAT_WRITE=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y @@ -64,4 +63,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 +CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index a963802..bf7700c 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -15,7 +15,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y -CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 3566223..e2a009e 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -3,11 +3,11 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" CONFIG_BOOTDELAY=-2 @@ -20,9 +20,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -57,6 +56,5 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y -CONFIG_OMAP_WATCHDOG=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index f07a46b..ba03758 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -3,11 +3,11 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" CONFIG_BOOTDELAY=-2 @@ -20,9 +20,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -57,6 +56,5 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y -CONFIG_OMAP_WATCHDOG=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 333e204..66e086d 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -3,13 +3,13 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" CONFIG_SPI_BOOT=y @@ -23,9 +23,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -65,6 +64,5 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y -CONFIG_OMAP_WATCHDOG=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index f558886..05ceba8 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -3,9 +3,10 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM33XX=y +CONFIG_TARGET_BRXRE1=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_BOOTDELAY=-2 # CONFIG_CONSOLE_MUX is not set @@ -17,9 +18,8 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set @@ -57,6 +57,7 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y +# CONFIG_OMAP_WATCHDOG is not set CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig index d96a71a..6b10abb 100644 --- a/configs/cairo_defconfig +++ b/configs/cairo_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_CAIRO=y CONFIG_BOOTDELAY=-2 CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig deleted file mode 100644 index d8a419c..0000000 --- a/configs/cam5200_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig deleted file mode 100644 index d7577a4..0000000 --- a/configs/cam5200_niosflash_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig deleted file mode 100644 index 87eb205..0000000 --- a/configs/canmb_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_CANMB=y -CONFIG_BOOTDELAY=5 -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set diff --git a/configs/charon_defconfig b/configs/charon_defconfig deleted file mode 100644 index 2e4ad65..0000000 --- a/configs/charon_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_CHARON=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 579df94..82b5276 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -9,14 +9,14 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FAT_SUPPORT=y CONFIG_BOOTDELAY=1 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 649ebf7..7d0351e 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" +CONFIG_DEBUG_UART=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 @@ -61,7 +62,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 6fc0dcc..8f33bb8 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -8,8 +8,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_CMD_IMLS is not set @@ -61,7 +63,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 @@ -74,7 +75,6 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 749cfd4..febbeb5 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -10,6 +10,7 @@ CONFIG_X86_RUN_64BIT=y CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK64=y +CONFIG_DEBUG_UART=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_HAVE_MRC=y CONFIG_SMP=y @@ -67,7 +68,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 5ebb556..e2f5782 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_DEBUG_UART=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_HAVE_MRC=y CONFIG_SMP=y @@ -50,7 +51,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index ef333c0..db1488a 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y @@ -61,7 +62,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 @@ -72,8 +72,8 @@ CONFIG_SYSRESET=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y -CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 60cb9a3..3e12bea 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x1800 CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" CONFIG_TARGET_CHROMEBOOK_SAMUS=y +CONFIG_DEBUG_UART=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_HAVE_MRC=y CONFIG_HAVE_REFCODE=y @@ -49,7 +50,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_DEBUG_UART_BOARD_INIT=y diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig index 8485137..bf753bc 100644 --- a/configs/cl-som-am57x_defconfig +++ b/configs/cl-som-am57x_defconfig @@ -5,7 +5,9 @@ CONFIG_TARGET_CL_SOM_AM57X=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +# CONFIG_SPL_EXT_SUPPORT is not set CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot# " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 0975068..3bb6c6b 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" +CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -26,8 +27,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SPL_OF_TRANSLATE=y CONFIG_MMC_SDHCI=y @@ -35,7 +34,6 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH=y CONFIG_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig deleted file mode 100644 index 860d23e..0000000 --- a/configs/cm5200_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_CM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_SILENT_CONSOLE=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_BAUDRATE=57600 -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index fb2f9fa..dc587a6 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -9,8 +9,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" CONFIG_BOOTDELAY=3 diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 876e332..be0536a 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -11,13 +11,13 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T335 # " CONFIG_CMD_BOOTZ=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index 9b81596..dbe34eb 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T3517=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index 29405f8..50f6c64 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T35=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index d813cc5..c652c4f 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_AM43XX=y CONFIG_TARGET_CM_T43=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y @@ -10,17 +10,16 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T43 # " CONFIG_CMD_BOOTZ=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index d5838acb..2ba6aea 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -2,9 +2,9 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_TARGET_COLIBRI_IMX7=y +CONFIG_VIDEO=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" CONFIG_BOOTDELAY=1 diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index cc9c4ee..3b510c3 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y -CONFIG_TARGET_COLIBRI_VF=y CONFIG_VIDEO=y +CONFIG_TARGET_COLIBRI_VF=y CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" CONFIG_BOOTDELAY=1 diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 5b05fd2..f856752 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -1,54 +1,44 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6328_POWER_DOMAIN=y -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y -CONFIG_BOARD_COMTREND_AR5387UN=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +CONFIG_SOC_BMIPS_BCM6328=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="AR-5387un # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y -CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_POWER_DOMAIN=y -CONFIG_RESET=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM6328=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_NO_FLASH=y -CONFIG_SYS_PROMPT="AR-5387un # " -CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 9ec0c41..27fcc8e 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -1,57 +1,45 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_GPIO=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y -CONFIG_BOARD_COMTREND_CT5361=y -CONFIG_CFI_FLASH=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +CONFIG_SOC_BMIPS_BCM6348=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="CT-5361 # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_FLASH=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y +CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y CONFIG_MTD=y -CONFIG_MTD_DEVICE=y CONFIG_MTD_NOR_FLASH=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_RESET=y +CONFIG_CFI_FLASH=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM6348=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_PROMPT="CT-5361 # " -CONFIG_SYS_TEXT_BASE=0x80010000 -CONFIG_WDT=y +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y CONFIG_WDT_BCM6345=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index c056d73..97f1c62 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -1,54 +1,44 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6328_POWER_DOMAIN=y -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y -CONFIG_BOARD_COMTREND_VR3032U=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +CONFIG_SOC_BMIPS_BCM63268=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="VR-3032u # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y -CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_POWER_DOMAIN=y -CONFIG_RESET=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM63268=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_NO_FLASH=y -CONFIG_SYS_PROMPT="VR-3032u # " -CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index d96bfcb..a0cce75 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_CONGATEC=y CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845" CONFIG_INTERNAL_UART=y +CONFIG_DEBUG_UART=y CONFIG_HAVE_INTEL_ME=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y @@ -62,7 +63,6 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 1642bf2..26eed7c 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_VENDOR_CONGATEC=y CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845" +CONFIG_DEBUG_UART=y CONFIG_HAVE_INTEL_ME=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y @@ -61,7 +62,6 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 037f338..31ad014 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_CONTROLCENTERDC=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -43,7 +44,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index d9b165f..55378ef 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" +CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -41,7 +42,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MVPP2=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 63fc4db..3831f40 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 @@ -45,7 +46,6 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 7bdcb81..d6068aa 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -43,7 +44,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 10ef7af..9e7e89e 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" +CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -41,7 +42,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 617228f..f587190 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_DEVKIT8000=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index d5bd66f..c86e0a9 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_VENDOR_DFI=y CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151" CONFIG_TARGET_DFI_BT700=y +CONFIG_DEBUG_UART=y CONFIG_HAVE_INTEL_ME=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y @@ -59,7 +60,6 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig deleted file mode 100644 index cda75d6..0000000 --- a/configs/digsy_mtc_RAMBOOT_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_DIGSY_MTC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_DIAG=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig deleted file mode 100644 index da9cec8..0000000 --- a/configs/digsy_mtc_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_DIGSY_MTC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR=" " -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_DIAG=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig deleted file mode 100644 index 1bba630..0000000 --- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_DIGSY_MTC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_DIAG=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig deleted file mode 100644 index 3491fdd..0000000 --- a/configs/digsy_mtc_rev5_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_DIGSY_MTC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_DIAG=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index be04402..6dd1baf 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -1,14 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OMAP54XX=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_DRA7XX_EVM=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -43,10 +43,9 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y -CONFIG_BLK=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_DM_SCSI=y CONFIG_DWC_AHCI=y -CONFIG_SPL_OF_TRANSLATE=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -54,13 +53,13 @@ CONFIG_DM_GPIO=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_ETH=y +CONFIG_SPL_PHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y @@ -90,6 +89,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 -CONFIG_SPL_PHY=y -CONFIG_PIPE3_PHY=y -CONFIG_SPL_PIPE3_PHY=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 84dd26b..3008a1f 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OMAP54XX=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 @@ -11,8 +11,8 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -56,13 +56,13 @@ CONFIG_DM_GPIO=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_ETH=y +CONFIG_SPL_PHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y @@ -92,6 +92,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 -CONFIG_SPL_PHY=y -CONFIG_PIPE3_PHY=y -CONFIG_SPL_PIPE3_PHY=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 0e50b31..1d32220 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_DRACO=y +CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 +CONFIG_TARGET_DRACO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -20,8 +21,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -65,4 +64,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 -CONFIG_OMAP_WATCHDOG=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 4e17bb9..bde54b6 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y @@ -35,7 +36,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index d567b89..1501368 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_ECO5PK=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index fb5203e..2fae904 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_VENDOR_EFI=y CONFIG_DEFAULT_DEVICE_TREE="efi" CONFIG_TARGET_EFI=y +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -31,7 +32,6 @@ CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DM_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_EFI_CONSOLE=y CONFIG_DEBUG_UART_BASE=0 CONFIG_DEBUG_UART_CLOCK=0 diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index b6911fd..5781974 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_ETAMIN=y +CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 +CONFIG_TARGET_ETAMIN=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -20,8 +21,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -65,4 +64,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 -CONFIG_OMAP_WATCHDOG=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 08b5f85..f71d0c1 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -3,21 +3,21 @@ CONFIG_ARCH_ASPEED=y CONFIG_ASPEED_AST2500=y CONFIG_TARGET_EVB_AST2500=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb" +CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_PRE_CON_BUF_ADDR=0x1e720000 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_I2C=y CONFIG_REGMAP=y CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_PINCTRL=y CONFIG_RAM=y +CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y -CONFIG_DM_RESET=y -CONFIG_PINCTRL=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_ASPEED=y -CONFIG_CMD_I2C=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig new file mode 100644 index 0000000..2c8c894 --- /dev/null +++ b/configs/evb-px5_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3368=y +CONFIG_TARGET_EVB_PX5=y +CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb" +CONFIG_DEBUG_UART=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3368=y +CONFIG_RAM=y +CONFIG_DEBUG_UART_BASE=0xFF1c0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 4a5664d..c60d175 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_EVB_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEBUG_UART=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set @@ -31,7 +32,6 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y CONFIG_RAM=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 227150d..0d28311 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -55,7 +56,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 96241f6..1384e87 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_DEBUG_UART=y CONFIG_FIT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_CMD_BOOTZ=y @@ -9,6 +10,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_REGMAP=y @@ -23,11 +25,18 @@ CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index c189e75..bdab07b 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -23,6 +24,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_OF_PLATDATA=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -34,12 +36,8 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_RK808=y -CONFIG_REGULATOR_RK808=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y @@ -53,7 +51,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig new file mode 100644 index 0000000..1c404e5 --- /dev/null +++ b/configs/evb-rv1108_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RV1108=y +CONFIG_TARGET_EVB_RV1108=y +CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" +CONFIG_DEBUG_UART=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RV1108=y +CONFIG_RAM=y +CONFIG_BAUDRATE=1500000 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_BASE=0x10210000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 6a32a3a..aacf808 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_FENNEC_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -55,7 +56,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 9cf576c..6190024 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_FIREFLY_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y @@ -58,7 +59,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index f30f131..5c2d925 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -39,7 +40,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_ROCKCHIP_RK3399_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y @@ -49,7 +50,6 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig deleted file mode 100644 index 24470f3..0000000 --- a/configs/fo300_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_TQM5200=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="FO300" -CONFIG_BOOTDELAY=5 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_BSP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig new file mode 100644 index 0000000..0a1e1dc --- /dev/null +++ b/configs/geekbox_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3368=y +CONFIG_TARGET_GEEKBOX=y +CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox" +CONFIG_DEBUG_UART=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_CMD_IMLS is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3368=y +CONFIG_RAM=y +CONFIG_DEBUG_UART_BASE=0xFF690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 0d0d142..a476dc2 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -9,7 +9,6 @@ CONFIG_CMD_GSC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_VIDEO=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_CMD_HDMIDETECT=y @@ -27,6 +26,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " CONFIG_CMD_BOOTZ=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 8f66189..bd38e6d 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -9,7 +9,6 @@ CONFIG_CMD_GSC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_VIDEO=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_CMD_HDMIDETECT=y @@ -27,6 +26,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " CONFIG_CMD_BOOTZ=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 5545171..296f015 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_VIDEO=y CONFIG_SPL_STACK_R_ADDR=0x18000000 CONFIG_CMD_HDMIDETECT=y @@ -28,6 +27,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " CONFIG_CMD_BOOTZ=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index c2e6472..a0a70b2 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -1,55 +1,44 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_GPIO=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y -CONFIG_BOARD_HUAWEI_HG556A=y -CONFIG_CFI_FLASH=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +CONFIG_SOC_BMIPS_BCM6358=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="HG556a # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_FLASH=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y +CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y CONFIG_MTD=y -CONFIG_MTD_DEVICE=y CONFIG_MTD_NOR_FLASH=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_RESET=y +CONFIG_CFI_FLASH=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM6358=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_PROMPT="HG556a # " -CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig index 6e0a5e9..3856d3f 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep0020_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020" CONFIG_BOOTDELAY=3 @@ -14,29 +14,17 @@ CONFIG_SPL=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_ONENAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig index 5908a35..2616fb2 100644 --- a/configs/igep0030_defconfig +++ b/configs/igep0030_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig index 53399e7..5859e6e 100644 --- a/configs/igep0032_defconfig +++ b/configs/igep0032_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_IGEP00X0=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 851dba2..b7785ba 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -7,10 +7,9 @@ CONFIG_TARGET_MX6Q_ICORE=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" -CONFIG_OF_LIST="imx6q-icore imx6dl-icore" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -34,6 +33,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIST="imx6q-icore imx6dl-icore" # CONFIG_BLK is not set CONFIG_SYS_I2C_MXC=y # CONFIG_DM_MMC_OPS is not set diff --git a/configs/imx6qdl_icore_rqs_mmc_defconfig b/configs/imx6qdl_icore_rqs_mmc_defconfig index b6a43ae..e746b48 100644 --- a/configs/imx6qdl_icore_rqs_mmc_defconfig +++ b/configs/imx6qdl_icore_rqs_mmc_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" -CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -33,6 +32,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs" # CONFIG_BLK is not set CONFIG_SYS_I2C_MXC=y # CONFIG_DM_MMC_OPS is not set diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig deleted file mode 100644 index c263cf6..0000000 --- a/configs/inka4x0_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_INKA4X0=y -CONFIG_BOOTDELAY=1 -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig deleted file mode 100644 index f86170d..0000000 --- a/configs/ipek01_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_IPEK01=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_LOOPW=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_BMP=y -CONFIG_CMD_FAT=y -CONFIG_CMD_IRQ=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_CONSOLE_EXTRA_INFO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig deleted file mode 100644 index 8e4e447..0000000 --- a/configs/jupiter_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_JUPITER=y -CONFIG_BOOTDELAY=5 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 83e2138..f09eb84 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -1,14 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2E_EVM=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -16,8 +15,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index d4ec83e..55eab61 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000060 -CONFIG_TARGET_K2E_EVM=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_TI_SECURE_DEVICE=y +CONFIG_TARGET_K2E_EVM=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 674ddcc..a5f1ac5 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -1,14 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2G_EVM=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -16,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -30,7 +30,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 2e06c8c..51c701e 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -1,12 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000060 -CONFIG_TARGET_K2G_EVM=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_TI_SECURE_DEVICE=y +CONFIG_TARGET_K2G_EVM=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" -CONFIG_FIT=y -CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -24,7 +21,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 7dc5cf5..0afdb6e 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -1,14 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2HK_EVM=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -16,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 67807e4..a66a256 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000060 -CONFIG_TARGET_K2HK_EVM=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_TI_SECURE_DEVICE=y +CONFIG_TARGET_K2HK_EVM=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 6be4941..fd8c173 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -1,14 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_KEYSTONE=y CONFIG_SYS_TEXT_BASE=0x0c000000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2L_EVM=y -CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -16,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index c923aa6..8d46b6a 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_KMP204X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 0a22f8d..db93dee 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_KM8360=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 6cbecf6..163f4f9 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_KM8360=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig index e4ff6d7..23859e9 100644 --- a/configs/kmlion1_defconfig +++ b/configs/kmlion1_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_KMP204X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 6874e02..9be448f 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index ecd297d..ba44606 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 9e20c02..c1e9df5 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 2c6e00e..3ea83eb 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index a0a7238..7ee2bb7 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 1cd19ed..5162c2c 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -9,7 +9,6 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y -CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 CONFIG_SPL_CRYPTO_SUPPORT=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 6146600..6548bc0 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -10,8 +10,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_NAND_BOOT=y CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index a6d2f81..f933b8f 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -2,12 +2,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" -CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -15,25 +14,19 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y -CONFIG_FSL_LS_PPA=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y -CONFIG_SPL_MMC_SUPPORT=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 5800213..58eb4c6 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -10,8 +10,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_NAND_BOOT=y CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 0d1730f..d8420ba 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -9,18 +9,15 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 -CONFIG_CMD_GREPENV=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y @@ -34,10 +31,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y CONFIG_FSL_DSPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 139ff08..76b2f32 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -9,18 +9,15 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 -CONFIG_CMD_GREPENV=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y @@ -34,10 +31,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y CONFIG_FSL_DSPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig index a33a601..cc4a74c 100644 --- a/configs/m53evk_defconfig +++ b/configs/m53evk_defconfig @@ -6,8 +6,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_M53EVK=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg" CONFIG_BOOTDELAY=3 diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 512810f..81d6c92 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,7 +32,6 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index 09dbc78..d0f361f 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y # CONFIG_SPL_GPIO_SUPPORT is not set -CONFIG_OMAP34XX=y CONFIG_TARGET_MCX=y CONFIG_VIDEO=y CONFIG_BOOTDELAY=3 diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig deleted file mode 100644 index 3937fe8..0000000 --- a/configs/mecp5123_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC512X=y -CONFIG_TARGET_MECP5123=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_BAUDRATE=9600 -CONFIG_OF_LIBFDT=y diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig deleted file mode 100644 index 58d6656..0000000 --- a/configs/mgcoge3ne_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_KM82XX=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MGCOGE3NE" -CONFIG_VERSION_VARIABLE=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_UBI=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig deleted file mode 100644 index c4f39b3..0000000 --- a/configs/mgcoge_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_KM82XX=y -CONFIG_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MGCOGE" -CONFIG_VERSION_VARIABLE=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_UBI=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index aa50e88..96a45aa 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_TARGET_MINNOWMAX=y CONFIG_INTERNAL_UART=y +CONFIG_DEBUG_UART=y CONFIG_HAVE_INTEL_ME=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y @@ -60,7 +61,6 @@ CONFIG_DM_ETH=y CONFIG_RTL8169=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 0706ff2..ffb68f7 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_MIQI_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y @@ -55,7 +56,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig deleted file mode 100644 index c4006bc..0000000 --- a/configs/motionpro_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_MOTIONPRO=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_VERSION_VARIABLE=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_BEDBUG=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=0 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_FREQ=10 -CONFIG_LED_STATUS1=y -CONFIG_LED_STATUS_BIT1=1 -CONFIG_LED_STATUS_FREQ1=10 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig deleted file mode 100644 index 5bb7807..0000000 --- a/configs/mpc5121ads_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC512X=y -CONFIG_TARGET_MPC5121ADS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig deleted file mode 100644 index e28fa19..0000000 --- a/configs/mpc5121ads_rev2_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC512X=y -CONFIG_TARGET_MPC5121ADS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2" -CONFIG_BOOTDELAY=5 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index c4a6f20..edd9e68 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_MT_VENTOUX=y CONFIG_VIDEO=y CONFIG_BOOTDELAY=10 diff --git a/configs/munices_defconfig b/configs/munices_defconfig deleted file mode 100644 index 0e2b188..0000000 --- a/configs/munices_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_CMD_IMMAP=y -CONFIG_TARGET_MUNICES=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 349c2ce..f2b2e5d 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_37XX=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -53,7 +54,6 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_MVEBU_A3700_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=25804800 diff --git a/configs/mvebu_db-88f7040-nand_defconfig b/configs/mvebu_db-88f7040-nand_defconfig index 8d48cb6..2aba8de 100644 --- a/configs/mvebu_db-88f7040-nand_defconfig +++ b/configs/mvebu_db-88f7040-nand_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db-nand" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -58,7 +59,6 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_8K=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig index 9f7b2c4..28af643 100644 --- a/configs/mvebu_db-88f7040_defconfig +++ b/configs/mvebu_db-88f7040_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -56,7 +57,6 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_8K=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/mvebu_db-88f8040_defconfig b/configs/mvebu_db-88f8040_defconfig index c21c977..7f36eda 100644 --- a/configs/mvebu_db-88f8040_defconfig +++ b/configs/mvebu_db-88f8040_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -56,7 +57,6 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_8K=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index d504745..9ab7f46 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_37XX=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -49,7 +50,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_MVEBU_COMPHY_SUPPORT=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_MVEBU_A3700_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=25804800 diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 4a7c592..a4fec5d 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -60,7 +61,6 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_8K=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_SERIAL_PRESENT is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 3f57c88..8f09c04 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX5=y CONFIG_TARGET_MX51EVK=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index d947d9f..e0c597c 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX5=y CONFIG_TARGET_MX53CX9020=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" CONFIG_BOOTDELAY=1 diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index b71c3ae..5727356 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX5=y CONFIG_TARGET_MX53LOCO=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index b180f54..7530de1 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -8,9 +8,9 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y # CONFIG_CMD_BMODE is not set CONFIG_CMD_HDMIDETECT=y -CONFIG_VIDEO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" # CONFIG_SYS_STDIO_DEREGISTER is not set diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index ff23345..2522eb7 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,8 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SXSABRESD=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig index c08cada..6d4fe63 100644 --- a/configs/mx6sxsabresd_spl_defconfig +++ b/configs/mx6sxsabresd_spl_defconfig @@ -8,8 +8,8 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 52faae4..dfe55ac 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -1,11 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_TARGET_MX7DSABRESD=y +CONFIG_VIDEO=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y # CONFIG_CMD_BMODE is not set -CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTDELAY=3 diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig new file mode 100644 index 0000000..d7a908d --- /dev/null +++ b/configs/nanopi_m1_plus_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="PH13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig new file mode 100644 index 0000000..c0ac100 --- /dev/null +++ b/configs/nanopi_neo2_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881977 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 5400d37..a73640e 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO_DE2 is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y @@ -15,4 +16,3 @@ CONFIG_SPL=y # CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y -# CONFIG_VIDEO_DE2 is not set diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index 5afd5d5..8b55497 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO_DE2 is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y @@ -16,4 +17,3 @@ CONFIG_SPL=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y -# CONFIG_VIDEO_DE2 is not set diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index a6eff10..e353794 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -1,56 +1,44 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_GPIO=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y -CONFIG_BOARD_NETGEAR_CG3100D=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="CG3100D # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="netgear,cg3100d" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y +CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_RESET=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM3380=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_NO_FLASH=y -CONFIG_SYS_PROMPT="CG3100D # " -CONFIG_SYS_TEXT_BASE=0x80010000 -CONFIG_WDT=y +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y CONFIG_WDT_BCM6345=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index ef9d9ed..3ca00b9 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_NOKIA_RX51=y CONFIG_VIDEO=y CONFIG_BOOTDELAY=30 diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 3c7589b..afacea7 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -9,9 +9,9 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y CONFIG_SPL_FAT_SUPPORT=y CONFIG_CMD_HDMIDETECT=y -CONFIG_VIDEO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index f0fad3e..fb2e479 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y @@ -62,5 +63,6 @@ CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_TEGRA124=y CONFIG_VIDEO_BRIDGE=y +CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_ERRNO_STR=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index c9d0103..547cd52 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -4,6 +4,7 @@ CONFIG_MESON_GXBB=y CONFIG_TARGET_ODROID_C2=y CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" +CONFIG_DEBUG_UART=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BDI is not set @@ -21,7 +22,6 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXBB=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_MESON=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index eb780ab..3e4dee7 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_BEAGLE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="NAND" diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 227f1d1..8d5bc8e 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_EVM=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index 6194a66..fa09a53 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" CONFIG_BOOTDELAY=3 diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index aa70358..db8f468 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit" @@ -29,7 +28,6 @@ CONFIG_OF_CONTROL=y # CONFIG_BLK is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y -# CONFIG_DM_MMC_OPS is not set CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP36XX_PINS=y CONFIG_SYS_NS16550=y diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig index e360780..f4c3d32 100644 --- a/configs/omap3_overo_defconfig +++ b/configs/omap3_overo_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_OVERO=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig index d219ad0..b86dfad 100644 --- a/configs/omap3_pandora_defconfig +++ b/configs/omap3_pandora_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_PANDORA=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/omap3_zoom1_defconfig b/configs/omap3_zoom1_defconfig index 8c0e830..a76ac6f 100644 --- a/configs/omap3_zoom1_defconfig +++ b/configs/omap3_zoom1_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_ZOOM1=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index cb351e4..c6f474a 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -24,11 +24,11 @@ CONFIG_CRC32_VERIFY=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000 CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y -# CONFIG_FAT_WRITE is not set CONFIG_OF_LIBFDT=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 1a9d6cd..f08e1dd 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -7,8 +7,8 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev" CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 201771e..dffba8c 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB1_VBUS_PIN="PG13" CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 38f4583..448a161 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -6,7 +6,6 @@ CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 56c9a87..97d0e06 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -6,7 +6,6 @@ CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 8e01284..5a64ad3 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -6,7 +6,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 9d4cb0e..af7568f 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -6,7 +6,6 @@ CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index 0addd19..935e96d 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 52ec86a4..3301ca0 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -8,7 +8,6 @@ CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 5e02869..34c5750 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -10,7 +10,6 @@ CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig new file mode 100644 index 0000000..85d8fa4 --- /dev/null +++ b/configs/orangepi_win_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 97ef089..c650ce8 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO_DE2 is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y @@ -15,4 +16,3 @@ CONFIG_SPL=y CONFIG_SPL_SPI_SUNXI=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y -# CONFIG_VIDEO_DE2 is not set diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig new file mode 100644 index 0000000..e3776f6 --- /dev/null +++ b/configs/orangepi_zero_plus2_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881977 +CONFIG_MMC0_CD_PIN="PH13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig deleted file mode 100644 index 0ef8750..0000000 --- a/configs/pcm030_LOWBOOT_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_PCM030=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" -CONFIG_BOOTDELAY=3 -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_JFFS2=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig deleted file mode 100644 index 3869991..0000000 --- a/configs/pcm030_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_PCM030=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=3 -CONFIG_SYS_PROMPT="uboot> " -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_JFFS2=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 6b4e229..466aa51 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="REV1" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -23,6 +22,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 6baca96..7150e79 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="REV3" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -23,6 +22,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig deleted file mode 100644 index 4ef0df1..0000000 --- a/configs/pdm360ng_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_PPC=y -CONFIG_VIDEO=y -CONFIG_MPC512X=y -CONFIG_TARGET_PDM360NG=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTDELAY=5 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 8693dea..973f3cd 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y @@ -24,6 +23,7 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index 4b122d6..11570a8 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -10,12 +10,12 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="pepper# " CONFIG_CMD_BOOTZ=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 593e24a..a509ca9 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -3,9 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" -CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set @@ -13,5 +11,6 @@ CONFIG_SPL=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index c9ad0c0..64d38b0 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_POPMETAL_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -55,7 +56,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 6245360..89f1620 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -8,11 +8,13 @@ CONFIG_TARGET_PUMA_RK3399=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma" +CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600" +CONFIG_DEBUG_UART=y CONFIG_FIT=y -CONFIG_SPL_FIT=y CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -24,11 +26,16 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -36,6 +43,9 @@ CONFIG_SPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y @@ -43,18 +53,21 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ9031=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 @@ -67,4 +80,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_ERRNO_STR=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 67bdfd6..58de0d4 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_PXM2=y +CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=720 +CONFIG_TARGET_PXM2=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -13,8 +14,8 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y CONFIG_VIDEO=y +CONFIG_SPL_FAT_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -23,8 +24,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -72,4 +71,3 @@ CONFIG_G_DNL_PRODUCT_NUM=0x02d2 # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_SYS_CONSOLE_BG_COL=0xff CONFIG_SYS_CONSOLE_FG_COL=0x00 -CONFIG_OMAP_WATCHDOG=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 36d0185..2b43827 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_X86_RUN_64BIT=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_TARGET_QEMU_X86_64=y +CONFIG_DEBUG_UART=y CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y @@ -65,7 +66,6 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 1eba299..c0e3999 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -3,30 +3,20 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y -CONFIG_DEFAULT_FDT_FILE=r8a7795-salvator-x.dtb +CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_FDT=y -CONFIG_R8A7795=y -CONFIG_SH_SDHI=y # CONFIG_CMD_IMLS is not set -CONFIG_CMD_EDITENV=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_NET=y -CONFIG_CMD_NFS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_USB=y +CONFIG_SH_SDHI=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y CONFIG_USB=y -CONFIG_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_USB_EHCI_RCAR_GEN3=y -CONFIG_DOS_PARTITION=y -CONFIG_MMC=y -CONFIG_GENERIC_MMC=y CONFIG_OF_LIBFDT=y -CONFIG_DM_ETH=y -CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 5bd762d..d573051 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -2,31 +2,22 @@ CONFIG_ARM=y CONFIG_ARCH_RMOBILE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y +CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y -CONFIG_DEFAULT_FDT_FILE=r8a7796-salvator-x.dtb +CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_FDT=y -CONFIG_R8A7796=y -CONFIG_SH_SDHI=y # CONFIG_CMD_IMLS is not set -CONFIG_CMD_EDITENV=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_NET=y -CONFIG_CMD_NFS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_USB=y +CONFIG_SH_SDHI=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y CONFIG_USB=y -CONFIG_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_USB_EHCI_RCAR_GEN3=y -CONFIG_DOS_PARTITION=y -CONFIG_MMC=y -CONFIG_GENERIC_MMC=y CONFIG_OF_LIBFDT=y -CONFIG_DM_ETH=y -CONFIG_RENESAS_RAVB=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index f77d4d4..6ba984f 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_RASTABAN=y +CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 +CONFIG_TARGET_RASTABAN=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -20,8 +21,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -65,4 +64,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 -CONFIG_OMAP_WATCHDOG=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 6b86812..eec0613 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_ROCK2=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y @@ -55,7 +56,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 8e81794..5d9b63b 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -8,6 +8,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_ROCK=y CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" +CONFIG_DEBUG_UART=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 @@ -41,7 +42,6 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y # CONFIG_TPL_DM_SERIAL is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/rut_defconfig b/configs/rut_defconfig index f09a67e..9edc4a5 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_RUT=y +CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=600 +CONFIG_TARGET_RUT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -13,8 +14,8 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y CONFIG_VIDEO=y +CONFIG_SPL_FAT_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-rut" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -24,8 +25,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -73,3 +72,4 @@ CONFIG_G_DNL_PRODUCT_NUM=0x02d2 # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_SYS_CONSOLE_BG_COL=0xff CONFIG_SYS_CONSOLE_FG_COL=0x00 +# CONFIG_OMAP_WATCHDOG is not set diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index 8e89c15..8b5d7f4 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -1,52 +1,42 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_GPIO=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y -CONFIG_BOARD_SAGEM_FAST1704=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +CONFIG_SOC_BMIPS_BCM6338=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="F@ST1704 # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y +CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_RESET=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM6338=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_NO_FLASH=y -CONFIG_SYS_PROMPT="F@ST1704 # " -CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index b60e00c..2602aff 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -4,13 +4,14 @@ CONFIG_TARGET_SAMA5D2_XPLAINED=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -59,7 +60,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 70a17ed..2680ab9 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -6,10 +6,11 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 @@ -57,7 +58,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xf8020000 CONFIG_DEBUG_UART_CLOCK=83000000 diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 8c34e64..1c5d85b 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -39,7 +40,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 9c72a67..e312bbf 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 @@ -39,7 +40,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 10db9c9..8db4f52 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D3XEK=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 @@ -39,7 +40,6 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 533dbcd..2e42a2e 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -54,7 +55,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index d00ef6a..0d5d2be 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 @@ -51,7 +52,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 7471985..4cbfa07 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -58,7 +59,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index a75767b..a8f09ed 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 @@ -53,7 +54,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 1d8491c..0166cb6 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 @@ -54,7 +55,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xffffee00 CONFIG_DEBUG_UART_CLOCK=132000000 diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index e23df47..157fbe4 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -53,7 +54,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 02defeb..bb791a3 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 @@ -50,7 +51,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 57dec69..e7e3169 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 @@ -52,7 +53,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 68da5f9..e78460d 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -56,7 +57,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 494edc1..5d43ce9 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 @@ -53,7 +54,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 41f16ea..98813bc 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 @@ -52,7 +53,6 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 CONFIG_DEBUG_UART_CLOCK=88000000 diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 662606c..6a6e774 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -4,10 +4,9 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_BOOTSTAGE_USER_COUNT=0x20 +CONFIG_BOOTSTAGE_USER_COUNT=32 CONFIG_BOOTSTAGE_FDT=y CONFIG_BOOTSTAGE_STASH=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -120,6 +119,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y @@ -175,10 +176,10 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_WDT=y +CONFIG_WDT_SANDBOX=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y -CONFIG_PHY=y -CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y @@ -187,5 +188,3 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y -CONFIG_WDT=y -CONFIG_WDT_SANDBOX=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 83efb23..c5ef69f 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -4,10 +4,9 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_BOOTSTAGE_USER_COUNT=0x20 +CONFIG_BOOTSTAGE_USER_COUNT=32 CONFIG_BOOTSTAGE_FDT=y CONFIG_BOOTSTAGE_STASH=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -112,6 +111,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y @@ -124,7 +125,6 @@ CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_PM8916=y -CONFIG_PMIC_RK808=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y CONFIG_PMIC_S5M8767=y @@ -134,10 +134,11 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_MAX77686=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S5M8767=y CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_PWM=y +CONFIG_PWM_SANDBOX=y CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y CONFIG_DM_RESET=y @@ -165,8 +166,6 @@ CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y -CONFIG_PHY=y -CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y @@ -175,5 +174,3 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y -CONFIG_DM_PWM=y -CONFIG_PWM_SANDBOX=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 519e91f..747d4b1 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -3,10 +3,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_BOOTSTAGE_USER_COUNT=0x20 +CONFIG_BOOTSTAGE_USER_COUNT=32 CONFIG_BOOTSTAGE_FDT=y CONFIG_BOOTSTAGE_STASH=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -123,6 +122,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y @@ -176,8 +177,6 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y -CONFIG_PHY=y -CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 761cfb6..6889206 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -12,7 +12,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_BOOTSTAGE_USER_COUNT=0x20 +CONFIG_BOOTSTAGE_USER_COUNT=32 CONFIG_BOOTSTAGE_FDT=y CONFIG_BOOTSTAGE_STASH=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -129,6 +129,8 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_SANDBOX=y @@ -182,8 +184,6 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y -CONFIG_PHY=y -CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index d7c8329..537fee7 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -1,56 +1,46 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_BMIPS=y -CONFIG_BAUDRATE=115200 -CONFIG_BCM6345_CLK=y -CONFIG_BCM6345_GPIO=y -CONFIG_BCM6345_SERIAL=y -CONFIG_BMIPS_BOOT_RAM=y +CONFIG_SOC_BMIPS_BCM6358=y CONFIG_BOARD_SFR_NB4_SER=y -CONFIG_CFI_FLASH=y -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTM=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="NB4-SER # " CONFIG_CMD_CPU=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_EDITENV is not set +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_FLASH=y -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_LED=y -CONFIG_CMD_LICENSE=y -CONFIG_CMD_LOADB=y -# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y -# CONFIG_CMD_MISC is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" -CONFIG_DISPLAY_CPUINFO=y +# CONFIG_CMD_MISC is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y -CONFIG_DM_RESET=y -CONFIG_DM_SERIAL=y -CONFIG_HUSH_PARSER=y +CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6358=y CONFIG_LED_GPIO=y -CONFIG_MIPS=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set -# CONFIG_MIPS_BOOT_ENV_LEGACY is not set -CONFIG_MIPS_BOOT_FDT=y CONFIG_MTD=y -CONFIG_MTD_DEVICE=y CONFIG_MTD_NOR_FLASH=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_RESET=y +CONFIG_CFI_FLASH=y +CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y -CONFIG_SOC_BMIPS_BCM6358=y # CONFIG_SPL_SERIAL_PRESENT is not set -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_PROMPT="NB4-SER # " -CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig new file mode 100644 index 0000000..9167e9d --- /dev/null +++ b/configs/sheep-rk3368_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3368=y +CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep" +CONFIG_DEBUG_UART=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_RAM=y +CONFIG_DEBUG_UART_BASE=0xFF1b0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index c041392..83df0bd 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_SNIPER=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 8050f24..5cccd91 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_EXYNOS5=y CONFIG_TARGET_SNOW=y CONFIG_IDENT_STRING=" for snow" CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" +CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y @@ -51,7 +52,6 @@ CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_PWM=y CONFIG_PWM_EXYNOS=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_S5P=y CONFIG_DEBUG_UART_BASE=0x12c30000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index aaa6855..ea3d175 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_VENDOR_ADVANTECH=y CONFIG_TARGET_SOM_DB5800_SOM_6867=y CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867" +CONFIG_DEBUG_UART=y CONFIG_HAVE_INTEL_ME=y CONFIG_ENABLE_MRC_CACHE=y CONFIG_SMP=y @@ -52,7 +53,6 @@ CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_SYS_NS16550=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig new file mode 100644 index 0000000..122bba3 --- /dev/null +++ b/configs/sopine_baseboard_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I=y +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 716f8c0..554ac77 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_EXYNOS5=y CONFIG_TARGET_SPRING=y CONFIG_IDENT_STRING=" for spring" CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring" +CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y @@ -51,7 +52,6 @@ CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_PWM=y CONFIG_PWM_EXYNOS=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_S5P=y CONFIG_DEBUG_UART_BASE=0x12c30000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 4322aad..f76d3c5 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_STM32=y +CONFIG_SYS_MALLOC_F_LEN=0xC00 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco" @@ -24,10 +25,10 @@ CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y -CONFIG_DM_SEQ_ALIAS=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_CLK=y +CONFIG_DM_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -39,17 +40,9 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_FULL is not set CONFIG_PINCTRL_STM32=y -# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_RAM=y +CONFIG_STM32_SDRAM=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set -CONFIG_CLK=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_FULL is not set -CONFIG_PINCTRL_STM32=y -CONFIG_RAM=y -CONFIG_STM32_SDRAM=y -CONFIG_DM_GPIO=y -CONFIG_STM32F7_GPIO=y -CONFIG_SYS_MALLOC_F_LEN=0xC00 diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index e5e100a..6cbda67 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index feb8fe6..93714d1 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index da042ae..ac8f9c6 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -2,11 +2,11 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_TBS2910=y -CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_VIDEO=y CONFIG_CMD_HDMIDETECT=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_PRE_CON_BUF_ADDR=0x7c000000 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 2164237..ada88e7 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" +CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_BOOTDELAY=3 @@ -49,7 +50,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PCI=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig index d5eef70..a9b5fab 100644 --- a/configs/theadorable_defconfig +++ b/configs/theadorable_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" +CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_BOOTDELAY=3 @@ -42,7 +43,6 @@ CONFIG_DM_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 914f70f..e2dc71b 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -4,8 +4,9 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_THUBAN=y +CONFIG_AM33XX=y CONFIG_SYS_MPUCLK=300 +CONFIG_TARGET_THUBAN=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y @@ -20,8 +21,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -65,4 +64,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 -CONFIG_OMAP_WATCHDOG=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 6d6bf67..a9b095c 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_THUNDERX_88XX=y CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core" CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set @@ -20,7 +21,6 @@ CONFIG_SYS_PROMPT="ThunderX_88XX> " CONFIG_DM=y # CONFIG_MMC is not set CONFIG_DM_SERIAL=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_PL011=y CONFIG_DEBUG_UART_BASE=0x87e024000000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index a72c764..1b127b8 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TI814X=y CONFIG_TARGET_TI814X_EVM=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 8021def..1c66082 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -3,27 +3,38 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TI816X=y CONFIG_TARGET_TI816X_EVM=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FAT_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_STACK_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="u-boot/ti816x# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y +# CONFIG_USE_PRIVATE_LIBGCC is not set diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index bac801e..35046a9 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -6,6 +6,7 @@ CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker" +CONFIG_DEBUG_UART=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -58,7 +59,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 9464ea8..8df2fb1 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt" CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y @@ -34,7 +35,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig new file mode 100644 index 0000000..a01a82a --- /dev/null +++ b/configs/topic_miamilite_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="topic" +CONFIG_SYS_CONFIG_NAME="topic_miami" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" +CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="zynq-uboot> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_RAM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 10762f8..f49cbcb 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -1,10 +1,11 @@ CONFIG_ARM=y CONFIG_SYS_VENDOR="topic" -CONFIG_SYS_CONFIG_NAME="topic_miamiplus" +CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt" CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=0 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y @@ -28,12 +29,12 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_NETDEVICES is not set -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig index 65b2b5a..03b99ec 100644 --- a/configs/tricorder_defconfig +++ b/configs/tricorder_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_TRICORDER=y CONFIG_BOOTDELAY=0 CONFIG_SILENT_CONSOLE=y diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig index a5d1bab..b777e84 100644 --- a/configs/tricorder_flash_defconfig +++ b/configs/tricorder_flash_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_TRICORDER=y CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" CONFIG_BOOTDELAY=0 diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index c3e5a9e..27edf05 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 515656d..c12a13d 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -1,6 +1,5 @@ CONFIG_PPC=y CONFIG_MPC83xx=y -CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig index 124506a..f7c9336 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_OMAP34XX=y CONFIG_TARGET_TWISTER=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig deleted file mode 100644 index c75e547..0000000 --- a/configs/v38b_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_V38B=y -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_CMD_IDE=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_DIAG=y -CONFIG_CMD_IRQ=y -CONFIG_MAC_PARTITION=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=16 -CONFIG_LED_STATUS_STATE=1 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig deleted file mode 100644 index 9d60509..0000000 --- a/configs/whistler_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_ARM=y -CONFIG_TEGRA=y -CONFIG_TEGRA20=y -CONFIG_TARGET_WHISTLER=y -CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler" -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_CONSOLE_MUX=y -CONFIG_SYS_STDIO_DEREGISTER=y -CONFIG_SYS_PROMPT="Tegra20 (Whistler) # " -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SPL_DM=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig deleted file mode 100644 index 2b81535..0000000 --- a/configs/wtk_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_TQM823L=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SHARP_LQ065T9DR51U" -CONFIG_BOOTDELAY=5 -# CONFIG_CONSOLE_MUX is not set -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_IDE=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_JFFS2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -# CONFIG_PCI is not set -CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 436a22f..a4b4059 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_ZYNQMP_USB=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -61,7 +62,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=25000000 diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index fbeabde..9daaa06 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -3,9 +3,10 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_ZYNQMP_USB=y CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1" +CONFIG_ZYNQMP_USB=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -53,7 +54,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 6682b67..3ac743b 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -4,10 +4,11 @@ CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 # CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2" # CONFIG_SPL_FAT_SUPPORT is not set CONFIG_ZYNQMP_USB=y -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2" CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" +CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -52,7 +53,6 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 61f3ff9..0f9e4b2 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4" CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" +CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -40,7 +41,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index bfb5c04..3616065 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -3,9 +3,10 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_ZYNQMP_USB=y CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102" +CONFIG_ZYNQMP_USB=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -54,7 +55,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 4ba1ac6..f3ba5a0 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -3,9 +3,10 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_ZYNQMP_USB=y CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102" +CONFIG_ZYNQMP_USB=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" +CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -54,7 +55,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 44e6850..8f20b09 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -47,7 +48,6 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index e5be0d1..f3f89cb 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_zybo" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -45,7 +46,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 diff --git a/doc/README.LED b/doc/README.LED index 7aa95bd..c21c9d5 100644 --- a/doc/README.LED +++ b/doc/README.LED @@ -73,6 +73,5 @@ These are weakly defined in arch/arm/lib/board.c to noops. Where applicable, def these functions in the board specific source. TBD : Describe older board dependent macros similar to what is done for -CONFIG_TQM8xxL. TBD : Describe general support via asm/status_led.h diff --git a/doc/README.MPC866 b/doc/README.MPC866 deleted file mode 100644 index 4707cb7..0000000 --- a/doc/README.MPC866 +++ /dev/null @@ -1,24 +0,0 @@ -The current implementation allows the user to specify the desired CPU -clock value, in MHz, via an environment variable "cpuclk". - -Four compile-time constants are used: - - CONFIG_8xx_OSCLK - input quartz clock - CONFIG_SYS_8xx_CPUCLK_MIN - minimum allowed CPU clock - CONFIG_SYS_8xx_CPUCLK_MAX - maximum allowed CPU clock - CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value - -If the "cpuclk" environment variable value is within the CPUCLK_MIN / -CPUCLK_MAX limits, the specified value is used. Otherwise, the -default CPU clock value is set. - -Please make sure you understand what you are doing, and understand -the restrictions of your hardware (board, processor). For example, -ethernet will stop working for CPU clock frequencies below 25 MHz. - -Please note that the new clock-handling code is enabled if -CONFIG_8xx_CPUCLK_DEFAULT is defined. Since this mechanism supports -only MPC866 and newer CPUs, this constant MUST NOT be defined for -MPC823/850/860/862 series. The clock generation algorithm for older -chips is different and has not been implemented yet. If you need it, -your patch is welcome. diff --git a/doc/README.chromium b/doc/README.chromium new file mode 100644 index 0000000..7bf4d87 --- /dev/null +++ b/doc/README.chromium @@ -0,0 +1,252 @@ +Running U-Boot from coreboot on Chromebooks +=========================================== + +U-Boot can be used as a secondary boot loader in a few situations such as from +UEFI and coreboot (see README.x86). Recent Chromebooks use coreboot even on +ARM platforms to start up the machine. + +This document aims to provide a guide to booting U-Boot on a Chromebook. It +is only a starting point, and there are many guides on the interwebs. But +placing this information in the U-Boot tree should make it easier to find for +those who use U-Boot habitually. + +Most of these platforms are supported by U-Boot natively, but it is risky to +replace the ROM unless you have a servo board and cable to restore it with. + + +For all of these the standard U-Boot build instructions apply. For example on +ARM: + + sudo apt install gcc-arm-linux-gnueabi + mkdir b + make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + +You can obtain the vbutil_kernel utility here: + + https://drive.google.com/open?id=0B7WYZbZ9zd-3dHlVVXo4VXE2T0U + + +Snow (Samsung ARM Chromebook) +----------------------------- + +See here: + +https://www.chromium.org/chromium-os/firmware-porting-guide/using-nv-u-boot-on-the-samsung-arm-chromebook + + +Nyan-big +-------- + +Compiled based on information here: +https://lists.denx.de/pipermail/u-boot/2015-March/209530.html +https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big +https://lists.denx.de/pipermail/u-boot/2017-May/289491.html +https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card + +1. Patch U-Boot + +Open include/configs/tegra124-common.h + +Change: + +#define CONFIG_SYS_TEXT_BASE 0x80110000 + +to: + +#define CONFIG_SYS_TEXT_BASE 0x81000100 + + +2. Build U-Boot + + mkdir b + make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + + +3. Select a .its file + +Select something from doc/chromium which matches your board, or create your +own. + +Note that the device tree node is required, even though it is not actually +used by U-Boot. This is because the Chromebook expects to pass it to the +kernel, and crashes if it is not present. + + +4. Build and sign an image + + ./b/nyan-big/tools/mkimage -f doc/chromium/nyan-big.its u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ + --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. Prepare an SD card + + DISK=/dev/sdc # Replace with your actual SD card device + sudo cgpt create $DISK + sudo cgpt add -b 34 -s 32768 -P 1 -S 1 -t kernel $DISK + sudo cgpt add -b 32802 -s 2000000 -t rootfs $DISK + sudo gdisk $DISK # Enter command 'w' to write a protective MBR to the disk + + +6. Write U-Boot to the SD card + + sudo dd if=u-boot.kpart of=/dev/sdc1; sync + + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display: + + U-Boot 2017.07-00637-g242eb42-dirty (May 22 2017 - 06:14:21 -0600) + + Model: Acer Chromebook 13 CB5-311 + Board: Google/NVIDIA Nyan-big, ID: 1 + + Net: No ethernet found. + Hit any key to stop autoboot: 0 + Tegra124 (Nyan-big) # + + +8. Known problems + +On the serial console the word MMC is chopped at the start of the line: + +C: sdhci@700b0000: 2, sdhci@700b0400: 1, sdhci@700b0600: 0 + +This is likely due to some problem with change-over of the serial driver +during relocation (or perhaps updating the clock setup in board_init()). + + +9. Notes + +To check that you copied the u-boot.its file correctly, use these commands. +You should see that the data at 0x100 in u-boot-chromium.fit is the first few +bytes of U-Boot: + + hd u-boot-chromium.fit |head -20 + ... + 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + hd b/nyan-big/u-boot.bin |head + 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + +The 'data' property of the FIT is set up to start at offset 0x100 bytes into +the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes +from the load address. If this changes, you either need to modify U-Boot to be +fully relocatable, or expect it to hang. + + +chromebook_jerry +---------------- + +The instruction are similar to those for Nyan with changes as noted below: + +1. Patch U-Boot + +Open include/configs/rk3288_common.h + +Change: + +#define CONFIG_SYS_TEXT_BASE 0x00100000 + +to: + +#define CONFIG_SYS_TEXT_BASE 0x02000100 + + + +2. Build U-Boot + + mkdir b + make -j8 O=b/chromebook_jerry CROSS_COMPILE=arm-linux-gnueabi- \ + chromebook_jerry_defconfig all + + +3. See above + +4. Build and sign an image + + ./b/chromebook_jerry/tools/mkimage -f doc/chromium/chromebook_jerry.its \ + u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ + --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. See above + +6. See above + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display: + + U-Boot 2017.05-00649-g72acdbf-dirty (May 29 2017 - 14:57:05 -0600) + + Model: Google Jerry + Net: Net Initialization Skipped + No ethernet found. + Hit any key to stop autoboot: 0 + + +8. Known problems + +None as yet. + + +9. Notes + +None as yet. + + +Other notes +=========== + +flashrom +-------- + + Used to make a backup of your firmware, or to replace it. + + See: https://www.chromium.org/chromium-os/packages/cros-flashrom + + +coreboot +-------- + +Coreboot itself is not designed to actually boot an OS. Instead, a program +called Depthcharge is used. This originally came out of U-Boot and was then +heavily hacked and modified such that is is almost unrecognisable. It does +include a very small part of the U-Boot command-line interface but is not +usable as a general-purpose boot loader. + +In addition, it has a very unusual design in that it does not do device init +itself, but instead relies on coreboot. This is similar to (in U-Boot) having +a SPI driver with an empty probe() method, relying on whatever was set up +beforehand. It can be quite hard to figure out between these two code bases +what settings are actually used. When chain-loading into U-Boot we must be +careful to reinit anything that U-Boot expects. If not, some peripherals (or +the whole machine) may not work. This makes the process of chainloading more +complicated than it could be on some platforms. + +Finally, it supports only a subset of the U-Boot's FIT format. In particular +it uses a fixed address to load the FIT and does not support load/exec +addresses. This means that U-Boot must be able to boot from whatever +address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting +in Depthcharge). In practice this means that the data in the kernel@1 FIT node +(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE. diff --git a/doc/README.fsl-clk b/doc/README.fsl-clk deleted file mode 100644 index 9e83c24..0000000 --- a/doc/README.fsl-clk +++ /dev/null @@ -1,6 +0,0 @@ -Freescale system clock options - - - CONFIG_SYS_FSL_CLK - Enable to call get_clocks() in board_init_f() for - non-PPC platforms and PCC 8xx platforms such as - TQM866M and TQM885D. diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index ba7cea8..61300c3 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -36,8 +36,8 @@ Endianness issues ------------------ The USB bus operates in little endian, but unfortunately there are -OHCI controllers that operate in big endian such as ppc4xx and -mpc5xxx. For these the config option +OHCI controllers that operate in big endian such as ppc4xx. For these the +config option CONFIG_SYS_OHCI_BE_CONTROLLER diff --git a/doc/README.idma2intr b/doc/README.idma2intr deleted file mode 100644 index 1828b51..0000000 --- a/doc/README.idma2intr +++ /dev/null @@ -1,10 +0,0 @@ -(C) 2003 Arun Dharankar - -Attached is an IDMA example code for MPC8260/PPCBoot. I had tried to -search around and could not find any for implementing IDMA, so -implemented one. Its not coded in the best way, but works. - -Also, I was able to test the IDMA specific code under Linux also -(with modifications). My requirement was to implement it for -CompactFlash implemented in memory mode, and it works for it under -PPCBoot and Linux. diff --git a/doc/README.mpc5xx b/doc/README.mpc5xx deleted file mode 100644 index df51b5c..0000000 --- a/doc/README.mpc5xx +++ /dev/null @@ -1,48 +0,0 @@ - -Summary: -======== - -This file contains information about the port of U-Boot to the -Motorola mpc5xx series of CPUs. Most of this code is taken from -existing code mainly from the mpc8xx port. In contrast to mpc8xx, -the mpc5xx has no CPM, MMU and cache facilities. - -The implemented features have been tested on the cmi board, a -customer specific board (see README.cmi). - -Hence this port is only tested on the cmi board further possible -tests on other boards will be very valuable. - -Not Tested Features: -==================== - -* System calls -* Interrupts - -Added or Changed Files: -======================= - -u-boot-0.2.0/common/cmd_boot.c -u-boot-0.2.0/common/cmd_reginfo.c -u-boot-0.2.0/common/environment.c -u-boot-0.2.0/arch/powerpc/cpu/mpc5xx/* -u-boot-0.2.0/include/cmd_reginfo.h -u-boot-0.2.0/include/common.h -u-boot-0.2.0/include/ppc_asm.tmpl -u-boot-0.2.0/include/watchdog.h -u-boot-0.2.0/include/mpc5xx.h -u-boot-0.2.0/include/status_led.h -u-boot-0.2.0/include/asm-ppc/u-boot.h -u-boot-0.2.0/include/asm-ppc/5xx_immap.h -u-boot-0.2.0/arch/powerpc/lib/board.c -u-boot-0.2.0/arch/powerpc/lib/cache.c -u-boot-0.2.0/arch/powerpc/lib/time.c -u-boot-0.2.0/Makefile -u-boot-0.2.0/CREDITS -u-boot-0.2.0/doc/README.mpc5xx -u-boot-0.2.0/doc/README.cmi -u-boot-0.2.0/README -u-boot-0.2.0/MAKEALL - -Regards, -Martin diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads deleted file mode 100644 index 9b35fb2..0000000 --- a/doc/README.mpc85xxads +++ /dev/null @@ -1,301 +0,0 @@ -Motorola MPC8540ADS and MPC8560ADS board - -Created 10/15/03 Xianghua Xiao -Updated 13-July-2004 Jon Loeliger ------------------------------------------ - -0. Toolchain - - The Binutils in current ELDK toolchain will not support MPC85xx - chip. You need to use binutils-2.14.tar.bz2 (or newer) from - http://ftp.gnu.org/gnu/binutils. - - The 8540/8560 ADS code base is known to compile using: - gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) - - -1. SWITCH SETTINGS & JUMPERS - -1.0 Nomenclature - - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1. - Luckily, we're SW types and virtual settings are handled daily. - - The switches for the Rev A board are numbered differently than - for the Pilot board. Oh yeah. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW18 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labeled 8 on Switch 4. - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2 - SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3 - -1.1 For the MPC85xxADS Pilot Board - - First, make sure the board default setting is consistent with the document - shipped with your board. Then apply the following changes: - SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used) - SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560) - SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode) - SW11[7]='ON' (rev2), 'OFF' (rev1) - SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector) - SW22[1-4]="OFF OFF ON OFF" - SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF" - J1 = "Enable Prog" (Make sure your flash is programmable for development) - - If you want to test PCI functionality with a 33Mhz PCI card, you will - have to change the system clock from the default 66Mhz to 33Mhz by - setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need - double your platform clock(SW6) because the system clock is now only - half of its original value. For example, if at 66MHz your system - clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10. - - SW17[8] ------+ SW6 - SW15[1] ----+ | [0:1] - V V V V - 33MHz 1 1 1 0 - 66MHz 0 0 0 1 - - Hmmm... That SW6 setting description is incomplete but it works. - - -1.3 For the MPC85xxADS Rev A Board - - As shipped, the board should be a 33MHz PCI bus with a CPU Clock - rate of 825 +/- fuzz: - - Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz - - For 33MHz PCI, the switch settings should be like this: - - SW18[7:1] = 0100001 = M==33 => 33MHz - SW18[8] = 1 => PWD Divider == 16 - SW16[1:2] = 11 => N == 16 as PWD==1 - - Use the magical formula: - Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz - - SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk - SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock - - - For 66MHz PCI, the switch settings should be like this: - - SW18[7:1] = 0100001 = M==33 => 33MHz - SW18[8] = 0 => PWD Divider == 1 - SW16[1:2] = 01 => N == 8 as PWD == 0 - - Use the magical formula: - Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz - - SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk - SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock - - In order to use PCI-X (only in the first PCI slot. The one with - the RIO connector), you need to set SW1[4] (config) to 1 (off). - Also, configure the board to run PCI at 66 MHz. - -2. MEMORY MAP TO WORK WITH LINUX KERNEL - -2.1. For the initial bringup, we adopted a consistent memory scheme - between U-Boot and linux kernel, you can customize it based on your - system requirements: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x9fff_ffff PCI MEM 512M - 0xc000_0000 0xdfff_ffff Rapid IO 512M - 0xe000_0000 0xe00f_ffff CCSR 1M - 0xe200_0000 0xe2ff_ffff PCI IO 16M - 0xf000_0000 0xf7ff_ffff SDRAM 128M - 0xf800_0000 0xf80f_ffff BCSR 1M - 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - -2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You - can download them from linuxppc-2.4 public source. Please make sure the - kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two - default configuration files as your starting points to configure the - kernel: - arch/powerpc/configs/mpc8540_ads_defconfig - arch/powerpc/configs/mpc8560_ads_defconfig - -3. DEFINITIONS AND COMPILATION - -3.1 Explanation on NEW definitions in: - include/configs/MPC8540ADS.h - include/configs/MPC8560ADS.h - - CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc) - CONFIG_E500 BOOKE e500 family(Motorola) - CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives - CONFIG_ARCH_MPC8540 MPC8540 specific - CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking - CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can - also manual config the DDR after undef this - definition. - CONFIG_DDR_ECC only for ECC DDR module - CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed - for more stability. - CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. - -Other than the above definitions, the rest in the config files are -straightforward. - - -3.2 Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC8560ADS_config (or make MPC8540ADS_config) - make - -4. Notes: - -4.1 When connecting with kermit, the following commands must be present.in - your .kermrc file. These are especially important when booting as - MPC8560, as the serial console will not work without them: - - set speed 115200 - set carrier-watch off - set handshake none - set flow-control none - robust - - -4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC - ethernet. If that happens, you can try the following steps to make - network work: - - MPC8560ADS>tftp 1000000 pImage - (if it hangs, use Ctrl-C to quit) - MPC8560ADS>nm fdf24524 - >0 - >1 - >. (to quit this memory operation) - MPC8560ADS>tftp 1000000 pImage - -4.3 If you're one of the early developers using the Rev1 8540/8560 chips, - please use U-Boot 1.0.0, as the newer silicon will only support Rev2 - and future revisions of 8540/8560. - - -4.4 Reflash U-Boot Image using U-Boot - - tftp 10000 u-boot.bin - protect off fff80000 ffffffff - erase fff80000 ffffffff - cp.b 10000 fff80000 80000 - - -4.5 Reflash U-Boot with a BDI-2000 - - BDI> erase 0xFFF80000 0x4000 0x20 - BDI> prog 0xfff80000 u-boot.bin.8560ads - BDI> verify - - -5. Screen dump MPC8540ADS board - -U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25) - -Freescale PowerPC - Core: E500, Version: 2.0, (0x80200020) - System: 8540, Version: 2.0, (0x80300020) - Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz - L1 D-cache 32KB, L1 I-cache 32KB enabled. -Board: ADS - PCI1: 32 bit, 66 MHz (compiled) -I2C: ready -DRAM: Initializing - SDRAM: 64 MB - DDR: 256 MB -FLASH: 16 MB -L2 cache enabled: 256KB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62) -MOTO ENET1: PHY is Marvell 88E1011S (1410c62) -MOTO ENET2: PHY is Davicom DM9161E (181b881) -MOTO ENET0, MOTO ENET1, MOTO ENET2 -Hit any key to stop autoboot: 0 -=> -=> fli - -Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K) - Size: 16 MB in 64 Sectors - Sector Start Addresses: - FF000000 FF040000 FF080000 FF0C0000 FF100000 - FF140000 FF180000 FF1C0000 FF200000 FF240000 - FF280000 FF2C0000 FF300000 FF340000 FF380000 - FF3C0000 FF400000 FF440000 FF480000 FF4C0000 - FF500000 FF540000 FF580000 FF5C0000 FF600000 - FF640000 FF680000 FF6C0000 FF700000 FF740000 - FF780000 FF7C0000 FF800000 FF840000 FF880000 - FF8C0000 FF900000 FF940000 FF980000 FF9C0000 - FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 - FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 - FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 - FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 - FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO) - -=> bdinfo -memstart = 0x00000000 -memsize = 0x10000000 -flashstart = 0xFF000000 -flashsize = 0x01000000 -flashoffset = 0x00000000 -sramstart = 0x00000000 -sramsize = 0x00000000 -immr_base = 0xE0000000 -bootflags = 0xE4013F80 -intfreq = 825 MHz -busfreq = 330 MHz -ethaddr = 00:E0:0C:00:00:FD -eth1addr = 00:E0:0C:00:01:FD -eth2addr = 00:E0:0C:00:02:FD -IP addr = 192.168.1.253 -baudrate = 115200 bps - - -=> printenv -bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr -ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr -nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr -bootdelay=10 -baudrate=115200 -loads_echo=1 -ethaddr=00:E0:0C:00:00:FD -eth1addr=00:E0:0C:00:01:FD -eth2addr=00:E0:0C:00:02:FD -ipaddr=192.168.1.253 -serverip=192.168.1.1 -rootpath=/nfsroot -gatewayip=192.168.1.1 -netmask=255.255.255.0 -hostname=unknown -bootfile=your.uImage -loadaddr=200000 -netdev=eth0 -consoledev=ttyS0 -ramdiskaddr=400000 -ramdiskfile=your.ramdisk.u-boot -stdin=serial -stdout=serial -stderr=serial -ethact=MOTO ENET0 - -Environment size: 1020/8188 bytes diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 200f670..5e5b07d 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -106,13 +106,9 @@ sbc35_a9g20 arm arm926ejs f6b42c14 2015-05-13 Albin Tonner sc3 powerpc ppc4xx 27e72156 2015-05-10 Heiko Schocher T4240EMU powerpc mpc85xx 7fc63cca 2015-05-05 York Sun korat powerpc ppc4xx 5043045d 2015-03-17 Larry Johnson -galaxy5200 powerpc mpc5xxx 41eb4e5c 2015-03-17 Eric Millbrandt W7OLMC powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen W7OLMG powerpc ppc4xx 6beecd5d 2015-03-17 Erik Theisen -aev powerpc mpc5xxx 470ee8b1 2015-03-17 -TB5200 powerpc mpc5xxx 470ee8b1 2015-03-17 JSE powerpc ppc4xx 2da8137b 2015-03-17 Stephen Williams -BC3450 powerpc mpc5xxx f8296d69 2015-03-17 hawkboard arm arm926ejs cb957cda 2015-02-24 Syed Mohammed Khasim :Sughosh Ganu tnetv107x arm arm1176 50b82c4b 2015-02-24 Chan-Taek Park a320evb arm arm920t 29fc6f24 2015-02-24 Po-Yu Chuang @@ -120,13 +116,6 @@ cm4008 arm arm920t a2f39e83 2015-02-24 Greg Ungerer cm41xx arm arm920t a2f39e83 2015-02-24 dkb arm arm926ejs 346cfba4 2015-02-24 Lei Wen jadecpu arm arm926ejs 41fbbbbc 2015-02-24 Matthias Weisser -icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk -Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23 -cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt -mecp5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt -pf5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt -PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner -Total5200 powerpc mpc5xxx ad734f7d 2015-01-23 CATcenter powerpc ppc4xx 5344cc1a 2015-01-23 PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson P2020DS powerpc mpc85xx 168dcc6c 2015-01-23 @@ -200,9 +189,6 @@ SPD823TS powerpc mpc8xx 72ba368f 2015-01-05 Wolfgang Den KUP4K powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck KUP4X powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck ELPT860 powerpc mpc8xx 3c5b20f1 2015-01-05 The LEOX team -hmi1001 powerpc mpc5xxx ceaf499b 2015-01-05 -mucmc52 powerpc mpc5xxx ceaf499b 2015-01-05 Heiko Schocher -uc101 powerpc mpc5xxx ceaf499b 2015-01-05 Heiko Schocher uc100 powerpc mpc8xx ceaf499b 2015-01-05 Stefan Roese FPS850L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk FPS860L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk @@ -211,9 +197,6 @@ SM850 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Den TK885D powerpc mpc8xx 5d2a5ef7 2015-01-05 virtlab2 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk hermes powerpc mpc8xx 36da51e 2014-12-08 Wolfgang Denk -PRS200 powerpc mpc5200 ecfdcee 2014-11-12 -MCC200 powerpc mpc5200 ecfdcee 2014-11-12 -TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk @@ -228,8 +211,6 @@ DB64360 powerpc 74xx_7xx 03b0040 2014-10-27 DB64460 powerpc 74xx_7xx 03b0040 2014-10-27 p3m750 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese p3m7448 powerpc 74xx_7xx 03b0040 2014-10-27 Stefan Roese -MVBC_P powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz -MVSMR powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz MERGERBOX powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz MVBLM7 powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz bluestone powerpc ppc4xx 9ed3246 2014-10-10 Tirumala Marri @@ -316,7 +297,6 @@ ADCIOP powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuc DASA_SIM powerpc ppc4xx 99bcad1 2012-09-19 Matthias Fuchs apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park tb0229 mips mips32 3f3110d 2011-12-12 -rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk OXC powerpc MPC8240 309a292 2011-12-07 BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling xm250 arm pxa c477d72 2011-11-25 @@ -373,8 +353,6 @@ CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Den logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk -spieval powerpc MPC5200 69434e4 2010-09-19 -smmaco4 powerpc MPC5200 9ddc3af 2010-09-19 HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange AmigaOneG3SE powerpc 74xx_7xx 953b7e6 2010-06-23 diff --git a/doc/README.serial_multi b/doc/README.serial_multi index ad61d42..c9049fd 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -52,29 +52,3 @@ PPC4XX Specific setenv stdout serial0 setenv stderr serial0 setenv stdin serial0 - -MPC5xxx Specific -================ - -Up to two PSCs can be used as console. - -Support for hardware handshake has not been implemented yet. - -*) The first (default) console port is defined by: - #define CONFIG_PSC_CONSOLE - -*) The second (alternative) console port is defined by: - #define CONFIG_PSC_CONSOLE2 - -*) Commands to switch to the second console: - setenv stdout serial1 - setenv stderr serial1 - setenv stdin serial1 - -*) Commands to switch to the first console: - setenv stdout serial0 - setenv stderr serial0 - setenv stdin serial0 - -*) If a file descriptor is set to "serial" then the - current serial device will be used. diff --git a/doc/chromium/chromebook_jerry.its b/doc/chromium/chromebook_jerry.its new file mode 100644 index 0000000..8cff840 --- /dev/null +++ b/doc/chromium/chromebook_jerry.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel@1 { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../../b/chromebook_jerry/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash@2 { + algo = "sha1"; + }; + }; + + fdt@1{ + description = "rk3288-veryron-jerry.dtb"; + data = /incbin/("../../b/chromebook_jerry/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot U-Boot"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; diff --git a/doc/chromium/devkeys/kernel.keyblock b/doc/chromium/devkeys/kernel.keyblock new file mode 100644 index 0000000..9740be4 Binary files /dev/null and b/doc/chromium/devkeys/kernel.keyblock differ diff --git a/doc/chromium/devkeys/kernel_data_key.vbprivk b/doc/chromium/devkeys/kernel_data_key.vbprivk new file mode 100644 index 0000000..8d392fb Binary files /dev/null and b/doc/chromium/devkeys/kernel_data_key.vbprivk differ diff --git a/doc/chromium/nyan-big.its b/doc/chromium/nyan-big.its new file mode 100644 index 0000000..8dc8d73 --- /dev/null +++ b/doc/chromium/nyan-big.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel@1 { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../.././b/nyan-big/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash@2 { + algo = "sha1"; + }; + }; + + fdt@1{ + description = "tegra124-nyan-big.dtb"; + data = /incbin/("../.././b/nyan-big/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot U-Boot"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index 07fa46e..929ae88 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -6,8 +6,8 @@ UPD data for configuring the SoC. All properties can be found within the `upd-region` struct in arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in -Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is -matched up to Intel's E3800 FSPv4 release. +Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties +is matched up to Intel's E3800 FSPv4 release. # Boolean properties: @@ -19,8 +19,6 @@ matched up to Intel's E3800 FSPv4 release. - fsp,enable-sata - fsp,enable-azalia - fsp,enable-xhci -- fsp,enable-lpe -- fsp,lpss-sio-enable-pci-mode - fsp,enable-dma0 - fsp,enable-dma1 - fsp,enable-i2-c0 @@ -35,7 +33,6 @@ matched up to Intel's E3800 FSPv4 release. - fsp,enable-hsi - fsp,mrc-debug-msg - fsp,isp-enable -- fsp,scc-enable-pci-mode - fsp,igd-render-standby - fsp,txe-uma-enable - fsp,emmc45-ddr50-enabled @@ -44,8 +41,8 @@ matched up to Intel's E3800 FSPv4 release. - fsp,enable-memory-down If you set "fsp,enable-memory-down" you are strongly encouraged to provide an -"fsp,memory-down-params{};" to specify how your memory is configured. If you do -not set "fsp,enable-memory-down", then the DIMM SPD information will be +"fsp,memory-down-params{};" to specify how your memory is configured. If you +do not set "fsp,enable-memory-down", then the DIMM SPD information will be discovered by the FSP and used to setup main memory. @@ -57,11 +54,12 @@ discovered by the FSP and used to setup main memory. - fsp,mrc-init-spd-addr2 - fsp,emmc-boot-mode - fsp,sata-mode +- fsp,lpe-mode +- fsp,lpss-sio-mode - fsp,igd-dvmt50-pre-alloc - fsp,aperture-size - fsp,gtt-size -- fsp,serial-debug-port-address -- fsp,serial-debug-port-type +- fsp,scc-mode - fsp,os-selection - fsp,emmc45-retune-timer-value @@ -74,41 +72,12 @@ discovered by the FSP and used to setup main memory. # Integer properties: - - fsp,dram-speed: - 0x0: "800 MHz" - 0x1: "1066 MHz" - 0x2: "1333 MHz" - 0x3: "1600 MHz" - + - fsp,dram-speed - fsp,dram-type - 0x0: "DDR3" - 0x1: "DDR3L" - 0x2: "DDR3U" - 0x4: "LPDDR2" - 0x5: "LPDDR3" - 0x6: "DDR4" - - fsp,dimm-width - 0x0: "x8" - 0x1: "x16" - 0x2: "x32" - - fsp,dimm-density - 0x0: "1 Gbit" - 0x1: "2 Gbit" - 0x2: "4 Gbit" - 0x3: "8 Gbit" - - fsp,dimm-bus-width - 0x0: "8 bits" - 0x1: "16 bits" - 0x2: "32 bits" - 0x3: "64 bits" - - fsp,dimm-sides - 0x0: "1 rank" - 0x1: "2 ranks" - - fsp,dimm-tcl - fsp,dimm-trpt-rcd - fsp,dimm-twr @@ -118,6 +87,9 @@ discovered by the FSP and used to setup main memory. - fsp,dimm-tfaw }; +For all integer properties, available options are listed in fsp_configs.h in +arch/x86/include/asm/arch-baytrail/fsp directory (eg: MRC_INIT_TSEG_SIZE_1MB). + Example (from MinnowMax Dual Core): ----------------------------------- @@ -127,20 +99,19 @@ Example (from MinnowMax Dual Core): fsp { compatible = "intel,baytrail-fsp"; - fsp,mrc-init-tseg-size = <0>; - fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-tseg-size = ; + fsp,mrc-init-mmio-size = ; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = ; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; fsp,enable-spi; fsp,enable-sata; - fsp,sata-mode = <1>; - fsp,enable-xhci; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,sata-mode = ; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -152,27 +123,24 @@ Example (from MinnowMax Dual Core): fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; - fsp,igd-dvmt50-pre-alloc = <2>; - fsp,aperture-size = <2>; - fsp,gtt-size = <2>; - fsp,serial-debug-port-address = <0x3f8>; - fsp,serial-debug-port-type = <1>; - fsp,mrc-debug-msg; - fsp,scc-enable-pci-mode; - fsp,os-selection = <4>; + fsp,igd-dvmt50-pre-alloc = ; + fsp,aperture-size = ; + fsp,gtt-size = ; + fsp,scc-mode = ; + fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; fsp,enable-igd; fsp,enable-memory-down; fsp,memory-down-params { compatible = "intel,baytrail-fsp-mdp"; - fsp,dram-speed = <1>; - fsp,dram-type = <1>; + fsp,dram-speed = ; + fsp,dram-type = ; fsp,dimm-0-enable; - fsp,dimm-width = <1>; - fsp,dimm-density = <2>; - fsp,dimm-bus-width = <3>; - fsp,dimm-sides = <0>; + fsp,dimm-width = ; + fsp,dimm-density = ; + fsp,dimm-bus-width = ; + fsp,dimm-sides = ; fsp,dimm-tcl = <0xb>; fsp,dimm-trpt-rcd = <0xb>; fsp,dimm-twr = <0xc>; diff --git a/doc/git-mailrc b/doc/git-mailrc index b9b5929..33317d1 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -77,7 +77,7 @@ alias tegra2 tegra alias ti uboot, trini alias uniphier uboot, masahiro alias zynq uboot, monstr -alias rockchip uboot, sjg, Lin huang +alias rockchip uboot, sjg, Kever Yang alias avr32 uboot, abiessmann alias bfin uboot, vapier, sonic diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 6145675..23f131b 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -453,6 +453,32 @@ int blk_prepare_device(struct udevice *dev) return 0; } +int blk_get_from_parent(struct udevice *parent, struct udevice **devp) +{ + struct udevice *dev; + enum uclass_id id; + int ret; + + device_find_first_child(parent, &dev); + if (!dev) { + debug("%s: No block device found for parent '%s'\n", __func__, + parent->name); + return -ENODEV; + } + id = device_get_uclass_id(dev); + if (id != UCLASS_BLK) { + debug("%s: Incorrect uclass %s for block device '%s'\n", + __func__, uclass_get_name(id), dev->name); + return -ENOTBLK; + } + ret = device_probe(dev); + if (ret) + return ret; + *devp = dev; + + return 0; +} + int blk_find_max_devnum(enum if_type if_type) { struct udevice *dev; diff --git a/drivers/block/ide.c b/drivers/block/ide.c index ac5b91c..308ad73 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -770,10 +770,6 @@ void ide_init(void) unsigned char c; int i, bus; -#ifdef CONFIG_IDE_8xx_PCCARD - extern int ide_devices_found; /* Initialized in check_ide_device() */ -#endif /* CONFIG_IDE_8xx_PCCARD */ - #ifdef CONFIG_IDE_PREINIT WATCHDOG_RESET(); @@ -812,13 +808,6 @@ void ide_init(void) bus * (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS); -#ifdef CONFIG_IDE_8xx_PCCARD - /* Skip non-ide devices from probing */ - if ((ide_devices_found & (1 << bus)) == 0) { - ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */ - continue; - } -#endif printf("Bus %d: ", bus); ide_bus_ok[bus] = 0; diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c index 65a4bb2..0c24fce 100644 --- a/drivers/block/sata_ceva.c +++ b/drivers/block/sata_ceva.c @@ -6,7 +6,6 @@ */ #include #include -#include #include #include #include diff --git a/drivers/block/sil680.c b/drivers/block/sil680.c index b1db257..bca3397 100644 --- a/drivers/block/sil680.c +++ b/drivers/block/sil680.c @@ -18,7 +18,6 @@ * #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 * * #define CONFIG_IDE - * #undef CONFIG_IDE_8xx_DIRECT * #undef CONFIG_IDE_LED * #undef CONFIG_IDE_RESET * #define CONFIG_IDE_PREINIT diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index d5ce450..0299a5a 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -14,26 +14,6 @@ */ #if !defined(CONFIG_SYS_BOOTCOUNT_ADDR) -#if defined(CONFIG_MPC5xxx) -#define CONFIG_SYS_BOOTCOUNT_ADDR (MPC5XXX_CDM_BRDCRMB) -#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD -#endif /* defined(CONFIG_MPC5xxx) */ - -#if defined(CONFIG_MPC512X) -#define CONFIG_SYS_BOOTCOUNT_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->clk.bcr) -#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD -#endif /* defined(CONFIG_MPC512X) */ - -#if defined(CONFIG_8xx) -#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \ - CPM_BOOTCOUNT_ADDR) -#endif /* defined(CONFIG_8xx) */ - -#if defined(CONFIG_MPC8260) -#include -#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) -#endif /* defined(CONFIG_MPC8260) */ - #if defined(CONFIG_QE) #include #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 1091a76..e404c0c 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -8,4 +8,6 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o +obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 0bee5db..28652df 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -65,12 +65,11 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (div->postdiv2 << PLL_POSTDIV2_SHIFT | - div->refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) @@ -87,8 +86,7 @@ static void rkclk_init(struct rk3036_cru *cru) /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | APLL_MODE_SLOW << APLL_MODE_SHIFT); @@ -97,8 +95,8 @@ static void rkclk_init(struct rk3036_cru *cru) rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); /* - * select apll as core clock pll source and - * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * select apll as cpu/core clock pll source and + * set up dependent divisors for PERI and ACLK clocks. * core hz : apll = 1:1 */ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; @@ -108,44 +106,40 @@ static void rkclk_init(struct rk3036_cru *cru) assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT | - CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT, + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 0 << CORE_DIV_CON_SHIFT); rk_clrsetreg(&cru->cru_clksel_con[1], - CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT | - CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, aclk_div << CORE_ACLK_DIV_SHIFT | pclk_div << CORE_PERI_DIV_SHIFT); /* - * select apll as cpu clock pll source and + * select apll as pd_bus bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ - aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; - assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f); + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); - pclk_div = APLL_HZ / CPU_PCLK_HZ - 1; - assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7); + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); - hclk_div = APLL_HZ / CPU_HCLK_HZ - 1; - assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3); + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); rk_clrsetreg(&cru->cru_clksel_con[0], - CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT | - ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT, - CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT | - aclk_div << ACLK_CPU_DIV_SHIFT); + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | + aclk_div << BUS_ACLK_DIV_SHIFT); rk_clrsetreg(&cru->cru_clksel_con[1], - CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | - CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, - pclk_div << CPU_PCLK_DIV_SHIFT | - hclk_div << CPU_HCLK_DIV_SHIFT); + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, + pclk_div << BUS_PCLK_DIV_SHIFT | + hclk_div << BUS_HCLK_DIV_SHIFT); /* - * select gpll as peri clock pll source and + * select gpll as pd_peri bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; @@ -153,17 +147,15 @@ static void rkclk_init(struct rk3036_cru *cru) hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == - PERI_ACLK_HZ && (pclk_div < 0x4)); + PERI_ACLK_HZ && (hclk_div < 0x4)); pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && pclk_div < 0x8); rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT | - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -171,8 +163,7 @@ static void rkclk_init(struct rk3036_cru *cru) /* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_NORM << GPLL_MODE_SHIFT | APLL_MODE_NORM << APLL_MODE_SHIFT); } @@ -189,9 +180,9 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, GPLL_MODE_SHIFT, 0xff }; - static u8 clk_mask[CLK_COUNT] = { - 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, - GPLL_MODE_MASK, 0xff + static u32 clk_mask[CLK_COUNT] = { + 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, + GPLL_MODE_MASK, 0xffffffff }; uint shift; uint mask; @@ -200,18 +191,18 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, shift = clk_shift[clk_id]; mask = clk_mask[clk_id]; - switch ((con >> shift) & mask) { + switch ((con & mask) >> shift) { case GPLL_MODE_SLOW: return OSC_HZ; case GPLL_MODE_NORM: /* normal mode */ con = readl(&pll->con0); - postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK; - fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK; + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; con = readl(&pll->con1); - postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK; - refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK; + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; case GPLL_MODE_DEEP: default: @@ -230,14 +221,14 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, case HCLK_EMMC: case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDIO: case SCLK_SDIO: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; default: return -EINVAL; @@ -269,16 +260,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, case HCLK_EMMC: case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDIO: case SCLK_SDIO: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break; diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 14851ca..792ee76 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -59,14 +59,14 @@ enum { PLL_RESET_SHIFT = 5, /* CLKSEL0 */ - CORE_SEL_PLL_MASK = 1, CORE_SEL_PLL_SHIFT = 15, - A17_DIV_MASK = 0x1f, + CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, A17_DIV_SHIFT = 8, - MP_DIV_MASK = 0xf, + A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, MP_DIV_SHIFT = 4, - M0_DIV_MASK = 0xf, + MP_DIV_MASK = 0xf << MP_DIV_SHIFT, M0_DIV_SHIFT = 0, + M0_DIV_MASK = 0xf << M0_DIV_SHIFT, /* CLKSEL1: pd bus clk pll sel: codec or general */ PD_BUS_SEL_PLL_MASK = 15, @@ -75,41 +75,41 @@ enum { /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ PD_BUS_PCLK_DIV_SHIFT = 12, - PD_BUS_PCLK_DIV_MASK = 7, + PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PD_BUS_HCLK_DIV_SHIFT = 8, - PD_BUS_HCLK_DIV_MASK = 3, + PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ PD_BUS_ACLK_DIV0_SHIFT = 3, - PD_BUS_ACLK_DIV0_MASK = 0x1f, + PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, PD_BUS_ACLK_DIV1_SHIFT = 0, - PD_BUS_ACLK_DIV1_MASK = 0x7, + PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, /* * CLKSEL10 * peripheral bus pclk div: * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 */ - PERI_SEL_PLL_MASK = 1, PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, PERI_SEL_CPLL = 0, PERI_SEL_GPLL, PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, /* * peripheral bus aclk div: * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) */ PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, SOCSTS_DPLL_LOCK = 1 << 5, SOCSTS_APLL_LOCK = 1 << 6, @@ -131,10 +131,8 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); -#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); -#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -154,8 +152,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, /* enter reset */ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); - rk_clrsetreg(&pll->con0, - CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); @@ -198,7 +195,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, } /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); @@ -208,7 +205,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); return 0; @@ -296,7 +293,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, { /* Assuming mac_clk is fed by an external clock */ rk_clrsetreg(&cru->cru_clksel_con[21], - RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_MASK, RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); return 0; @@ -313,7 +310,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, if (ret) return ret; - rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_SLOW << NPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_NEW, &npll_config); @@ -324,7 +321,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); } - rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); /* vop dclk source clk: npll,dclk_div: 1 */ @@ -341,9 +338,8 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, return 0; } -#endif +#endif /* CONFIG_SPL_BUILD */ -#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) { u32 aclk_div; @@ -352,8 +348,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); @@ -382,10 +377,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PD_BUS_ACLK_HZ && pclk_div < 0x7); rk_clrsetreg(&cru->cru_clksel_con[1], - PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT | - PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT | - PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT | - PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT, + PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | + PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, pclk_div << PD_BUS_PCLK_DIV_SHIFT | hclk_div << PD_BUS_HCLK_DIV_SHIFT | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | @@ -407,9 +400,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PERI_ACLK_HZ && (pclk_div < 0x4)); rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | + PERI_ACLK_DIV_MASK, PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -417,18 +409,15 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) /* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } -#endif void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_SLOW << APLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); @@ -444,10 +433,8 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT | - A17_DIV_MASK << A17_DIV_SHIFT | - MP_DIV_MASK << MP_DIV_SHIFT | - M0_DIV_MASK << M0_DIV_SHIFT, + CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | + M0_DIV_MASK, 0 << A17_DIV_SHIFT | 3 << MP_DIV_SHIFT | 1 << M0_DIV_SHIFT); @@ -457,16 +444,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ rk_clrsetreg(&cru->cru_clksel_con[37], - CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT | - ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT | - PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT, + CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | + PCLK_CORE_DBG_DIV_MASK, 1 << CLK_L2RAM_DIV_SHIFT | 3 << ATCLK_CORE_DIV_CON_SHIFT | 3 << PCLK_CORE_DBG_DIV_SHIFT); /* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_NORMAL << APLL_MODE_SHIFT); } @@ -486,16 +471,16 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, con = readl(&cru->cru_mode_con); shift = clk_shift[clk_id]; - switch ((con >> shift) & APLL_MODE_MASK) { + switch ((con >> shift) & CRU_MODE_MASK) { case APLL_MODE_SLOW: return OSC_HZ; case APLL_MODE_NORMAL: /* normal mode */ con = readl(&pll->con0); - no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; - nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; + nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; con = readl(&pll->con1); - nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; return (24 * nf / (nr * no)) * 1000000; case APLL_MODE_DEEP: @@ -515,20 +500,20 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->cru_clksel_con[11]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; case HCLK_SDIO0: case SCLK_SDIO0: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; - div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; + mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; + div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; break; default: return -EINVAL; @@ -561,24 +546,21 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDMMC: case SCLK_SDMMC: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break; case HCLK_SDIO0: case SCLK_SDIO0: rk_clrsetreg(&cru->cru_clksel_con[12], - SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | - SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, + SDIO0_PLL_MASK | SDIO0_DIV_MASK, mux << SDIO0_PLL_SHIFT | (src_clk_div - 1) << SDIO0_DIV_SHIFT); break; @@ -598,18 +580,18 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK; - div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; + div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; break; case SCLK_SPI1: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK; - div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; + div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; break; case SCLK_SPI2: con = readl(&cru->cru_clksel_con[39]); - mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK; - div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK; + mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; + div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; break; default: return -EINVAL; @@ -629,22 +611,19 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI0_PLL_MASK << SPI0_PLL_SHIFT | - SPI0_DIV_MASK << SPI0_DIV_SHIFT, + SPI0_PLL_MASK | SPI0_DIV_MASK, SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | src_clk_div << SPI0_DIV_SHIFT); break; case SCLK_SPI1: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI1_PLL_MASK << SPI1_PLL_SHIFT | - SPI1_DIV_MASK << SPI1_DIV_SHIFT, + SPI1_PLL_MASK | SPI1_DIV_MASK, SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | src_clk_div << SPI1_DIV_SHIFT); break; case SCLK_SPI2: rk_clrsetreg(&cru->cru_clksel_con[39], - SPI2_PLL_MASK << SPI2_PLL_SHIFT | - SPI2_DIV_MASK << SPI2_DIV_SHIFT, + SPI2_PLL_MASK | SPI2_DIV_MASK, SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | src_clk_div << SPI2_DIV_SHIFT); break; @@ -803,6 +782,7 @@ static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) static int rk3288_clk_probe(struct udevice *dev) { struct rk3288_clk_priv *priv = dev_get_priv(dev); + bool init_clocks = false; priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) @@ -813,8 +793,24 @@ static int rk3288_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif - rkclk_init(priv->cru, priv->grf); + init_clocks = true; #endif + if (!(gd->flags & GD_FLG_RELOC)) { + u32 reg; + + /* + * Init clocks in U-Boot proper if the NPLL is runnning. This + * indicates that a previous boot loader set up the clocks, so + * we need to redo it. U-Boot's SPL does not set this clock. + */ + reg = readl(&priv->cru->cru_mode_con); + if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == + NPLL_MODE_NORMAL) + init_clocks = true; + } + + if (init_clocks) + rkclk_init(priv->cru, priv->grf); return 0; } diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c new file mode 100644 index 0000000..52cad38 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +#define OSC_HZ (24 * 1000 * 1000) +#define APLL_L_HZ (800 * 1000 * 1000) +#define APLL_B_HZ (816 * 1000 * 1000) +#define GPLL_HZ (576 * 1000 * 1000) +#define CPLL_HZ (400 * 1000 * 1000) + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) { \ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ + "divisors on line " __stringify(__LINE__)); + +static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); +static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, + enum rk3368_pll_id pll_id) +{ + uint32_t nr, no, nf; + uint32_t con; + struct rk3368_pll *pll = &cru->pll[pll_id]; + + con = readl(&pll->con3); + + switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { + case PLL_MODE_SLOW: + return OSC_HZ; + case PLL_MODE_NORMAL: + con = readl(&pll->con0); + no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; + nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; + con = readl(&pll->con1); + nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; + + return (24 * nf / (nr * no)) * 1000000; + case PLL_MODE_DEEP_SLOW: + default: + return 32768; + } +} + +static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, + const struct pll_div *div, bool has_bwadj) +{ + struct rk3368_pll *pll = &cru->pll[pll_id]; + /* All PLLs have same VCO and output frequency range restrictions*/ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", + pll, div->nf, div->nr, div->no, vco_hz, output_hz); + + /* enter slow mode and reset pll */ + rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, + PLL_RESET << PLL_RESET_SHIFT); + + rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, + ((div->nr - 1) << PLL_NR_SHIFT) | + ((div->no - 1) << PLL_OD_SHIFT)); + writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); + udelay(10); + + /* return from reset */ + rk_clrreg(&pll->con3, PLL_RESET_MASK); + + /* waiting for pll lock */ + while (!(readl(&pll->con1) & PLL_LOCK_STA)) + udelay(1); + + rk_clrsetreg(&pll->con3, PLL_MODE_MASK, + PLL_MODE_NORMAL << PLL_MODE_SHIFT); + + return 0; +} + +static void rkclk_init(struct rk3368_cru *cru) +{ + u32 apllb, aplll, dpll, cpll, gpll; + + rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false); + rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false); + rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false); + rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false); + + apllb = rkclk_pll_get_rate(cru, APLLB); + aplll = rkclk_pll_get_rate(cru, APLLL); + dpll = rkclk_pll_get_rate(cru, DPLL); + cpll = rkclk_pll_get_rate(cru, CPLL); + gpll = rkclk_pll_get_rate(cru, GPLL); + + debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", + __func__, apllb, aplll, dpll, cpll, gpll); +} + +static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) +{ + u32 div, con, con_id, rate; + u32 pll_rate; + + switch (clk_id) { + case SCLK_SDMMC: + con_id = 50; + break; + case SCLK_EMMC: + con_id = 51; + break; + case SCLK_SDIO0: + con_id = 48; + break; + default: + return -EINVAL; + } + + con = readl(&cru->clksel_con[con_id]); + switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) { + case MMC_PLL_SEL_GPLL: + pll_rate = rkclk_pll_get_rate(cru, GPLL); + break; + case MMC_PLL_SEL_24M: + pll_rate = OSC_HZ; + break; + case MMC_PLL_SEL_CPLL: + case MMC_PLL_SEL_USBPHY_480M: + default: + return -EINVAL; + } + div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT; + rate = DIV_TO_RATE(pll_rate, div); + + return rate >> 1; +} + +static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru, + ulong clk_id, ulong rate) +{ + u32 div; + u32 con_id; + u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL); + + div = RATE_TO_DIV(gpll_rate, rate << 1); + + switch (clk_id) { + case SCLK_SDMMC: + con_id = 50; + break; + case SCLK_EMMC: + con_id = 51; + break; + case SCLK_SDIO0: + con_id = 48; + break; + default: + return -EINVAL; + } + + if (div > 0x3f) { + div = RATE_TO_DIV(OSC_HZ, rate); + rk_clrsetreg(&cru->clksel_con[con_id], + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, + (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) | + (div << MMC_CLK_DIV_SHIFT)); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, + (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) | + div << MMC_CLK_DIV_SHIFT); + } + + return rk3368_mmc_get_clk(cru, clk_id); +} + +static ulong rk3368_clk_get_rate(struct clk *clk) +{ + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + debug("%s id:%ld\n", __func__, clk->id); + switch (clk->id) { + case HCLK_SDMMC: + case HCLK_EMMC: + rate = rk3368_mmc_get_clk(priv->cru, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate); + switch (clk->id) { + case SCLK_SDMMC: + case SCLK_EMMC: + ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static struct clk_ops rk3368_clk_ops = { + .get_rate = rk3368_clk_get_rate, + .set_rate = rk3368_clk_set_rate, +}; + +static int rk3368_clk_probe(struct udevice *dev) +{ + struct rk3368_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk3368_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3368_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev); + + return 0; +} + +static int rk3368_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev); + if (ret) + error("bind RK3368 reset driver failed: ret=%d\n", ret); + + return ret; +} + +static const struct udevice_id rk3368_clk_ids[] = { + { .compatible = "rockchip,rk3368-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3368_cru) = { + .name = "rockchip_rk3368_cru", + .id = UCLASS_CLK, + .of_match = rk3368_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3368_cru), + .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata, + .ops = &rk3368_clk_ops, + .bind = rk3368_clk_bind, + .probe = rk3368_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c new file mode 100644 index 0000000..0a3ba3b --- /dev/null +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use interge mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static inline int rv1108_pll_id(enum rk_clk_id clk_id) +{ + int id = 0; + + switch (clk_id) { + case CLK_ARM: + case CLK_DDR: + id = clk_id - 1; + break; + case CLK_GENERAL: + id = 2; + break; + default: + printf("invalid pll id:%d\n", clk_id); + id = -1; + break; + } + + return id; +} + +static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con0, con1, con3; + int pll_id = rv1108_pll_id(clk_id); + struct rv1108_pll *pll = &cru->pll[pll_id]; + uint32_t freq; + + con3 = readl(&pll->con3); + + if (con3 & WORK_MODE_MASK) { + con0 = readl(&pll->con0); + con1 = readl(&pll->con1); + fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; + postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; + postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; + refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; + freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + } else { + freq = OSC_HZ; + } + + return freq; +} + +static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) +{ + uint32_t con = readl(&cru->clksel_con[24]); + ulong pll_rate; + uint8_t div; + + if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + else + pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); + + /*default set 50MHZ for gmac*/ + if (!rate) + rate = 50000000; + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x1f) + rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, + div << MAC_CLK_DIV_SHIFT); + else + debug("Unsupported div for gmac:%d\n", div); + + return DIV_TO_RATE(pll_rate, div); +} + +static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) +{ + u32 con = readl(&cru->clksel_con[27]); + u32 pll_rate; + u32 div; + + if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL) + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + else + pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x3f) + rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, + div << SFC_CLK_DIV_SHIFT); + else + debug("Unsupported sfc clk rate:%d\n", rate); + + return DIV_TO_RATE(pll_rate, div); +} + +static ulong rv1108_clk_get_rate(struct clk *clk) +{ + struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0 ... 63: + return rkclk_pll_get_rate(priv->cru, clk->id); + default: + return -ENOENT; + } +} + +static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate; + + switch (clk->id) { + case SCLK_MAC: + new_rate = rv1108_mac_set_clk(priv->cru, rate); + break; + case SCLK_SFC: + new_rate = rv1108_sfc_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static const struct clk_ops rv1108_clk_ops = { + .get_rate = rv1108_clk_get_rate, + .set_rate = rv1108_clk_set_rate, +}; + +static void rkclk_init(struct rv1108_cru *cru) +{ + unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM); + unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); + unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); + + rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, + 0 << MAC_CLK_DIV_SHIFT); + + printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); +} + +static int rv1108_clk_probe(struct udevice *dev) +{ + struct rv1108_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rv1108_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev); + if (ret) + error("No Rv1108 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rv1108_clk_ids[] = { + { .compatible = "rockchip,rv1108-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rv1108) = { + .name = "clk_rv1108", + .id = UCLASS_CLK, + .of_match = rv1108_clk_ids, + .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv), + .ops = &rv1108_clk_ops, + .bind = rv1108_clk_bind, + .probe = rv1108_clk_probe, +}; diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 94ef3cc..93a6560 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -244,6 +244,12 @@ static struct device_node *__of_get_next_child(const struct device_node *node, return NULL; next = prev ? prev->sibling : node->child; + /* + * coverity[dead_error_line : FALSE] + * Dead code here since our current implementation of of_node_get() + * always returns NULL (Coverity CID 163245). But we leave it as is + * since we may want to implement get/put later. + */ for (; next; next = next->sibling) if (of_node_get(next)) break; diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 5b7ced5..aaf4dfb 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -12,6 +12,7 @@ #include #include #include +#include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 21687dd..c0ee858 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -16,6 +16,10 @@ #include #include #include +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_ARM) +#include +#endif /* * Determine Rtt value. diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index e0f9e2c..3349fc5 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -11,6 +11,10 @@ #include #include #include +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_ARM) +#include +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \ defined(CONFIG_SYS_FSL_ERRATUM_A009803) diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 202ad13..653bbab 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -154,7 +154,9 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, static const struct options_string options[] = { COMMON_TIMING(tckmin_x_ps), COMMON_TIMING(tckmax_ps), +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) COMMON_TIMING(taamin_ps), +#endif COMMON_TIMING(trcd_ps), COMMON_TIMING(trp_ps), COMMON_TIMING(tras_ps), @@ -422,7 +424,9 @@ static void print_lowest_common_dimm_parameters( const common_timing_params_t *plcd_dimm_params) { static const struct options_string options[] = { +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) COMMON_TIMING(taamin_ps), +#endif COMMON_TIMING(trcd_ps), COMMON_TIMING(trp_ps), COMMON_TIMING(tras_ps), diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index b45a879..20edd2d 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -9,6 +9,10 @@ #include #include +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_ARM) +#include +#endif /* * Use our own stack based buffer before relocation to allow accessing longer diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index b58784b..0a305b3 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -13,6 +13,10 @@ #include #include #include +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_ARM) +#include +#endif /* To avoid 64-bit full-divides, we factor this here */ #define ULL_2E12 2000000000000ULL diff --git a/drivers/ddr/marvell/axp/ddr3_dqs.c b/drivers/ddr/marvell/axp/ddr3_dqs.c index 71a986d..4644336 100644 --- a/drivers/ddr/marvell/axp/ddr3_dqs.c +++ b/drivers/ddr/marvell/axp/ddr3_dqs.c @@ -1268,7 +1268,7 @@ int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, max_pup = (ecc + (1 - ecc) * dram_info->num_of_std_pups); - DEBUG_DQS_RESULTS_S("\n############ LOG LEVEL 2(Windows margins) ############\n");; + DEBUG_DQS_RESULTS_S("\n############ LOG LEVEL 2(Windows margins) ############\n"); if (is_tx) { DEBUG_DQS_RESULTS_C("DDR3 - DQS TX - Set Dqs Centralization Results - CS: ", diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 9702eee..b6d5fe2 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -20,7 +20,8 @@ static long dfu_get_medium_size_sf(struct dfu_entity *dfu) static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { - return spi_flash_read(dfu->data.sf.dev, offset, *len, buf); + return spi_flash_read(dfu->data.sf.dev, dfu->data.sf.start + offset, + *len, buf); } static u64 find_sector(struct dfu_entity *dfu, u64 start, u64 offset) diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 23039c3..57a4e6c 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -10,6 +10,7 @@ #include #include #include +#include #define DUMMY_WORD 0xffffffff @@ -191,25 +192,14 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, return 0; } -static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2) -{ - struct pt_regs regs; - regs.regs[0] = id; - regs.regs[1] = reg0; - regs.regs[2] = reg1; - regs.regs[3] = reg2; - - smc_call(®s); - - return regs.regs[0]; -} - static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { u32 swap; - ulong bin_buf, flags; + ulong bin_buf; int ret; + u32 buf_lo, buf_hi; + u32 ret_payload[PAYLOAD_ARG_CNT]; if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap)) return FPGA_FAIL; @@ -224,9 +214,10 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, else bsize = bsize / 4; - flags = (u32)bsize | ((u64)bstype << 32); - - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0); + buf_lo = (u32)bin_buf; + buf_hi = upper_32_bits(bin_buf); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, + bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n"); diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 03df558..8937e99 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -42,7 +42,6 @@ obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o -obj-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o diff --git a/drivers/gpio/bcm6345_gpio.c b/drivers/gpio/bcm6345_gpio.c index 009e2fc..b9100cd 100644 --- a/drivers/gpio/bcm6345_gpio.c +++ b/drivers/gpio/bcm6345_gpio.c @@ -64,6 +64,8 @@ static int bcm6345_gpio_direction_output(struct udevice *dev, unsigned offset, { struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + bcm6345_gpio_set_value(dev, offset, value); + return bcm6345_gpio_set_direction(priv->reg_dirout, offset, 0); } diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c deleted file mode 100644 index d6c7eeb..0000000 --- a/drivers/gpio/s3c2440_gpio.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) 2012 - * Gabriel Huau - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 - -#define S3C_GPIO_CON 0x0 -#define S3C_GPIO_DAT 0x4 - -static uint32_t s3c_gpio_get_bank_addr(unsigned gpio) -{ - /* There is up to 16 pins per bank, one bank is 0x10 big. */ - uint32_t addr = gpio & ~0xf; - - if (addr >= 0x80 && addr != 0xd0) { /* Wrong GPIO bank. */ - printf("Invalid GPIO bank (bank %02x)\n", addr); - return 0xffffffff; - } - - return addr | S3C24X0_GPIO_BASE; -} - -int gpio_set_value(unsigned gpio, int value) -{ - uint32_t addr = s3c_gpio_get_bank_addr(gpio); - - if (addr == 0xffffffff) - return -EINVAL; - - if (value) - setbits_le32(addr | S3C_GPIO_DAT, 1 << (gpio & 0xf)); - else - clrbits_le32(addr | S3C_GPIO_DAT, 1 << (gpio & 0xf)); - - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - uint32_t addr = s3c_gpio_get_bank_addr(gpio); - - if (addr == 0xffffffff) - return -EINVAL; - - return !!(readl(addr | S3C_GPIO_DAT) & (1 << (gpio & 0xf))); -} - -int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -static int s3c_gpio_direction(unsigned gpio, uint8_t dir) -{ - uint32_t addr = s3c_gpio_get_bank_addr(gpio); - const uint32_t mask = 0x3 << ((gpio & 0xf) << 1); - const uint32_t dirm = dir << ((gpio & 0xf) << 1); - - if (addr == 0xffffffff) - return -EINVAL; - - clrsetbits_le32(addr | S3C_GPIO_CON, mask, dirm); - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - return s3c_gpio_direction(gpio, GPIO_INPUT); -} - -int gpio_direction_output(unsigned gpio, int value) -{ - return s3c_gpio_direction(gpio, GPIO_OUTPUT); -} diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 19769da..911563b 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -323,11 +323,6 @@ uint8_t i2c_reg_read(uint8_t addr, uint8_t reg) { uint8_t buf; -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - /* maybe it is now the time for it ... */ - i2c_set_bus_num(i2c_get_bus_num()); -#endif i2c_read(addr, reg, 1, &buf, 1); #ifdef DEBUG @@ -340,12 +335,6 @@ uint8_t i2c_reg_read(uint8_t addr, uint8_t reg) void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val) { -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - /* maybe it is now the time for it ... */ - i2c_set_bus_num(i2c_get_bus_num()); -#endif - #ifdef DEBUG printf("%s: bus=%d addr=0x%02x, reg=0x%02x, val=0x%02x\n", __func__, i2c_get_bus_num(), addr, reg, val); diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 06fe0a5..996a651 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -5,10 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* This code should work for both the S3C2400 and the S3C2410 - * as they seem to have the same I2C controller inside. - * The different address mapping is handled by the s3c24xx.h files below. - */ #include #include #include diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index c102a1a..de3758d 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -17,10 +17,6 @@ */ #include -#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ -#include -#include -#endif #if defined(CONFIG_AVR32) #include #endif @@ -94,15 +90,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = \ - ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = \ - (immap_t *)CONFIG_SYS_IMMR; -# else # define I2C_SOFT_DECLARATIONS -# endif #endif #if !defined(CONFIG_SYS_I2C_SOFT_SPEED) diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c index 7af5868..84ee015 100644 --- a/drivers/input/keyboard.c +++ b/drivers/input/keyboard.c @@ -20,7 +20,7 @@ static struct input_config config; static int kbd_read_keys(struct input_config *config) { -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \ +#if defined(CONFIG_ARCH_MPC8540) || \ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) /* no ISR is used, so received chars must be polled */ ps2ser_check(); diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index bcbe52a..0b5ce06 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -29,25 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PS2SER_BAUD 57600 -#ifdef CONFIG_MPC5xxx -#if CONFIG_PS2SERIAL == 1 -#define PSC_BASE MPC5XXX_PSC1 -#elif CONFIG_PS2SERIAL == 2 -#define PSC_BASE MPC5XXX_PSC2 -#elif CONFIG_PS2SERIAL == 3 -#define PSC_BASE MPC5XXX_PSC3 -#elif CONFIG_PS2SERIAL == 4 -#define PSC_BASE MPC5XXX_PSC4 -#elif CONFIG_PS2SERIAL == 5 -#define PSC_BASE MPC5XXX_PSC5 -#elif CONFIG_PS2SERIAL == 6 -#define PSC_BASE MPC5XXX_PSC6 -#else -#error CONFIG_PS2SERIAL must be in 1 ... 6 -#endif - -#else - #if CONFIG_PS2SERIAL == 1 #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500) #elif CONFIG_PS2SERIAL == 2 @@ -56,8 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 2 #endif -#endif /* CONFIG_MPC5xxx / other */ - static int ps2ser_getc_hw(void); static void ps2ser_interrupt(void *dev_id); @@ -68,45 +47,6 @@ static atomic_t ps2buf_cnt; static int ps2buf_in_idx; static int ps2buf_out_idx; -#ifdef CONFIG_MPC5xxx -int ps2ser_init(void) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; - unsigned long baseclk; - int div; - - /* reset PSC */ - psc->command = PSC_SEL_MODE_REG_1; - - /* select clock sources */ - psc->psc_clock_select = 0; - baseclk = (gd->arch.ipb_clk + 16) / 32; - - /* switch to UART mode */ - psc->sicr = 0; - - /* configure parity, bit length and so on */ - psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; - psc->mode = PSC_MODE_ONE_STOP; - - /* set up UART divisor */ - div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD; - psc->ctur = (div >> 8) & 0xff; - psc->ctlr = div & 0xff; - - /* disable all interrupts */ - psc->psc_imr = 0; - - /* reset and enable Rx/Tx */ - psc->command = PSC_RST_RX; - psc->command = PSC_RST_TX; - psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; - - return (0); -} - -#else - int ps2ser_init(void) { NS16550_t com_port = (NS16550_t)COM_BASE; @@ -122,45 +62,23 @@ int ps2ser_init(void) return (0); } -#endif /* CONFIG_MPC5xxx / other */ - void ps2ser_putc(int chr) { -#ifdef CONFIG_MPC5xxx - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#else NS16550_t com_port = (NS16550_t)COM_BASE; -#endif debug(">>>> 0x%02x\n", chr); -#ifdef CONFIG_MPC5xxx - while (!(psc->psc_status & PSC_SR_TXRDY)); - - psc->psc_buffer_8 = chr; -#else while ((com_port->lsr & UART_LSR_THRE) == 0); com_port->thr = chr; -#endif } static int ps2ser_getc_hw(void) { -#ifdef CONFIG_MPC5xxx - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#else NS16550_t com_port = (NS16550_t)COM_BASE; -#endif int res = -1; -#ifdef CONFIG_MPC5xxx - if (psc->psc_status & PSC_SR_RXRDY) { - res = (psc->psc_buffer_8); - } -#else if (com_port->lsr & UART_LSR_DR) { res = com_port->rbr; } -#endif return res; } @@ -206,21 +124,13 @@ int ps2ser_check(void) static void ps2ser_interrupt(void *dev_id) { -#ifdef CONFIG_MPC5xxx - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#else NS16550_t com_port = (NS16550_t)COM_BASE; -#endif int chr; int status; do { chr = ps2ser_getc_hw(); -#ifdef CONFIG_MPC5xxx - status = psc->psc_status; -#else status = com_port->lsr; -#endif if (chr < 0) continue; if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) { @@ -230,11 +140,7 @@ static void ps2ser_interrupt(void *dev_id) } else { printf ("ps2ser.c: buffer overflow\n"); } -#ifdef CONFIG_MPC5xxx - } while (status & PSC_SR_RXRDY); -#else } while (status & UART_LSR_DR); -#endif if (atomic_read(&ps2buf_cnt)) { ps2mult_callback(atomic_read(&ps2buf_cnt)); } diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ecca159..92f348f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -20,6 +20,19 @@ config ALTERA_SYSID Select this to enable a sysid for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ROCKCHIP_EFUSE + bool "Rockchip e-fuse support" + depends on MISC + help + Enable (read-only) access for the e-fuse block found in Rockchip + SoCs: accesses can either be made using byte addressing and a length + or through child-nodes that are generated based on the e-fuse map + retrieved from the DTS. + + This driver currently supports the RK3399 only, but can easily be + extended (by porting the read function from the Linux kernel sources) + to support other recent Rockchip devices. + config CMD_CROS_EC bool "Enable crosec command" depends on CROS_EC diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 4543cd6..ea64677 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -50,3 +50,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_QFW) += qfw.o +obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c index 2feb182..3c9f029 100644 --- a/drivers/misc/fsl_iim.c +++ b/drivers/misc/fsl_iim.c @@ -13,9 +13,7 @@ #include #include #include -#ifndef CONFIG_MPC512X #include -#endif #if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include #endif diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c new file mode 100644 index 0000000..423d24c --- /dev/null +++ b/drivers/misc/rockchip-efuse.c @@ -0,0 +1,161 @@ +/* + * eFuse driver for Rockchip devices + * + * Copyright 2017, Theobroma Systems Design und Consulting GmbH + * Written by Philipp Tomsich + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RK3399_A_SHIFT 16 +#define RK3399_A_MASK 0x3ff +#define RK3399_NFUSES 32 +#define RK3399_BYTES_PER_FUSE 4 +#define RK3399_STROBSFTSEL BIT(9) +#define RK3399_RSB BIT(7) +#define RK3399_PD BIT(5) +#define RK3399_PGENB BIT(3) +#define RK3399_LOAD BIT(2) +#define RK3399_STROBE BIT(1) +#define RK3399_CSB BIT(0) + +struct rockchip_efuse_regs { + u32 ctrl; /* 0x00 efuse control register */ + u32 dout; /* 0x04 efuse data out register */ + u32 rf; /* 0x08 efuse redundancy bit used register */ + u32 _rsvd0; + u32 jtag_pass; /* 0x10 JTAG password */ + u32 strobe_finish_ctrl; + /* 0x14 efuse strobe finish control register */ +}; + +struct rockchip_efuse_platdata { + void __iomem *base; + struct clk *clk; +}; + +#if defined(DEBUG) +static int dump_efuses(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + /* + * N.B.: This function is tailored towards the RK3399 and assumes that + * there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to + * be read. + */ + + struct udevice *dev; + u8 fuses[128]; + int ret; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + printf("%s: no misc-device found\n", __func__); + return 0; + } + + ret = misc_read(dev, 0, &fuses, sizeof(fuses)); + if (ret) { + printf("%s: misc_read failed\n", __func__); + return 0; + } + + printf("efuse-contents:\n"); + print_buffer(0, fuses, 1, 128, 16); + + return 0; +} + +U_BOOT_CMD( + rk3399_dump_efuses, 1, 1, dump_efuses, + "Dump the content of the efuses", + "" +); +#endif + +static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset, + void *buf, int size) +{ + struct rockchip_efuse_platdata *plat = dev_get_platdata(dev); + struct rockchip_efuse_regs *efuse = + (struct rockchip_efuse_regs *)plat->base; + + unsigned int addr_start, addr_end, addr_offset; + u32 out_value; + u8 bytes[RK3399_NFUSES * RK3399_BYTES_PER_FUSE]; + int i = 0; + u32 addr; + + addr_start = offset / RK3399_BYTES_PER_FUSE; + addr_offset = offset % RK3399_BYTES_PER_FUSE; + addr_end = DIV_ROUND_UP(offset + size, RK3399_BYTES_PER_FUSE); + + /* cap to the size of the efuse block */ + if (addr_end > RK3399_NFUSES) + addr_end = RK3399_NFUSES; + + writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, + &efuse->ctrl); + udelay(1); + for (addr = addr_start; addr < addr_end; addr++) { + setbits_le32(&efuse->ctrl, + RK3399_STROBE | (addr << RK3399_A_SHIFT)); + udelay(1); + out_value = readl(&efuse->dout); + clrbits_le32(&efuse->ctrl, RK3399_STROBE); + udelay(1); + + memcpy(&bytes[i], &out_value, RK3399_BYTES_PER_FUSE); + i += RK3399_BYTES_PER_FUSE; + } + + /* Switch to standby mode */ + writel(RK3399_PD | RK3399_CSB, &efuse->ctrl); + + memcpy(buf, bytes + addr_offset, size); + + return 0; +} + +static int rockchip_efuse_read(struct udevice *dev, int offset, + void *buf, int size) +{ + return rockchip_rk3399_efuse_read(dev, offset, buf, size); +} + +static const struct misc_ops rockchip_efuse_ops = { + .read = rockchip_efuse_read, +}; + +static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev) +{ + struct rockchip_efuse_platdata *plat = dev_get_platdata(dev); + + plat->base = (void *)devfdt_get_addr(dev); + return 0; +} + +static const struct udevice_id rockchip_efuse_ids[] = { + { .compatible = "rockchip,rk3399-efuse" }, + {} +}; + +U_BOOT_DRIVER(rockchip_efuse) = { + .name = "rockchip_efuse", + .id = UCLASS_MISC, + .of_match = rockchip_efuse_ids, + .ofdata_to_platdata = rockchip_efuse_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct rockchip_efuse_platdata), + .ops = &rockchip_efuse_ops, +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0dd4443..82b8d75 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -156,7 +156,7 @@ config MMC_OMAP36XX_PINS config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" - depends on RMOBILE + depends on ARCH_RMOBILE help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a078649..2d781c3 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_MMC_MXS) += mxsmmc.o obj-$(CONFIG_MMC_PCI) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o -obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 4dc3925..994d268 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -97,7 +97,7 @@ struct mmc *find_mmc_device(int dev_num) struct udevice *dev, *mmc_dev; int ret; - ret = blk_get_device(IF_TYPE_MMC, dev_num, &dev); + ret = blk_find_device(IF_TYPE_MMC, dev_num, &dev); if (ret) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) @@ -108,7 +108,9 @@ struct mmc *find_mmc_device(int dev_num) mmc_dev = dev_get_parent(dev); - return mmc_get_mmc_dev(mmc_dev); + struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); + + return mmc; } int get_mmc_num(void) diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c deleted file mode 100644 index faf7b83..0000000 --- a/drivers/mmc/s3c_sdi.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * S3C24xx SD/MMC driver - * - * Based on OpenMoko S3C24xx driver by Harald Welte - * - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#define S3C2440_SDICON_SDRESET (1 << 8) -#define S3C2410_SDICON_FIFORESET (1 << 1) -#define S3C2410_SDICON_CLOCKTYPE (1 << 0) - -#define S3C2410_SDICMDCON_LONGRSP (1 << 10) -#define S3C2410_SDICMDCON_WAITRSP (1 << 9) -#define S3C2410_SDICMDCON_CMDSTART (1 << 8) -#define S3C2410_SDICMDCON_SENDERHOST (1 << 6) -#define S3C2410_SDICMDCON_INDEX 0x3f - -#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12) -#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11) -#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10) -#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9) - -#define S3C2440_SDIDCON_DS_WORD (2 << 22) -#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20) -#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19) -#define S3C2410_SDIDCON_BLOCKMODE (1 << 17) -#define S3C2410_SDIDCON_WIDEBUS (1 << 16) -#define S3C2440_SDIDCON_DATSTART (1 << 14) -#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12) -#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12) -#define S3C2410_SDIDCON_BLKNUM 0x7ff - -#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8) -#define S3C2410_SDIDSTA_CRCFAIL (1 << 7) -#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6) -#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5) -#define S3C2410_SDIDSTA_XFERFINISH (1 << 4) - -#define S3C2410_SDIFSTA_TFHALF (1 << 11) -#define S3C2410_SDIFSTA_COUNTMASK 0x7f - -/* - * WARNING: We only support one SD IP block. - * NOTE: It's not likely there will ever exist an S3C24xx with two, - * at least not in this universe all right. - */ -static int wide_bus; - -static int -s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) -{ - struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi(); - uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta; - uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT; - unsigned int timeout = 100000; - int ret = 0, xfer_len, data_offset = 0; - const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL | - S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL | - S3C2410_SDIDSTA_DATATIMEOUT; - - - writel(0xffffffff, &sdi_regs->sdicsta); - writel(0xffffffff, &sdi_regs->sdidsta); - writel(0xffffffff, &sdi_regs->sdifsta); - - /* Set up data transfer (if applicable). */ - if (data) { - writel(data->blocksize, &sdi_regs->sdibsize); - - sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM; - sdidcon |= S3C2410_SDIDCON_BLOCKMODE; -#if defined(CONFIG_S3C2440) - sdidcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART; -#endif - if (wide_bus) - sdidcon |= S3C2410_SDIDCON_WIDEBUS; - - if (data->flags & MMC_DATA_READ) { - sdidcon |= S3C2410_SDIDCON_RXAFTERCMD; - sdidcon |= S3C2410_SDIDCON_XFER_RXSTART; - } else { - sdidcon |= S3C2410_SDIDCON_TXAFTERRESP; - sdidcon |= S3C2410_SDIDCON_XFER_TXSTART; - } - - writel(sdidcon, &sdi_regs->sdidcon); - } - - /* Write CMD arg. */ - writel(cmd->cmdarg, &sdi_regs->sdicarg); - - /* Write CMD index. */ - sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX; - sdiccon |= S3C2410_SDICMDCON_SENDERHOST; - sdiccon |= S3C2410_SDICMDCON_CMDSTART; - - /* Command with short response. */ - if (cmd->resp_type & MMC_RSP_PRESENT) { - sdiccon |= S3C2410_SDICMDCON_WAITRSP; - sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN; - } - - /* Command with long response. */ - if (cmd->resp_type & MMC_RSP_136) - sdiccon |= S3C2410_SDICMDCON_LONGRSP; - - /* Start the command. */ - writel(sdiccon, &sdi_regs->sdiccon); - - /* Wait for the command to complete or for response. */ - for (timeout = 100000; timeout; timeout--) { - sdicsta = readl(&sdi_regs->sdicsta); - if (sdicsta & sdicsta_wait_bit) - break; - - if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT) - timeout = 1; - } - - /* Clean the status bits. */ - setbits_le32(&sdi_regs->sdicsta, 0xf << 9); - - if (!timeout) { - puts("S3C SDI: Command timed out!\n"); - ret = -ETIMEDOUT; - goto error; - } - - /* Read out the response. */ - if (cmd->resp_type & MMC_RSP_136) { - cmd->response[0] = readl(&sdi_regs->sdirsp0); - cmd->response[1] = readl(&sdi_regs->sdirsp1); - cmd->response[2] = readl(&sdi_regs->sdirsp2); - cmd->response[3] = readl(&sdi_regs->sdirsp3); - } else { - cmd->response[0] = readl(&sdi_regs->sdirsp0); - } - - /* If there are no data, we're done. */ - if (!data) - return 0; - - xfer_len = data->blocksize * data->blocks; - - while (xfer_len > 0) { - sdidsta = readl(&sdi_regs->sdidsta); - sdifsta = readl(&sdi_regs->sdifsta); - - if (sdidsta & sdidsta_err_mask) { - printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta); - ret = -EIO; - goto error; - } - - if (data->flags & MMC_DATA_READ) { - if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4) - continue; - sdidat = readl(&sdi_regs->sdidat); - put_unaligned_le32(sdidat, data->dest + data_offset); - } else { /* Write */ - /* TX FIFO half full. */ - if (!(sdifsta & S3C2410_SDIFSTA_TFHALF)) - continue; - - /* TX FIFO is below 32b full, write. */ - sdidat = get_unaligned_le32(data->src + data_offset); - writel(sdidat, &sdi_regs->sdidat); - } - data_offset += 4; - xfer_len -= 4; - } - - /* Wait for the command to complete or for response. */ - for (timeout = 100000; timeout; timeout--) { - sdidsta = readl(&sdi_regs->sdidsta); - if (sdidsta & S3C2410_SDIDSTA_XFERFINISH) - break; - - if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT) - timeout = 1; - } - - /* Clear status bits. */ - writel(0x6f8, &sdi_regs->sdidsta); - - if (!timeout) { - puts("S3C SDI: Command timed out!\n"); - ret = -ETIMEDOUT; - goto error; - } - - writel(0, &sdi_regs->sdidcon); - - return 0; -error: - return ret; -} - -static int s3cmmc_set_ios(struct mmc *mmc) -{ - struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi(); - uint32_t divider = 0; - - wide_bus = (mmc->bus_width == 4); - - if (!mmc->clock) - return 0; - - divider = DIV_ROUND_UP(get_PCLK(), mmc->clock); - if (divider) - divider--; - - writel(divider, &sdi_regs->sdipre); - mdelay(125); - - return 0; -} - -static int s3cmmc_init(struct mmc *mmc) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi(); - - /* Start the clock. */ - setbits_le32(&clk_power->clkcon, 1 << 9); - -#if defined(CONFIG_S3C2440) - writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon); - mdelay(10); - writel(0x7fffff, &sdi_regs->sdidtimer); -#else - writel(0xffff, &sdi_regs->sdidtimer); -#endif - writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize); - writel(0x0, &sdi_regs->sdiimsk); - - writel(S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE, - &sdi_regs->sdicon); - - mdelay(125); - - return 0; -} - -struct s3cmmc_priv { - struct mmc_config cfg; - int (*getcd)(struct mmc *); - int (*getwp)(struct mmc *); -}; - -static int s3cmmc_getcd(struct mmc *mmc) -{ - struct s3cmmc_priv *priv = mmc->priv; - if (priv->getcd) - return priv->getcd(mmc); - else - return 0; -} - -static int s3cmmc_getwp(struct mmc *mmc) -{ - struct s3cmmc_priv *priv = mmc->priv; - if (priv->getwp) - return priv->getwp(mmc); - else - return 0; -} - -static const struct mmc_ops s3cmmc_ops = { - .send_cmd = s3cmmc_send_cmd, - .set_ios = s3cmmc_set_ios, - .init = s3cmmc_init, - .getcd = s3cmmc_getcd, - .getwp = s3cmmc_getwp, -}; - -int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *), - int (*getwp)(struct mmc *)) -{ - struct s3cmmc_priv *priv; - struct mmc *mmc; - struct mmc_config *cfg; - - priv = calloc(1, sizeof(*priv)); - if (!priv) - return -ENOMEM; - cfg = &priv->cfg; - - cfg->name = "S3C MMC"; - cfg->ops = &s3cmmc_ops; - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS; - cfg->f_min = 400000; - cfg->f_max = get_PCLK() / 2; - cfg->b_max = 0x80; - -#if defined(CONFIG_S3C2410) - /* - * S3C2410 has some bug that prevents reliable - * operation at higher speed - */ - cfg->f_max /= 2; -#endif - - mmc = mmc_create(cfg, priv); - if (!mmc) { - free(priv); - return -ENOMEM; - } - - return 0; -} diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index 25224e2..d181b63 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -3,7 +3,7 @@ * * SD/MMC driver for Renesas rmobile ARM SoCs. * - * Copyright (C) 2011,2013-2014 Renesas Electronics Corporation + * Copyright (C) 2011,2013-2017 Renesas Electronics Corporation * Copyright (C) 2014 Nobuhiro Iwamatsu * Copyright (C) 2008-2009 Renesas Solutions Corp. * @@ -29,6 +29,17 @@ struct sh_sdhi_host { unsigned char sd_error; unsigned char detect_waiting; }; + +static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val) +{ + writeq(val, host->addr + (reg << host->bus_shift)); +} + +static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg) +{ + return readq(host->addr + (reg << host->bus_shift)); +} + static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val) { writew(val, host->addr + (reg << host->bus_shift)); @@ -261,6 +272,7 @@ static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data) long time; unsigned short blocksize, i; unsigned short *p = (unsigned short *)data->dest; + u64 *q = (u64 *)data->dest; if ((unsigned long)p & 0x00000001) { debug(DRIVER_NAME": %s: The data pointer is unaligned.", @@ -281,8 +293,12 @@ static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data) host->wait_int = 0; blocksize = sh_sdhi_readw(host, SDHI_SIZE); - for (i = 0; i < blocksize / 2; i++) - *p++ = sh_sdhi_readw(host, SDHI_BUF0); + if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) + for (i = 0; i < blocksize / 8; i++) + *q++ = sh_sdhi_readq(host, SDHI_BUF0); + else + for (i = 0; i < blocksize / 2; i++) + *p++ = sh_sdhi_readw(host, SDHI_BUF0); time = sh_sdhi_wait_interrupt_flag(host); if (time == 0 || host->sd_error != 0) @@ -297,6 +313,7 @@ static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data) long time; unsigned short blocksize, i, sec; unsigned short *p = (unsigned short *)data->dest; + u64 *q = (u64 *)data->dest; if ((unsigned long)p & 0x00000001) { debug(DRIVER_NAME": %s: The data pointer is unaligned.", @@ -319,8 +336,12 @@ static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data) host->wait_int = 0; blocksize = sh_sdhi_readw(host, SDHI_SIZE); - for (i = 0; i < blocksize / 2; i++) - *p++ = sh_sdhi_readw(host, SDHI_BUF0); + if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) + for (i = 0; i < blocksize / 8; i++) + *q++ = sh_sdhi_readq(host, SDHI_BUF0); + else + for (i = 0; i < blocksize / 2; i++) + *p++ = sh_sdhi_readw(host, SDHI_BUF0); } return 0; @@ -332,6 +353,7 @@ static int sh_sdhi_single_write(struct sh_sdhi_host *host, long time; unsigned short blocksize, i; const unsigned short *p = (const unsigned short *)data->src; + const u64 *q = (const u64 *)data->src; if ((unsigned long)p & 0x00000001) { debug(DRIVER_NAME": %s: The data pointer is unaligned.", @@ -356,8 +378,12 @@ static int sh_sdhi_single_write(struct sh_sdhi_host *host, host->wait_int = 0; blocksize = sh_sdhi_readw(host, SDHI_SIZE); - for (i = 0; i < blocksize / 2; i++) - sh_sdhi_writew(host, SDHI_BUF0, *p++); + if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) + for (i = 0; i < blocksize / 8; i++) + sh_sdhi_writeq(host, SDHI_BUF0, *q++); + else + for (i = 0; i < blocksize / 2; i++) + sh_sdhi_writew(host, SDHI_BUF0, *p++); time = sh_sdhi_wait_interrupt_flag(host); if (time == 0 || host->sd_error != 0) @@ -372,6 +398,7 @@ static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data) long time; unsigned short i, sec, blocksize; const unsigned short *p = (const unsigned short *)data->src; + const u64 *q = (const u64 *)data->src; debug("%s: blocks = %d, blocksize = %d\n", __func__, data->blocks, data->blocksize); @@ -388,8 +415,12 @@ static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data) host->wait_int = 0; blocksize = sh_sdhi_readw(host, SDHI_SIZE); - for (i = 0; i < blocksize / 2; i++) - sh_sdhi_writew(host, SDHI_BUF0, *p++); + if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) + for (i = 0; i < blocksize / 8; i++) + sh_sdhi_writeq(host, SDHI_BUF0, *q++); + else + for (i = 0; i < blocksize / 2; i++) + sh_sdhi_writew(host, SDHI_BUF0, *p++); } return 0; @@ -458,6 +489,13 @@ static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host, else /* SD_SWITCH */ opc = SDHI_SD_SWITCH; break; + case MMC_CMD_SEND_OP_COND: + opc = SDHI_MMC_SEND_OP_COND; + break; + case MMC_CMD_SEND_EXT_CSD: + if (data) + opc = SDHI_MMC_SEND_EXT_CSD; + break; default: break; } @@ -482,6 +520,7 @@ static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host, case MMC_CMD_READ_SINGLE_BLOCK: case SDHI_SD_APP_SEND_SCR: case SDHI_SD_SWITCH: /* SD_SWITCH */ + case SDHI_MMC_SEND_EXT_CSD: ret = sh_sdhi_single_read(host, data); break; default: @@ -546,8 +585,6 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, break; } - sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK)); - host->wait_int = 0; sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK)); @@ -557,6 +594,8 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, INFO2M_RESP_TIMEOUT | INFO2M_ILA) & sh_sdhi_readw(host, SDHI_INFO2_MASK)); + sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK)); + time = sh_sdhi_wait_interrupt_flag(host); if (!time) return sh_sdhi_error_manage(host); @@ -617,12 +656,18 @@ static int sh_sdhi_set_ios(struct mmc *mmc) if (ret) return -EINVAL; - if (mmc->bus_width == 4) - sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 & - sh_sdhi_readw(host, SDHI_OPTION)); + if (mmc->bus_width == 8) + sh_sdhi_writew(host, SDHI_OPTION, + OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M & + sh_sdhi_readw(host, SDHI_OPTION))); + else if (mmc->bus_width == 4) + sh_sdhi_writew(host, SDHI_OPTION, + OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M & + sh_sdhi_readw(host, SDHI_OPTION))); else - sh_sdhi_writew(host, SDHI_OPTION, OPT_BUS_WIDTH_1 | - sh_sdhi_readw(host, SDHI_OPTION)); + sh_sdhi_writew(host, SDHI_OPTION, + OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M & + sh_sdhi_readw(host, SDHI_OPTION))); debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); @@ -653,6 +698,19 @@ static const struct mmc_ops sh_sdhi_ops = { .init = sh_sdhi_initialize, }; +#ifdef CONFIG_RCAR_GEN3 +static struct mmc_config sh_sdhi_cfg = { + .name = DRIVER_NAME, + .ops = &sh_sdhi_ops, + .f_min = CLKDEV_INIT, + .f_max = CLKDEV_HS_DATA, + .voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS | + MMC_MODE_HS_52MHz, + .part_type = PART_TYPE_DOS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; +#else static struct mmc_config sh_sdhi_cfg = { .name = DRIVER_NAME, .ops = &sh_sdhi_ops, @@ -663,6 +721,7 @@ static struct mmc_config sh_sdhi_cfg = { .part_type = PART_TYPE_DOS, .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, }; +#endif int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) { @@ -687,7 +746,9 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) host->addr = addr; host->quirks = quirks; - if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) + if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) + host->bus_shift = 2; + else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) host->bus_shift = 1; return ret; diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 338e42b..7d945a1 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -438,7 +438,7 @@ static int tegra_mmc_set_ios(struct udevice *dev) else if (mmc->bus_width == 4) ctrl |= (1 << 1); else - ctrl &= ~(1 << 1); + ctrl &= ~(1 << 1 | 1 << 5); writeb(ctrl, &priv->reg->hostctl); debug("mmc_set_ios: hostctl = %08X\n", ctrl); diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c index 3fb6ed6..2d2c318 100644 --- a/drivers/mtd/dataflash.c +++ b/drivers/mtd/dataflash.c @@ -49,7 +49,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; - found[i] += dfcode;; + found[i] += dfcode; break; case AT45DB081: @@ -61,7 +61,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; - found[i] += dfcode;; + found[i] += dfcode; break; case AT45DB161: @@ -73,7 +73,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; - found[i] += dfcode;; + found[i] += dfcode; break; case AT45DB321: @@ -85,7 +85,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; - found[i] += dfcode;; + found[i] += dfcode; break; case AT45DB642: @@ -97,7 +97,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; - found[i] += dfcode;; + found[i] += dfcode; break; case AT45DB128: @@ -109,7 +109,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.DataFlash_state = IDLE; dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; - found[i] += dfcode;; + found[i] += dfcode; break; default: diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index a7b76f4..ce8ba99 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -33,11 +33,11 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES used to preserve the bad block marker in the OOB area. config NAND_VF610_NFC - bool "Support for Freescale NFC for VF610/MPC5125" + bool "Support for Freescale NFC for VF610" select SYS_NAND_SELF_INIT help Enables support for NAND Flash Controller on some Freescale - processors like the VF610, MPC5125, MCF54418 or Kinetis K70. + processors like the VF610, MCF54418 or Kinetis K70. The driver supports a maximum 2k page size. The driver currently does not support hardware ECC. diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 82358f6..c3d4a99 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -53,13 +53,11 @@ obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o -obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_NDFC) += ndfc.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o -obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c deleted file mode 100644 index 7faabdd..0000000 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ /dev/null @@ -1,656 +0,0 @@ -/* - * Copyright 2004-2008 Freescale Semiconductor, Inc. - * Copyright 2009 Semihalf. - * (C) Copyright 2009 Stefan Roese - * - * Based on original driver from Freescale Semiconductor - * written by John Rigby on basis - * of drivers/mtd/nand/mxc_nand.c. Reworked and extended - * Piotr Ziecik . - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DRV_NAME "mpc5121_nfc" - -/* Timeouts */ -#define NFC_RESET_TIMEOUT 1000 /* 1 ms */ -#define NFC_TIMEOUT 2000 /* 2000 us */ - -/* Addresses for NFC MAIN RAM BUFFER areas */ -#define NFC_MAIN_AREA(n) ((n) * 0x200) - -/* Addresses for NFC SPARE BUFFER areas */ -#define NFC_SPARE_BUFFERS 8 -#define NFC_SPARE_LEN 0x40 -#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN)) - -/* MPC5121 NFC registers */ -#define NFC_BUF_ADDR 0x1E04 -#define NFC_FLASH_ADDR 0x1E06 -#define NFC_FLASH_CMD 0x1E08 -#define NFC_CONFIG 0x1E0A -#define NFC_ECC_STATUS1 0x1E0C -#define NFC_ECC_STATUS2 0x1E0E -#define NFC_SPAS 0x1E10 -#define NFC_WRPROT 0x1E12 -#define NFC_NF_WRPRST 0x1E18 -#define NFC_CONFIG1 0x1E1A -#define NFC_CONFIG2 0x1E1C -#define NFC_UNLOCKSTART_BLK0 0x1E20 -#define NFC_UNLOCKEND_BLK0 0x1E22 -#define NFC_UNLOCKSTART_BLK1 0x1E24 -#define NFC_UNLOCKEND_BLK1 0x1E26 -#define NFC_UNLOCKSTART_BLK2 0x1E28 -#define NFC_UNLOCKEND_BLK2 0x1E2A -#define NFC_UNLOCKSTART_BLK3 0x1E2C -#define NFC_UNLOCKEND_BLK3 0x1E2E - -/* Bit Definitions: NFC_BUF_ADDR */ -#define NFC_RBA_MASK (7 << 0) -#define NFC_ACTIVE_CS_SHIFT 5 -#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT) - -/* Bit Definitions: NFC_CONFIG */ -#define NFC_BLS_UNLOCKED (1 << 1) - -/* Bit Definitions: NFC_CONFIG1 */ -#define NFC_ECC_4BIT (1 << 0) -#define NFC_FULL_PAGE_DMA (1 << 1) -#define NFC_SPARE_ONLY (1 << 2) -#define NFC_ECC_ENABLE (1 << 3) -#define NFC_INT_MASK (1 << 4) -#define NFC_BIG_ENDIAN (1 << 5) -#define NFC_RESET (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) -#define NFC_PPB_32 (0 << 9) -#define NFC_PPB_64 (1 << 9) -#define NFC_PPB_128 (2 << 9) -#define NFC_PPB_256 (3 << 9) -#define NFC_PPB_MASK (3 << 9) -#define NFC_FULL_PAGE_INT (1 << 11) - -/* Bit Definitions: NFC_CONFIG2 */ -#define NFC_COMMAND (1 << 0) -#define NFC_ADDRESS (1 << 1) -#define NFC_INPUT (1 << 2) -#define NFC_OUTPUT (1 << 3) -#define NFC_ID (1 << 4) -#define NFC_STATUS (1 << 5) -#define NFC_CMD_FAIL (1 << 15) -#define NFC_INT (1 << 15) - -/* Bit Definitions: NFC_WRPROT */ -#define NFC_WPC_LOCK_TIGHT (1 << 0) -#define NFC_WPC_LOCK (1 << 1) -#define NFC_WPC_UNLOCK (1 << 2) - -struct mpc5121_nfc_prv { - struct nand_chip chip; - int irq; - void __iomem *regs; - struct clk *clk; - uint column; - int spareonly; - int chipsel; -}; - -int mpc5121_nfc_chip = 0; - -static void mpc5121_nfc_done(struct mtd_info *mtd); - -/* Read NFC register */ -static inline u16 nfc_read(struct mtd_info *mtd, uint reg) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); - - return in_be16(prv->regs + reg); -} - -/* Write NFC register */ -static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); - - out_be16(prv->regs + reg, val); -} - -/* Set bits in NFC register */ -static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits) -{ - nfc_write(mtd, reg, nfc_read(mtd, reg) | bits); -} - -/* Clear bits in NFC register */ -static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits) -{ - nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits); -} - -/* Invoke address cycle */ -static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr) -{ - nfc_write(mtd, NFC_FLASH_ADDR, addr); - nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS); - mpc5121_nfc_done(mtd); -} - -/* Invoke command cycle */ -static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd) -{ - nfc_write(mtd, NFC_FLASH_CMD, cmd); - nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND); - mpc5121_nfc_done(mtd); -} - -/* Send data from NFC buffers to NAND flash */ -static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd) -{ - nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); - nfc_write(mtd, NFC_CONFIG2, NFC_INPUT); - mpc5121_nfc_done(mtd); -} - -/* Receive data from NAND flash */ -static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd) -{ - nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); - nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT); - mpc5121_nfc_done(mtd); -} - -/* Receive ID from NAND flash */ -static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd) -{ - nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); - nfc_write(mtd, NFC_CONFIG2, NFC_ID); - mpc5121_nfc_done(mtd); -} - -/* Receive status from NAND flash */ -static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd) -{ - nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); - nfc_write(mtd, NFC_CONFIG2, NFC_STATUS); - mpc5121_nfc_done(mtd); -} - -static void mpc5121_nfc_done(struct mtd_info *mtd) -{ - int max_retries = NFC_TIMEOUT; - - while (1) { - max_retries--; - if (nfc_read(mtd, NFC_CONFIG2) & NFC_INT) - break; - udelay(1); - } - - if (max_retries <= 0) - printk(KERN_WARNING DRV_NAME - ": Timeout while waiting for completion.\n"); -} - -/* Do address cycle(s) */ -static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - u32 pagemask = chip->pagemask; - - if (column != -1) { - mpc5121_nfc_send_addr(mtd, column); - if (mtd->writesize > 512) - mpc5121_nfc_send_addr(mtd, column >> 8); - } - - if (page != -1) { - do { - mpc5121_nfc_send_addr(mtd, page & 0xFF); - page >>= 8; - pagemask >>= 8; - } while (pagemask); - } -} - -/* Control chip select signals */ - -/* - * Selecting the active device: - * - * This is different than the linux version. Switching between chips - * is done via board_nand_select_device(). The Linux select_chip - * function used here in U-Boot has only 2 valid chip numbers: - * 0 select - * -1 deselect - */ - -/* - * Implement it as a weak default, so that boards with a specific - * chip-select routine can use their own function. - */ -void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) -{ - if (chip < 0) { - nfc_clear(mtd, NFC_CONFIG1, NFC_CE); - return; - } - - nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK); - nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) & - NFC_ACTIVE_CS_MASK); - nfc_set(mtd, NFC_CONFIG1, NFC_CE); -} -void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) - __attribute__((weak, alias("__mpc5121_nfc_select_chip"))); - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - /* - * Only save this chip number in global variable here. This - * will be used later in mpc5121_nfc_select_chip(). - */ - mpc5121_nfc_chip = chip; -} - -/* Read NAND Ready/Busy signal */ -static int mpc5121_nfc_dev_ready(struct mtd_info *mtd) -{ - /* - * NFC handles ready/busy signal internally. Therefore, this function - * always returns status as ready. - */ - return 1; -} - -/* Write command to NAND flash */ -static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command, - int column, int page) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); - - prv->column = (column >= 0) ? column : 0; - prv->spareonly = 0; - - switch (command) { - case NAND_CMD_PAGEPROG: - mpc5121_nfc_send_prog_page(mtd); - break; - /* - * NFC does not support sub-page reads and writes, - * so emulate them using full page transfers. - */ - case NAND_CMD_READ0: - column = 0; - break; - - case NAND_CMD_READ1: - prv->column += 256; - command = NAND_CMD_READ0; - column = 0; - break; - - case NAND_CMD_READOOB: - prv->spareonly = 1; - command = NAND_CMD_READ0; - column = 0; - break; - - case NAND_CMD_SEQIN: - mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page); - column = 0; - break; - - case NAND_CMD_ERASE1: - case NAND_CMD_ERASE2: - case NAND_CMD_READID: - case NAND_CMD_STATUS: - case NAND_CMD_RESET: - break; - - default: - return; - } - - mpc5121_nfc_send_cmd(mtd, command); - mpc5121_nfc_addr_cycle(mtd, column, page); - - switch (command) { - case NAND_CMD_READ0: - if (mtd->writesize > 512) - mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART); - mpc5121_nfc_send_read_page(mtd); - break; - - case NAND_CMD_READID: - mpc5121_nfc_send_read_id(mtd); - break; - - case NAND_CMD_STATUS: - mpc5121_nfc_send_read_status(mtd); - if (chip->options & NAND_BUSWIDTH_16) - prv->column = 1; - else - prv->column = 0; - break; - } -} - -/* Copy data from/to NFC spare buffers. */ -static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset, - u8 * buffer, uint size, int wr) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand); - uint o, s, sbsize, blksize; - - /* - * NAND spare area is available through NFC spare buffers. - * The NFC divides spare area into (page_size / 512) chunks. - * Each chunk is placed into separate spare memory area, using - * first (spare_size / num_of_chunks) bytes of the buffer. - * - * For NAND device in which the spare area is not divided fully - * by the number of chunks, number of used bytes in each spare - * buffer is rounded down to the nearest even number of bytes, - * and all remaining bytes are added to the last used spare area. - * - * For more information read section 26.6.10 of MPC5121e - * Microcontroller Reference Manual, Rev. 3. - */ - - /* Calculate number of valid bytes in each spare buffer */ - sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1; - - while (size) { - /* Calculate spare buffer number */ - s = offset / sbsize; - if (s > NFC_SPARE_BUFFERS - 1) - s = NFC_SPARE_BUFFERS - 1; - - /* - * Calculate offset to requested data block in selected spare - * buffer and its size. - */ - o = offset - (s * sbsize); - blksize = min(sbsize - o, size); - - if (wr) - memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o, - buffer, blksize); - else - memcpy_fromio(buffer, - prv->regs + NFC_SPARE_AREA(s) + o, - blksize); - - buffer += blksize; - offset += blksize; - size -= blksize; - }; -} - -/* Copy data from/to NFC main and spare buffers */ -static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len, - int wr) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); - uint c = prv->column; - uint l; - - /* Handle spare area access */ - if (prv->spareonly || c >= mtd->writesize) { - /* Calculate offset from beginning of spare area */ - if (c >= mtd->writesize) - c -= mtd->writesize; - - prv->column += len; - mpc5121_nfc_copy_spare(mtd, c, buf, len, wr); - return; - } - - /* - * Handle main area access - limit copy length to prevent - * crossing main/spare boundary. - */ - l = min((uint) len, mtd->writesize - c); - prv->column += l; - - if (wr) - memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l); - else - memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l); - - /* Handle crossing main/spare boundary */ - if (l != len) { - buf += l; - len -= l; - mpc5121_nfc_buf_copy(mtd, buf, len, wr); - } -} - -/* Read data from NFC buffers */ -static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char * buf, int len) -{ - mpc5121_nfc_buf_copy(mtd, buf, len, 0); -} - -/* Write data to NFC buffers */ -static void mpc5121_nfc_write_buf(struct mtd_info *mtd, - const u_char * buf, int len) -{ - mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1); -} - -/* Read byte from NFC buffers */ -static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd) -{ - u8 tmp; - - mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp)); - - return tmp; -} - -/* Read word from NFC buffers */ -static u16 mpc5121_nfc_read_word(struct mtd_info *mtd) -{ - u16 tmp; - - mpc5121_nfc_read_buf(mtd, (u_char *) & tmp, sizeof(tmp)); - - return tmp; -} - -/* - * Read NFC configuration from Reset Config Word - * - * NFC is configured during reset in basis of information stored - * in Reset Config Word. There is no other way to set NAND block - * size, spare size and bus width. - */ -static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - struct nand_chip *chip = mtd_to_nand(mtd); - uint rcw_pagesize = 0; - uint rcw_sparesize = 0; - uint rcw_width; - uint rcwh; - uint romloc, ps; - - rcwh = in_be32(&(im->reset.rcwh)); - - /* Bit 6: NFC bus width */ - rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1; - - /* Bit 7: NFC Page/Spare size */ - ps = (rcwh >> 7) & 0x1; - - /* Bits [22:21]: ROM Location */ - romloc = (rcwh >> 21) & 0x3; - - /* Decode RCW bits */ - switch ((ps << 2) | romloc) { - case 0x00: - case 0x01: - rcw_pagesize = 512; - rcw_sparesize = 16; - break; - case 0x02: - case 0x03: - rcw_pagesize = 4096; - rcw_sparesize = 128; - break; - case 0x04: - case 0x05: - rcw_pagesize = 2048; - rcw_sparesize = 64; - break; - case 0x06: - case 0x07: - rcw_pagesize = 4096; - rcw_sparesize = 218; - break; - } - - mtd->writesize = rcw_pagesize; - mtd->oobsize = rcw_sparesize; - if (rcw_width == 2) - chip->options |= NAND_BUSWIDTH_16; - - debug(KERN_NOTICE DRV_NAME ": Configured for " - "%u-bit NAND, page size %u with %u spare.\n", - rcw_width * 8, rcw_pagesize, rcw_sparesize); - return 0; -} - -int board_nand_init(struct nand_chip *chip) -{ - struct mpc5121_nfc_prv *prv; - struct mtd_info *mtd; - int resettime = 0; - int retval = 0; - int rev; - - /* - * Check SoC revision. This driver supports only NFC - * in MPC5121 revision 2. - */ - rev = (mfspr(SPRN_SVR) >> 4) & 0xF; - if (rev != 2) { - printk(KERN_ERR DRV_NAME - ": SoC revision %u is not supported!\n", rev); - return -ENXIO; - } - - prv = malloc(sizeof(*prv)); - if (!prv) { - printk(KERN_ERR DRV_NAME ": Memory exhausted!\n"); - return -ENOMEM; - } - - mtd = &chip->mtd; - nand_set_controller_data(chip, prv); - - /* Read NFC configuration from Reset Config Word */ - retval = mpc5121_nfc_read_hw_config(mtd); - if (retval) { - printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n"); - return retval; - } - - prv->regs = (void __iomem *)CONFIG_SYS_NAND_BASE; - chip->dev_ready = mpc5121_nfc_dev_ready; - chip->cmdfunc = mpc5121_nfc_command; - chip->read_byte = mpc5121_nfc_read_byte; - chip->read_word = mpc5121_nfc_read_word; - chip->read_buf = mpc5121_nfc_read_buf; - chip->write_buf = mpc5121_nfc_write_buf; - chip->select_chip = mpc5121_nfc_select_chip; - chip->bbt_options = NAND_BBT_USE_FLASH; - chip->ecc.mode = NAND_ECC_SOFT; - - /* Reset NAND Flash controller */ - nfc_set(mtd, NFC_CONFIG1, NFC_RESET); - while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) { - if (resettime++ >= NFC_RESET_TIMEOUT) { - printk(KERN_ERR DRV_NAME - ": Timeout while resetting NFC!\n"); - retval = -EINVAL; - goto error; - } - - udelay(1); - } - - /* Enable write to NFC memory */ - nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED); - - /* Enable write to all NAND pages */ - nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000); - nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF); - nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK); - - /* - * Setup NFC: - * - Big Endian transfers, - * - Interrupt after full page read/write. - */ - nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK | - NFC_FULL_PAGE_INT); - - /* Set spare area size */ - nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1); - - /* Detect NAND chips */ - if (nand_scan(mtd, 1)) { - printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n"); - retval = -ENXIO; - goto error; - } - - /* Set erase block size */ - switch (mtd->erasesize / mtd->writesize) { - case 32: - nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32); - break; - - case 64: - nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64); - break; - - case 128: - nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128); - break; - - case 256: - nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256); - break; - - default: - printk(KERN_ERR DRV_NAME ": Unsupported NAND flash!\n"); - retval = -ENXIO; - goto error; - } - - return 0; -error: - return retval; -} diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c deleted file mode 100644 index dd742a6..0000000 --- a/drivers/mtd/nand/s3c2410_nand.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * (C) Copyright 2006 OpenMoko, Inc. - * Author: Harald Welte - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include -#include -#include - -#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) - -#define S3C2410_ADDR_NALE 4 -#define S3C2410_ADDR_NCLE 8 - -#ifdef CONFIG_NAND_SPL - -/* in the early stage of NAND flash booting, printf() is not available */ -#define printf(fmt, args...) - -static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd_to_nand(mtd); - - for (i = 0; i < len; i++) - buf[i] = readb(this->IO_ADDR_R); -} -#endif - -static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); - - debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong)nand; - - if (!(ctrl & NAND_CLE)) - IO_ADDR_W |= S3C2410_ADDR_NCLE; - if (!(ctrl & NAND_ALE)) - IO_ADDR_W |= S3C2410_ADDR_NALE; - - chip->IO_ADDR_W = (void *)IO_ADDR_W; - - if (ctrl & NAND_NCE) - writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, - &nand->nfconf); - else - writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, - &nand->nfconf); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, chip->IO_ADDR_W); -} - -static int s3c24x0_dev_ready(struct mtd_info *mtd) -{ - struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); - debug("dev_ready\n"); - return readl(&nand->nfstat) & 0x01; -} - -#ifdef CONFIG_S3C2410_NAND_HWECC -void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode) -{ - struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); - debug("s3c24x0_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); -} - -static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, - u_char *ecc_code) -{ - struct s3c24x0_nand *nand = s3c24x0_get_base_nand(); - ecc_code[0] = readb(&nand->nfecc); - ecc_code[1] = readb(&nand->nfecc + 1); - ecc_code[2] = readb(&nand->nfecc + 2); - debug("s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); - - return 0; -} - -static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - if (read_ecc[0] == calc_ecc[0] && - read_ecc[1] == calc_ecc[1] && - read_ecc[2] == calc_ecc[2]) - return 0; - - printf("s3c24x0_nand_correct_data: not implemented\n"); - return -EBADMSG; -} -#endif - -int board_nand_init(struct nand_chip *nand) -{ - u_int32_t cfg; - u_int8_t tacls, twrph0, twrph1; - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand(); - - debug("board_nand_init()\n"); - - writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); - - /* initialize hardware */ -#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING) - tacls = CONFIG_S3C24XX_TACLS; - twrph0 = CONFIG_S3C24XX_TWRPH0; - twrph1 = CONFIG_S3C24XX_TWRPH1; -#else - tacls = 4; - twrph0 = 8; - twrph1 = 8; -#endif - - cfg = S3C2410_NFCONF_EN; - cfg |= S3C2410_NFCONF_TACLS(tacls - 1); - cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); - cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->nfconf); - - /* initialize nand_chip data structure */ - nand->IO_ADDR_R = (void *)&nand_reg->nfdata; - nand->IO_ADDR_W = (void *)&nand_reg->nfdata; - - nand->select_chip = NULL; - - /* read_buf and write_buf are default */ - /* read_byte and write_byte are default */ -#ifdef CONFIG_NAND_SPL - nand->read_buf = nand_read_buf; -#endif - - /* hwcontrol always must be implemented */ - nand->cmd_ctrl = s3c24x0_hwcontrol; - - nand->dev_ready = s3c24x0_dev_ready; - -#ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c24x0_nand_enable_hwecc; - nand->ecc.calculate = s3c24x0_nand_calculate_ecc; - nand->ecc.correct = s3c24x0_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.strength = 1; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif - -#ifdef CONFIG_S3C2410_NAND_BBT - nand->bbt_options |= NAND_BBT_USE_FLASH; -#endif - - debug("end of nand_init\n"); - - return 0; -} diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 5ca0a71..5700859 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -42,6 +42,13 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SF_DUAL_FLASH + bool "SPI DUAL flash memory support" + depends on SPI_FLASH + help + Enable this option to support two flash memories connected to a single + controller. Currently Xilinx Zynq qspi supports this. + if SPI_FLASH config SPI_FLASH_ATMEL diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index ca11396..e759339 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -67,7 +67,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0aaac6b..03ed224 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,8 +39,6 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o -obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o -obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 86dc13d..6e31244 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include "qbman_portal.h" /* QBMan portal management command codes */ diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 15a3ce0..628b420 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -475,7 +475,7 @@ static void fec_halt(struct eth_device *dev) /* Disable DMA tasks */ MCD_killDma(info->txTask); - MCD_killDma(info->rxTask);; + MCD_killDma(info->rxTask); /* Disable the Ethernet Controller */ fecp->ecr &= ~FEC_ECR_ETHER_EN; diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c deleted file mode 100644 index b3746fb..0000000 --- a/drivers/net/mpc512x_fec.c +++ /dev/null @@ -1,769 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Derived from the MPC8xx FEC driver. - * Adapted for MPC512x by Grzegorz Bernacki - */ - -#include -#include -#include -#include -#include -#include -#include "mpc512x_fec.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define DEBUG 0 - -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, - int regAddr); -int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, - int regAddr, u16 data); -int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); - -static uchar rx_buff[FEC_BUFFER_SIZE]; -static int rx_buff_idx = 0; - -/********************************************************************/ -#if (DEBUG & 0x2) -static void mpc512x_fec_phydump (char *devname) -{ - u16 phyStatus, i; - u8 phyAddr = CONFIG_PHY_ADDR; - u8 reg_mask[] = { - /* regs to print: 0...8, 21,27,31 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, - }; - - for (i = 0; i < 32; i++) { - if (reg_mask[i]) { - miiphy_read (devname, phyAddr, i, &phyStatus); - printf ("Mii reg %d: 0x%04x\n", i, phyStatus); - } - } -} -#endif - -/********************************************************************/ -static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) -{ - int ix; - - /* - * Receive BDs init - */ - for (ix = 0; ix < FEC_RBD_NUM; ix++) { - fec->bdBase->rbd[ix].dataPointer = - (u32)&fec->bdBase->recv_frames[ix]; - fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY; - fec->bdBase->rbd[ix].dataLength = 0; - } - - /* - * have the last RBD to close the ring - */ - fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP; - fec->rbdIndex = 0; - - /* - * Trasmit BDs init - */ - for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->bdBase->tbd[ix].status = 0; - } - - /* - * Have the last TBD to close the ring - */ - fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; - - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; - - return 0; -} - -/********************************************************************/ -static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd) -{ - /* - * Reset buffer descriptor as empty - */ - if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) - pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); - else - pRbd->status = FEC_RBD_EMPTY; - - pRbd->dataLength = 0; - - /* - * Increment BD count - */ - fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; - - /* - * Now, we have an empty RxBD, notify FEC - * Set Descriptor polling active - */ - out_be32(&fec->eth->r_des_active, 0x01000000); -} - -/********************************************************************/ -static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) -{ - volatile FEC_TBD *pUsedTbd; - -#if (DEBUG & 0x1) - printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", - fec->cleanTbdNum, fec->usedTbdIndex); -#endif - - /* - * process all the consumed TBDs - */ - while (fec->cleanTbdNum < FEC_TBD_NUM) { - pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex]; - if (pUsedTbd->status & FEC_TBD_READY) { -#if (DEBUG & 0x20) - printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex); -#endif - return; - } - - /* - * clean this buffer descriptor - */ - if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) - pUsedTbd->status = FEC_TBD_WRAP; - else - pUsedTbd->status = 0; - - /* - * update some indeces for a correct handling of the TBD ring - */ - fec->cleanTbdNum++; - fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; - } -} - -/********************************************************************/ -static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac) -{ - u8 currByte; /* byte for which to compute the CRC */ - int byte; /* loop - counter */ - int bit; /* loop - counter */ - u32 crc = 0xffffffff; /* initial value */ - - /* - * The algorithm used is the following: - * we loop on each of the six bytes of the provided address, - * and we compute the CRC by left-shifting the previous - * value by one position, so that each bit in the current - * byte of the address may contribute the calculation. If - * the latter and the MSB in the CRC are different, then - * the CRC value so computed is also ex-ored with the - * "polynomium generator". The current byte of the address - * is also shifted right by one bit at each iteration. - * This is because the CRC generatore in hardware is implemented - * as a shift-register with as many ex-ores as the radixes - * in the polynomium. This suggests that we represent the - * polynomiumm itself as a 32-bit constant. - */ - for (byte = 0; byte < 6; byte++) { - currByte = mac[byte]; - for (bit = 0; bit < 8; bit++) { - if ((currByte & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - currByte >>= 1; - } - } - - crc = crc >> 26; - - /* - * Set individual hash table register - */ - if (crc >= 32) { - out_be32(&fec->eth->iaddr1, (1 << (crc - 32))); - out_be32(&fec->eth->iaddr2, 0); - } else { - out_be32(&fec->eth->iaddr1, 0); - out_be32(&fec->eth->iaddr2, (1 << crc)); - } - - /* - * Set physical address - */ - out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) + - (mac[2] << 8) + mac[3]); - out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) + - 0x8808); -} - -/********************************************************************/ -static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) -{ - mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; - -#if (DEBUG & 0x1) - printf ("mpc512x_fec_init... Begin\n"); -#endif - - mpc512x_fec_set_hwaddr (fec, dev->enetaddr); - out_be32(&fec->eth->gaddr1, 0x00000000); - out_be32(&fec->eth->gaddr2, 0x00000000); - - mpc512x_fec_init_phy (dev, bis); - - /* Set interrupt mask register */ - out_be32(&fec->eth->imask, 0x00000000); - - /* Clear FEC-Lite interrupt event register(IEVENT) */ - out_be32(&fec->eth->ievent, 0xffffffff); - - /* Set transmit fifo watermark register(X_WMRK), default = 64 */ - out_be32(&fec->eth->x_wmrk, 0x0); - - /* Set Opcode/Pause Duration Register */ - out_be32(&fec->eth->op_pause, 0x00010020); - - /* Frame length=1522; MII mode */ - out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24); - - /* Half-duplex, heartbeat disabled */ - out_be32(&fec->eth->x_cntrl, 0x00000000); - - /* Enable MIB counters */ - out_be32(&fec->eth->mib_control, 0x0); - - /* Setup recv fifo start and buff size */ - out_be32(&fec->eth->r_fstart, 0x500); - out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE); - - /* Setup BD base addresses */ - out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd); - out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd); - - /* DMA Control */ - out_be32(&fec->eth->dma_control, 0xc0000000); - - /* Enable FEC */ - setbits_be32(&fec->eth->ecntrl, 0x00000006); - - /* Initilize addresses and status words of BDs */ - mpc512x_fec_bd_init (fec); - - /* Descriptor polling active */ - out_be32(&fec->eth->r_des_active, 0x01000000); - -#if (DEBUG & 0x1) - printf("mpc512x_fec_init... Done \n"); -#endif - return 1; -} - -/********************************************************************/ -int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) -{ - mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; - const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ - int timeout = 1; - u16 phyStatus; - -#if (DEBUG & 0x1) - printf ("mpc512x_fec_init_phy... Begin\n"); -#endif - - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - out_be32(&fec->eth->ievent, 0xffffffff); - - /* - * Set interrupt mask register - */ - out_be32(&fec->eth->imask, 0x00000000); - - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - out_be32(&fec->eth->mii_speed, - (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1); - - /* - * Reset PHY, then delay 300ns - */ - miiphy_write (dev->name, phyAddr, 0x0, 0x8000); - udelay (1000); - - if (fec->xcv_type == MII10) { - /* - * Force 10Base-T, FDX operation - */ -#if (DEBUG & 0x2) - printf ("Forcing 10 Mbps ethernet link... "); -#endif - miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); - - miiphy_write (dev->name, phyAddr, 0x0, 0x0180); - - timeout = 20; - do { /* wait for link status to go down */ - udelay (10000); - if ((timeout--) == 0) { -#if (DEBUG & 0x2) - printf ("hmmm, should not have waited..."); -#endif - break; - } - miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); -#if (DEBUG & 0x2) - printf ("="); -#endif - } while ((phyStatus & 0x0004)); /* !link up */ - - timeout = 1000; - do { /* wait for link status to come back up */ - udelay (10000); - if ((timeout--) == 0) { - printf ("failed. Link is down.\n"); - break; - } - miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); -#if (DEBUG & 0x2) - printf ("+"); -#endif - } while (!(phyStatus & 0x0004)); /* !link up */ - -#if (DEBUG & 0x2) - printf ("done.\n"); -#endif - } else { /* MII100 */ - /* - * Set the auto-negotiation advertisement register bits - */ - miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); - - /* - * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation - */ - miiphy_write (dev->name, phyAddr, 0x0, 0x1200); - - /* - * Wait for AN completion - */ - timeout = 2500; - do { - udelay (1000); - - if ((timeout--) == 0) { -#if (DEBUG & 0x2) - printf ("PHY auto neg 0 failed...\n"); -#endif - return -1; - } - - if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) { -#if (DEBUG & 0x2) - printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); -#endif - return -1; - } - } while (!(phyStatus & 0x0004)); - -#if (DEBUG & 0x2) - printf ("PHY auto neg complete! \n"); -#endif - } - } - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc512x_fec_phydump (dev->name); -#endif - -#if (DEBUG & 0x1) - printf ("mpc512x_fec_init_phy... Done \n"); -#endif - return 1; -} - -/********************************************************************/ -static void mpc512x_fec_halt (struct eth_device *dev) -{ - mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; - int counter = 0xffff; - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc512x_fec_phydump (dev->name); -#endif - - /* - * mask FEC chip interrupts - */ - out_be32(&fec->eth->imask, 0); - - /* - * issue graceful stop command to the FEC transmitter if necessary - */ - setbits_be32(&fec->eth->x_cntrl, 0x00000001); - - /* - * wait for graceful stop to register - */ - while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000))) - ; - - /* - * Disable the Ethernet Controller - */ - clrbits_be32(&fec->eth->ecntrl, 0x00000002); - - /* - * Issue a reset command to the FEC chip - */ - setbits_be32(&fec->eth->ecntrl, 0x1); - - /* - * wait at least 16 clock cycles - */ - udelay (10); -#if (DEBUG & 0x3) - printf ("Ethernet task stopped\n"); -#endif -} - -/********************************************************************/ - -static int mpc512x_fec_send(struct eth_device *dev, void *eth_data, - int data_length) -{ - /* - * This routine transmits one frame. This routine only accepts - * 6-byte Ethernet addresses. - */ - mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; - volatile FEC_TBD *pTbd; - -#if (DEBUG & 0x20) - printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status); -#endif - - /* - * Clear Tx BD ring at first - */ - mpc512x_fec_tbd_scrub (fec); - - /* - * Check for valid length of data. - */ - if ((data_length > 1500) || (data_length <= 0)) { - return -1; - } - - /* - * Check the number of vacant TxBDs. - */ - if (fec->cleanTbdNum < 1) { -#if (DEBUG & 0x20) - printf ("No available TxBDs ...\n"); -#endif - return -1; - } - - /* - * Get the first TxBD to send the mac header - */ - pTbd = &fec->bdBase->tbd[fec->tbdIndex]; - pTbd->dataLength = data_length; - pTbd->dataPointer = (u32)eth_data; - pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; - fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - - /* Activate transmit Buffer Descriptor polling */ - out_be32(&fec->eth->x_des_active, 0x01000000); - -#if (DEBUG & 0x8) - printf ( "+" ); -#endif - - fec->cleanTbdNum -= 1; - - /* - * wait until frame is sent . - */ - while (pTbd->status & FEC_TBD_READY) { - udelay (10); -#if (DEBUG & 0x8) - printf ("TDB status = %04x\n", pTbd->status); -#endif - } - - return 0; -} - - -/********************************************************************/ -static int mpc512x_fec_recv (struct eth_device *dev) -{ - /* - * This command pulls one frame from the card - */ - mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; - volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; - unsigned long ievent; - int frame_length = 0; - -#if (DEBUG & 0x1) - printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); -#endif -#if (DEBUG & 0x8) - printf( "-" ); -#endif - - /* - * Check if any critical events have happened - */ - ievent = in_be32(&fec->eth->ievent); - out_be32(&fec->eth->ievent, ievent); - if (ievent & 0x20060000) { - /* BABT, Rx/Tx FIFO errors */ - mpc512x_fec_halt (dev); - mpc512x_fec_init (dev, NULL); - return 0; - } - if (ievent & 0x80000000) { - /* Heartbeat error */ - setbits_be32(&fec->eth->x_cntrl, 0x00000001); - } - if (ievent & 0x10000000) { - /* Graceful stop complete */ - if (in_be32(&fec->eth->x_cntrl) & 0x00000001) { - mpc512x_fec_halt (dev); - clrbits_be32(&fec->eth->x_cntrl, 0x00000001);; - mpc512x_fec_init (dev, NULL); - } - } - - if (!(pRbd->status & FEC_RBD_EMPTY)) { - if (!(pRbd->status & FEC_RBD_ERR) && - ((pRbd->dataLength - 4) > 14)) { - - /* - * Get buffer size - */ - if (pRbd->status & FEC_RBD_LAST) - frame_length = pRbd->dataLength - 4; - else - frame_length = pRbd->dataLength; -#if (DEBUG & 0x20) - { - int i; - printf ("recv data length 0x%08x data hdr: ", - pRbd->dataLength); - for (i = 0; i < 14; i++) - printf ("%x ", *((u8*)pRbd->dataPointer + i)); - printf("\n"); - } -#endif - /* - * Fill the buffer and pass it to upper layers - */ - memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer, - frame_length - rx_buff_idx); - rx_buff_idx = frame_length; - - if (pRbd->status & FEC_RBD_LAST) { - net_process_received_packet((uchar *)rx_buff, - frame_length); - rx_buff_idx = 0; - } - } - - /* - * Reset buffer descriptor as empty - */ - mpc512x_fec_rbd_clean (fec, pRbd); - } - - /* Try to fill Buffer Descriptors */ - out_be32(&fec->eth->r_des_active, 0x01000000); - - return frame_length; -} - -/********************************************************************/ -int mpc512x_fec_initialize (bd_t * bis) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - mpc512x_fec_priv *fec; - struct eth_device *dev; - void * bd; - - fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); - dev = (struct eth_device *) malloc (sizeof(*dev)); - memset (dev, 0, sizeof *dev); - - fec->eth = &im->fec; - -# ifndef CONFIG_FEC_10MBIT - fec->xcv_type = MII100; -# else - fec->xcv_type = MII10; -# endif - dev->priv = (void *)fec; - dev->iobase = (int)&im->fec; - dev->init = mpc512x_fec_init; - dev->halt = mpc512x_fec_halt; - dev->send = mpc512x_fec_send; - dev->recv = mpc512x_fec_recv; - - strcpy(dev->name, "FEC"); - eth_register (dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = fec512x_miiphy_read; - mdiodev->write = fec512x_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - /* Clean up space FEC's MIB and FIFO RAM ...*/ - memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib)); - memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo)); - - /* - * Malloc space for BDs (must be quad word-aligned) - * this pointer is lost, so cannot be freed - */ - bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); - fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0); - memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); - - /* - * Set interrupt mask register - */ - out_be32(&fec->eth->imask, 0x00000000); - - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - out_be32(&fec->eth->ievent, 0xffffffff); - - return 1; -} - -/* MII-interface related functions */ -/********************************************************************/ -int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, - int regAddr) -{ - u16 retVal = 0; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fec512x_t *eth = &im->fec; - u32 reg; /* convenient holder for the PHY register */ - u32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - /* - * reading from any PHY's register is done by properly - * programming the FEC's MII data register. - */ - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - out_be32(ð->mii_data, FEC_MII_DATA_ST | - FEC_MII_DATA_OP_RD | - FEC_MII_DATA_TA | - phy | reg); - - /* - * wait for the related interrupt - */ - while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000))) - ; - - if (timeout == 0) { -#if (DEBUG & 0x2) - printf ("Read MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear mii interrupt bit - */ - out_be32(ð->ievent, 0x00800000); - - /* - * it's now safe to read the PHY's register - */ - retVal = (u16) in_be32(ð->mii_data); - - return retVal; -} - -/********************************************************************/ -int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, - int regAddr, u16 data) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fec512x_t *eth = &im->fec; - u32 reg; /* convenient holder for the PHY register */ - u32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - out_be32(ð->mii_data, FEC_MII_DATA_ST | - FEC_MII_DATA_OP_WR | - FEC_MII_DATA_TA | - phy | reg | data); - - /* - * wait for the MII interrupt - */ - while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000))) - ; - - if (timeout == 0) { -#if (DEBUG & 0x2) - printf ("Write MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear MII interrupt bit - */ - out_be32(ð->ievent, 0x00800000); - - return 0; -} diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h deleted file mode 100644 index a083cca..0000000 --- a/drivers/net/mpc512x_fec.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2003 - 2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Derived from the MPC8xx driver's header file. - */ - -#ifndef __MPC512X_FEC_H -#define __MPC512X_FEC_H - -#include - -/* Receive & Transmit Buffer Descriptor definitions */ -typedef struct BufferDescriptor { - u16 status; - u16 dataLength; - u32 dataPointer; -} FEC_RBD; - -typedef struct { - u16 status; - u16 dataLength; - u32 dataPointer; -} FEC_TBD; - -/* private structure */ -typedef enum { - SEVENWIRE, /* 7-wire */ - MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ -} xceiver_type; - -/* BD Numer definitions */ -#define FEC_TBD_NUM 48 /* The user can adjust this value */ -#define FEC_RBD_NUM 32 /* The user can adjust this value */ - -/* packet size limit */ -#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */ - -/* Buffer size must be evenly divisible by 16 */ -#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf)) - -typedef struct { - u8 frame[FEC_BUFFER_SIZE]; -} mpc512x_frame; - -typedef struct { - FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */ - FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */ - mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */ -} mpc512x_buff_descs; - -typedef struct { - volatile fec512x_t *eth; - xceiver_type xcv_type; /* transceiver type */ - mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */ - u16 rbdIndex; /* next receive BD to read */ - u16 tbdIndex; /* next transmit BD to send */ - u16 usedTbdIndex; /* next transmit BD to clean */ - u16 cleanTbdNum; /* the number of available transmit BDs */ -} mpc512x_fec_priv; - -/* RBD bits definitions */ -#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ -#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ -#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ -#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ -#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ -#define FEC_RBD_LG 0x0020 /* Frame length violation */ -#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ -#define FEC_RBD_SH 0x0008 /* Short frame */ -#define FEC_RBD_CR 0x0004 /* CRC error */ -#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ -#define FEC_RBD_TR 0x0001 /* Frame is truncated */ -#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ - FEC_RBD_OV | FEC_RBD_TR) - -/* TBD bits definitions */ -#define FEC_TBD_READY 0x8000 /* Buffer is ready */ -#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ -#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ -#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ - -/* MII-related definitios */ -#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ -#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ -#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ -#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ -#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ -#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ -#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ - -#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ -#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ - -#endif /* __MPC512X_FEC_H */ diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c deleted file mode 100644 index d75e858..0000000 --- a/drivers/net/mpc5xxx_fec.c +++ /dev/null @@ -1,1031 +0,0 @@ -/* - * (C) Copyright 2003-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on mpc4200fec.c, - * (C) Copyright Motorola, Inc., 2000 - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mpc5xxx_fec.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* #define DEBUG 0x28 */ - -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#if (DEBUG & 0x60) -static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); -static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); -#endif /* DEBUG */ - -typedef struct { - uint8 data[1500]; /* actual data */ - int length; /* actual length */ - int used; /* buffer in use or not */ - uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ -} NBUF; - -int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, - int regAddr); -int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, - int regAddr, u16 data); - -static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis); - -/********************************************************************/ -#if (DEBUG & 0x2) -static void mpc5xxx_fec_phydump (char *devname) -{ - uint16 phyStatus, i; - uint8 phyAddr = CONFIG_PHY_ADDR; - uint8 reg_mask[] = { -#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ - /* regs to print: 0...7, 16...19, 21, 23, 24 */ - 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, -#else - /* regs to print: 0...8, 16...20 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -#endif - }; - - for (i = 0; i < 32; i++) { - if (reg_mask[i]) { - miiphy_read(devname, phyAddr, i, &phyStatus); - printf("Mii reg %d: 0x%04x\n", i, phyStatus); - } - } -} -#endif - -/********************************************************************/ -static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec) -{ - int ix; - char *data; - static int once = 0; - - for (ix = 0; ix < FEC_RBD_NUM; ix++) { - if (!once) { - data = (char *)malloc(FEC_MAX_PKT_SIZE); - if (data == NULL) { - printf ("RBD INIT FAILED\n"); - return -1; - } - fec->rbdBase[ix].dataPointer = (uint32)data; - } - fec->rbdBase[ix].status = FEC_RBD_EMPTY; - fec->rbdBase[ix].dataLength = 0; - } - once ++; - - /* - * have the last RBD to close the ring - */ - fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; - fec->rbdIndex = 0; - - return 0; -} - -/********************************************************************/ -static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec) -{ - int ix; - - for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->tbdBase[ix].status = 0; - } - - /* - * Have the last TBD to close the ring - */ - fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; - - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; -} - -/********************************************************************/ -static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd) -{ - /* - * Reset buffer descriptor as empty - */ - if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) - pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); - else - pRbd->status = FEC_RBD_EMPTY; - - pRbd->dataLength = 0; - - /* - * Now, we have an empty RxBD, restart the SmartDMA receive task - */ - SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); - - /* - * Increment BD count - */ - fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; -} - -/********************************************************************/ -static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec) -{ - volatile FEC_TBD *pUsedTbd; - -#if (DEBUG & 0x1) - printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", - fec->cleanTbdNum, fec->usedTbdIndex); -#endif - - /* - * process all the consumed TBDs - */ - while (fec->cleanTbdNum < FEC_TBD_NUM) { - pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; - if (pUsedTbd->status & FEC_TBD_READY) { -#if (DEBUG & 0x20) - printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum); -#endif - return; - } - - /* - * clean this buffer descriptor - */ - if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) - pUsedTbd->status = FEC_TBD_WRAP; - else - pUsedTbd->status = 0; - - /* - * update some indeces for a correct handling of the TBD ring - */ - fec->cleanTbdNum++; - fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; - } -} - -/********************************************************************/ -static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac) -{ - uint8 currByte; /* byte for which to compute the CRC */ - int byte; /* loop - counter */ - int bit; /* loop - counter */ - uint32 crc = 0xffffffff; /* initial value */ - - /* - * The algorithm used is the following: - * we loop on each of the six bytes of the provided address, - * and we compute the CRC by left-shifting the previous - * value by one position, so that each bit in the current - * byte of the address may contribute the calculation. If - * the latter and the MSB in the CRC are different, then - * the CRC value so computed is also ex-ored with the - * "polynomium generator". The current byte of the address - * is also shifted right by one bit at each iteration. - * This is because the CRC generatore in hardware is implemented - * as a shift-register with as many ex-ores as the radixes - * in the polynomium. This suggests that we represent the - * polynomiumm itself as a 32-bit constant. - */ - for (byte = 0; byte < 6; byte++) { - currByte = mac[byte]; - for (bit = 0; bit < 8; bit++) { - if ((currByte & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - currByte >>= 1; - } - } - - crc = crc >> 26; - - /* - * Set individual hash table register - */ - if (crc >= 32) { - fec->eth->iaddr1 = (1 << (crc - 32)); - fec->eth->iaddr2 = 0; - } else { - fec->eth->iaddr1 = 0; - fec->eth->iaddr2 = (1 << crc); - } - - /* - * Set physical address - */ - fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; - fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; -} - -/********************************************************************/ -static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) -{ - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; - -#if (DEBUG & 0x1) - printf ("mpc5xxx_fec_init... Begin\n"); -#endif - - mpc5xxx_fec_init_phy(dev, bis); - - /* - * Call board-specific PHY fixups (if any) - */ -#ifdef CONFIG_RESET_PHY_R - reset_phy(); -#endif - - /* - * Initialize RxBD/TxBD rings - */ - mpc5xxx_fec_rbd_init(fec); - mpc5xxx_fec_tbd_init(fec); - - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - fec->eth->ievent = 0xffffffff; - - /* - * Set interrupt mask register - */ - fec->eth->imask = 0x00000000; - - /* - * Set FEC-Lite receive control register(R_CNTRL): - */ - if (fec->xcv_type == SEVENWIRE) { - /* - * Frame length=1518; 7-wire mode - */ - fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ - } else { - /* - * Frame length=1518; MII mode; - */ - fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ - } - - fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ - - /* - * Set Opcode/Pause Duration Register - */ - fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */ - - /* - * Set Rx FIFO alarm and granularity value - */ - fec->eth->rfifo_cntrl = 0x0c000000 - | (fec->eth->rfifo_cntrl & ~0x0f000000); - fec->eth->rfifo_alarm = 0x0000030c; -#if (DEBUG & 0x22) - if (fec->eth->rfifo_status & 0x00700000 ) { - printf("mpc5xxx_fec_init() RFIFO error\n"); - } -#endif - - /* - * Set Tx FIFO granularity value - */ - fec->eth->tfifo_cntrl = 0x0c000000 - | (fec->eth->tfifo_cntrl & ~0x0f000000); -#if (DEBUG & 0x2) - printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); - printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); -#endif - - /* - * Set transmit fifo watermark register(X_WMRK), default = 64 - */ - fec->eth->tfifo_alarm = 0x00000080; - fec->eth->x_wmrk = 0x2; - - /* - * Set individual address filter for unicast address - * and set physical address registers. - */ - mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr); - - /* - * Set multicast address filter - */ - fec->eth->gaddr1 = 0x00000000; - fec->eth->gaddr2 = 0x00000000; - - /* - * Turn ON cheater FSM: ???? - */ - fec->eth->xmit_fsm = 0x03000000; - - /* - * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't - * work w/ the current receive task. - */ - sdma->PtdCntrl |= 0x00000001; - - /* - * Set priority of different initiators - */ - sdma->IPR0 = 7; /* always */ - sdma->IPR3 = 6; /* Eth RX */ - sdma->IPR4 = 5; /* Eth Tx */ - - /* - * Clear SmartDMA task interrupt pending bits - */ - SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); - - /* - * Initialize SmartDMA parameters stored in SRAM - */ - *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase; - *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase; - *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase; - *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase; - - /* - * Enable FEC-Lite controller - */ - fec->eth->ecntrl |= 0x00000006; - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (dev->name); -#endif - - /* - * Enable SmartDMA receive task - */ - SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); - -#if (DEBUG & 0x1) - printf("mpc5xxx_fec_init... Done \n"); -#endif - - return 1; -} - -/********************************************************************/ -static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) -{ - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ - static int initialized = 0; - - if(initialized) - return 0; - initialized = 1; - -#if (DEBUG & 0x1) - printf ("mpc5xxx_fec_init_phy... Begin\n"); -#endif - - /* - * Initialize GPIO pins - */ - if (fec->xcv_type == SEVENWIRE) { - /* 10MBit with 7-wire operation */ - /* 7-wire only */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; - } else { - /* 100MBit with MD operation */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; - } - - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - fec->eth->ievent = 0xffffffff; - - /* - * Set interrupt mask register - */ - fec->eth->imask = 0x00000000; - -/* - * In original Promess-provided code PHY initialization is disabled with the - * following comment: "Phy initialization is DISABLED for now. There was a - * problem with running 100 Mbps on PRO board". Thus we temporarily disable - * PHY initialization for the Motion-PRO board, until a proper fix is found. - */ - - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - * No MII for 7-wire mode - */ - fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); - } - - if (fec->xcv_type != SEVENWIRE) { - /* - * Initialize PHY(LXT971A): - * - * Generally, on power up, the LXT971A reads its configuration - * pins to check for forced operation, If not cofigured for - * forced operation, it uses auto-negotiation/parallel detection - * to automatically determine line operating conditions. - * If the PHY device on the other side of the link supports - * auto-negotiation, the LXT971A auto-negotiates with it - * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not - * support auto-negotiation, the LXT971A automatically detects - * the presence of either link pulses(10Mbps PHY) or Idle - * symbols(100Mbps) and sets its operating conditions accordingly. - * - * When auto-negotiation is controlled by software, the following - * steps are recommended. - * - * Note: - * The physical address is dependent on hardware configuration. - * - */ - int timeout = 1; - uint16 phyStatus; - - /* - * Reset PHY, then delay 300ns - */ - miiphy_write(dev->name, phyAddr, 0x0, 0x8000); - udelay(1000); - - if (fec->xcv_type == MII10) { - /* - * Force 10Base-T, FDX operation - */ -#if (DEBUG & 0x2) - printf("Forcing 10 Mbps ethernet link... "); -#endif - miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); - /* - miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100); - */ - miiphy_write(dev->name, phyAddr, 0x0, 0x0180); - - timeout = 20; - do { /* wait for link status to go down */ - udelay(10000); - if ((timeout--) == 0) { -#if (DEBUG & 0x2) - printf("hmmm, should not have waited..."); -#endif - break; - } - miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); -#if (DEBUG & 0x2) - printf("="); -#endif - } while ((phyStatus & 0x0004)); /* !link up */ - - timeout = 1000; - do { /* wait for link status to come back up */ - udelay(10000); - if ((timeout--) == 0) { - printf("failed. Link is down.\n"); - break; - } - miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); -#if (DEBUG & 0x2) - printf("+"); -#endif - } while (!(phyStatus & 0x0004)); /* !link up */ - -#if (DEBUG & 0x2) - printf ("done.\n"); -#endif - } else { /* MII100 */ - /* - * Set the auto-negotiation advertisement register bits - */ - miiphy_write(dev->name, phyAddr, 0x4, 0x01e1); - - /* - * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation - */ - miiphy_write(dev->name, phyAddr, 0x0, 0x1200); - - /* - * Wait for AN completion - */ - timeout = 5000; - do { - udelay(1000); - - if ((timeout--) == 0) { -#if (DEBUG & 0x2) - printf("PHY auto neg 0 failed...\n"); -#endif - return -1; - } - - if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) { -#if (DEBUG & 0x2) - printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus); -#endif - return -1; - } - } while (!(phyStatus & 0x0004)); - -#if (DEBUG & 0x2) - printf("PHY auto neg complete! \n"); -#endif - } - - } - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (dev->name); -#endif - - -#if (DEBUG & 0x1) - printf("mpc5xxx_fec_init_phy... Done \n"); -#endif - - return 1; -} - -/********************************************************************/ -static void mpc5xxx_fec_halt(struct eth_device *dev) -{ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - int counter = 0xffff; - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (dev->name); -#endif - - /* - * mask FEC chip interrupts - */ - fec->eth->imask = 0; - - /* - * issue graceful stop command to the FEC transmitter if necessary - */ - fec->eth->x_cntrl |= 0x00000001; - - /* - * wait for graceful stop to register - */ - while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; - - /* - * Disable SmartDMA tasks - */ - SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); - SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); - - /* - * Turn on COMM bus prefetch in the MPC5200 BestComm after we're - * done. It doesn't work w/ the current receive task. - */ - sdma->PtdCntrl &= ~0x00000001; - - /* - * Disable the Ethernet Controller - */ - fec->eth->ecntrl &= 0xfffffffd; - - /* - * Clear FIFO status registers - */ - fec->eth->rfifo_status &= 0x00700000; - fec->eth->tfifo_status &= 0x00700000; - - fec->eth->reset_cntrl = 0x01000000; - - /* - * Issue a reset command to the FEC chip - */ - fec->eth->ecntrl |= 0x1; - - /* - * wait at least 16 clock cycles - */ - udelay(10); - - /* don't leave the MII speed set to zero */ - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - * No MII for 7-wire mode - */ - fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); - } - -#if (DEBUG & 0x3) - printf("Ethernet task stopped\n"); -#endif -} - -#if (DEBUG & 0x60) -/********************************************************************/ - -static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec) -{ - uint16 phyAddr = CONFIG_PHY_ADDR; - uint16 phyStatus; - - if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) - || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { - - miiphy_read(devname, phyAddr, 0x1, &phyStatus); - printf("\nphyStatus: 0x%04x\n", phyStatus); - printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); - printf("ievent: 0x%08x\n", fec->eth->ievent); - printf("x_status: 0x%08x\n", fec->eth->x_status); - printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status); - - printf(" control 0x%08x\n", fec->eth->tfifo_cntrl); - printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); - printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); - printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm); - printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr); - printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr); - } -} - -static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) -{ - uint16 phyAddr = CONFIG_PHY_ADDR; - uint16 phyStatus; - - if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) - || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { - - miiphy_read(devname, phyAddr, 0x1, &phyStatus); - printf("\nphyStatus: 0x%04x\n", phyStatus); - printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); - printf("ievent: 0x%08x\n", fec->eth->ievent); - printf("x_status: 0x%08x\n", fec->eth->x_status); - printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status); - - printf(" control 0x%08x\n", fec->eth->rfifo_cntrl); - printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); - printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); - printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm); - printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr); - printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr); - } -} -#endif /* DEBUG */ - -/********************************************************************/ - -static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data, - int data_length) -{ - /* - * This routine transmits one frame. This routine only accepts - * 6-byte Ethernet addresses. - */ - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - volatile FEC_TBD *pTbd; - -#if (DEBUG & 0x20) - printf("tbd status: 0x%04x\n", fec->tbdBase[0].status); - tfifo_print(dev->name, fec); -#endif - - /* - * Clear Tx BD ring at first - */ - mpc5xxx_fec_tbd_scrub(fec); - - /* - * Check for valid length of data. - */ - if ((data_length > 1500) || (data_length <= 0)) { - return -1; - } - - /* - * Check the number of vacant TxBDs. - */ - if (fec->cleanTbdNum < 1) { -#if (DEBUG & 0x20) - printf("No available TxBDs ...\n"); -#endif - return -1; - } - - /* - * Get the first TxBD to send the mac header - */ - pTbd = &fec->tbdBase[fec->tbdIndex]; - pTbd->dataLength = data_length; - pTbd->dataPointer = (uint32)eth_data; - pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; - fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - -#if (DEBUG & 0x100) - printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); -#endif - - /* - * Kick the MII i/f - */ - if (fec->xcv_type != SEVENWIRE) { - uint16 phyStatus; - miiphy_read(dev->name, 0, 0x1, &phyStatus); - } - - /* - * Enable SmartDMA transmit task - */ - -#if (DEBUG & 0x20) - tfifo_print(dev->name, fec); -#endif - SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO); -#if (DEBUG & 0x20) - tfifo_print(dev->name, fec); -#endif -#if (DEBUG & 0x8) - printf( "+" ); -#endif - - fec->cleanTbdNum -= 1; - -#if (DEBUG & 0x129) && (DEBUG & 0x80000000) - printf ("smartDMA ethernet Tx task enabled\n"); -#endif - /* - * wait until frame is sent . - */ - while (pTbd->status & FEC_TBD_READY) { - udelay(10); -#if (DEBUG & 0x8) - printf ("TDB status = %04x\n", pTbd->status); -#endif - } - - return 0; -} - - -/********************************************************************/ -static int mpc5xxx_fec_recv(struct eth_device *dev) -{ - /* - * This command pulls one frame from the card - */ - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; - unsigned long ievent; - int frame_length, len = 0; - NBUF *frame; - uchar buff[FEC_MAX_PKT_SIZE]; - -#if (DEBUG & 0x1) - printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex); -#endif -#if (DEBUG & 0x8) - printf( "-" ); -#endif - - /* - * Check if any critical events have happened - */ - ievent = fec->eth->ievent; - fec->eth->ievent = ievent; - if (ievent & 0x20060000) { - /* BABT, Rx/Tx FIFO errors */ - mpc5xxx_fec_halt(dev); - mpc5xxx_fec_init(dev, NULL); - return 0; - } - if (ievent & 0x80000000) { - /* Heartbeat error */ - fec->eth->x_cntrl |= 0x00000001; - } - if (ievent & 0x10000000) { - /* Graceful stop complete */ - if (fec->eth->x_cntrl & 0x00000001) { - mpc5xxx_fec_halt(dev); - fec->eth->x_cntrl &= ~0x00000001; - mpc5xxx_fec_init(dev, NULL); - } - } - - if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && - ((pRbd->dataLength - 4) > 14)) { - - /* - * Get buffer address and size - */ - frame = (NBUF *)pRbd->dataPointer; - frame_length = pRbd->dataLength - 4; - -#if (DEBUG & 0x20) - { - int i; - printf("recv data hdr:"); - for (i = 0; i < 14; i++) - printf("%x ", *(frame->head + i)); - printf("\n"); - } -#endif - /* - * Fill the buffer and pass it to upper layers - */ - memcpy(buff, frame->head, 14); - memcpy(buff + 14, frame->data, frame_length); - net_process_received_packet(buff, frame_length); - len = frame_length; - } - /* - * Reset buffer descriptor as empty - */ - mpc5xxx_fec_rbd_clean(fec, pRbd); - } - SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); - return len; -} - - -/********************************************************************/ -int mpc5xxx_fec_initialize(bd_t * bis) -{ - mpc5xxx_fec_priv *fec; - struct eth_device *dev; - char *tmp, *end; - char env_enetaddr[6]; - int i; - - fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); - dev = (struct eth_device *)malloc(sizeof(*dev)); - memset(dev, 0, sizeof *dev); - - fec->eth = (ethernet_regs *)MPC5XXX_FEC; - fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; - fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); -#if defined(CONFIG_MPC5xxx_FEC_MII100) - fec->xcv_type = MII100; -#elif defined(CONFIG_MPC5xxx_FEC_MII10) - fec->xcv_type = MII10; -#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE) - fec->xcv_type = SEVENWIRE; -#else -#error fec->xcv_type not initialized. -#endif - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - * No MII for 7-wire mode - */ - fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); - } - - dev->priv = (void *)fec; - dev->iobase = MPC5XXX_FEC; - dev->init = mpc5xxx_fec_init; - dev->halt = mpc5xxx_fec_halt; - dev->send = mpc5xxx_fec_send; - dev->recv = mpc5xxx_fec_recv; - - strcpy(dev->name, "FEC"); - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = fec5xxx_miiphy_read; - mdiodev->write = fec5xxx_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - /* - * Try to set the mac address now. The fec mac address is - * a garbage after reset. When not using fec for booting - * the Linux fec driver will try to work with this garbage. - */ - tmp = getenv("ethaddr"); - if (tmp) { - for (i=0; i<6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - mpc5xxx_fec_set_hwaddr(fec, env_enetaddr); - } - - return 1; -} - -/* MII-interface related functions */ -/********************************************************************/ -int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, - int regAddr) -{ - uint16 retVal = 0; - ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; - uint32 reg; /* convenient holder for the PHY register */ - uint32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - /* - * reading from any PHY's register is done by properly - * programming the FEC's MII data register. - */ - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); - - /* - * wait for the related interrupt - */ - while ((timeout--) && (!(eth->ievent & 0x00800000))) ; - - if (timeout == 0) { -#if (DEBUG & 0x2) - printf ("Read MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear mii interrupt bit - */ - eth->ievent = 0x00800000; - - /* - * it's now safe to read the PHY's register - */ - retVal = (uint16) eth->mii_data; - - return retVal; -} - -/********************************************************************/ -int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, - int regAddr, u16 data) -{ - ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; - uint32 reg; /* convenient holder for the PHY register */ - uint32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | - FEC_MII_DATA_TA | phy | reg | data); - - /* - * wait for the MII interrupt - */ - while ((timeout--) && (!(eth->ievent & 0x00800000))) ; - - if (timeout == 0) { -#if (DEBUG & 0x2) - printf ("Write MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear MII interrupt bit - */ - eth->ievent = 0x00800000; - - return 0; -} diff --git a/drivers/net/mpc5xxx_fec.h b/drivers/net/mpc5xxx_fec.h deleted file mode 100644 index 16c3e8e..0000000 --- a/drivers/net/mpc5xxx_fec.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on mpc4200fec.h - * (C) Copyright Motorola, Inc., 2000 - * - * odin ethernet header file - */ - -#ifndef __MPC5XXX_FEC_H -#define __MPC5XXX_FEC_H - -typedef unsigned long uint32; -typedef unsigned short uint16; -typedef unsigned char uint8; - -typedef struct ethernet_register_set { - -/* [10:2]addr = 00 */ - -/* Control and status Registers (offset 000-1FF) */ - - volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ - volatile uint32 ievent; /* MBAR_ETH + 0x004 */ - volatile uint32 imask; /* MBAR_ETH + 0x008 */ - - volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ - volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ - volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ - volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */ - volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */ - volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */ - volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ - - volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */ - volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ - volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ - volatile uint32 mii_status; /* MBAR_ETH + 0x048 */ - - volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ - volatile uint32 mib_data; /* MBAR_ETH + 0x060 */ - volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ - - volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */ - volatile uint32 r_activate; /* MBAR_ETH + 0x080 */ - volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ - volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ - volatile uint32 r_data; /* MBAR_ETH + 0x08C */ - volatile uint32 ar_done; /* MBAR_ETH + 0x090 */ - volatile uint32 r_test; /* MBAR_ETH + 0x094 */ - volatile uint32 r_mib; /* MBAR_ETH + 0x098 */ - volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */ - volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */ - - volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ - volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */ - volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ - volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */ - volatile uint32 x_data; /* MBAR_ETH + 0x0CC */ - volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */ - volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */ - volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */ - volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ - volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ - volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ - volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ - volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ - - volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ - volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */ - volatile uint32 context_reg; /* MBAR_ETH + 0x104 */ - volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */ - volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */ - volatile uint32 ones; /* MBAR_ETH + 0x110 */ - volatile uint32 zeros; /* MBAR_ETH + 0x114 */ - volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ - volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ - volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ - volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ - volatile uint32 random; /* MBAR_ETH + 0x128 */ - volatile uint32 rand1; /* MBAR_ETH + 0x12C */ - volatile uint32 tmp; /* MBAR_ETH + 0x130 */ - - volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */ - volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ - volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ - volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */ - volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ - volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ - volatile uint32 r_count; /* MBAR_ETH + 0x154 */ - volatile uint32 r_lag; /* MBAR_ETH + 0x158 */ - volatile uint32 r_read; /* MBAR_ETH + 0x15C */ - volatile uint32 r_write; /* MBAR_ETH + 0x160 */ - volatile uint32 x_count; /* MBAR_ETH + 0x164 */ - volatile uint32 x_lag; /* MBAR_ETH + 0x168 */ - volatile uint32 x_retry; /* MBAR_ETH + 0x16C */ - volatile uint32 x_write; /* MBAR_ETH + 0x170 */ - volatile uint32 x_read; /* MBAR_ETH + 0x174 */ - - volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */ - volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */ - volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */ - volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */ - volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ - volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ - volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ - volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */ - volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ - volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ - volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */ - volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */ - volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ - volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ - volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ - volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ - volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ - volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ - - volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ - volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ - - volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ - volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */ - volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */ - volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */ - volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */ - volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */ - volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */ - volatile uint32 status; /* MBAR_ETH + 0x1F0 */ - volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ - volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */ - volatile uint32 data; /* MBAR_ETH + 0x1FC */ - -/* MIB COUNTERS (Offset 200-2FF) */ - - volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ - volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ - volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ - volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ - volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ - volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ - volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ - volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ - volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ - volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ - volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ - volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ - volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ - volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ - volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ - volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ - volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ - volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ - volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ - volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ - volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ - volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ - volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ - volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ - volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ - volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ - volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ - volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ - volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ - volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ - - volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */ - volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ - volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ - volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ - volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ - volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ - volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ - volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ - volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ - volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ - - volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ - - volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ - volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ - volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ - volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ - volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ - volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ - volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ - volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ - volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ - volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ - volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ - volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ - volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ - volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ - volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ - - volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ - - volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ -} ethernet_regs; - -/* Receive & Transmit Buffer Descriptor definitions */ -typedef struct BufferDescriptor { - uint16 status; - uint16 dataLength; - uint32 dataPointer; -} FEC_RBD; -typedef struct { - uint16 status; - uint16 dataLength; - uint32 dataPointer; -} FEC_TBD; - -/* private structure */ -typedef enum { - SEVENWIRE, /* 7-wire */ - MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ -} xceiver_type; - -typedef struct { - ethernet_regs *eth; - xceiver_type xcv_type; /* transceiver type */ - FEC_RBD *rbdBase; /* RBD ring */ - FEC_TBD *tbdBase; /* TBD ring */ - uint16 rbdIndex; /* next receive BD to read */ - uint16 tbdIndex; /* next transmit BD to send */ - uint16 usedTbdIndex; /* next transmit BD to clean */ - uint16 cleanTbdNum; /* the number of available transmit BDs */ -} mpc5xxx_fec_priv; - -/* Ethernet parameter area */ -#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) -#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) -#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) -#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) - -/* BD Numer definitions */ -#define FEC_TBD_NUM 48 /* The user can adjust this value */ -#define FEC_RBD_NUM 32 /* The user can adjust this value */ - -/* packet size limit */ -#define FEC_MAX_PKT_SIZE 1536 - -/* RBD bits definitions */ -#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ -#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_RBD_INT 0x1000 /* Interrupt */ -#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ -#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ -#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ -#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ -#define FEC_RBD_LG 0x0020 /* Frame length violation */ -#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ -#define FEC_RBD_SH 0x0008 /* Short frame */ -#define FEC_RBD_CR 0x0004 /* CRC error */ -#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ -#define FEC_RBD_TR 0x0001 /* Frame is truncated */ -#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ - FEC_RBD_OV | FEC_RBD_TR) - -/* TBD bits definitions */ -#define FEC_TBD_READY 0x8000 /* Buffer is ready */ -#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_TBD_INT 0x1000 /* Interrupt */ -#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ -#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ -#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ - -/* MII-related definitios */ -#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ -#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ -#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ -#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ -#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ -#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ -#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ - -#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ -#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ - -#endif /* __MPC5XXX_FEC_H */ diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index 67bf140..377d87f 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -495,7 +495,7 @@ dp83902a_recv(u8 *data, int len) printf(" %02x", tmp); if (0 == (++dx % 16)) printf("\n "); #endif - *data++ = tmp;; + *data++ = tmp; mlen--; } } diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 8041922..b7f300e 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -482,7 +482,10 @@ static int m88e1145_config(struct phy_device *phydev) genphy_config_aneg(phydev); - phy_reset(phydev); + /* soft reset */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + reg |= BMCR_RESET; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); return 0; } diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c index aee0bd6..efa13a2 100644 --- a/drivers/pci/pci_indirect.c +++ b/drivers/pci/pci_indirect.c @@ -17,22 +17,7 @@ #define cfg_read(val, addr, type, op) *val = op((type)(addr)) #define cfg_write(val, addr, type, op) op((type *)(addr), (val)) -#if defined(CONFIG_MPC8260) -#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ -static int \ -indirect_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 b, d,f; \ - b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ - b = b - hose->first_busno; \ - dev = PCI_BDF(b, d, f); \ - out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ - sync(); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - return 0; \ -} -#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 7565e2f..78cde21 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -13,6 +13,10 @@ #include #include #include +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_ARM) +#include +#endif #include "pcie_layerscape.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index ce709bf..9e6c2f5 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -14,6 +14,9 @@ #ifdef CONFIG_OF_BOARD_SETUP #include #include +#ifdef CONFIG_ARM +#include +#endif #include "pcie_layerscape.h" #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index c506f79..b7e6188 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -5,7 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o -obj-y += tqm8xx_pcmcia.o obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c deleted file mode 100644 index dae5560..0000000 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ /dev/null @@ -1,258 +0,0 @@ -#include -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_PCMCIA) - -#if defined(CONFIG_IDE_8xx_PCCARD) -extern int check_ide_device (int slot); -#endif - -extern int pcmcia_hardware_enable (int slot); -extern int pcmcia_voltage_set(int slot, int vcc, int vpp); - -#if defined(CONFIG_CMD_PCMCIA) -extern int pcmcia_hardware_disable(int slot); -#endif - -static u_int m8xx_get_graycode(u_int size); -#if 0 /* Disabled */ -static u_int m8xx_get_speed(u_int ns, u_int is_io); -#endif - -/* look up table for pgcrx registers */ -u_int *pcmcia_pgcrx[2] = { - &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra, - &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb, -}; - -/* - * Search this table to see if the windowsize is - * supported... - */ - -#define M8XX_SIZES_NO 32 - -static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = -{ 0x00000001, 0x00000002, 0x00000008, 0x00000004, - 0x00000080, 0x00000040, 0x00000010, 0x00000020, - 0x00008000, 0x00004000, 0x00001000, 0x00002000, - 0x00000100, 0x00000200, 0x00000800, 0x00000400, - - 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0x01000000, 0x02000000, 0xffffffff, 0x04000000, - 0x00010000, 0x00020000, 0x00080000, 0x00040000, - 0x00800000, 0x00400000, 0x00100000, 0x00200000 }; - - -/* -------------------------------------------------------------------- */ - -#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \ - | PCMCIA_SST(4) \ - | PCMCIA_SL(9)) - -/* -------------------------------------------------------------------- */ - -int pcmcia_on (void) -{ - u_long reg, base; - pcmcia_win_t *win; - u_int rc, slot; - __maybe_unused u_int slotbit; - int i; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - /* intialize the fixed memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0); - base = CONFIG_SYS_PCMCIA_MEM_ADDR; - - if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) { - printf ("Cannot set window size to 0x%08x\n", - CONFIG_SYS_PCMCIA_MEM_SIZE); - return (1); - } - - slotbit = PCMCIA_SLOT_x; - for (i=0; ibr = base; - -#if (PCMCIA_SOCKETS_NO == 2) - if (i == 4) /* Another slot starting from win 4 */ - slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B); -#endif - switch (i) { -#ifdef CONFIG_IDE_8xx_PCCARD - case 4: - case 0: { /* map attribute memory */ - win->or = ( PCMCIA_BSIZE_64M - | PCMCIA_PPS_8 - | PCMCIA_PRS_ATTR - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } - case 5: - case 1: { /* map I/O window for data reg */ - win->or = ( PCMCIA_BSIZE_1K - | PCMCIA_PPS_16 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } - case 6: - case 2: { /* map I/O window for cmd/ctrl reg block */ - win->or = ( PCMCIA_BSIZE_1K - | PCMCIA_PPS_8 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } -#endif /* CONFIG_IDE_8xx_PCCARD */ - default: /* set to not valid */ - win->or = 0; - break; - } - - debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", - i, win->br, win->or); - base += CONFIG_SYS_PCMCIA_MEM_SIZE; - ++win; - } - - for (i=0, rc=0, slot=_slot_; iim_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); - ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* turn off interrupt and disable CxOE */ - PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; - - /* turn off memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0); - - for (i=0; ior = 0; - ++win; - } - - /* turn off voltage */ - pcmcia_voltage_set(_slot_, 0, 0); - - /* disable external hardware */ - printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n"); - pcmcia_hardware_disable(_slot_); - return 0; -} -#endif - - -static u_int m8xx_get_graycode(u_int size) -{ - u_int k; - - for (k = 0; k < M8XX_SIZES_NO; k++) { - if(m8xx_size_to_gray[k] == size) - break; - } - - if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) - k = -1; - - return k; -} - -#if 0 - -static u_int m8xx_get_speed(u_int ns, u_int is_io) -{ - u_int reg, clocks, psst, psl, psht; - - if(!ns) { - - /* - * We get called with IO maps setup to 0ns - * if not specified by the user. - * They should be 255ns. - */ - - if(is_io) - ns = 255; - else - ns = 100; /* fast memory if 0 */ - } - - /* - * In PSST, PSL, PSHT fields we tell the controller - * timing parameters in CLKOUT clock cycles. - * CLKOUT is the same as GCLK2_50. - */ - - /* how we want to adjust the timing - in percent */ - -#define ADJ 180 /* 80 % longer accesstime - to be sure */ - - clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; - clocks = (clocks * ADJ) / (100*1000); - - if(clocks >= PCMCIA_BMT_LIMIT) { - DEBUG(0, "Max access time limit reached\n"); - clocks = PCMCIA_BMT_LIMIT-1; - } - - psst = clocks / 7; /* setup time */ - psht = clocks / 7; /* hold time */ - psl = (clocks * 5) / 7; /* strobe length */ - - psst += clocks - (psst + psht + psl); - - reg = psst << 12; - reg |= psl << 7; - reg |= psht << 16; - - return reg; -} -#endif /* 0 */ - -#endif /* CONFIG_PCMCIA */ diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c deleted file mode 100644 index edff50f..0000000 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ /dev/null @@ -1,254 +0,0 @@ -/* -------------------------------------------------------------------- */ -/* TQM8xxL Boards by TQ Components */ -/* SC8xx Boards by SinoVee Microsystems */ -/* -------------------------------------------------------------------- */ -#include -#include -#ifdef CONFIG_8xx -#include -#endif -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_PCMCIA) \ - && defined(CONFIG_TQM8xxL) - -#if defined(CONFIG_TQM8xxL) -#define PCMCIA_BOARD_MSG "TQM8xxL" -#endif - -static inline void power_config(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable - */ - clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 | 0x0004); - clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 | 0x0004); -} - -static inline void power_off(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 | 0x0004); -} - -static inline void power_on_5_0(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004); - setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004); -} - -static inline void power_on_3_3(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002); - setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004); -} - -/* - * Function to retrieve the PIPR register, used for debuging purposes. - */ -static inline uint32_t debug_get_pipr(void) -{ - uint32_t pipr = 0; -#ifdef DEBUG - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - pipr = in_be32(&immap->im_pcmcia.pcmc_pipr); -#endif - return pipr; -} - - -static inline int check_card_is_absent(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr); - return pipr & (0x18000000 >> (slot << 4)); -} - -#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE - -int pcmcia_hardware_enable(int slot) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - uint reg, mask; - - debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - - /* Set DBGC to 00 */ - clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11); - - /* Clear interrupt state, and disable interrupts */ - out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot)); - clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot)); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= NSCU_GCRX_CXOE; - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - power_config(slot); - power_off(slot); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - reg = debug_get_pipr(); - debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__, - &immap->im_pcmcia.pcmc_pipr, reg); - - if (check_card_is_absent(slot)) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = in_be32(&immap->im_pcmcia.pcmc_pipr); - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg & PCMCIA_VS1(slot)) ? "n" : "ff", - (reg & PCMCIA_VS2(slot)) ? "n" : "ff"); - - if ((reg & mask) == mask) { - power_on_5_0(slot); - puts (" 5.0V card found: "); - } else { - power_on_3_3(slot); - puts (" 3.3V card found: "); - } - -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - - udelay(1000); - debug("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - reg &= ~NSCU_GCRX_CXOE; - - PCMCIA_PGCRX(slot) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - u_long reg; - - debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* remove all power */ - power_off(slot); - - debug("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= NSCU_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - - udelay(10000); - - return (0); -} -#endif - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg; - uint32_t pipr = 0; - - debug("voltage_set: " PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - reg |= NSCU_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug("PCMCIA power OFF\n"); - power_config(slot); - power_off(slot); - - switch(vcc) { - case 0: break; - case 33: power_on_3_3(slot); break; - case 50: power_on_5_0(slot); break; - default: goto done; - } - - /* Checking supported voltages */ - pipr = debug_get_pipr(); - debug("PIPR: 0x%x --> %s\n", pipr, - (pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - if (vcc) - debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3"); - else - debug("PCMCIA powered down\n"); - -done: - debug("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - reg &= ~NSCU_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); - return 0; -} - -#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f6616c5..f948783 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -69,6 +69,7 @@ config SPL_PINCTRL config SPL_PINCTRL_FULL bool "Support full pin controllers in SPL" depends on SPL_PINCTRL && SPL_OF_CONTROL + default n if TARGET_STM32F746_DISCO default y help This option is an SPL-variant of the PINCTRL_FULL option. @@ -197,6 +198,16 @@ config PINCTRL_ROCKCHIP_RK3328 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK3368 + bool "Rockchip RK3368 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3368 SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_ROCKCHIP_RK3399 bool "Rockchip rk3399 pin control driver" depends on DM @@ -207,6 +218,16 @@ config PINCTRL_ROCKCHIP_RK3399 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RV1108 + bool "Rockchip rv1108 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rv1108 SoC. + + The driver is controlled by a device tree node which contains + both the GPIO definitions and pin control functions for each + available multiplex function. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 69eef4c..a1c655d 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -9,4 +9,6 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o +obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3399) += pinctrl_rk3399.o +obj-$(CONFIG_PINCTRL_ROCKCHIP_RV1108) += pinctrl_rv1108.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c index 8d42584..9215d6c 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -26,19 +26,19 @@ static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id) { switch (pwm_id) { case PERIPH_ID_PWM0: - rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT, + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, GPIO0D2_PWM0 << GPIO0D2_SHIFT); break; case PERIPH_ID_PWM1: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT, + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK, GPIO0A0_PWM1 << GPIO0A0_SHIFT); break; case PERIPH_ID_PWM2: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT, + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK, GPIO0A1_PWM2 << GPIO0A1_SHIFT); break; case PERIPH_ID_PWM3: - rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT, + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK, GPIO0D3_PWM3 << GPIO0D3_SHIFT); break; default: @@ -52,23 +52,20 @@ static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id) switch (i2c_id) { case PERIPH_ID_I2C0: rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A1_MASK << GPIO0A1_SHIFT | - GPIO0A0_MASK << GPIO0A0_SHIFT, + GPIO0A1_MASK | GPIO0A0_MASK, GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); break; case PERIPH_ID_I2C1: rk_clrsetreg(&grf->gpio0a_iomux, - GPIO0A3_MASK << GPIO0A3_SHIFT | - GPIO0A2_MASK << GPIO0A2_SHIFT, + GPIO0A3_MASK | GPIO0A2_MASK, GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); break; case PERIPH_ID_I2C2: rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C5_MASK << GPIO2C5_SHIFT | - GPIO2C4_MASK << GPIO2C4_SHIFT, + GPIO2C5_MASK | GPIO2C4_MASK, GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); @@ -80,24 +77,20 @@ static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs) { switch (cs) { case 0: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D6_MASK << GPIO1D6_SHIFT, + rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK, GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT); break; case 1: - rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D7_MASK << GPIO1D7_SHIFT, + rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK, GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT); break; } rk_clrsetreg(&grf->gpio1d_iomux, - GPIO1D5_MASK << GPIO1D5_SHIFT | - GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_MASK | GPIO1D4_MASK, GPIO1D5_SPI_TXD << GPIO1D5_SHIFT | GPIO1D4_SPI_RXD << GPIO1D4_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A0_MASK << GPIO2A0_SHIFT, + rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK, GPIO2A0_SPI_CLK << GPIO2A0_SHIFT); } @@ -106,10 +99,8 @@ static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) switch (uart_id) { case PERIPH_ID_UART0: rk_clrsetreg(&grf->gpio0c_iomux, - GPIO0C3_MASK << GPIO0C3_SHIFT | - GPIO0C2_MASK << GPIO0C2_SHIFT | - GPIO0C1_MASK << GPIO0C1_SHIFT | - GPIO0C0_MASK << GPIO0C0_SHIFT, + GPIO0C3_MASK | GPIO0C2_MASK | + GPIO0C1_MASK | GPIO0C0_MASK, GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT | GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT | GPIO0C1_UART0_SIN << GPIO0C1_SHIFT | @@ -117,15 +108,13 @@ static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id) break; case PERIPH_ID_UART1: rk_clrsetreg(&grf->gpio2c_iomux, - GPIO2C7_MASK << GPIO2C7_SHIFT | - GPIO2C6_MASK << GPIO2C6_SHIFT, + GPIO2C7_MASK | GPIO2C6_MASK, GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT | GPIO2C6_UART1_SIN << GPIO2C6_SHIFT); break; case PERIPH_ID_UART2: rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C3_MASK << GPIO1C3_SHIFT | - GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_MASK | GPIO1C2_MASK, GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); break; @@ -146,8 +135,7 @@ static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id) GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); rk_clrsetreg(&grf->gpio2a_iomux, - GPIO2A4_MASK << GPIO2A4_SHIFT | - GPIO2A1_MASK << GPIO2A1_SHIFT, + GPIO2A4_MASK | GPIO2A1_MASK, GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT | GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT); break; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index b6beec5..d0ffeb1 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -21,135 +21,28 @@ struct rk3328_pinctrl_priv { struct rk3328_grf_regs *grf; }; -enum { - /* GRF_GPIO0A_IOMUX */ - GRF_GPIO0A5_SEL_SHIFT = 10, - GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT, - GRF_I2C3_SCL = 2, - - GRF_GPIO0A6_SEL_SHIFT = 12, - GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT, - GRF_I2C3_SDA = 2, - - GRF_GPIO0A7_SEL_SHIFT = 14, - GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT, - GRF_EMMC_DATA0 = 2, - - /* GRF_GPIO1A_IOMUX */ - GRF_GPIO1A0_SEL_SHIFT = 0, - GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT, - GRF_CARD_DATA_CLK_CMD_DETN = 0x1555, - - /* GRF_GPIO2A_IOMUX */ - GRF_GPIO2A0_SEL_SHIFT = 0, - GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, - GRF_UART2_TX_M1 = 1, - - GRF_GPIO2A1_SEL_SHIFT = 2, - GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, - GRF_UART2_RX_M1 = 1, - - GRF_GPIO2A2_SEL_SHIFT = 4, - GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT, - GRF_PWM_IR = 1, - - GRF_GPIO2A4_SEL_SHIFT = 8, - GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT, - GRF_PWM_0 = 1, - GRF_I2C1_SDA, - - GRF_GPIO2A5_SEL_SHIFT = 10, - GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT, - GRF_PWM_1 = 1, - GRF_I2C1_SCL, - - GRF_GPIO2A6_SEL_SHIFT = 12, - GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT, - GRF_PWM_2 = 1, - - GRF_GPIO2A7_SEL_SHIFT = 14, - GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, - GRF_CARD_PWR_EN_M0 = 1, - - /* GRF_GPIO2BL_IOMUX */ - GRF_GPIO2BL0_SEL_SHIFT = 0, - GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT, - GRF_SPI_CLK_TX_RX_M0 = 0x15, - - GRF_GPIO2BL3_SEL_SHIFT = 6, - GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT, - GRF_SPI_CSN0_M0 = 1, - - GRF_GPIO2BL4_SEL_SHIFT = 8, - GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT, - GRF_SPI_CSN1_M0 = 1, - - GRF_GPIO2BL5_SEL_SHIFT = 10, - GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT, - GRF_I2C2_SDA = 1, - - GRF_GPIO2BL6_SEL_SHIFT = 12, - GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT, - GRF_I2C2_SCL = 1, - - /* GRF_GPIO2D_IOMUX */ - GRF_GPIO2D0_SEL_SHIFT = 0, - GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT, - GRF_I2C0_SCL = 1, - - GRF_GPIO2D1_SEL_SHIFT = 2, - GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT, - GRF_I2C0_SDA = 1, - - GRF_GPIO2D4_SEL_SHIFT = 8, - GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT, - GRF_EMMC_DATA123 = 0xaa, - - /* GRF_GPIO3C_IOMUX */ - GRF_GPIO3C0_SEL_SHIFT = 0, - GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT, - GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, - - /* GRF_COM_IOMUX */ - GRF_UART2_IOMUX_SEL_SHIFT = 0, - GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT, - GRF_UART2_IOMUX_SEL_M0 = 0, - GRF_UART2_IOMUX_SEL_M1, - - GRF_SPI_IOMUX_SEL_SHIFT = 4, - GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT, - GRF_SPI_IOMUX_SEL_M0 = 0, - GRF_SPI_IOMUX_SEL_M1, - GRF_SPI_IOMUX_SEL_M2, - - GRF_CARD_IOMUX_SEL_SHIFT = 7, - GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT, - GRF_CARD_IOMUX_SEL_M0 = 0, - GRF_CARD_IOMUX_SEL_M1, -}; - static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id) { switch (pwm_id) { case PERIPH_ID_PWM0: rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A4_SEL_MASK, - GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT); + GPIO2A4_SEL_MASK, + GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT); break; case PERIPH_ID_PWM1: rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A5_SEL_MASK, - GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT); + GPIO2A5_SEL_MASK, + GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT); break; case PERIPH_ID_PWM2: rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A6_SEL_MASK, - GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT); + GPIO2A6_SEL_MASK, + GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT); break; case PERIPH_ID_PWM3: rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A2_SEL_MASK, - GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT); + GPIO2A2_SEL_MASK, + GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT); break; default: debug("pwm id = %d iomux error!\n", pwm_id); @@ -162,27 +55,27 @@ static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id) switch (i2c_id) { case PERIPH_ID_I2C0: rk_clrsetreg(&grf->gpio2d_iomux, - GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK, - GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT - | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT); + GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK, + GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT | + GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT); break; case PERIPH_ID_I2C1: rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK, - GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT - | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT); + GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK, + GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT | + GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT); break; case PERIPH_ID_I2C2: rk_clrsetreg(&grf->gpio2bl_iomux, - GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK, - GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT - | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT); + GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK, + GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT | + GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT); break; case PERIPH_ID_I2C3: rk_clrsetreg(&grf->gpio0a_iomux, - GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK, - GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT - | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT); + GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK, + GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT | + GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT); break; default: debug("i2c id = %d iomux error!\n", i2c_id); @@ -204,29 +97,35 @@ static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id) static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf, enum periph_id spi_id, int cs) { - rk_clrsetreg(&grf->com_iomux, - GRF_SPI_IOMUX_SEL_MASK, - GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT); + u32 com_iomux = readl(&grf->com_iomux); + + if ((com_iomux & IOMUX_SEL_SPI_MASK) != + IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) { + debug("driver do not support iomux other than m0\n"); + goto err; + } switch (spi_id) { case PERIPH_ID_SPI0: switch (cs) { case 0: rk_clrsetreg(&grf->gpio2bl_iomux, - GRF_GPIO2BL3_SEL_MASK, - GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT); + GPIO2BL3_SEL_MASK, + GPIO2BL3_SPI_CSN0_M0 + << GPIO2BL3_SEL_SHIFT); break; case 1: rk_clrsetreg(&grf->gpio2bl_iomux, - GRF_GPIO2BL4_SEL_MASK, - GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT); + GPIO2BL4_SEL_MASK, + GPIO2BL4_SPI_CSN1_M0 + << GPIO2BL4_SEL_SHIFT); break; default: goto err; } rk_clrsetreg(&grf->gpio2bl_iomux, - GRF_GPIO2BL0_SEL_MASK, - GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT); + GPIO2BL0_SEL_MASK, + GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT); break; default: goto err; @@ -240,18 +139,17 @@ err: static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id) { + u32 com_iomux = readl(&grf->com_iomux); + switch (uart_id) { case PERIPH_ID_UART2: break; - /* uart2 iomux select m1 */ - rk_clrsetreg(&grf->com_iomux, - GRF_UART2_IOMUX_SEL_MASK, - GRF_UART2_IOMUX_SEL_M1 - << GRF_UART2_IOMUX_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK, - GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT | - GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT); + if (com_iomux & IOMUX_SEL_UART2_MASK) + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK, + GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT | + GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); + break; case PERIPH_ID_UART0: case PERIPH_ID_UART1: @@ -266,31 +164,37 @@ static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id) static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, int mmc_id) { + u32 com_iomux = readl(&grf->com_iomux); + switch (mmc_id) { case PERIPH_ID_EMMC: rk_clrsetreg(&grf->gpio0a_iomux, - GRF_GPIO0A7_SEL_MASK, - GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT); + GPIO0A7_SEL_MASK, + GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT); rk_clrsetreg(&grf->gpio2d_iomux, - GRF_GPIO2D4_SEL_MASK, - GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT); + GPIO2D4_SEL_MASK, + GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT); rk_clrsetreg(&grf->gpio3c_iomux, - GRF_GPIO3C0_SEL_MASK, - GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD - << GRF_GPIO3C0_SEL_SHIFT); + GPIO3C0_SEL_MASK, + GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD + << GPIO3C0_SEL_SHIFT); break; case PERIPH_ID_SDCARD: - /* sdcard iomux select m0 */ - rk_clrsetreg(&grf->com_iomux, - GRF_CARD_IOMUX_SEL_MASK, - GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2a_iomux, - GRF_GPIO2A7_SEL_MASK, - GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT); + /* SDMMC_PWREN use GPIO and init as regulator-fiexed */ + if (com_iomux & IOMUX_SEL_SDMMC_MASK) + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D6_SEL_MASK, + GPIO0D6_SDMMC0_PWRENM1 + << GPIO0D6_SEL_SHIFT); + else + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A7_SEL_MASK, + GPIO2A7_SDMMC0_PWRENM0 + << GPIO2A7_SEL_SHIFT); rk_clrsetreg(&grf->gpio1a_iomux, - GRF_GPIO1A0_SEL_MASK, - GRF_CARD_DATA_CLK_CMD_DETN - << GRF_GPIO1A0_SEL_SHIFT); + GPIO1A0_SEL_MASK, + GPIO1A0_CARD_DATA_CLK_CMD_DETN + << GPIO1A0_SEL_SHIFT); break; default: debug("mmc id = %d iomux error!\n", mmc_id); diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c new file mode 100644 index 0000000..bdf0758 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3368_pinctrl_priv { + struct rk3368_grf *grf; + struct rk3368_pmu_grf *pmugrf; +}; + +static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv, + int uart_id) +{ + struct rk3368_grf *grf = priv->grf; + struct rk3368_pmu_grf *pmugrf = priv->pmugrf; + + switch (uart_id) { + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A6_MASK | GPIO2A5_MASK, + GPIO2A6_UART2_SIN << GPIO2A6_SHIFT | + GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT); + break; + case PERIPH_ID_UART0: + break; + case PERIPH_ID_UART1: + break; + case PERIPH_ID_UART3: + break; + case PERIPH_ID_UART4: + rk_clrsetreg(&pmugrf->gpio0d_iomux, + GPIO0D0_MASK | GPIO0D1_MASK | + GPIO0D2_MASK | GPIO0D3_MASK, + GPIO0D0_GPIO << GPIO0D0_SHIFT | + GPIO0D1_GPIO << GPIO0D1_SHIFT | + GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT | + GPIO0D3_UART4_SIN << GPIO0D3_SHIFT); + break; + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%d, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3368_uart_config(priv, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3368_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 59: + return PERIPH_ID_UART4; + case 58: + return PERIPH_ID_UART3; + case 57: + return PERIPH_ID_UART2; + case 56: + return PERIPH_ID_UART1; + case 55: + return PERIPH_ID_UART0; + } + + return -ENOENT; +} + +static int rk3368_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3368_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + + return rk3368_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3368_pinctrl_ops = { + .set_state_simple = rk3368_pinctrl_set_state_simple, + .request = rk3368_pinctrl_request, + .get_periph_id = rk3368_pinctrl_get_periph_id, +}; + +static int rk3368_pinctrl_probe(struct udevice *dev) +{ + struct rk3368_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf); + + return ret; +} + +static const struct udevice_id rk3368_pinctrl_ids[] = { + { .compatible = "rockchip,rk3368-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3368) = { + .name = "rockchip_rk3368_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3368_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv), + .ops = &rk3368_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk3368_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c new file mode 100644 index 0000000..bdf3910 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct rv1108_pinctrl_priv { + struct rv1108_grf *grf; +}; + +static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A6_MASK | GPIO3A5_MASK, + GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT | + GPIO3A5_UART1_SIN << GPIO3A5_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK | + GPIO1D0_MASK, + GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT | + GPIO1D2_UART0_SIN << GPIO1D2_SHIFT | + GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT | + GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D2_MASK | GPIO2D1_MASK, + GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | + GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); + break; + } +} + +static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func) +{ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK | + GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK, + GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT | + GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT | + GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT | + GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT | + GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT | + GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT); + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C5_MASK | GPIO1C4_MASK | + GPIO1C3_MASK | GPIO1C2_MASK, + GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT | + GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT | + GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT | + GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT); + writel(0xffff57f5, &grf->gpio1b_drv); +} + +static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf) +{ + rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK | + GPIO2A1_MASK | GPIO2A0_MASK, + GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT | + GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT | + GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT | + GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT); + rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK, + GPIO2B7_SFC_CLK << GPIO2B7_SHIFT | + GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT); +} + +static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rv1108_pinctrl_priv *priv = dev_get_priv(dev); + + switch (func) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + pinctrl_rv1108_uart_config(priv->grf, func); + break; + case PERIPH_ID_GMAC: + pinctrl_rv1108_gmac_config(priv->grf, func); + case PERIPH_ID_SFC: + pinctrl_rv1108_sfc_config(priv->grf); + default: + return -EINVAL; + } + + return 0; +} + +static int rv1108_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 11: + return PERIPH_ID_SDCARD; + case 13: + return PERIPH_ID_EMMC; + case 19: + return PERIPH_ID_GMAC; + case 30: + return PERIPH_ID_I2C0; + case 31: + return PERIPH_ID_I2C1; + case 32: + return PERIPH_ID_I2C2; + case 39: + return PERIPH_ID_PWM0; + case 44: + return PERIPH_ID_UART0; + case 45: + return PERIPH_ID_UART1; + case 46: + return PERIPH_ID_UART2; + case 56: + return PERIPH_ID_SFC; + } + + return -ENOENT; +} + +static int rv1108_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rv1108_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + + return rv1108_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rv1108_pinctrl_ops = { + .set_state_simple = rv1108_pinctrl_set_state_simple, + .request = rv1108_pinctrl_request, + .get_periph_id = rv1108_pinctrl_get_periph_id, +}; + +static int rv1108_pinctrl_probe(struct udevice *dev) +{ + struct rv1108_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + return 0; +} + +static const struct udevice_id rv1108_pinctrl_ids[] = { + {.compatible = "rockchip,rv1108-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rv1108) = { + .name = "pinctrl_rv1108", + .id = UCLASS_PINCTRL, + .of_match = rv1108_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv), + .ops = &rv1108_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rv1108_pinctrl_probe, +}; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 3f50c12..e3f9e4d 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -188,6 +188,13 @@ config PMIC_LP873X The LP873X is a PMIC containing couple of LDOs and couple of SMPS. This driver binds the pmic children. +config PMIC_LP87565 + bool "Enable driver for Texas Instruments LP87565 PMIC" + depends on DM_PMIC + ---help--- + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children. + config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" ---help--- diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index f409e3a..f488799 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o +obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c new file mode 100644 index 0000000..782a46c --- /dev/null +++ b/drivers/power/pmic/lp87565.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2017 Texas Instruments Incorporated, + * Keerthy + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "buck", .driver = LP87565_BUCK_DRIVER }, + { }, +}; + +static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) + error("write error to device: %p register: %#x!", dev, reg); + + return ret; +} + +static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) + error("read error from device: %p register: %#x!", dev, reg); + + return ret; +} + +static int lp87565_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children; + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + printf("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops lp87565_ops = { + .read = lp87565_read, + .write = lp87565_write, +}; + +static const struct udevice_id lp87565_ids[] = { + { .compatible = "ti,lp87565", .data = LP87565 }, + { .compatible = "ti,lp87565-q1", .data = LP87565_Q1 }, + { } +}; + +U_BOOT_DRIVER(pmic_lp87565) = { + .name = "lp87565_pmic", + .id = UCLASS_PMIC, + .of_match = lp87565_ids, + .bind = lp87565_bind, + .ops = &lp87565_ops, +}; diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index c5e768a..911f639 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -96,7 +96,8 @@ int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) { if ((dc_cntrl_reg != TPS65218_DCDC1) && - (dc_cntrl_reg != TPS65218_DCDC2)) + (dc_cntrl_reg != TPS65218_DCDC2) && + (dc_cntrl_reg != TPS65218_DCDC3)) return 1; /* set voltage level */ diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 09b9b54..eb3ec0f 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -111,6 +111,7 @@ U_BOOT_DRIVER(pmic_rk8xx) = { #if CONFIG_IS_ENABLED(PMIC_CHILDREN) .bind = rk8xx_bind, #endif + .priv_auto_alloc_size = sizeof(struct rk8xx_priv), .probe = rk8xx_probe, .ops = &rk8xx_ops, }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index ef057e0..f213487 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -149,3 +149,13 @@ config DM_REGULATOR_LP873X This enables implementation of driver-model regulator uclass features for REGULATOR LP873X and the family of LP873X PMICs. The driver implements get/set api for: value and enable. + +config DM_REGULATOR_LP87565 + bool "Enable driver for LP87565 PMIC regulators" + depends on PMIC_LP87565 + ---help--- + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 3e01021..ce14d08 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c new file mode 100644 index 0000000..2a0b8ca --- /dev/null +++ b/drivers/power/regulator/lp87565_regulator.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2017 + * Texas Instruments Incorporated, + * + * Keerthy + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6}; +static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE }; + +static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable) +{ + int ret; + unsigned int adr; + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + adr = uc_pdata->ctrl_reg; + + ret = pmic_reg_read(dev->parent, adr); + if (ret < 0) + return ret; + + if (op == PMIC_OP_GET) { + ret &= LP87565_BUCK_MODE_MASK; + + if (ret) + *enable = true; + else + *enable = false; + + return 0; + } else if (op == PMIC_OP_SET) { + if (*enable) + ret |= LP87565_BUCK_MODE_MASK; + else + ret &= ~LP87565_BUCK_MODE_MASK; + ret = pmic_reg_write(dev->parent, adr, ret); + if (ret) + return ret; + } + + return 0; +} + +static int lp87565_buck_volt2val(int uV) +{ + if (uV > LP87565_BUCK_VOLT_MAX) + return -EINVAL; + else if (uV > 1400000) + return (uV - 1420000) / 20000 + 0x9E; + else if (uV > 730000) + return (uV - 735000) / 5000 + 0x18; + else if (uV >= 500000) + return (uV - 500000) / 10000; + else + return -EINVAL; +} + +static int lp87565_buck_val2volt(int val) +{ + if (val > LP87565_BUCK_VOLT_MAX_HEX) + return -EINVAL; + else if (val > 0x9D) + return 1400000 + (val - 0x9D) * 20000; + else if (val > 0x17) + return 730000 + (val - 0x17) * 5000; + else if (val >= 0x0) + return 500000 + val * 10000; + else + return -EINVAL; +} + +static int lp87565_buck_val(struct udevice *dev, int op, int *uV) +{ + unsigned int hex, adr; + int ret; + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + + if (op == PMIC_OP_GET) + *uV = 0; + + adr = uc_pdata->volt_reg; + + ret = pmic_reg_read(dev->parent, adr); + if (ret < 0) + return ret; + + if (op == PMIC_OP_GET) { + ret &= LP87565_BUCK_VOLT_MASK; + ret = lp87565_buck_val2volt(ret); + if (ret < 0) + return ret; + *uV = ret; + + return 0; + } + + hex = lp87565_buck_volt2val(*uV); + if (hex < 0) + return hex; + + ret &= 0x0; + ret = hex; + + ret = pmic_reg_write(dev->parent, adr, ret); + + return ret; +} + +static int lp87565_buck_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + int idx; + + uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata->type = REGULATOR_TYPE_BUCK; + + idx = dev->driver_data; + if (idx == 0 || idx == 1 || idx == 2 || idx == 3) { + debug("Single phase regulator\n"); + } else if (idx == 23) { + idx = 5; + } else if (idx == 10) { + idx = 4; + } else { + printf("Wrong ID for regulator\n"); + return -EINVAL; + } + + uc_pdata->ctrl_reg = lp87565_buck_ctrl1[idx]; + uc_pdata->volt_reg = lp87565_buck_vout[idx]; + + return 0; +} + +static int buck_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = lp87565_buck_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int buck_set_value(struct udevice *dev, int uV) +{ + return lp87565_buck_val(dev, PMIC_OP_SET, &uV); +} + +static bool buck_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + + ret = lp87565_buck_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int buck_set_enable(struct udevice *dev, bool enable) +{ + return lp87565_buck_enable(dev, PMIC_OP_SET, &enable); +} + +static const struct dm_regulator_ops lp87565_buck_ops = { + .get_value = buck_get_value, + .set_value = buck_set_value, + .get_enable = buck_get_enable, + .set_enable = buck_set_enable, +}; + +U_BOOT_DRIVER(lp87565_buck) = { + .name = LP87565_BUCK_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &lp87565_buck_ops, + .probe = lp87565_buck_probe, +}; diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c index 399f7a5..841c03a 100644 --- a/drivers/power/regulator/palmas_regulator.c +++ b/drivers/power/regulator/palmas_regulator.c @@ -377,7 +377,11 @@ static int palmas_smps_probe(struct udevice *dev) uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx]; uc_pdata->volt_reg = palmas_smps_volt[type][idx]; break; - + case 12: + idx = 0; + uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx]; + uc_pdata->volt_reg = palmas_smps_volt[type][idx]; + break; default: printf("Wrong ID for regulator\n"); } diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c index a6c9fcc..00a7cca 100644 --- a/drivers/power/regulator/pwm_regulator.c +++ b/drivers/power/regulator/pwm_regulator.c @@ -32,13 +32,13 @@ struct pwm_regulator_info { bool polarity; struct udevice *pwm; /* initialize voltage of regulator */ - unsigned int init_voltage; + int init_voltage; /* the maximum voltage of regulator */ - unsigned int max_voltage; + int max_voltage; /* the minimum voltage of regulator */ - unsigned int min_voltage; + int min_voltage; /* the current voltage of regulator */ - unsigned int volt_uV; + int volt_uV; }; static int pwm_regulator_enable(struct udevice *dev, bool enable) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index a42f80b..0a1d1b3 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -146,8 +146,10 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; ret = uclass_find_next_device(&dev)) { - if (ret) + if (ret) { + debug("regulator %s, ret=%d\n", dev->name, ret); continue; + } uc_pdata = dev_get_uclass_platdata(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) @@ -156,7 +158,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) return uclass_get_device_tail(dev, 0, devp); } - debug("%s: can't find: %s\n", __func__, plat_name); + debug("%s: can't find: %s, ret=%d\n", __func__, plat_name, ret); return -ENODEV; } @@ -219,7 +221,7 @@ int regulator_autoset_by_name(const char *platname, struct udevice **devp) if (devp) *devp = dev; if (ret) { - debug("Can get the regulator: %s!", platname); + debug("Can get the regulator: %s (err=%d)\n", platname, ret); return ret; } diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index e655c2d..c1ece96 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -92,9 +92,9 @@ static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, struct rk8xx_priv *priv = dev_get_priv(pmic); switch (priv->variant) { case RK818_ID: - return &rk818_ldo[num - 1]; + return &rk818_ldo[num]; default: - return &rk808_ldo[num - 1]; + return &rk808_ldo[num]; } } diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 59eae09..28de62d 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -92,6 +92,7 @@ static int rk_pwm_probe(struct udevice *dev) return -EINVAL; } priv->freq = clk_get_rate(&clk); + priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; return 0; } diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index b640519..902de2b 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -132,8 +132,8 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) static int stm32_fmc_probe(struct udevice *dev) { -#ifdef CONFIG_CLK int ret; +#ifdef CONFIG_CLK struct clk clk; ret = clk_get_by_index(dev, 0, &clk); diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index 0c32a3d..a79708c 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -30,6 +30,8 @@ struct sti_reset { * @reset_bit: Bit number in reset register. * @ack_offset: Ack reset register offset in syscon bank. * @ack_bit: Bit number in Ack reset register. + * @deassert_cnt: incremented when reset is deasserted, reset can only be + * asserted when equal to 0 */ struct syscfg_reset_channel_data { @@ -38,6 +40,7 @@ struct syscfg_reset_channel_data { int reset_bit; int ack_offset; int ack_bit; + int deassert_cnt; }; /** @@ -54,7 +57,7 @@ struct syscfg_reset_controller_data { bool wait_for_ack; bool active_low; int nr_channels; - const struct syscfg_reset_channel_data *channels; + struct syscfg_reset_channel_data *channels; }; /* STiH407 Peripheral powerdown definitions. */ @@ -102,7 +105,7 @@ static const char stih407_lpm[] = "st,stih407-lpm-syscfg"; #define SYSSTAT_4520 0x820 #define SYSCFG_4002 0x8 -static const struct syscfg_reset_channel_data stih407_powerdowns[] = { +static struct syscfg_reset_channel_data stih407_powerdowns[] = { [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), @@ -122,7 +125,7 @@ static const struct syscfg_reset_channel_data stih407_powerdowns[] = { #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ -static const struct syscfg_reset_channel_data stih407_softresets[] = { +static struct syscfg_reset_channel_data stih407_softresets[] = { [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), @@ -161,7 +164,7 @@ static const struct syscfg_reset_channel_data stih407_softresets[] = { /* PicoPHY reset/control */ #define SYSCFG_5061 0x0f4 -static const struct syscfg_reset_channel_data stih407_picophyresets[] = { +static struct syscfg_reset_channel_data stih407_picophyresets[] = { [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), @@ -223,7 +226,7 @@ static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert) struct udevice *dev = reset_ctl->dev; struct syscfg_reset_controller_data *reset_desc = (struct syscfg_reset_controller_data *)(dev->driver_data); - struct syscfg_reset_channel_data ch; + struct syscfg_reset_channel_data *ch; phys_addr_t base; u32 ctrl_val = reset_desc->active_low ? !assert : !!assert; void __iomem *reg; @@ -235,19 +238,35 @@ static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert) /* get reset sysconf register base address */ base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible); - ch = reset_desc->channels[reset_ctl->id]; - reg = (void __iomem *)base + ch.reset_offset; + ch = &reset_desc->channels[reset_ctl->id]; + + /* check the deassert counter to assert reset when it reaches 0 */ + if (!assert) { + ch->deassert_cnt++; + if (ch->deassert_cnt > 1) + return 0; + } else { + if (ch->deassert_cnt > 0) { + ch->deassert_cnt--; + if (ch->deassert_cnt > 0) + return 0; + } else + error("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n", + reset_ctl, reset_ctl->dev, reset_ctl->id); + } + + reg = (void __iomem *)base + ch->reset_offset; if (ctrl_val) - generic_set_bit(ch.reset_bit, reg); + generic_set_bit(ch->reset_bit, reg); else - generic_clear_bit(ch.reset_bit, reg); + generic_clear_bit(ch->reset_bit, reg); if (!reset_desc->wait_for_ack) return 0; - reg = (void __iomem *)base + ch.ack_offset; - if (wait_for_bit(__func__, reg, BIT(ch.ack_bit), ctrl_val, + reg = (void __iomem *)base + ch->ack_offset; + if (wait_for_bit(__func__, reg, BIT(ch->ack_bit), ctrl_val, 1000, false)) { error("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n", reset_ctl, reset_ctl->dev, reset_ctl->id); diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 438681d..003e31a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -38,8 +38,6 @@ obj-$(CONFIG_RTC_MC146818) += mc146818.o obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o obj-$(CONFIG_RTC_MK48T59) += mk48t59.o -obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o -obj-$(CONFIG_RTC_MPC8xx) += mpc8xx.o obj-$(CONFIG_RTC_MV) += mvrtc.o obj-$(CONFIG_RTC_MX27) += mx27rtc.o obj-$(CONFIG_RTC_MXS) += mxsrtc.o diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index dae1b3c..4b73d17 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -150,11 +150,11 @@ int rtc_set (struct rtc_time *tmp) * SQW/INTB* pin and program it for 32,768 Hz output. Note that * according to the datasheet, turning on the square wave output * increases the current drain on the backup battery from about - * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn + * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn * off the OSC output. */ -#ifdef CONFIG_SYS_RTC_DS1337_NOOSC +#ifdef CONFIG_RTC_DS1337_NOOSC #define RTC_DS1337_RESET_VAL \ (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #else @@ -162,16 +162,16 @@ int rtc_set (struct rtc_time *tmp) #endif void rtc_reset (void) { -#ifdef CONFIG_SYS_RTC_DS1337 +#ifdef CONFIG_RTC_DS1337 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); -#elif defined CONFIG_SYS_RTC_DS1388 +#elif defined CONFIG_RTC_DS1388 rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */ #endif -#ifdef CONFIG_SYS_DS1339_TCR_VAL - rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL); +#ifdef CONFIG_RTC_DS1339_TCR_VAL + rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); #endif -#ifdef CONFIG_SYS_DS1388_TCR_VAL - rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL); +#ifdef CONFIG_RTC_DS1388_TCR_VAL + rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); #endif } diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c deleted file mode 100644 index 929783e..0000000 --- a/drivers/rtc/mpc5xxx.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2004 - * Reinhard Meyer, EMK Elektronik GmbH - * r.meyer@emk-elektronik.de - * www.emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/***************************************************************************** - * Date & Time support for internal RTC of MPC52xx - *****************************************************************************/ -/*#define DEBUG*/ - -#include -#include -#include - -#if defined(CONFIG_CMD_DATE) - -/***************************************************************************** - * this structure should be defined in mpc5200.h ... - *****************************************************************************/ -typedef struct rtc5200 { - volatile ulong tsr; /* MBAR+0x800: time set register */ - volatile ulong dsr; /* MBAR+0x804: data set register */ - volatile ulong nysr; /* MBAR+0x808: new year and stopwatch register */ - volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */ - volatile ulong ctr; /* MBAR+0x810: current time register */ - volatile ulong cdr; /* MBAR+0x814: current data register */ - volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */ - volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */ - volatile ulong trdr; /* MBAR+0x820: test register/divides register */ -} RTC5200; - -#define RTC_SET 0x02000000 -#define RTC_PAUSE 0x01000000 - -/***************************************************************************** - * get time - *****************************************************************************/ -int rtc_get (struct rtc_time *tmp) -{ - RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800); - ulong time, date, time2; - - /* read twice to avoid getting a funny time when the second is just changing */ - do { - time = rtc->ctr; - date = rtc->cdr; - time2 = rtc->ctr; - } while (time != time2); - - tmp->tm_year = date & 0xfff; - tmp->tm_mon = (date >> 24) & 0xf; - tmp->tm_mday = (date >> 16) & 0x1f; - tmp->tm_wday = (date >> 21) & 7; - /* sunday is 7 in 5200 but 0 in rtc_time */ - if (tmp->tm_wday == 7) - tmp->tm_wday = 0; - tmp->tm_hour = (time >> 16) & 0x1f; - tmp->tm_min = (time >> 8) & 0x3f; - tmp->tm_sec = time & 0x3f; - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/***************************************************************************** - * set time - *****************************************************************************/ -int rtc_set (struct rtc_time *tmp) -{ - RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800); - ulong time, date, year; - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - time = (tmp->tm_hour << 16) | (tmp->tm_min << 8) | tmp->tm_sec; - date = (tmp->tm_mon << 16) | tmp->tm_mday; - if (tmp->tm_wday == 0) - date |= (7 << 8); - else - date |= (tmp->tm_wday << 8); - year = tmp->tm_year; - - /* mask unwanted bits that might show up when rtc_time is corrupt */ - time &= 0x001f3f3f; - date &= 0x001f071f; - year &= 0x00000fff; - - /* pause and set the RTC */ - rtc->nysr = year; - rtc->dsr = date | RTC_PAUSE; - udelay (1000); - rtc->dsr = date | RTC_PAUSE | RTC_SET; - udelay (1000); - rtc->dsr = date | RTC_PAUSE; - udelay (1000); - rtc->dsr = date; - udelay (1000); - - rtc->tsr = time | RTC_PAUSE; - udelay (1000); - rtc->tsr = time | RTC_PAUSE | RTC_SET; - udelay (1000); - rtc->tsr = time | RTC_PAUSE; - udelay (1000); - rtc->tsr = time; - udelay (1000); - - return 0; -} - -/***************************************************************************** - * reset rtc circuit - *****************************************************************************/ -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#endif diff --git a/drivers/rtc/mpc8xx.c b/drivers/rtc/mpc8xx.c deleted file mode 100644 index 147a225..0000000 --- a/drivers/rtc/mpc8xx.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Date & Time support for internal RTC of MPC8xx - */ - -/*#define DEBUG*/ - -#include -#include -#include - -#if defined(CONFIG_CMD_DATE) - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong tim; - - tim = immr->im_sit.sit_rtc; - - rtc_to_tm(tim, tmp); - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong tim; - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - tim = rtc_mktime(tmp); - - immr->im_sitk.sitk_rtck = KAPWR_KEY; - immr->im_sit.sit_rtc = tim; - - return 0; -} - -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index f1bd15b..f2bd0e4 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -133,7 +133,6 @@ serial_initfunc(marvell_serial_initialize); serial_initfunc(max3100_serial_initialize); serial_initfunc(mcf_serial_initialize); serial_initfunc(ml2_serial_initialize); -serial_initfunc(mpc512x_serial_initialize); serial_initfunc(mpc5xx_serial_initialize); serial_initfunc(mpc8260_scc_serial_initialize); serial_initfunc(mpc8260_smc_serial_initialize); @@ -224,10 +223,6 @@ void serial_initialize(void) max3100_serial_initialize(); mcf_serial_initialize(); ml2_serial_initialize(); - mpc512x_serial_initialize(); - mpc5xx_serial_initialize(); - mpc8260_scc_serial_initialize(); - mpc8260_smc_serial_initialize(); mpc85xx_serial_initialize(); mpc8xx_serial_initialize(); mxc_serial_initialize(); diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index bdabf87..61e8167 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -20,7 +20,7 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate) { struct stm32x7_serial_platdata *plat = dev->platdata; struct stm32_usart *const usart = plat->base; - u32 clock, int_div, frac_div, tmp; + u32 clock, int_div, mantissa, fraction, oversampling; if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE) clock = clock_get(CLOCK_APB1); @@ -29,11 +29,20 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate) else return -EINVAL; - int_div = (25 * clock) / (4 * baudrate); - tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK; - frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT)); - tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK; - writel(tmp, &usart->brr); + int_div = DIV_ROUND_CLOSEST(clock, baudrate); + + if (int_div < 16) { + oversampling = 8; + setbits_le32(&usart->cr1, USART_CR1_OVER8); + } else { + oversampling = 16; + clrbits_le32(&usart->cr1, USART_CR1_OVER8); + } + + mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT; + fraction = int_div % oversampling; + + writel(mantissa | fraction, &usart->brr); return 0; } @@ -93,6 +102,9 @@ static int stm32_serial_probe(struct udevice *dev) } #endif + /* Disable usart-> disable overrun-> enable usart */ + clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); + setbits_le32(&usart->cr3, USART_CR3_OVRDIS); setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); return 0; @@ -100,8 +112,8 @@ static int stm32_serial_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_CONTROL) static const struct udevice_id stm32_serial_id[] = { - {.compatible = "st,stm32-usart"}, - {.compatible = "st,stm32-uart"}, + {.compatible = "st,stm32f7-usart"}, + {.compatible = "st,stm32f7-uart"}, {} }; diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h index 6190d67..facfdba 100644 --- a/drivers/serial/serial_stm32x7.h +++ b/drivers/serial/serial_stm32x7.h @@ -23,10 +23,13 @@ struct stm32_usart { }; -#define USART_CR1_RE (1 << 2) +#define USART_CR1_OVER8 (1 << 15) #define USART_CR1_TE (1 << 3) +#define USART_CR1_RE (1 << 2) #define USART_CR1_UE (1 << 0) +#define USART_CR3_OVRDIS (1 << 12) + #define USART_SR_FLAG_RXNE (1 << 5) #define USART_SR_FLAG_TXE (1 << 7) diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 802117e..9165934 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -152,6 +152,7 @@ static int tegra114_spi_probe(struct udevice *bus) bus->name, priv->freq, rate); } } + udelay(plat->deactivate_delay_us); /* Clear stale status here */ setbits_le32(®s->fifo_status, diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index b683811..a5200d3 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -15,7 +15,9 @@ endif obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o +obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o +obj-$(CONFIG_ROCKCHIP_RV1108) += sysreset_rv1108.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o diff --git a/drivers/sysreset/sysreset_rk3368.c b/drivers/sysreset/sysreset_rk3368.c new file mode 100644 index 0000000..de62921 --- /dev/null +++ b/drivers/sysreset/sysreset_rk3368.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru) +{ + struct rk3368_pll *pll; + int i; + + for (i = 0; i < 6; i++) { + pll = &cru->pll[i]; + rk_clrreg(&pll->con3, PLL_MODE_MASK); + } +} + +static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3368_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + rk3368_pll_enter_slow_mode(cru); + rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK, + PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT); + writel(0xeca8, &cru->glb_srst_snd_val); + break; + case SYSRESET_COLD: + rk3368_pll_enter_slow_mode(cru); + rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK, + PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT); + writel(0xfdb9, &cru->glb_srst_fst_val); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3368_sysreset = { + .request = rk3368_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3368) = { + .name = "rk3368_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3368_sysreset, +}; diff --git a/drivers/sysreset/sysreset_rv1108.c b/drivers/sysreset/sysreset_rv1108.c new file mode 100644 index 0000000..9d8e9f7 --- /dev/null +++ b/drivers/sysreset/sysreset_rv1108.c @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * Author: Andy Yan + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rv1108_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->glb_srst_snd_val); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->glb_srst_fst_val); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rv1108_sysreset = { + .request = rv1108_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rv1108) = { + .name = "rv1108_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rv1108_sysreset, +}; diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 338ac08..4e642ae 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -9,6 +9,10 @@ #include #include #include +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ + defined(CONFIG_ARM) +#include +#endif /* USB Erratum Checking code */ #if defined(CONFIG_PPC) || defined(CONFIG_ARM) diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 0fbbb7c..5e316a7 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -41,7 +41,6 @@ ifdef CONFIG_USB_DEVICE obj-y += core.o obj-y += ep0.o obj-$(CONFIG_DW_UDC) += designware_udc.o -obj-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o endif endif diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index f5bc277..01a5907 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -1386,11 +1386,6 @@ static void at91rm9200_udc_pullup(struct at91_udc *udc, int is_on) gpio_set_value(udc->board.pullup_pin, !active); } -static const struct at91_udc_caps at91rm9200_udc_caps = { - .init = at91rm9200_udc_init, - .pullup = at91rm9200_udc_pullup, -}; - static int at91sam9260_udc_init(struct at91_udc *udc) { struct at91_ep *ep; @@ -1503,11 +1498,6 @@ static int at91sam9263_udc_init(struct at91_udc *udc) return 0; } -static const struct at91_udc_caps at91sam9263_udc_caps = { - .init = at91sam9263_udc_init, - .pullup = at91sam9260_udc_pullup, -}; - int usb_gadget_handle_interrupts(int index) { struct at91_udc *udc = controller; diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 973cd97..f320708 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -91,12 +91,6 @@ #define gadget_is_atmel_usba(g) 0 #endif -#ifdef CONFIG_USB_GADGET_S3C2410 -#define gadget_is_s3c2410(g) (!strcmp("s3c2410_udc", (g)->name)) -#else -#define gadget_is_s3c2410(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_AT91 #define gadget_is_at91(g) (!strcmp("at91_udc", (g)->name)) #else @@ -131,13 +125,6 @@ #define gadget_is_musbhdrc(g) 0 #endif -/* from Montavista kernel (?) */ -#ifdef CONFIG_USB_GADGET_MPC8272 -#define gadget_is_mpc8272(g) (!strcmp("mpc8272_udc", (g)->name)) -#else -#define gadget_is_mpc8272(g) 0 -#endif - #ifdef CONFIG_USB_GADGET_M66592 #define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name)) #else @@ -207,8 +194,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x09; else if (gadget_is_pxa27x(gadget)) return 0x10; - else if (gadget_is_s3c2410(gadget)) - return 0x11; else if (gadget_is_at91(gadget)) return 0x12; else if (gadget_is_imx(gadget)) @@ -217,8 +202,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x14; else if (gadget_is_musbhdrc(gadget)) return 0x15; - else if (gadget_is_mpc8272(gadget)) - return 0x16; else if (gadget_is_atmel_usba(gadget)) return 0x17; else if (gadget_is_fsl_usb2(gadget)) diff --git a/drivers/usb/gadget/mpc8xx_udc.c b/drivers/usb/gadget/mpc8xx_udc.c deleted file mode 100644 index ad5ea7a..0000000 --- a/drivers/usb/gadget/mpc8xx_udc.c +++ /dev/null @@ -1,1386 +0,0 @@ -/* - * Copyright (C) 2006 by Bryan O'Donoghue, CodeHermit - * bodonoghue@CodeHermit.ie - * - * References - * DasUBoot/drivers/usb/gadget/omap1510_udc.c, for design and implementation - * ideas. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Notes : - * 1. #define __SIMULATE_ERROR__ to inject a CRC error into every 2nd TX - * packet to force the USB re-transmit protocol. - * - * 2. #define __DEBUG_UDC__ to switch on debug tracing to serial console - * be careful that tracing doesn't create Hiesen-bugs with respect to - * response timeouts to control requests. - * - * 3. This driver should be able to support any higher level driver that - * that wants to do either of the two standard UDC implementations - * Control-Bulk-Interrupt or Bulk-IN/Bulk-Out standards. Hence - * gserial and cdc_acm should work with this code. - * - * 4. NAK events never actually get raised at all, the documentation - * is just wrong ! - * - * 5. For some reason, cbd_datlen is *always* +2 the value it should be. - * this means that having an RX cbd of 16 bytes is not possible, since - * the same size is reported for 14 bytes received as 16 bytes received - * until we can find out why this happens, RX cbds must be limited to 8 - * bytes. TODO: check errata for this behaviour. - * - * 6. Right now this code doesn't support properly powering up with the USB - * cable attached to the USB host my development board the Adder87x doesn't - * have a pull-up fitted to allow this, so it is necessary to power the - * board and *then* attached the USB cable to the host. However somebody - * with a different design in their board may be able to keep the cable - * constantly connected and simply enable/disable a pull-up re - * figure 31.1 in MPC885RM.pdf instead of having to power up the board and - * then attach the cable ! - * - */ -#include -#include -#include -#include -#include -#include - -#include "ep0.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define ERR(fmt, args...)\ - serial_printf("ERROR : [%s] %s:%d: "fmt,\ - __FILE__,__FUNCTION__,__LINE__, ##args) -#ifdef __DEBUG_UDC__ -#define DBG(fmt,args...)\ - serial_printf("[%s] %s:%d: "fmt,\ - __FILE__,__FUNCTION__,__LINE__, ##args) -#else -#define DBG(fmt,args...) -#endif - -/* Static Data */ -#ifdef __SIMULATE_ERROR__ -static char err_poison_test = 0; -#endif -static struct mpc8xx_ep ep_ref[MAX_ENDPOINTS]; -static u32 address_base = STATE_NOT_READY; -static mpc8xx_udc_state_t udc_state = 0; -static struct usb_device_instance *udc_device = 0; -static volatile usb_epb_t *endpoints[MAX_ENDPOINTS]; -static volatile cbd_t *tx_cbd[TX_RING_SIZE]; -static volatile cbd_t *rx_cbd[RX_RING_SIZE]; -static volatile immap_t *immr = 0; -static volatile cpm8xx_t *cp = 0; -static volatile usb_pram_t *usb_paramp = 0; -static volatile usb_t *usbp = 0; -static int rx_ct = 0; -static int tx_ct = 0; - -/* Static Function Declarations */ -static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final); -static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final); -static void mpc8xx_udc_stall (unsigned int ep); -static void mpc8xx_udc_flush_tx_fifo (int epid); -static void mpc8xx_udc_flush_rx_fifo (void); -static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, - struct urb *tx_urb); -static void mpc8xx_udc_dump_request (struct usb_device_request *request); -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp); -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi); -static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_cbd_init (void); -static void mpc8xx_udc_endpoint_init (void); -static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size); -static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment); -static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp); -static void mpc8xx_udc_set_nak (unsigned int ep); -static short mpc8xx_udc_handle_txerr (void); -static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid); - -/****************************************************************************** - Global Linkage - *****************************************************************************/ - -/* udc_init - * - * Do initial bus gluing - */ -int udc_init (void) -{ - /* Init various pointers */ - immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8xx_t *) & (immr->im_cpm); - usb_paramp = (usb_pram_t *) & (cp->cp_dparam[PROFF_USB]); - usbp = (usb_t *) & (cp->cp_scc[0]); - - memset (ep_ref, 0x00, (sizeof (struct mpc8xx_ep) * MAX_ENDPOINTS)); - - udc_device = 0; - udc_state = STATE_NOT_READY; - - usbp->usmod = 0x00; - usbp->uscom = 0; - - /* Set USB Frame #0, Respond at Address & Get a clock source */ - usbp->usaddr = 0x00; - mpc8xx_udc_clock_init (immr, cp); - - /* PA15, PA14 as perhiperal USBRXD and USBOE */ - immr->im_ioport.iop_padir &= ~0x0003; - immr->im_ioport.iop_papar |= 0x0003; - - /* PC11/PC10 as peripheral USBRXP USBRXN */ - immr->im_ioport.iop_pcso |= 0x0030; - - /* PC7/PC6 as perhiperal USBTXP and USBTXN */ - immr->im_ioport.iop_pcdir |= 0x0300; - immr->im_ioport.iop_pcpar |= 0x0300; - - /* Set the base address */ - address_base = (u32) (cp->cp_dpmem + CPM_USB_BASE); - - /* Initialise endpoints and circular buffers */ - mpc8xx_udc_endpoint_init (); - mpc8xx_udc_cbd_init (); - - /* Assign allocated Dual Port Endpoint descriptors */ - usb_paramp->ep0ptr = (u32) endpoints[0]; - usb_paramp->ep1ptr = (u32) endpoints[1]; - usb_paramp->ep2ptr = (u32) endpoints[2]; - usb_paramp->ep3ptr = (u32) endpoints[3]; - usb_paramp->frame_n = 0; - - DBG ("ep0ptr=0x%08x ep1ptr=0x%08x ep2ptr=0x%08x ep3ptr=0x%08x\n", - usb_paramp->ep0ptr, usb_paramp->ep1ptr, usb_paramp->ep2ptr, - usb_paramp->ep3ptr); - - return 0; -} - -/* udc_irq - * - * Poll for whatever events may have occurred - */ -void udc_irq (void) -{ - int epid = 0; - volatile cbd_t *rx_cbdp = 0; - volatile cbd_t *rx_cbdp_base = 0; - - if (udc_state != STATE_READY) { - return; - } - - if (usbp->usber & USB_E_BSY) { - /* This shouldn't happen. If it does then it's a bug ! */ - usbp->usber |= USB_E_BSY; - mpc8xx_udc_flush_rx_fifo (); - } - - /* Scan all RX/Bidirectional Endpoints for RX data. */ - for (epid = 0; epid < MAX_ENDPOINTS; epid++) { - if (!ep_ref[epid].prx) { - continue; - } - rx_cbdp = rx_cbdp_base = ep_ref[epid].prx; - - do { - if (!(rx_cbdp->cbd_sc & RX_BD_E)) { - - if (rx_cbdp->cbd_sc & 0x1F) { - /* Corrupt data discard it. - * Controller has NAK'd this packet. - */ - mpc8xx_udc_clear_rxbd (rx_cbdp); - - } else { - if (!epid) { - mpc8xx_udc_ep0_rx (rx_cbdp); - - } else { - /* Process data */ - mpc8xx_udc_set_nak (epid); - mpc8xx_udc_epn_rx (epid, rx_cbdp); - mpc8xx_udc_clear_rxbd (rx_cbdp); - } - } - - /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx (&rx_cbdp, epid); - ep_ref[epid].prx = rx_cbdp; - } else { - /* Advance RX CBD pointer */ - mpc8xx_udc_advance_rx (&rx_cbdp, epid); - } - - } while (rx_cbdp != rx_cbdp_base); - } - - /* Handle TX events as appropiate, the correct place to do this is - * in a tx routine. Perhaps TX on epn was pre-empted by ep0 - */ - - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - - if (usbp->usber & (USB_TX_ERRMASK)) { - mpc8xx_udc_handle_txerr (); - } - - /* Switch to the default state, respond at the default address */ - if (usbp->usber & USB_E_RESET) { - usbp->usber |= USB_E_RESET; - usbp->usaddr = 0x00; - udc_device->device_state = STATE_DEFAULT; - } - - /* if(usbp->usber&USB_E_IDLE){ - We could suspend here ! - usbp->usber|=USB_E_IDLE; - DBG("idle state change\n"); - } - if(usbp->usbs){ - We could resume here when IDLE is deasserted ! - Not worth doing, so long as we are self powered though. - } - */ - - return; -} - -/* udc_endpoint_write - * - * Write some data to an endpoint - */ -int udc_endpoint_write (struct usb_endpoint_instance *epi) -{ - int ep = 0; - short epid = 1, unnak = 0, ret = 0; - - if (udc_state != STATE_READY) { - ERR ("invalid udc_state != STATE_READY!\n"); - return -1; - } - - if (!udc_device || !epi) { - return -1; - } - - if (udc_device->device_state != STATE_CONFIGURED) { - return -1; - } - - ep = epi->endpoint_address & 0x03; - if (ep >= MAX_ENDPOINTS) { - return -1; - } - - /* Set NAK for all RX endpoints during TX */ - for (epid = 1; epid < MAX_ENDPOINTS; epid++) { - - /* Don't set NAK on DATA IN/CONTROL endpoints */ - if (ep_ref[epid].sc & USB_DIR_IN) { - continue; - } - - if (!(usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK))) { - unnak |= 1 << epid; - } - - mpc8xx_udc_set_nak (epid); - } - - mpc8xx_udc_init_tx (&udc_device->bus->endpoint_array[ep], - epi->tx_urb); - ret = mpc8xx_udc_ep_tx (&udc_device->bus->endpoint_array[ep]); - - /* Remove temporary NAK */ - for (epid = 1; epid < MAX_ENDPOINTS; epid++) { - if (unnak & (1 << epid)) { - udc_unset_nak (epid); - } - } - - return ret; -} - -/* mpc8xx_udc_assign_urb - * - * Associate a given urb to an endpoint TX or RX transmit/receive buffers - */ -static int mpc8xx_udc_assign_urb (int ep, char direction) -{ - struct usb_endpoint_instance *epi = 0; - - if (ep >= MAX_ENDPOINTS) { - goto err; - } - epi = &udc_device->bus->endpoint_array[ep]; - if (!epi) { - goto err; - } - - if (!ep_ref[ep].urb) { - ep_ref[ep].urb = usbd_alloc_urb (udc_device, udc_device->bus->endpoint_array); - if (!ep_ref[ep].urb) { - goto err; - } - } else { - ep_ref[ep].urb->actual_length = 0; - } - - switch (direction) { - case USB_DIR_IN: - epi->tx_urb = ep_ref[ep].urb; - break; - case USB_DIR_OUT: - epi->rcv_urb = ep_ref[ep].urb; - break; - default: - goto err; - } - return 0; - - err: - udc_state = STATE_ERROR; - return -1; -} - -/* udc_setup_ep - * - * Associate U-Boot software endpoints to mpc8xx endpoint parameter ram - * Isochronous endpoints aren't yet supported! - */ -void udc_setup_ep (struct usb_device_instance *device, unsigned int ep, - struct usb_endpoint_instance *epi) -{ - uchar direction = 0; - int ep_attrib = 0; - - if (epi && (ep < MAX_ENDPOINTS)) { - - if (ep == 0) { - if (epi->rcv_attributes != USB_ENDPOINT_XFER_CONTROL - || epi->tx_attributes != - USB_ENDPOINT_XFER_CONTROL) { - - /* ep0 must be a control endpoint */ - udc_state = STATE_ERROR; - return; - - } - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - mpc8xx_udc_cbd_attach (ep, epi->tx_packetSize, - epi->rcv_packetSize); - } - usbp->usep[ep] = 0x0000; - return; - } - - if ((epi->endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { - - direction = 1; - ep_attrib = epi->tx_attributes; - epi->rcv_packetSize = 0; - ep_ref[ep].sc |= USB_DIR_IN; - } else { - - direction = 0; - ep_attrib = epi->rcv_attributes; - epi->tx_packetSize = 0; - ep_ref[ep].sc &= ~USB_DIR_IN; - } - - if (mpc8xx_udc_assign_urb (ep, epi->endpoint_address - & USB_ENDPOINT_DIR_MASK)) { - return; - } - - switch (ep_attrib) { - case USB_ENDPOINT_XFER_CONTROL: - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - epi->rcv_packetSize); - } - usbp->usep[ep] = ep << 12; - epi->rcv_urb = epi->tx_urb = ep_ref[ep].urb; - - break; - case USB_ENDPOINT_XFER_BULK: - case USB_ENDPOINT_XFER_INT: - if (!(ep_ref[ep].sc & EP_ATTACHED)) { - if (direction) { - mpc8xx_udc_cbd_attach (ep, - epi->tx_packetSize, - 0); - } else { - mpc8xx_udc_cbd_attach (ep, - 0, - epi->rcv_packetSize); - } - } - usbp->usep[ep] = (ep << 12) | ((ep_attrib) << 8); - - break; - case USB_ENDPOINT_XFER_ISOC: - default: - serial_printf ("Error endpoint attrib %d>3\n", ep_attrib); - udc_state = STATE_ERROR; - break; - } - } - -} - -/* udc_connect - * - * Move state, switch on the USB - */ -void udc_connect (void) -{ - /* Enable pull-up resistor on D+ - * TODO: fit a pull-up resistor to drive SE0 for > 2.5us - */ - - if (udc_state != STATE_ERROR) { - udc_state = STATE_READY; - usbp->usmod |= USMOD_EN; - } -} - -/* udc_disconnect - * - * Disconnect is not used but, is included for completeness - */ -void udc_disconnect (void) -{ - /* Disable pull-up resistor on D- - * TODO: fix a pullup resistor to control this - */ - - if (udc_state != STATE_ERROR) { - udc_state = STATE_NOT_READY; - } - usbp->usmod &= ~USMOD_EN; -} - -/* udc_enable - * - * Grab an EP0 URB, register interest in a subset of USB events - */ -void udc_enable (struct usb_device_instance *device) -{ - if (udc_state == STATE_ERROR) { - return; - } - - udc_device = device; - - if (!ep_ref[0].urb) { - ep_ref[0].urb = usbd_alloc_urb (device, device->bus->endpoint_array); - } - - /* Register interest in all events except SOF, enable transceiver */ - usbp->usber = 0x03FF; - usbp->usbmr = 0x02F7; - - return; -} - -/* udc_disable - * - * disable the currently hooked device - */ -void udc_disable (void) -{ - int i = 0; - - if (udc_state == STATE_ERROR) { - DBG ("Won't disable UDC. udc_state==STATE_ERROR !\n"); - return; - } - - udc_device = 0; - - for (; i < MAX_ENDPOINTS; i++) { - if (ep_ref[i].urb) { - usbd_dealloc_urb (ep_ref[i].urb); - ep_ref[i].urb = 0; - } - } - - usbp->usbmr = 0x00; - usbp->usmod = ~USMOD_EN; - udc_state = STATE_NOT_READY; -} - -/* udc_startup_events - * - * Enable the specified device - */ -void udc_startup_events (struct usb_device_instance *device) -{ - udc_enable (device); - if (udc_state == STATE_READY) { - usbd_device_event_irq (device, DEVICE_CREATE, 0); - } -} - -/* udc_set_nak - * - * Allow upper layers to signal lower layers should not accept more RX data - * - */ -void udc_set_nak (int epid) -{ - if (epid) { - mpc8xx_udc_set_nak (epid); - } -} - -/* udc_unset_nak - * - * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint. - * Switch off NAKing on this endpoint to accept more data output from host. - * - */ -void udc_unset_nak (int epid) -{ - if (epid > MAX_ENDPOINTS) { - return; - } - - if (usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK)) { - usbp->usep[epid] &= ~(USEP_THS_NAK | USEP_RHS_NAK); - __asm__ ("eieio"); - } -} - -/****************************************************************************** - Static Linkage -******************************************************************************/ - -/* udc_state_transition_up - * udc_state_transition_down - * - * Helper functions to implement device state changes. The device states and - * the events that transition between them are: - * - * STATE_ATTACHED - * || /\ - * \/ || - * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET - * || /\ - * \/ || - * STATE_POWERED - * || /\ - * \/ || - * DEVICE_RESET DEVICE_POWER_INTERRUPTION - * || /\ - * \/ || - * STATE_DEFAULT - * || /\ - * \/ || - * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET - * || /\ - * \/ || - * STATE_ADDRESSED - * || /\ - * \/ || - * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED - * || /\ - * \/ || - * STATE_CONFIGURED - * - * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED - * to STATE_CONFIGURED) from the specified initial state to the specified final - * state, passing through each intermediate state on the way. If the initial - * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then - * no state transitions will take place. - * - * udc_state_transition_down transitions down (in the direction from - * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the - * specified final state, passing through each intermediate state on the way. - * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final - * state, then no state transitions will take place. - * - */ - -static void mpc8xx_udc_state_transition_up (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial < final) { - switch (initial) { - case STATE_ATTACHED: - usbd_device_event_irq (udc_device, - DEVICE_HUB_CONFIGURED, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_ADDRESS_ASSIGNED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, - 0); - case STATE_CONFIGURED: - break; - default: - break; - } - } -} - -static void mpc8xx_udc_state_transition_down (usb_device_state_t initial, - usb_device_state_t final) -{ - if (initial > final) { - switch (initial) { - case STATE_CONFIGURED: - usbd_device_event_irq (udc_device, - DEVICE_DE_CONFIGURED, 0); - if (final == STATE_ADDRESSED) - break; - case STATE_ADDRESSED: - usbd_device_event_irq (udc_device, DEVICE_RESET, 0); - if (final == STATE_DEFAULT) - break; - case STATE_DEFAULT: - usbd_device_event_irq (udc_device, - DEVICE_POWER_INTERRUPTION, 0); - if (final == STATE_POWERED) - break; - case STATE_POWERED: - usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, - 0); - case STATE_ATTACHED: - break; - default: - break; - } - } -} - -/* mpc8xx_udc_stall - * - * Force returning of STALL tokens on the given endpoint. Protocol or function - * STALL conditions are permissable here - */ -static void mpc8xx_udc_stall (unsigned int ep) -{ - usbp->usep[ep] |= STALL_BITMASK; -} - -/* mpc8xx_udc_set_nak - * - * Force returning of NAK responses for the given endpoint as a kind of very - * simple flow control - */ -static void mpc8xx_udc_set_nak (unsigned int ep) -{ - usbp->usep[ep] |= NAK_BITMASK; - __asm__ ("eieio"); -} - -/* mpc8xx_udc_handle_txerr - * - * Handle errors relevant to TX. Return a status code to allow calling - * indicative of what if anything happened - */ -static short mpc8xx_udc_handle_txerr () -{ - short ep = 0, ret = 0; - - for (; ep < TX_RING_SIZE; ep++) { - if (usbp->usber & (0x10 << ep)) { - - /* Timeout or underrun */ - if (tx_cbd[ep]->cbd_sc & 0x06) { - ret = 1; - mpc8xx_udc_flush_tx_fifo (ep); - - } else { - if (usbp->usep[ep] & STALL_BITMASK) { - if (!ep) { - usbp->usep[ep] &= ~STALL_BITMASK; - } - } /* else NAK */ - } - usbp->usber |= (0x10 << ep); - } - } - return ret; -} - -/* mpc8xx_udc_advance_rx - * - * Advance cbd rx - */ -static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid) -{ - if ((*rx_cbdp)->cbd_sc & RX_BD_W) { - *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CONFIG_SYS_IMMR); - - } else { - (*rx_cbdp)++; - } -} - - -/* mpc8xx_udc_flush_tx_fifo - * - * Flush a given TX fifo. Assumes one tx cbd per endpoint - */ -static void mpc8xx_udc_flush_tx_fifo (int epid) -{ - volatile cbd_t *tx_cbdp = 0; - - if (epid > MAX_ENDPOINTS) { - return; - } - - /* TX stop */ - immr->im_cpm.cp_cpcr = ((epid << 2) | 0x1D01); - __asm__ ("eieio"); - while (immr->im_cpm.cp_cpcr & 0x01); - - usbp->uscom = 0x40 | 0; - - /* reset ring */ - tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CONFIG_SYS_IMMR); - tx_cbdp->cbd_sc = (TX_BD_I | TX_BD_W); - - - endpoints[epid]->tptr = endpoints[epid]->tbase; - endpoints[epid]->tstate = 0x00; - endpoints[epid]->tbcnt = 0x00; - - /* TX start */ - immr->im_cpm.cp_cpcr = ((epid << 2) | 0x2D01); - __asm__ ("eieio"); - while (immr->im_cpm.cp_cpcr & 0x01); - - return; -} - -/* mpc8xx_udc_flush_rx_fifo - * - * For the sake of completeness of the namespace, it seems like - * a good-design-decision (tm) to include mpc8xx_udc_flush_rx_fifo(); - * If RX_BD_E is true => a driver bug either here or in an upper layer - * not polling frequently enough. If RX_BD_E is true we have told the host - * we have accepted data but, the CPM found it had no-where to put that data - * which needless to say would be a bad thing. - */ -static void mpc8xx_udc_flush_rx_fifo () -{ - int i = 0; - - for (i = 0; i < RX_RING_SIZE; i++) { - if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { - ERR ("buf %p used rx data len = 0x%x sc=0x%x!\n", - rx_cbd[i], rx_cbd[i]->cbd_datlen, - rx_cbd[i]->cbd_sc); - - } - } - ERR ("BUG : Input over-run\n"); -} - -/* mpc8xx_udc_clear_rxbd - * - * Release control of RX CBD to CP. - */ -static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp) -{ - rx_cbdp->cbd_datlen = 0x0000; - rx_cbdp->cbd_sc = ((rx_cbdp->cbd_sc & RX_BD_W) | (RX_BD_E | RX_BD_I)); - __asm__ ("eieio"); -} - -/* mpc8xx_udc_tx_irq - * - * Parse for tx timeout, control RX or USB reset/busy conditions - * Return -1 on timeout, -2 on fatal error, else return zero - */ -static int mpc8xx_udc_tx_irq (int ep) -{ - int i = 0; - - if (usbp->usber & (USB_TX_ERRMASK)) { - if (mpc8xx_udc_handle_txerr ()) { - /* Timeout, controlling function must retry send */ - return -1; - } - } - - if (usbp->usber & (USB_E_RESET | USB_E_BSY)) { - /* Fatal, abandon TX transaction */ - return -2; - } - - if (usbp->usber & USB_E_RXB) { - for (i = 0; i < RX_RING_SIZE; i++) { - if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) { - if ((rx_cbd[i] == ep_ref[0].prx) || ep) { - return -2; - } - } - } - } - - return 0; -} - -/* mpc8xx_udc_ep_tx - * - * Transmit in a re-entrant fashion outbound USB packets. - * Implement retry/timeout mechanism described in USB specification - * Toggle DATA0/DATA1 pids as necessary - * Introduces non-standard tx_retry. The USB standard has no scope for slave - * devices to give up TX, however tx_retry stops us getting stuck in an endless - * TX loop. - */ -static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) -{ - struct urb *urb = epi->tx_urb; - volatile cbd_t *tx_cbdp = 0; - unsigned int ep = 0, pkt_len = 0, x = 0, tx_retry = 0; - int ret = 0; - - if (!epi || (epi->endpoint_address & 0x03) >= MAX_ENDPOINTS || !urb) { - return -1; - } - - ep = epi->endpoint_address & 0x03; - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); - - if (tx_cbdp->cbd_sc & TX_BD_R || usbp->usber & USB_E_TXB) { - mpc8xx_udc_flush_tx_fifo (ep); - usbp->usber |= USB_E_TXB; - }; - - while (tx_retry++ < 100) { - ret = mpc8xx_udc_tx_irq (ep); - if (ret == -1) { - /* ignore timeout here */ - } else if (ret == -2) { - /* Abandon TX */ - mpc8xx_udc_flush_tx_fifo (ep); - return -1; - } - - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); - while (tx_cbdp->cbd_sc & TX_BD_R) { - }; - tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc & TX_BD_W); - - pkt_len = urb->actual_length - epi->sent; - - if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) { - pkt_len = min(epi->tx_packetSize, EP_MAX_PKT); - } - - for (x = 0; x < pkt_len; x++) { - *((unsigned char *) (tx_cbdp->cbd_bufaddr + x)) = - urb->buffer[epi->sent + x]; - } - tx_cbdp->cbd_datlen = pkt_len; - tx_cbdp->cbd_sc |= (CBD_TX_BITMASK | ep_ref[ep].pid); - __asm__ ("eieio"); - -#ifdef __SIMULATE_ERROR__ - if (++err_poison_test == 2) { - err_poison_test = 0; - tx_cbdp->cbd_sc &= ~TX_BD_TC; - } -#endif - - usbp->uscom = (USCOM_STR | ep); - - while (!(usbp->usber & USB_E_TXB)) { - ret = mpc8xx_udc_tx_irq (ep); - if (ret == -1) { - /* TX timeout */ - break; - } else if (ret == -2) { - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - mpc8xx_udc_flush_tx_fifo (ep); - return -1; - } - }; - - if (usbp->usber & USB_E_TXB) { - usbp->usber |= USB_E_TXB; - } - - /* ACK must be present <= 18bit times from TX */ - if (ret == -1) { - continue; - } - - /* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */ - epi->sent += pkt_len; - epi->last = min(urb->actual_length - epi->sent, epi->tx_packetSize); - TOGGLE_TX_PID (ep_ref[ep].pid); - - if (epi->sent >= epi->tx_urb->actual_length) { - - epi->tx_urb->actual_length = 0; - epi->sent = 0; - - if (ep_ref[ep].sc & EP_SEND_ZLP) { - ep_ref[ep].sc &= ~EP_SEND_ZLP; - } else { - return 0; - } - } - } - - ERR ("TX fail, endpoint 0x%x tx bytes 0x%x/0x%x\n", ep, epi->sent, - epi->tx_urb->actual_length); - - return -1; -} - -/* mpc8xx_udc_dump_request - * - * Dump a control request to console - */ -static void mpc8xx_udc_dump_request (struct usb_device_request *request) -{ - DBG ("bmRequestType:%02x bRequest:%02x wValue:%04x " - "wIndex:%04x wLength:%04x ?\n", - request->bmRequestType, - request->bRequest, - request->wValue, request->wIndex, request->wLength); - - return; -} - -/* mpc8xx_udc_ep0_rx_setup - * - * Decode received ep0 SETUP packet. return non-zero on error - */ -static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp) -{ - unsigned int x = 0; - struct urb *purb = ep_ref[0].urb; - struct usb_endpoint_instance *epi = - &udc_device->bus->endpoint_array[0]; - - for (; x < rx_cbdp->cbd_datlen; x++) { - *(((unsigned char *) &ep_ref[0].urb->device_request) + x) = - *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); - } - - mpc8xx_udc_clear_rxbd (rx_cbdp); - - if (ep0_recv_setup (purb)) { - mpc8xx_udc_dump_request (&purb->device_request); - return -1; - } - - if ((purb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) - == USB_REQ_HOST2DEVICE) { - - switch (purb->device_request.bRequest) { - case USB_REQ_SET_ADDRESS: - /* Send the Status OUT ZLP */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx (epi, purb); - mpc8xx_udc_ep_tx (epi); - - /* Move to the addressed state */ - usbp->usaddr = udc_device->address; - mpc8xx_udc_state_transition_up (udc_device->device_state, - STATE_ADDRESSED); - return 0; - - case USB_REQ_SET_CONFIGURATION: - if (!purb->device_request.wValue) { - /* Respond at default address */ - usbp->usaddr = 0x00; - mpc8xx_udc_state_transition_down (udc_device->device_state, - STATE_ADDRESSED); - } else { - /* TODO: Support multiple configurations */ - mpc8xx_udc_state_transition_up (udc_device->device_state, - STATE_CONFIGURED); - for (x = 1; x < MAX_ENDPOINTS; x++) { - if ((udc_device->bus->endpoint_array[x].endpoint_address & USB_ENDPOINT_DIR_MASK) - == USB_DIR_IN) { - ep_ref[x].pid = TX_BD_PID_DATA0; - } else { - ep_ref[x].pid = RX_BD_PID_DATA0; - } - /* Set configuration must unstall endpoints */ - usbp->usep[x] &= ~STALL_BITMASK; - } - } - break; - default: - /* CDC/Vendor specific */ - break; - } - - /* Send ZLP as ACK in Status OUT phase */ - ep_ref[0].pid = TX_BD_PID_DATA1; - purb->actual_length = 0; - mpc8xx_udc_init_tx (epi, purb); - mpc8xx_udc_ep_tx (epi); - - } else { - - if (purb->actual_length) { - ep_ref[0].pid = TX_BD_PID_DATA1; - mpc8xx_udc_init_tx (epi, purb); - - if (!(purb->actual_length % EP0_MAX_PACKET_SIZE)) { - ep_ref[0].sc |= EP_SEND_ZLP; - } - - if (purb->device_request.wValue == - USB_DESCRIPTOR_TYPE_DEVICE) { - if (le16_to_cpu (purb->device_request.wLength) - > purb->actual_length) { - /* Send EP0_MAX_PACKET_SIZE bytes - * unless correct size requested. - */ - if (purb->actual_length > epi->tx_packetSize) { - purb->actual_length = epi->tx_packetSize; - } - } - } - mpc8xx_udc_ep_tx (epi); - - } else { - /* Corrupt SETUP packet? */ - ERR ("Zero length data or SETUP with DATA-IN phase ?\n"); - return 1; - } - } - return 0; -} - -/* mpc8xx_udc_init_tx - * - * Setup some basic parameters for a TX transaction - */ -static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi, - struct urb *tx_urb) -{ - epi->sent = 0; - epi->last = 0; - epi->tx_urb = tx_urb; -} - -/* mpc8xx_udc_ep0_rx - * - * Receive ep0/control USB data. Parse and possibly send a response. - */ -static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp) -{ - if (rx_cbdp->cbd_sc & RX_BD_PID_SETUP) { - - /* Unconditionally accept SETUP packets */ - if (mpc8xx_udc_ep0_rx_setup (rx_cbdp)) { - mpc8xx_udc_stall (0); - } - - } else { - - mpc8xx_udc_clear_rxbd (rx_cbdp); - - if ((rx_cbdp->cbd_datlen - 2)) { - /* SETUP with a DATA phase - * outside of SETUP packet. - * Reply with STALL. - */ - mpc8xx_udc_stall (0); - } - } -} - -/* mpc8xx_udc_epn_rx - * - * Receive some data from cbd into USB system urb data abstraction - * Upper layers should NAK if there is insufficient RX data space - */ -static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp) -{ - struct usb_endpoint_instance *epi = 0; - struct urb *urb = 0; - unsigned int x = 0; - - if (epid >= MAX_ENDPOINTS || !rx_cbdp->cbd_datlen) { - return 0; - } - - /* USB 2.0 PDF section 8.6.4 - * Discard data with invalid PID it is a resend. - */ - if (ep_ref[epid].pid != (rx_cbdp->cbd_sc & 0xC0)) { - return 1; - } - TOGGLE_RX_PID (ep_ref[epid].pid); - - epi = &udc_device->bus->endpoint_array[epid]; - urb = epi->rcv_urb; - - for (; x < (rx_cbdp->cbd_datlen - 2); x++) { - *((unsigned char *) (urb->buffer + urb->actual_length + x)) = - *((unsigned char *) (rx_cbdp->cbd_bufaddr + x)); - } - - if (x) { - usbd_rcv_complete (epi, x, 0); - if (ep_ref[epid].urb->status == RECV_ERROR) { - DBG ("RX error unset NAK\n"); - udc_unset_nak (epid); - } - } - return x; -} - -/* mpc8xx_udc_clock_init - * - * Obtain a clock reference for Full Speed Signaling - */ -static void mpc8xx_udc_clock_init (volatile immap_t * immr, - volatile cpm8xx_t * cp) -{ - -#if defined(CONFIG_SYS_USB_EXTC_CLK) - - /* This has been tested with a 48MHz crystal on CLK6 */ - switch (CONFIG_SYS_USB_EXTC_CLK) { - case 1: - immr->im_ioport.iop_papar |= 0x0100; - immr->im_ioport.iop_padir &= ~0x0100; - cp->cp_sicr |= 0x24; - break; - case 2: - immr->im_ioport.iop_papar |= 0x0200; - immr->im_ioport.iop_padir &= ~0x0200; - cp->cp_sicr |= 0x2D; - break; - case 3: - immr->im_ioport.iop_papar |= 0x0400; - immr->im_ioport.iop_padir &= ~0x0400; - cp->cp_sicr |= 0x36; - break; - case 4: - immr->im_ioport.iop_papar |= 0x0800; - immr->im_ioport.iop_padir &= ~0x0800; - cp->cp_sicr |= 0x3F; - break; - default: - udc_state = STATE_ERROR; - break; - } - -#elif defined(CONFIG_SYS_USB_BRGCLK) - - /* This has been tested with brgclk == 50MHz */ - int divisor = 0; - - if (gd->cpu_clk < 48000000L) { - ERR ("brgclk is too slow for full-speed USB!\n"); - udc_state = STATE_ERROR; - return; - } - - /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48MHz) - * but, can /probably/ live with close-ish alternative rates. - */ - divisor = (gd->cpu_clk / 48000000L) - 1; - cp->cp_sicr &= ~0x0000003F; - - switch (CONFIG_SYS_USB_BRGCLK) { - case 1: - cp->cp_brgc1 |= (divisor | CPM_BRG_EN); - cp->cp_sicr &= ~0x2F; - break; - case 2: - cp->cp_brgc2 |= (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x00000009; - break; - case 3: - cp->cp_brgc3 |= (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x00000012; - break; - case 4: - cp->cp_brgc4 = (divisor | CPM_BRG_EN); - cp->cp_sicr |= 0x0000001B; - break; - default: - udc_state = STATE_ERROR; - break; - } - -#else -#error "CONFIG_SYS_USB_EXTC_CLK or CONFIG_SYS_USB_BRGCLK must be defined" -#endif - -} - -/* mpc8xx_udc_cbd_attach - * - * attach a cbd to and endpoint - */ -static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size) -{ - - if (!tx_cbd[ep] || !rx_cbd[ep] || ep >= MAX_ENDPOINTS) { - udc_state = STATE_ERROR; - return; - } - - if (tx_size > USB_MAX_PKT || rx_size > USB_MAX_PKT || - (!tx_size && !rx_size)) { - udc_state = STATE_ERROR; - return; - } - - /* Attach CBD to appropiate Parameter RAM Endpoint data structure */ - if (rx_size) { - endpoints[ep]->rbase = (u32) rx_cbd[rx_ct]; - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_ct++; - - if (!ep) { - - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; - rx_ct++; - - } else { - rx_ct += 2; - endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct]; - rx_cbd[rx_ct]->cbd_sc |= RX_BD_W; - rx_ct++; - } - - /* Where we expect to RX data on this endpoint */ - ep_ref[ep].prx = rx_cbd[rx_ct - 1]; - } else { - - ep_ref[ep].prx = 0; - endpoints[ep]->rbase = 0; - endpoints[ep]->rbptr = 0; - } - - if (tx_size) { - endpoints[ep]->tbase = (u32) tx_cbd[tx_ct]; - endpoints[ep]->tbptr = (u32) tx_cbd[tx_ct]; - tx_ct++; - } else { - endpoints[ep]->tbase = 0; - endpoints[ep]->tbptr = 0; - } - - endpoints[ep]->tstate = 0; - endpoints[ep]->tbcnt = 0; - endpoints[ep]->mrblr = EP_MAX_PKT; - endpoints[ep]->rfcr = 0x18; - endpoints[ep]->tfcr = 0x18; - ep_ref[ep].sc |= EP_ATTACHED; - - DBG ("ep %d rbase 0x%08x rbptr 0x%08x tbase 0x%08x tbptr 0x%08x prx = %p\n", - ep, endpoints[ep]->rbase, endpoints[ep]->rbptr, - endpoints[ep]->tbase, endpoints[ep]->tbptr, - ep_ref[ep].prx); - - return; -} - -/* mpc8xx_udc_cbd_init - * - * Allocate space for a cbd and allocate TX/RX data space - */ -static void mpc8xx_udc_cbd_init (void) -{ - int i = 0; - - for (; i < TX_RING_SIZE; i++) { - tx_cbd[i] = (cbd_t *) - mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int)); - } - - for (i = 0; i < RX_RING_SIZE; i++) { - rx_cbd[i] = (cbd_t *) - mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int)); - } - - for (i = 0; i < TX_RING_SIZE; i++) { - tx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - - tx_cbd[i]->cbd_sc = (TX_BD_I | TX_BD_W); - tx_cbd[i]->cbd_datlen = 0x0000; - } - - - for (i = 0; i < RX_RING_SIZE; i++) { - rx_cbd[i]->cbd_bufaddr = - mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int)); - rx_cbd[i]->cbd_sc = (RX_BD_I | RX_BD_E); - rx_cbd[i]->cbd_datlen = 0x0000; - - } - - return; -} - -/* mpc8xx_udc_endpoint_init - * - * Attach an endpoint to some dpram - */ -static void mpc8xx_udc_endpoint_init (void) -{ - int i = 0; - - for (; i < MAX_ENDPOINTS; i++) { - endpoints[i] = (usb_epb_t *) - mpc8xx_udc_alloc (sizeof (usb_epb_t), 32); - } -} - -/* mpc8xx_udc_alloc - * - * Grab the address of some dpram - */ -static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment) -{ - u32 retaddr = address_base; - - while (retaddr % alignment) { - retaddr++; - } - address_base += data_size; - - return retaddr; -} diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 4ece0a2..ab5a99f 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -17,7 +17,6 @@ obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o -obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o @@ -27,11 +26,7 @@ obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o -ifdef CONFIG_MPC512X -obj-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o -else obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o -endif obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index bbaefd2..841e596 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -43,6 +43,7 @@ struct dwc2_priv { struct dwc2_core_regs *regs; int root_hub_devnum; bool ext_vbus; + bool hnp_srp_disable; bool oc_disable; }; @@ -394,6 +395,9 @@ static void dwc_otg_core_init(struct dwc2_priv *priv) usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; } #endif + if (priv->hnp_srp_disable) + usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE; + writel(usbcfg, ®s->gusbcfg); /* Program the GAHBCFG Register. */ @@ -422,12 +426,16 @@ static void dwc_otg_core_init(struct dwc2_priv *priv) writel(ahbcfg, ®s->gahbcfg); - /* Program the GUSBCFG register for HNP/SRP. */ - setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); + /* Program the capabilities in GUSBCFG Register */ + usbcfg = 0; + if (!priv->hnp_srp_disable) + usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; #ifdef CONFIG_DWC2_IC_USB_CAP - setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); + usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; #endif + + setbits_le32(®s->gusbcfg, usbcfg); } /* @@ -1244,6 +1252,11 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) if (prop) priv->oc_disable = true; + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + "hnp-srp-disable", NULL); + if (prop) + priv->hnp_srp_disable = true; + return 0; } diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c deleted file mode 100644 index bb4f461..0000000 --- a/drivers/usb/host/ehci-mpc512x.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2010, Damien Dusha, - * - * (C) Copyright 2009, Value Team S.p.A. - * Francesco Rendine, - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB - * - * Author: Tor Krill tor@excito.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include "ehci.h" - -static void fsl_setup_phy(volatile struct ehci_hcor *); -static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci); -static int reset_usb_controller(volatile struct usb_ehci *ehci); -static void usb_platform_dr_init(volatile struct usb_ehci *ehci); - -/* - * Initialize SOC FSL EHCI Controller - * - * This code is derived from EHCI FSL USB Linux driver for MPC5121 - * - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - volatile struct usb_ehci *ehci; - - /* Hook the memory mapped registers for EHCI-Controller */ - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - *hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength)); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - /* configure interface for UTMI_WIDE */ - usb_platform_dr_init(ehci); - - /* Init Phy USB0 to UTMI+ */ - fsl_setup_phy(*hcor); - - /* Set to host mode */ - fsl_platform_set_host_mode(ehci); - - /* - * Setting the burst size seems to be required to prevent the - * USB from hanging when communicating with certain USB Mass - * storage devices. This was determined by analysing the - * EHCI registers under Linux vs U-Boot and burstsize was the - * major non-interrupt related difference between the two - * implementations. - * - * Some USB sticks behave better than others. In particular, - * the following USB stick is especially problematic: - * 0930:6545 Toshiba Corp - * - * The burstsize is set here to match the Linux implementation. - */ - out_be32(&ehci->burstsize, FSL_EHCI_TXPBURST(8) | - FSL_EHCI_RXPBURST(8)); - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - volatile struct usb_ehci *ehci; - int exit_status = 0; - - /* Reset the USB controller */ - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - exit_status = reset_usb_controller(ehci); - - return exit_status; -} - -static int reset_usb_controller(volatile struct usb_ehci *ehci) -{ - unsigned int i; - - /* Command a reset of the USB Controller */ - out_be32(&(ehci->usbcmd), CMD_RESET); - - /* Wait for the reset process to finish */ - for (i = 65535 ; i > 0 ; i--) { - /* - * The host will set this bit to zero once the - * reset process is complete - */ - if ((in_be32(&(ehci->usbcmd)) & CMD_RESET) == 0) - return 0; - } - - /* Hub did not reset in time */ - return -1; -} - -static void fsl_setup_phy(volatile struct ehci_hcor *hcor) -{ - uint32_t portsc; - - portsc = ehci_readl(&hcor->or_portsc[0]); - portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); - - /* Enable the phy mode to UTMI Wide */ - portsc |= PORT_PTS_PTW; - portsc |= PORT_PTS_UTMI; - - ehci_writel(&hcor->or_portsc[0], portsc); -} - -static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci) -{ - uint32_t temp; - - temp = in_le32(&ehci->usbmode); - temp |= CM_HOST | ES_BE; - out_le32(&ehci->usbmode, temp); -} - -static void usb_platform_dr_init(volatile struct usb_ehci *ehci) -{ - /* Configure interface for UTMI_WIDE */ - out_be32(&ehci->isiphyctrl, PHYCTRL_PHYE | PHYCTRL_PXE); - out_be32(&ehci->usbgenctrl, GC_PPP | GC_PFP ); -} diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 2367671..f348ec9 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "ehci.h" diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index f20fc33..dceba4b 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "ehci.h" diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 734d7f0..2ab830d 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -102,13 +102,11 @@ struct usb_linux_config_descriptor { } __attribute__ ((packed)); #if defined CONFIG_EHCI_DESC_BIG_ENDIAN -#define ehci_readl(x) cpu_to_be32((*((volatile u32 *)(x)))) -#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ - cpu_to_be32(((volatile u32)b))) +#define ehci_readl(x) cpu_to_be32(readl(x)) +#define ehci_writel(a, b) writel(cpu_to_be32(b), a) #else -#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x)))) -#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ - cpu_to_le32(((volatile u32)b))) +#define ehci_readl(x) cpu_to_le32(readl(x)) +#define ehci_writel(a, b) writel(cpu_to_le32(b), a) #endif #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 80cfe11..272df07 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -51,10 +51,8 @@ #endif #if defined(CONFIG_CPU_ARM920T) || \ - defined(CONFIG_S3C24X0) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ - defined(CONFIG_MPC5200) || \ defined(CONFIG_SYS_OHCI_USE_NPS) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ #endif @@ -1089,10 +1087,6 @@ static void check_status(td_t *td_list) *phwHeadP &= m32_swap(0xfffffff2); flush_dcache_ed(td_list->ed); } -#ifdef CONFIG_MPC5200 - td_list->hwNextTD = 0; - flush_dcache_td(td_list); -#endif } } diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c deleted file mode 100644 index 28b9ab5..0000000 --- a/drivers/usb/host/ohci-s3c24xx.c +++ /dev/null @@ -1,1688 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include -/* #include no PCI on the S3C24X0 */ - -#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) - -#include -#include -#include -#include -#include "ohci-s3c24xx.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ - - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#undef DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#undef SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global struct ohci */ -static struct ohci gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -struct urb_priv urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a(struct ohci *hc) -{ - return read_roothub(hc, a, 0xfc0fe000); -} -static inline u32 roothub_b(struct ohci *hc) -{ - return readl(&hc->regs->roothub.b); -} -static inline u32 roothub_status(struct ohci *hc) -{ - return readl(&hc->regs->roothub.status); -} -static u32 roothub_portstatus(struct ohci *hc, int i) -{ - return read_roothub(hc, portstatus[i], 0xffe0fce0); -} - -/* forward declaration */ -static int hc_interrupt(void); -static void td_submit_job(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, - struct devrequest *setup, struct urb_priv *urb, - int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv(struct urb_priv *urb) -{ - int i; - int last; - struct td *td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number(struct usb_device *dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, char *str, - int small) -{ - struct urb_priv *purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number(dev), - usb_pipedevice(pipe), - usb_pipeendpoint(pipe), - usb_pipeout(pipe) ? 'O' : 'I', - usb_pipetype(pipe) < 2 ? - (usb_pipeint(pipe) ? "INTR" : "ISOC") : - (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), - purb->actual_length, transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol(pipe)) { - printf(__FILE__ ": cmd(8):"); - for (i = 0; i < 8; i++) - printf(" %02x", ((__u8 *) setup)[i]); - printf("\n"); - } - if (transfer_len > 0 && buffer) { - printf(__FILE__ ": data(%d/%d):", - purb->actual_length, transfer_len); - len = usb_pipeout(pipe) ? - transfer_len : purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf(" %02x", ((__u8 *) buffer)[i]); - printf("%s\n", i < len ? "..." : ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the - int ed tree inclusive iso eds*/ -void ep_print_int_eds(struct ohci *ohci, char *str) -{ - int i, j; - __u32 *ed_p; - for (i = 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table[i]); - if (*ed_p == 0) - continue; - printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - struct ed *ed = (struct ed *) m32_swap(ed_p); - printf(" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf("\n"); - } -} - -static void ohci_dump_intr_mask(char *label, __u32 mask) -{ - dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : ""); -} - -static void maybe_print_eds(char *label, __u32 value) -{ - struct ed *edp = (struct ed *) value; - - if (value) { - dbg("%s %08x", label, value); - dbg("%08x", edp->hwINFO); - dbg("%08x", edp->hwTailP); - dbg("%08x", edp->hwHeadP); - dbg("%08x", edp->hwNextED); - } -} - -static char *hcfs2string(int state) -{ - switch (state) { - case OHCI_USB_RESET: - return "reset"; - case OHCI_USB_RESUME: - return "resume"; - case OHCI_USB_OPER: - return "operational"; - case OHCI_USB_SUSPEND: - return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status(struct ohci *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl(®s->revision) & 0xff; - if (temp != 0x10) - dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl(®s->control); - dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string(temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR); - - temp = readl(®s->cmdstatus); - dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : ""); - - ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus)); - ohci_dump_intr_mask("intrenable", readl(®s->intrenable)); - - maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent)); - - maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead)); - maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent)); - - maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead)); - maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent)); - - maybe_print_eds("donehead", readl(®s->donehead)); -} - -static void ohci_dump_roothub(struct ohci *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a(controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", ndp); - temp = roothub_b(controller); - dbg("roothub.b: %08x PPCM=%04x DR=%04x", - temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR) - ); - temp = roothub_status(controller); - dbg("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : ""); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus(controller, i); - dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : ""); - } -} - -static void ohci_dump(struct ohci *controller, int verbose) -{ - dbg("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status(controller); - if (verbose) - ep_print_int_eds(controller, "hcca"); - dbg("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub(controller, 1); -} - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - struct ohci *ohci; - struct ed *ed; - struct urb_priv *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here - so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - ed = ep_add_ed(dev, pipe); - if (!ed) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype(pipe)) { - case PIPE_BULK: - /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: - /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc(dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv(purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv(purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link(ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, - interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number(struct usb_device *usb_dev) -{ - struct ohci *ohci = &gohci; - - return m16_swap(ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link(struct ohci *ohci, struct ed *edi) -{ - struct ed *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel((u32)ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel(ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel((u32)ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel(ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink(struct ohci *ohci, struct ed *ed) -{ - struct ed *next; - ed->hwINFO |= m32_swap(OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel(ohci->hc_control, &ohci->regs->control); - } - writel(m32_swap(*((__u32 *) &ed->hwNextED)), - &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED)); - next->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel(ohci->hc_control, &ohci->regs->control); - } - writel(m32_swap(*((__u32 *) &ed->hwNextED)), - &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED)); - next->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration - * command, but the USB stack is a little bit stateless so we do it at every - * transaction. If the state of the ed is ED_NEW then a dummy td is added and - * the state is changed to ED_UNLINK. In all other cases the state is left - * unchanged. The ed info fields are setted anyway even though most of them - * should not change */ - -static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe) -{ - struct td *td; - struct ed *ed_ret; - struct ed *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | - (usb_pipecontrol(pipe) ? 0 : - usb_pipeout(pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc(usb_dev); - ed->hwTailP = (__u32) m32_swap(td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype(pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap(usb_pipedevice(pipe) - | usb_pipeendpoint(pipe) << 7 - | (usb_pipeisoc(pipe) ? 0x8000 : 0) - | (usb_pipecontrol(pipe) ? 0 : - (usb_pipeout(pipe) ? 0x800 : 0x1000)) - | (usb_dev->speed == USB_SPEED_LOW) << 13 | - usb_maxpacket(usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len, - struct usb_device *dev, int index, - struct urb_priv *urb_priv) -{ - struct td *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td[index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td[index] = - (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32) data; -#ifdef OHCI_FILL_TRACE - if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ", i, - ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = (__u32) m32_swap(info); - td->hwCBP = (__u32) m32_swap(data); - if (data) - td->hwBE = (__u32) m32_swap(data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = (__u32) m32_swap(td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -static void td_submit_job(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, - struct devrequest *setup, struct urb_priv *urb, - int interval) -{ - struct ohci *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just - use the USB-toggle bits for resetting */ - if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), - 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype(pipe)) { - case PIPE_BULK: - info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN; - while (data_len > 4096) { - td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, - 4096, dev, cnt, urb); - data += 4096; - data_len -= 4096; - cnt++; - } - info = usb_pipeout(pipe) ? - TD_CC | TD_DP_OUT : - TD_CC | TD_R | TD_DP_IN; - td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, - data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - /* start bulk list */ - writel(OHCI_BLF, &ohci->regs->cmdstatus); - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill(ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout(pipe) ? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : - TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill(ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout(pipe) ? - TD_CC | TD_DP_IN | TD_T_DATA1 : - TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill(ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - /* start Control list */ - writel(OHCI_CLF, &ohci->regs->cmdstatus); - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(struct td *td) -{ - __u32 tdBE, tdCBP; - struct urb_priv *lurb_priv = &urb_priv; - - tdBE = m32_swap(td->hwBE); - tdCBP = m32_swap(td->hwCBP); - - if (!(usb_pipecontrol(lurb_priv->pipe) && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static struct td *dl_reverse_done_list(struct ohci *ohci) -{ - __u32 td_list_hc; - __u32 tmp; - struct td *td_rev = NULL; - struct td *td_list = NULL; - struct urb_priv *lurb_priv = NULL; - - td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (struct td *) td_list_hc; - - if (TD_CC_GET(m32_swap(td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET(m32_swap(td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap(0x1)) { - if (lurb_priv && - ((td_list->index+1) < lurb_priv->length)) { - tmp = lurb_priv->length - 1; - td_list->ed->hwHeadP = - (lurb_priv->td[tmp]->hwNextTD & - m32_swap(0xfffffff0)) | - (td_list->ed->hwHeadP & - m32_swap(0x2)); - lurb_priv->td_cnt += lurb_priv->length - - td_list->index - 1; - } else - td_list->ed->hwHeadP &= - m32_swap(0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; - } - - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list(struct ohci *ohci, struct td *td_list) -{ - struct td *td_list_next = NULL; - struct ed *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - struct urb_priv *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap(td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET(tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - /* see if this done list makes for all TD's of current URB, - * and mark the URB finished if so */ - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK))) - urb_finished = 1; - else - dbg("dl_done_list: strange.., ED state %x, " - "ed->state\n"); - } else - dbg("dl_done_list: processing TD %x, len %x\n", - lurb_priv->td_cnt, lurb_priv->length); - - if (ed->state != ED_NEW) { - edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap(ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink(ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -#include - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) \ -{ \ - info("WR:status %#8x", (x)); \ - writel((x), &gohci.regs->roothub.status); \ -} -#define WR_RH_PORTSTAT(x) \ -{ \ - info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \ - writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \ -} -#else -#define WR_RH_STAT(x) \ - writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x)\ - writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(struct ohci *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a(controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus(controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, - struct devrequest *cmd) -{ - void *data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - union { - __u32 word[4]; - __u16 hword[8]; - __u8 byte[16]; - } datab; - __u8 *data_buf = datab.byte; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (usb_pipeint(pipe)) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap(cmd->value); - wIndex = m16_swap(cmd->index); - wLength = m16_swap(cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - datab.hword[0] = m16_swap(1); - OK(2); - case RH_GET_STATUS | RH_INTERFACE: - datab.hword[0] = m16_swap(0); - OK(2); - case RH_GET_STATUS | RH_ENDPOINT: - datab.hword[0] = m16_swap(0); - OK(2); - case RH_GET_STATUS | RH_CLASS: - datab.word[0] = - m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK(4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - datab.word[0] = m32_swap(RD_RH_PORTSTAT); - OK(4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): - OK(0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); - OK(0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT(RH_PS_CCS); - OK(0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT(RH_PS_POCI); - OK(0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT(RH_PS_LSDA); - OK(0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT(RH_PS_CSC); - OK(0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT(RH_PS_PESC); - OK(0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT(RH_PS_PSSC); - OK(0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT(RH_PS_OCIC); - OK(0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT(RH_PS_PRSC); - OK(0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT(RH_PS_PSS); - OK(0); - case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT(RH_PS_PRS); - OK(0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT(RH_PS_PPS); - OK(0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT(RH_PS_PES); - OK(0); - } - break; - - case RH_SET_ADDRESS: - gohci.rh.devnum = wValue; - OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_dev_des), wLength)); - data_buf = root_hub_dev_des; - OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; - OK(len); - case (0x03): /* string descriptors */ - if (wValue == 0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if (wValue == 0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a(&gohci); - - data_buf[0] = 9; /* min length; */ - data_buf[1] = 0x29; - data_buf[2] = temp & RH_A_NDP; - data_buf[3] = 0; - if (temp & RH_A_PSM) - /* per-port power switching? */ - data_buf[3] |= 0x1; - if (temp & RH_A_NOCP) - /* no overcurrent reporting? */ - data_buf[3] |= 0x10; - else if (temp & RH_A_OCPM) - /* per-port overcurrent reporting? */ - data_buf[3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab.word[1] = 0; - data_buf[5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b(&gohci); - data_buf[7] = temp & RH_B_DR; - if (data_buf[2] < 7) { - data_buf[8] = 0xff; - } else { - data_buf[0] += 2; - data_buf[8] = (temp & RH_B_DR) >> 8; - data_buf[10] = data_buf[9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf[0], wLength)); - OK(len); - } - - case RH_GET_CONFIGURATION: - *(__u8 *) data_buf = 0x01; - OK(1); - - case RH_SET_CONFIGURATION: - WR_RH_STAT(0x10000); - OK(0); - - default: - dbg("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub(&gohci, 1); -#else - mdelay(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy(data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", - 0 /*usb_pipein(pipe) */); -#else - mdelay(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < - 0) { - err("sohci_submit_job failed"); - return -1; - } - - mdelay(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipebulk(pipe)) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - mdelay(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } - -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub(&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here - in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv(&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset(struct ohci *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { - /* SMM owns the HC - request ownership */ - writel(OHCI_OCR, &ohci->regs->cmdstatus); - info("USB HC TakeOver from SMM"); - while (readl(&ohci->regs->control) & OHCI_CTRL_IR) { - mdelay(10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, readl(&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel(0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel(OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay(1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start(struct ohci *ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel(0, &ohci->regs->ed_controlhead); - writel(0, &ohci->regs->ed_bulkhead); - - /* a reset clears this */ - writel((__u32) ohci->hcca, &ohci->regs->hcca); - - fminterval = 0x2edf; - writel((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel(fminterval, &ohci->regs->fminterval); - writel(0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel(ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel(mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel(mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel(mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel(RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay((roothub_a(ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int hc_interrupt(void) -{ - struct ohci *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(m32_swap(ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else { - ints = readl(®s->intrstatus); - if (ints == ~(u32) 0) { - ohci->disabled++; - err("%s device removed!", ohci->slot_name); - return -1; - } - ints &= readl(®s->intrenable); - if (ints == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - } - - /* dbg("Interrupt: %x frame: %x", ints, - le16_to_cpu(ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump(ohci, 1); -#else - mdelay(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset(ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - mdelay(1); - - writel(OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci)); - writel(OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel(OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; - mdelay(1); - writel(OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel(OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel(ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci(struct ohci *ohci) -{ - dbg("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset(ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); - - /* - * Set the 48 MHz UPLL clocking. Values are taken from - * "PLL value selection guide", 6-23, s3c2400_UM.pdf. - */ - clk_power->upllcon = ((40 << 12) + (1 << 4) + 2); - gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */ - - /* - * Enable USB host clock. - */ - clk_power->clkcon |= (1 << 4); - - memset(&gohci, 0, sizeof(struct ohci)); - memset(&urb_priv, 0, sizeof(struct urb_priv)); - - /* align the storage */ - if ((__u32) &ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32) &ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1)); - if ((__u32) gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset(phcca, 0, sizeof(struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE; - - gohci.flags = 0; - gohci.slot_name = "s3c2400"; - - if (hc_reset(&gohci) < 0) { - hc_release_ohci(&gohci); - /* Initialization failed */ - clk_power->clkcon &= ~(1 << 4); - return -1; - } - - /* FIXME this is a second HC reset; why?? */ - gohci.hc_control = OHCI_USB_RESET; - writel(gohci.hc_control, &gohci.regs->control); - mdelay(10); - - if (hc_start(&gohci) < 0) { - err("can't start usb-%s", gohci.slot_name); - hc_release_ohci(&gohci); - /* Initialization failed */ - clk_power->clkcon &= ~(1 << 4); - return -1; - } -#ifdef DEBUG - ohci_dump(&gohci, 1); -#else - mdelay(1); -#endif - ohci_inited = 1; - urb_finished = 1; - - return 0; -} - -int usb_lowlevel_stop(int index) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset(&gohci); - /* may not want to do this */ - clk_power->clkcon &= ~(1 << 4); - return 0; -} - -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */ - -#if defined(CONFIG_USB_OHCI_NEW) && \ - defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ - defined(CONFIG_S3C24X0) - -int usb_cpu_init(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); - - /* - * Set the 48 MHz UPLL clocking. Values are taken from - * "PLL value selection guide", 6-23, s3c2400_UM.pdf. - */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); - /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); - - /* - * Enable USB host clock. - */ - writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); - - return 0; -} - -int usb_cpu_stop(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - /* may not want to do this */ - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); - return 0; -} - -int usb_cpu_init_fail(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); - return 0; -} - -#endif /* defined(CONFIG_USB_OHCI_NEW) && \ - defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ - defined(CONFIG_S3C24X0) */ diff --git a/drivers/usb/host/ohci-s3c24xx.h b/drivers/usb/host/ohci-s3c24xx.h deleted file mode 100644 index f272d78..0000000 --- a/drivers/usb/host/ohci-s3c24xx.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute__ ((aligned(16))); - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f) -#define TD_CC_SET(td_p, cc) \ - {(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)} -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute__ ((aligned(32))); - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute__ ((aligned(256))); - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute__ ((aligned(32))); - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status */ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -struct urb_priv { - struct ed *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs - associated with this request */ -}; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma; */ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */ - struct ed *ed_bulktail; /* last endpoint of bulk list */ - struct ed *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -}; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - struct ed ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(struct ohci *ohci, struct ed *ed); -static int ep_unlink(struct ohci *ohci, struct ed *ed); -static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -struct td gtd[NUM_TD + 1]; - -/* pointers to aligned storage */ -struct td *ptd; - -/* TDs ... */ -static inline struct td *td_alloc(struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) { - if (ptd[i].usb_dev == NULL) { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void ed_free(struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index db0924c..2350831 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -115,9 +115,7 @@ struct td { __u32 hwNextTD; /* Next TD Pointer */ __u32 hwBE; /* Memory Buffer End Pointer */ -/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */ __u16 hwPSW[MAXPSW]; -/* #endif */ __u8 unused; __u8 index; struct ed *ed; @@ -141,13 +139,8 @@ typedef struct td td_t; #define NUM_INTS 32 /* part of the OHCI standard */ struct ohci_hcca { __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) - __u16 pad1; /* set to 0 on each frame_no change */ - __u16 frame_no; /* current frame number */ -#else __u16 frame_no; /* current frame number */ __u16 pad1; /* set to 0 on each frame_no change */ -#endif __u32 done_head; /* info returned for an interrupt */ u8 reserved_for_hc[116]; } __attribute__((aligned(256))); diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index 38e1c68..c4ae55f 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -11,10 +11,10 @@ #include #include #include -#include #include #include #include +#include #include "xhci.h" @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; struct rockchip_xhci_platdata { fdt_addr_t hcd_base; fdt_addr_t phy_base; - struct gpio_desc vbus_gpio; + struct udevice *vbus_supply; }; /* @@ -66,11 +66,13 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) return -ENXIO; } - /* Vbus gpio */ - ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0, - &plat->vbus_gpio, GPIOD_IS_OUT); +#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) + /* Vbus regulator */ + ret = device_get_supply_regulator(dev, "vbus-supply", + &plat->vbus_supply); if (ret) - debug("rockchip,vbus-gpio node missing!"); + debug("Can't get vbus supply\n"); +#endif return 0; } @@ -153,9 +155,11 @@ static int xhci_usb_probe(struct udevice *dev) hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); - /* setup the Vbus gpio here */ - if (dm_gpio_is_valid(&plat->vbus_gpio)) - dm_gpio_set_value(&plat->vbus_gpio, 1); +#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) + ret = regulator_set_enable(plat->vbus_supply, true); + if (ret) + debug("XHCI: Failed to enable vbus supply\n"); +#endif ret = rockchip_xhci_core_init(ctx, dev); if (ret) { @@ -168,6 +172,7 @@ static int xhci_usb_probe(struct udevice *dev) static int xhci_usb_remove(struct udevice *dev) { + struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); struct rockchip_xhci *ctx = dev_get_priv(dev); int ret; @@ -178,11 +183,18 @@ static int xhci_usb_remove(struct udevice *dev) if (ret) return ret; +#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) + ret = regulator_set_enable(plat->vbus_supply, false); + if (ret) + debug("XHCI: Failed to disable vbus supply\n"); +#endif + return 0; } static const struct udevice_id xhci_usb_ids[] = { { .compatible = "rockchip,rk3399-xhci" }, + { .compatible = "rockchip,rk3328-xhci" }, { } }; @@ -202,6 +214,7 @@ U_BOOT_DRIVER(usb_xhci) = { static const struct udevice_id usb_phy_ids[] = { { .compatible = "rockchip,rk3399-usb3-phy" }, + { .compatible = "rockchip,rk3328-usb3-phy" }, { } }; diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 58f5de5..ac5371f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o -obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 47078fd..f77da2e 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -426,7 +426,9 @@ static void atmel_hlcdc_init(struct udevice *dev) writel(~0UL, ®s->lcdc_baseidr); /* Setup the DMA descriptor, this descriptor will loop to itself */ - desc = (struct lcd_dma_desc *)(uc_plat->base - 16); + desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc)); + if (!desc) + return; desc->address = (u32)uc_plat->base; @@ -436,7 +438,9 @@ static void atmel_hlcdc_init(struct udevice *dev) desc->next = (u32)desc; /* Flush the DMA descriptor if we enabled dcache */ - flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); + flush_dcache_range((u32)desc, + ALIGN(((u32)desc + sizeof(*desc)), + CONFIG_SYS_CACHELINE_SIZE)); writel(desc->address, ®s->lcdc_baseaddr); writel(desc->control, ®s->lcdc_basectrl); diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c deleted file mode 100644 index b08576e..0000000 --- a/drivers/video/mpc8xx_lcd.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -/* #define DEBUG */ - -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_POST) -#include -#endif -#include - -#ifdef CONFIG_LCD - -/************************************************************************/ -/* ** CONFIG STUFF -- should be moved to board config file */ -/************************************************************************/ -#ifndef CONFIG_LCD_INFO -#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ -#endif - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_KYOCERA_KCS057QV1AJ -/* - * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. - */ -#define LCD_BPP LCD_COLOR4 - -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SP19X001_Z1A -/* - * Hitachi SP19X001-. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HITACHI_SP19X001_Z1A */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_NEC_NL6448AC33 -/* - * NEC NL6448AC33-18. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448AC33 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC20 -/* - * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC20 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC33_54 -/* - * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC33_54 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ104V7DS01 -/* - * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, - 3, 0, 0, 1, 1, 25, 1, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ104V7DS01 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_16x9 -/* - * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am - * not sure what it is....... - */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 -}; -#endif /* CONFIG_SHARP_16x9 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ057Q3DC02 -/* - * Sharp LQ057Q3DC02 display. Active, color, single scan. - */ -#undef LCD_DF -#define LCD_DF 12 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ057Q3DC02 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ64D341 -/* - * Sharp LQ64D341 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 128, 16, 0, 32 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ64D341 */ - -#ifdef CONFIG_SHARP_LQ065T9DR51U -/* - * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. - */ -vidinfo_t panel_info = { - 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 248, 4, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ065T9DR51U */ - -#ifdef CONFIG_SHARP_LQ084V1DG21 -/* - * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ084V1DG21 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_HLD1045 -/* - * HLD1045 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HLD1045 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_PRIMEVIEW_V16C6448AC -/* - * Prime View V16C6448AC - */ -vidinfo_t panel_info = { - 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_OPTREX_BW -/* - * Optrex CBL50840-2 NF-FW 99 22 M5 - * or - * Hitachi LMG6912RPFC-00T - * or - * Hitachi SP14Q002 - * - * 320x240. Black & white. - */ -#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ - /* 1 - 4 grey levels, 2 bpp */ - /* 2 - 16 grey levels, 4 bpp */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, - OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 -}; -#endif /* CONFIG_OPTREX_BW */ - -/************************************************************************/ -/* ----------------- chipset specific functions ----------------------- */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - - return size; -} - -void lcd_ctrl_init (void *lcdbase) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - uint lccrtmp; - uint lchcr_hpc_tmp; - - /* Initialize the LCD control register according to the LCD - * parameters defined. We do everything here but enable - * the controller. - */ - - lccrtmp = LCDBIT (LCCR_BNUM_BIT, - (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); - - lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | - LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | - LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | - LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | - LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | - LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | - LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | - LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | - LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | - LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); - -#if 0 - lccrtmp |= ((SIU_LEVEL5 / 2) << 12); - lccrtmp |= LCCR_EIEN; -#endif - - lcdp->lcd_lccr = lccrtmp; - lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ - - /* Initialize LCD controller bus priorities. - */ - immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ - - /* set SHFT/CLOCK division factor 4 - * This needs to be set based upon display type and processor - * speed. The TFT displays run about 20 to 30 MHz. - * I was running 64 MHz processor speed. - * The value for this divider must be chosen so the result is - * an integer of the processor speed (i.e., divide by 3 with - * 64 MHz would be bad). - */ - immr->im_clkrst.car_sccr &= ~0x1F; - immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ - - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1FFF; - immr->im_ioport.iop_pddir |= 0x1FFF; - - /* Enable LCD_A/B/C on port B. - */ - immr->im_cpm.cp_pbpar |= 0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; - - /* Load the physical address of the linear frame buffer - * into the LCD controller. - * BIG NOTE: This has to be modified to load A and B depending - * upon the split mode of the LCD. - */ - lcdp->lcd_lcfaa = (ulong)lcdbase; - lcdp->lcd_lcfba = (ulong)lcdbase; - - /* MORE HACKS...This must be updated according to 823 manual - * for different panels. - * Udi Finkelstein - done - see below: - * Note: You better not try unsupported combinations such as - * 4-bit wide passive dual scan LCD at 4/8 Bit color. - */ - lchcr_hpc_tmp = - (panel_info.vl_col * - (panel_info.vl_tft ? 8 : - (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ - /* use << to mult by: single scan = 1, dual scan = 2 */ - panel_info.vl_splt) * - (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ - - lcdp->lcd_lchcr = LCHCR_BO | - LCDBIT (LCHCR_AT_BIT, 4) | - LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | - panel_info.vl_wbl; - - lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | - LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | - LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | - panel_info.vl_wbf; - -} - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = ((red & 0x0F) << 8) | - ((green & 0x0F) << 4) | - (blue & 0x0F) ; - - *cmap_ptr = colreg; - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", - regno, &(cp->lcd_cmap[regno * 2]), - red, green, blue, - cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ - -ushort *configuration_get_cmap(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - cpm8xx_t *cp = &(immr->im_cpm); - return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]); -} - -#if defined(CONFIG_MPC823) -void fb_put_byte(uchar **fb, uchar **from) -{ - *(*fb)++ = (255 - *(*from)++); -} -#endif - -#ifdef CONFIG_LCD_LOGO -#include -void lcd_logo_set_cmap(void) -{ - int i; - ushort *cmap; - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - cpm8xx_t *cp = &(immr->im_cpm); - cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]); - - for (i = 0; i < BMP_LOGO_COLORS; ++i) - *cmap++ = bmp_logo_palette[i]; -} -#endif - -void lcd_enable (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - /* Enable the LCD panel */ - immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ - lcdp->lcd_lccr |= LCCR_PON; -} - -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 80e399f..b1d7c62 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -12,11 +12,30 @@ menuconfig VIDEO_ROCKCHIP bool "Enable Rockchip Video Support" depends on DM_VIDEO help - Rockchip SoCs provide video output capabilities for High-Definition - Multimedia Interface (HDMI), Low-voltage Differential Signalling - (LVDS), embedded DisplayPort (eDP) and Display Serial Interface - (DSI). This driver supports the on-chip video output device, and - targets the Rockchip RK3288 and RK3399. + Rockchip SoCs provide video output capabilities for High-Definition + Multimedia Interface (HDMI), Low-voltage Differential Signalling + (LVDS), embedded DisplayPort (eDP) and Display Serial Interface (DSI). + + This driver supports the on-chip video output device, and targets the + Rockchip RK3288 and RK3399. + +config VIDEO_ROCKCHIP_MAX_XRES + int "Maximum horizontal resolution (for memory allocation purposes)" + depends on VIDEO_ROCKCHIP + default 1920 + help + The maximum horizontal resolution to support for the framebuffer. + This configuration is used for reserving/allocating memory for the + framebuffer during device-model binding/probing. + +config VIDEO_ROCKCHIP_MAX_YRES + int "Maximum vertical resolution (for memory allocation purposes)" + depends on VIDEO_ROCKCHIP + default 1080 + help + The maximum vertical resolution to support for the framebuffer. + This configuration is used for reserving/allocating memory for the + framebuffer during device-model binding/probing. if VIDEO_ROCKCHIP diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index cd54b12..872dc0f 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -7,8 +7,12 @@ ifdef CONFIG_VIDEO_ROCKCHIP obj-y += rk_vop.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o +obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o -obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o +obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o +obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y) obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o endif diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c new file mode 100644 index 0000000..eae0dd2 --- /dev/null +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk_hdmi.h" + +static int rk3288_hdmi_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *edid) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + int vop_id = uc_plat->source_id; + struct rk3288_grf *grf = priv->grf; + + /* hdmi source select hdmi controller */ + rk_setreg(&grf->soc_con6, 1 << 15); + + /* hdmi data from vop id */ + rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); + + return 0; +} + +static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; + + hdmi->i2c_clk_high = 0x7a; + hdmi->i2c_clk_low = 0x8d; + + /* + * TODO(sjg@chromium.org): The above values don't work - these + * ones work better, but generate lots of errors in the data. + */ + hdmi->i2c_clk_high = 0x0d; + hdmi->i2c_clk_low = 0x0d; + + return rk_hdmi_ofdata_to_platdata(dev); +} + +static int rk3288_clk_config(struct udevice *dev) +{ + struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + struct clk clk; + int ret; + + /* + * Configure the maximum clock to permit whatever resolution the + * monitor wants + */ + ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); + if (ret >= 0) { + ret = clk_set_rate(&clk, 384000000); + clk_free(&clk); + } + if (ret < 0) { + debug("%s: Failed to set clock in source device '%s': ret=%d\n", + __func__, uc_plat->src_dev->name, ret); + return ret; + } + + return 0; +} + +static const char * const rk3288_regulator_names[] = { + "vcc50_hdmi" +}; + +static int rk3288_hdmi_probe(struct udevice *dev) +{ + /* Enable VOP clock for RK3288 */ + rk3288_clk_config(dev); + + /* Enable regulators required for HDMI */ + rk_hdmi_probe_regulators(dev, rk3288_regulator_names, + ARRAY_SIZE(rk3288_regulator_names)); + + return rk_hdmi_probe(dev); +} + +static const struct dm_display_ops rk3288_hdmi_ops = { + .read_edid = rk_hdmi_read_edid, + .enable = rk3288_hdmi_enable, +}; + +static const struct udevice_id rk3288_hdmi_ids[] = { + { .compatible = "rockchip,rk3288-dw-hdmi" }, + { } +}; + +U_BOOT_DRIVER(rk3288_hdmi_rockchip) = { + .name = "rk3288_hdmi_rockchip", + .id = UCLASS_DISPLAY, + .of_match = rk3288_hdmi_ids, + .ops = &rk3288_hdmi_ops, + .ofdata_to_platdata = rk3288_hdmi_ofdata_to_platdata, + .probe = rk3288_hdmi_probe, + .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv), +}; diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c new file mode 100644 index 0000000..3a5740a --- /dev/null +++ b/drivers/video/rockchip/rk3288_vop.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk_vop.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void rk3288_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + /* The RK3328 VOP (v3.1) has its polarity configuration in ctrl0 */ + clrsetbits_le32(®s->dsp_ctrl0, + M_DSP_DCLK_POL | M_DSP_DEN_POL | + M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, + V_DSP_PIN_POL(polarity)); +} + +static void rk3288_set_io_vsel(struct udevice *dev) +{ + struct rk3288_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* lcdc(vop) iodomain select 1.8V */ + rk_setreg(&grf->io_vsel, 1 << 0); +} + +/* + * Try some common regulators. We should really get these from the + * device tree somehow. + */ +static const char * const rk3288_regulator_names[] = { + "vcc18_lcd", + "VCC18_LCD", + "vdd10_lcd_pwren_h", + "vdd10_lcd", + "VDD10_LCD", + "vcc33_lcd" +}; + +static int rk3288_vop_probe(struct udevice *dev) +{ + /* Before relocation we don't need to do anything */ + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + /* Set the LCDC(vop) iodomain to 1.8V */ + rk3288_set_io_vsel(dev); + + /* Probe regulators required for the RK3288 VOP */ + rk_vop_probe_regulators(dev, rk3288_regulator_names, + ARRAY_SIZE(rk3288_regulator_names)); + + return rk_vop_probe(dev); +} + +static int rk_vop_remove(struct udevice *dev) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + setbits_le32(®s->sys_ctrl, V_STANDBY_EN(1)); + + /* wait frame complete (60Hz) to enter standby */ + mdelay(17); + + return 0; +} + +struct rkvop_driverdata rk3288_driverdata = { + .features = VOP_FEATURE_OUTPUT_10BIT, + .set_pin_polarity = rk3288_set_pin_polarity, +}; + +static const struct udevice_id rk3288_vop_ids[] = { + { .compatible = "rockchip,rk3288-vop", + .data = (ulong)&rk3288_driverdata }, + { } +}; + +static const struct video_ops rk3288_vop_ops = { +}; + +U_BOOT_DRIVER(rk_vop) = { + .name = "rk3288_vop", + .id = UCLASS_VIDEO, + .of_match = rk3288_vop_ids, + .ops = &rk3288_vop_ops, + .bind = rk_vop_bind, + .probe = rk3288_vop_probe, + .remove = rk_vop_remove, + .priv_auto_alloc_size = sizeof(struct rk_vop_priv), +}; diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c new file mode 100644 index 0000000..b1e5097 --- /dev/null +++ b/drivers/video/rockchip/rk3399_hdmi.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk_hdmi.h" + +static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *edid) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + int vop_id = uc_plat->source_id; + struct rk3399_grf_regs *grf = priv->grf; + + /* select the hdmi encoder input data from our source_id */ + rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK, + (vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0); + + return dw_hdmi_enable(&priv->hdmi, edid); +} + +static int rk3399_hdmi_ofdata_to_platdata(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; + + hdmi->i2c_clk_high = 0x7a; + hdmi->i2c_clk_low = 0x8d; + + return rk_hdmi_ofdata_to_platdata(dev); +} + +static const char * const rk3399_regulator_names[] = { + "vcc1v8_hdmi", + "vcc0v9_hdmi" +}; + +static int rk3399_hdmi_probe(struct udevice *dev) +{ + /* Enable regulators required for HDMI */ + rk_hdmi_probe_regulators(dev, rk3399_regulator_names, + ARRAY_SIZE(rk3399_regulator_names)); + + return rk_hdmi_probe(dev); +} + +static const struct dm_display_ops rk3399_hdmi_ops = { + .read_edid = rk_hdmi_read_edid, + .enable = rk3399_hdmi_enable, +}; + +static const struct udevice_id rk3399_hdmi_ids[] = { + { .compatible = "rockchip,rk3399-dw-hdmi" }, + { } +}; + +U_BOOT_DRIVER(rk3399_hdmi_rockchip) = { + .name = "rk3399_hdmi_rockchip", + .id = UCLASS_DISPLAY, + .of_match = rk3399_hdmi_ids, + .ops = &rk3399_hdmi_ops, + .ofdata_to_platdata = rk3399_hdmi_ofdata_to_platdata, + .probe = rk3399_hdmi_probe, + .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv), +}; diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c new file mode 100644 index 0000000..91a40ab --- /dev/null +++ b/drivers/video/rockchip/rk3399_vop.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rk_vop.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void rk3399_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + /* + * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of + * the polarity configuration (in ctrl1). + */ + switch (mode) { + case VOP_MODE_HDMI: + clrsetbits_le32(®s->dsp_ctrl1, + M_RK3399_DSP_HDMI_POL, + V_RK3399_DSP_HDMI_POL(polarity)); + break; + + case VOP_MODE_EDP: + clrsetbits_le32(®s->dsp_ctrl1, + M_RK3399_DSP_EDP_POL, + V_RK3399_DSP_EDP_POL(polarity)); + break; + + case VOP_MODE_MIPI: + clrsetbits_le32(®s->dsp_ctrl1, + M_RK3399_DSP_MIPI_POL, + V_RK3399_DSP_MIPI_POL(polarity)); + break; + + case VOP_MODE_LVDS: + /* The RK3399 has neither parallel RGB nor LVDS output. */ + default: + debug("%s: unsupported output mode %x\n", __func__, mode); + } +} + +/* + * Try some common regulators. We should really get these from the + * device tree somehow. + */ +static const char * const rk3399_regulator_names[] = { + "vcc33_lcd" +}; + +static int rk3399_vop_probe(struct udevice *dev) +{ + /* Before relocation we don't need to do anything */ + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + /* Probe regulators required for the RK3399 VOP */ + rk_vop_probe_regulators(dev, rk3399_regulator_names, + ARRAY_SIZE(rk3399_regulator_names)); + + return rk_vop_probe(dev); +} + +struct rkvop_driverdata rk3399_lit_driverdata = { + .set_pin_polarity = rk3399_set_pin_polarity, +}; + +struct rkvop_driverdata rk3399_big_driverdata = { + .features = VOP_FEATURE_OUTPUT_10BIT, + .set_pin_polarity = rk3399_set_pin_polarity, +}; + +static const struct udevice_id rk3399_vop_ids[] = { + { .compatible = "rockchip,rk3399-vop-big", + .data = (ulong)&rk3399_big_driverdata }, + { .compatible = "rockchip,rk3399-vop-lit", + .data = (ulong)&rk3399_lit_driverdata }, + { } +}; + +static const struct video_ops rk3399_vop_ops = { +}; + +U_BOOT_DRIVER(rk3399_vop) = { + .name = "rk3399_vop", + .id = UCLASS_VIDEO, + .of_match = rk3399_vop_ids, + .ops = &rk3399_vop_ops, + .bind = rk_vop_bind, + .probe = rk3399_vop_probe, + .priv_auto_alloc_size = sizeof(struct rk_vop_priv), +}; diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 4e2030e..1527f96 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1004,7 +1004,20 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev) return 0; } -int rk_edp_probe(struct udevice *dev) +static int rk_edp_remove(struct udevice *dev) +{ + struct rk_edp_priv *priv = dev_get_priv(dev); + struct rk3288_edp *regs = priv->regs; + + setbits_le32(®s->video_ctl_1, VIDEO_MUTE); + clrbits_le32(®s->video_ctl_1, VIDEO_EN); + clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL); + setbits_le32(®s->func_en_1, SW_FUNC_EN_N); + + return 0; +} + +static int rk_edp_probe(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct rk_edp_priv *priv = dev_get_priv(dev); @@ -1080,5 +1093,6 @@ U_BOOT_DRIVER(dp_rockchip) = { .ops = &dp_rockchip_ops, .ofdata_to_platdata = rk_edp_ofdata_to_platdata, .probe = rk_edp_probe, + .remove = rk_edp_remove, .priv_auto_alloc_size = sizeof(struct rk_edp_priv), }; diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index cd695ca..a9c8fba 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -1,4 +1,5 @@ /* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. * @@ -14,15 +15,12 @@ #include #include #include +#include #include #include -#include -#include - -struct rk_hdmi_priv { - struct dw_hdmi hdmi; - struct rk3288_grf *grf; -}; +#include +#include "rk_hdmi.h" +#include "rk_vop.h" /* for rk_vop_probe_regulators */ static const struct hdmi_phy_config rockchip_phy_config[] = { { @@ -35,6 +33,9 @@ static const struct hdmi_phy_config rockchip_phy_config[] = { .mpixelclock = 297000000, .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, }, { + .mpixelclock = 584000000, + .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d, + }, { .mpixelclock = ~0ul, .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000, } @@ -60,27 +61,25 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { .mpixelclock = 148500000, .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, }, { + .mpixelclock = 272000000, + .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000, + }, { + .mpixelclock = 340000000, + .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000, + }, { .mpixelclock = ~0ul, .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, } }; -static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) +int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) { struct rk_hdmi_priv *priv = dev_get_priv(dev); return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); } -static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, - const struct display_timing *edid) -{ - struct rk_hdmi_priv *priv = dev_get_priv(dev); - - return dw_hdmi_enable(&priv->hdmi, edid); -} - -static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) +int rk_hdmi_ofdata_to_platdata(struct udevice *dev) { struct rk_hdmi_priv *priv = dev_get_priv(dev); struct dw_hdmi *hdmi = &priv->hdmi; @@ -88,15 +87,9 @@ static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) hdmi->ioaddr = (ulong)devfdt_get_addr(dev); hdmi->mpll_cfg = rockchip_mpll_cfg; hdmi->phy_cfg = rockchip_phy_config; - hdmi->i2c_clk_high = 0x7a; - hdmi->i2c_clk_low = 0x8d; - - /* - * TODO(sjg@chromium.org): The above values don't work - these ones - * work better, but generate lots of errors in the data. - */ - hdmi->i2c_clk_high = 0x0d; - hdmi->i2c_clk_low = 0x0d; + + /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */ + hdmi->reg_io_width = 4; hdmi->phy_set = dw_hdmi_phy_cfg; @@ -105,53 +98,17 @@ static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) return 0; } -static int rk_hdmi_probe(struct udevice *dev) +void rk_hdmi_probe_regulators(struct udevice *dev, + const char * const *names, int cnt) +{ + rk_vop_probe_regulators(dev, names, cnt); +} + +int rk_hdmi_probe(struct udevice *dev) { - struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct rk_hdmi_priv *priv = dev_get_priv(dev); struct dw_hdmi *hdmi = &priv->hdmi; - struct udevice *reg; - struct clk clk; int ret; - int vop_id = uc_plat->source_id; - - ret = clk_get_by_index(dev, 0, &clk); - if (ret >= 0) { - ret = clk_set_rate(&clk, 0); - clk_free(&clk); - } - if (ret) { - debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret); - return ret; - } - - /* - * Configure the maximum clock to permit whatever resolution the - * monitor wants - */ - ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); - if (ret >= 0) { - ret = clk_set_rate(&clk, 384000000); - clk_free(&clk); - } - if (ret < 0) { - debug("%s: Failed to set clock in source device '%s': ret=%d\n", - __func__, uc_plat->src_dev->name, ret); - return ret; - } - - ret = regulator_get_by_platname("vcc50_hdmi", ®); - if (!ret) - ret = regulator_set_enable(reg, true); - if (ret) - debug("%s: Cannot set regulator vcc50_hdmi\n", __func__); - - /* hdmi source select hdmi controller */ - rk_setreg(&priv->grf->soc_con6, 1 << 15); - - /* hdmi data from vop id */ - rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, - (vop_id == 1) ? (1 << 4) : 0); ret = dw_hdmi_phy_wait_for_hpd(hdmi); if (ret < 0) { @@ -164,23 +121,3 @@ static int rk_hdmi_probe(struct udevice *dev) return 0; } - -static const struct dm_display_ops rk_hdmi_ops = { - .read_edid = rk_hdmi_read_edid, - .enable = rk_hdmi_enable, -}; - -static const struct udevice_id rk_hdmi_ids[] = { - { .compatible = "rockchip,rk3288-dw-hdmi" }, - { } -}; - -U_BOOT_DRIVER(hdmi_rockchip) = { - .name = "hdmi_rockchip", - .id = UCLASS_DISPLAY, - .of_match = rk_hdmi_ids, - .ops = &rk_hdmi_ops, - .ofdata_to_platdata = rk_hdmi_ofdata_to_platdata, - .probe = rk_hdmi_probe, - .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv), -}; diff --git a/drivers/video/rockchip/rk_hdmi.h b/drivers/video/rockchip/rk_hdmi.h new file mode 100644 index 0000000..ec39668 --- /dev/null +++ b/drivers/video/rockchip/rk_hdmi.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RK_HDMI_H__ +#define __RK_HDMI_H__ + +struct rkhdmi_driverdata { + /* configuration */ + u8 i2c_clk_high; + u8 i2c_clk_low; + const char * const *regulator_names; + u32 regulator_names_cnt; + /* setters/getters */ + int (*set_input_vop)(struct udevice *dev); + int (*clk_config)(struct udevice *dev); +}; + +struct rk_hdmi_priv { + struct dw_hdmi hdmi; + void *grf; +}; + +/** + * rk_hdmi_read_edid() - read the attached HDMI/DVI monitor's EDID + * + * N.B.: The buffer should be large enough to hold 2 EDID blocks, as + * this function calls dw_hdmi_read_edid, which ignores buf_size + * argument and assumes that there's always enough space for 2 + * EDID blocks. + * + * @dev: device + * @buf: output buffer for the EDID + * @buf_size: number of bytes in the buffer + * @return number of bytes read if OK, -ve if something went wrong + */ +int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size); + +/** + * rk_hdmi_probe_regulators() - probe (autoset + enable) regulators + * + * Probes a list of regulators by performing autoset and enable + * operations on them. The list of regulators is an array of string + * pointers and any individual regulator-probe may fail without + * counting as an error. + * + * @dev: device + * @names: array of string-pointers to regulator names to probe + * @cnt: number of elements in the 'names' array + */ +void rk_hdmi_probe_regulators(struct udevice *dev, + const char * const *names, int cnt); +/** + * rk_hdmi_ofdata_to_platdata() - common ofdata_to_platdata implementation + * + * @dev: device + * @return 0 if OK, -ve if something went wrong + */ +int rk_hdmi_ofdata_to_platdata(struct udevice *dev); + +/** + * rk_hdmi_probe() - common probe implementation + * + * Performs the following, common initialisation steps: + * 1. checks for HPD (i.e. a HDMI monitor being attached) + * 2. initialises the Designware HDMI core + * 3. initialises the Designware HDMI PHY + * + * @dev: device + * @return 0 if OK, -ve if something went wrong + */ +int rk_hdmi_probe(struct udevice *dev); + +#endif diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 48bfcd4..c979049 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -17,24 +17,25 @@ #include #include #include -#include -#include #include #include #include #include -#include #include +#include "rk_vop.h" DECLARE_GLOBAL_DATA_PTR; -struct rk_vop_priv { - struct rk3288_vop *regs; - struct rk3288_grf *grf; +enum vop_pol { + HSYNC_POSITIVE = 0, + VSYNC_POSITIVE = 1, + DEN_NEGATIVE = 2, + DCLK_INVERT = 3 }; -void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, - int fb_bits_per_pixel, const struct display_timing *edid) +static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, + int fb_bits_per_pixel, + const struct display_timing *edid) { u32 lb_mode; u32 rgb_mode; @@ -89,54 +90,86 @@ void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, writel(0x01, ®s->reg_cfg_done); /* enable reg config */ } -void rkvop_mode_set(struct rk3288_vop *regs, - const struct display_timing *edid, enum vop_modes mode) +static void rkvop_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) { - u32 hactive = edid->hactive.typ; - u32 vactive = edid->vactive.typ; - u32 hsync_len = edid->hsync_len.typ; - u32 hback_porch = edid->hback_porch.typ; - u32 vsync_len = edid->vsync_len.typ; - u32 vback_porch = edid->vback_porch.typ; - u32 hfront_porch = edid->hfront_porch.typ; - u32 vfront_porch = edid->vfront_porch.typ; - uint flags; - int mode_flags; + struct rkvop_driverdata *ops = + (struct rkvop_driverdata *)dev_get_driver_data(dev); + + if (ops->set_pin_polarity) + ops->set_pin_polarity(dev, mode, polarity); +} + +static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + /* remove from standby */ + clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1)); switch (mode) { case VOP_MODE_HDMI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); break; + case VOP_MODE_EDP: - default: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1)); break; + case VOP_MODE_LVDS: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_RGB_OUT_EN(1)); break; + case VOP_MODE_MIPI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_MIPI_OUT_EN(1)); - break; + break; + + default: + debug("%s: unsupported output mode %x\n", __func__, mode); } +} - if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP) - /* RGBaaa */ - mode_flags = 15; - else - /* RGB888 */ - mode_flags = 0; +static void rkvop_mode_set(struct udevice *dev, + const struct display_timing *edid, + enum vop_modes mode) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + struct rkvop_driverdata *data = + (struct rkvop_driverdata *)dev_get_driver_data(dev); + + u32 hactive = edid->hactive.typ; + u32 vactive = edid->vactive.typ; + u32 hsync_len = edid->hsync_len.typ; + u32 hback_porch = edid->hback_porch.typ; + u32 vsync_len = edid->vsync_len.typ; + u32 vback_porch = edid->vback_porch.typ; + u32 hfront_porch = edid->hfront_porch.typ; + u32 vfront_porch = edid->vfront_porch.typ; + int mode_flags; + u32 pin_polarity; + + pin_polarity = BIT(DCLK_INVERT); + if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) + pin_polarity |= BIT(HSYNC_POSITIVE); + if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH) + pin_polarity |= BIT(VSYNC_POSITIVE); + + rkvop_set_pin_polarity(dev, mode, pin_polarity); + rkvop_enable_output(dev, mode); - flags = V_DSP_OUT_MODE(mode_flags) | - V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) | - V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)); + mode_flags = 0; /* RGB888 */ + if ((data->features & VOP_FEATURE_OUTPUT_10BIT) && + (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)) + mode_flags = 15; /* RGBaaa */ - clrsetbits_le32(®s->dsp_ctrl0, - M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, - flags); + clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE, + V_DSP_OUT_MODE(mode_flags)); writel(V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), @@ -185,7 +218,7 @@ void rkvop_mode_set(struct rk3288_vop *regs, * node within the VOP's 'port' list. * @return 0 if OK, -ve if something went wrong */ -int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) +static int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); const void *blob = gd->fdt_blob; @@ -255,18 +288,18 @@ int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) /* Set bitwidth for vop display according to vop mode */ switch (vop_id) { case VOP_MODE_EDP: - case VOP_MODE_HDMI: case VOP_MODE_LVDS: l2bpp = VIDEO_BPP16; break; + case VOP_MODE_HDMI: case VOP_MODE_MIPI: l2bpp = VIDEO_BPP32; break; default: l2bpp = VIDEO_BPP16; } - rkvop_mode_set(regs, &timing, vop_id); + rkvop_mode_set(dev, &timing, vop_id); rkvop_enable(regs, fbbase, 1 << l2bpp, &timing); ret = display_enable(disp, 1 << l2bpp, &timing); @@ -281,53 +314,37 @@ int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node) return 0; } -static int rk_vop_probe(struct udevice *dev) +void rk_vop_probe_regulators(struct udevice *dev, + const char * const *names, int cnt) +{ + int i, ret; + const char *name; + struct udevice *reg; + + for (i = 0; i < cnt; ++i) { + name = names[i]; + debug("%s: probing regulator '%s'\n", dev->name, name); + + ret = regulator_autoset_by_name(name, ®); + if (!ret) + ret = regulator_set_enable(reg, true); + } +} + +int rk_vop_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); const void *blob = gd->fdt_blob; struct rk_vop_priv *priv = dev_get_priv(dev); - struct udevice *reg; - int ret, port, node; + int ret = 0; + int port, node; /* Before relocation we don't need to do anything */ if (!(gd->flags & GD_FLG_RELOC)) return 0; - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->regs = (struct rk3288_vop *)devfdt_get_addr(dev); - /* lcdc(vop) iodomain select 1.8V */ - rk_setreg(&priv->grf->io_vsel, 1 << 0); - - /* - * Try some common regulators. We should really get these from the - * device tree somehow. - */ - ret = regulator_autoset_by_name("vcc18_lcd", ®); - if (ret) - debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__); - ret = regulator_autoset_by_name("VCC18_LCD", ®); - if (ret) - debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__); - ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", ®); - if (ret) { - debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n", - __func__); - } - ret = regulator_autoset_by_name("vdd10_lcd", ®); - if (ret) { - debug("%s: Cannot autoset regulator vdd10_lcd\n", - __func__); - } - ret = regulator_autoset_by_name("VDD10_LCD", ®); - if (ret) { - debug("%s: Cannot autoset regulator VDD10_LCD\n", - __func__); - } - ret = regulator_autoset_by_name("vcc33_lcd", ®); - if (ret) - debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__); - /* * Try all the ports until we find one that works. In practice this * tries EDP first if available, then HDMI. @@ -353,31 +370,12 @@ static int rk_vop_probe(struct udevice *dev) return ret; } -static int rk_vop_bind(struct udevice *dev) +int rk_vop_bind(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); - plat->size = 1920 * 1200 * 4; + plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES * + CONFIG_VIDEO_ROCKCHIP_MAX_YRES); return 0; } - -static const struct video_ops rk_vop_ops = { -}; - -static const struct udevice_id rk_vop_ids[] = { - { .compatible = "rockchip,rk3399-vop-big" }, - { .compatible = "rockchip,rk3399-vop-lit" }, - { .compatible = "rockchip,rk3288-vop" }, - { } -}; - -U_BOOT_DRIVER(rk_vop) = { - .name = "rk_vop", - .id = UCLASS_VIDEO, - .of_match = rk_vop_ids, - .ops = &rk_vop_ops, - .bind = rk_vop_bind, - .probe = rk_vop_probe, - .priv_auto_alloc_size = sizeof(struct rk_vop_priv), -}; diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h new file mode 100644 index 0000000..b2b29c4 --- /dev/null +++ b/drivers/video/rockchip/rk_vop.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RK_VOP_H__ +#define __RK_VOP_H__ + +#include + +struct rk_vop_priv { + void *grf; + void *regs; +}; + +enum vop_features { + VOP_FEATURE_OUTPUT_10BIT = (1 << 0), +}; + +struct rkvop_driverdata { + /* configuration */ + u32 features; + /* block-specific setters/getters */ + void (*set_pin_polarity)(struct udevice *, enum vop_modes, u32); +}; + +/** + * rk_vop_probe() - common probe implementation + * + * Performs the rk_display_init on each port-subnode until finding a + * working port (or returning an error if none of the ports could be + * successfully initialised). + * + * @dev: device + * @return 0 if OK, -ve if something went wrong + */ +int rk_vop_probe(struct udevice *dev); + +/** + * rk_vop_bind() - common bind implementation + * + * Sets the plat->size field to the amount of memory to be reserved for + * the framebuffer: this is always + * (32 BPP) x VIDEO_ROCKCHIP_MAX_XRES x VIDEO_ROCKCHIP_MAX_YRES + * + * @dev: device + * @return 0 (always OK) + */ +int rk_vop_bind(struct udevice *dev); + +/** + * rk_vop_probe_regulators() - probe (autoset + enable) regulators + * + * Probes a list of regulators by performing autoset and enable + * operations on them. The list of regulators is an array of string + * pointers and any individual regulator-probe may fail without + * counting as an error. + * + * @dev: device + * @names: array of string-pointers to regulator names to probe + * @cnt: number of elements in the 'names' array + */ +void rk_vop_probe_regulators(struct udevice *dev, + const char * const *names, int cnt); + +#endif diff --git a/drivers/video/sm501.c b/drivers/video/sm501.c index cafaae5..a468bd9 100644 --- a/drivers/video/sm501.c +++ b/drivers/video/sm501.c @@ -16,6 +16,7 @@ #include #include +#include #include #include diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile index dbaab61..0d64c20 100644 --- a/drivers/video/sunxi/Makefile +++ b/drivers/video/sunxi/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve.o ../videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 9a32c3a..ee67764 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -56,7 +56,7 @@ static void sunxi_de2_composer_init(void) } static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, - int bpp, ulong address) + int bpp, ulong address, bool is_composite) { ulong de_mux_base = (mux == 0) ? SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE; @@ -72,6 +72,9 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, (struct de_ui *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS + SUNXI_DE2_MUX_CHAN_SZ * 1); + struct de_csc * const de_csc_regs = + (struct de_csc *)(de_mux_base + + SUNXI_DE2_MUX_DCSC_REGS); u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); int channel; u32 format; @@ -128,7 +131,27 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS); writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS); writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS); - writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS); + + if (is_composite) { + /* set CSC coefficients */ + writel(0x107, &de_csc_regs->coef11); + writel(0x204, &de_csc_regs->coef12); + writel(0x64, &de_csc_regs->coef13); + writel(0x4200, &de_csc_regs->coef14); + writel(0x1f68, &de_csc_regs->coef21); + writel(0x1ed6, &de_csc_regs->coef22); + writel(0x1c2, &de_csc_regs->coef23); + writel(0x20200, &de_csc_regs->coef24); + writel(0x1c2, &de_csc_regs->coef31); + writel(0x1e87, &de_csc_regs->coef32); + writel(0x1fb7, &de_csc_regs->coef33); + writel(0x20200, &de_csc_regs->coef34); + + /* enable CSC unit */ + writel(1, &de_csc_regs->csc_ctl); + } else { + writel(0, &de_csc_regs->csc_ctl); + } switch (bpp) { case 16: @@ -153,7 +176,7 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, static int sunxi_de2_init(struct udevice *dev, ulong fbbase, enum video_log2_bpp l2bpp, - struct udevice *disp, int mux) + struct udevice *disp, int mux, bool is_composite) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct display_timing timing; @@ -183,7 +206,7 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, } sunxi_de2_composer_init(); - sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase); + sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite); ret = display_enable(disp, 1 << l2bpp, &timing); if (ret) { @@ -204,7 +227,6 @@ static int sunxi_de2_probe(struct udevice *dev) struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct udevice *disp; int ret; - int mux; /* Before relocation we don't need to do anything */ if (!(gd->flags & GD_FLG_RELOC)) @@ -212,17 +234,31 @@ static int sunxi_de2_probe(struct udevice *dev) ret = uclass_find_device_by_name(UCLASS_DISPLAY, "sunxi_dw_hdmi", &disp); + if (!ret) { + int mux; + if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) + mux = 0; + else + mux = 1; + + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, + false); + if (!ret) { + video_set_flush_dcache(dev, 1); + return 0; + } + } + + debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); + + ret = uclass_find_device_by_name(UCLASS_DISPLAY, + "sunxi_tve", &disp); if (ret) { - debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); + debug("%s: tv not found (ret=%d)\n", __func__, ret); return ret; } - if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) - mux = 0; - else - mux = 1; - - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux); + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); if (ret) return ret; diff --git a/drivers/video/sunxi/tve.c b/drivers/video/sunxi/tve_common.c similarity index 100% rename from drivers/video/sunxi/tve.c rename to drivers/video/sunxi/tve_common.c diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index 5e4140f..4324071 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -466,11 +466,20 @@ void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); + u32 reg; int ret; if (sor->power_is_up) return 0; + /* + * If for some reason it is already powered up, don't do it again. + * This can happen if U-Boot is the secondary boot loader. + */ + reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); + if (reg & DP_PADCTL_PD_TXD_0_NO) + return 0; + /* Set link bw */ tegra_dc_sor_set_link_bandwidth(dev, is_lvds ? CLK_CNTRL_DP_LINK_SPEED_LVDS : diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 5a6ae00..c9d6206 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -9,9 +9,6 @@ extra-y := hello_world extra-$(CONFIG_SMC91111) += smc91111_eeprom extra-$(CONFIG_SMC911X) += smc911x_eeprom extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 -extra-$(CONFIG_MPC5xxx) += interrupt -extra-$(CONFIG_8xx) += test_burst timer -extra-$(CONFIG_MPC8260) += mem_to_mem_idma2intr extra-$(CONFIG_PPC) += sched # @@ -29,7 +26,6 @@ COBJS := $(ELF:=.o) LIB = $(obj)/libstubs.o LIBOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o -LIBOBJS-$(CONFIG_8xx) += test_burst_lib.o LIBOBJS-y += stubs.o .SECONDARY: $(call objectify,$(COBJS)) diff --git a/examples/standalone/interrupt.c b/examples/standalone/interrupt.c deleted file mode 100644 index 6e00860..0000000 --- a/examples/standalone/interrupt.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2006 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This is a very simple standalone application demonstrating - * catching IRQs on the MPC52xx architecture. - * - * The interrupt to be intercepted can be specified as an argument - * to the application. Specifying nothing will intercept IRQ1 on the - * MPC5200 platform. On the CR825 carrier board from MicroSys this - * maps to the ABORT switch :) - * - * Note that the specified vector is only a logical number specified - * by the respective header file. - */ - -#include -#include -#include - -#if defined(CONFIG_MPC5xxx) -#define DFL_IRQ MPC5XXX_IRQ1 -#else -#define DFL_IRQ 0 -#endif - -static void irq_handler (void *arg); - -int interrupt (int argc, char * const argv[]) -{ - int c, irq = -1; - - app_startup (argv); - - if (argc > 1) - irq = simple_strtoul (argv[1], NULL, 0); - if ((irq < 0) || (irq > NR_IRQS)) - irq = DFL_IRQ; - - printf ("Installing handler for irq vector %d and doing busy wait\n", - irq); - printf ("Press 'q' to quit\n"); - - /* Install interrupt handler */ - install_hdlr (irq, irq_handler, NULL); - while ((c = getc ()) != 'q') { - printf ("Ok, ok, I am still alive!\n"); - } - - free_hdlr (irq); - printf ("\nInterrupt handler has been uninstalled\n"); - - return (0); -} - -/* - * Handler for interrupt - */ -static void irq_handler (void *arg) -{ - /* just for demonstration */ - printf ("+"); -} diff --git a/examples/standalone/mem_to_mem_idma2intr.c b/examples/standalone/mem_to_mem_idma2intr.c deleted file mode 100644 index ce6e6c4..0000000 --- a/examples/standalone/mem_to_mem_idma2intr.c +++ /dev/null @@ -1,379 +0,0 @@ -/* The dpalloc function used and implemented in this file was derieved - * from PPCBoot/U-Boot file "arch/powerpc/cpu/mpc8260/commproc.c". - */ - -/* Author: Arun Dharankar - * This example is meant to only demonstrate how the IDMA could be used. - */ - -/* - * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ - - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define STANDALONE - -#ifndef STANDALONE /* Linked into/Part of PPCBoot */ -#include -#include -#else /* Standalone app of PPCBoot */ -#define WATCHDOG_RESET() { \ - *(ushort *)(CONFIG_SYS_IMMR + 0x1000E) = 0x556c; \ - *(ushort *)(CONFIG_SYS_IMMR + 0x1000E) = 0xaa39; \ - } -#endif /* STANDALONE */ - -static int debug = 1; - -#define DEBUG(fmt, args...) { \ - if(debug != 0) { \ - printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \ - printf(fmt, ##args); \ - } \ -} - -#define CPM_CR_IDMA1_SBLOCK (0x14) -#define CPM_CR_IDMA2_SBLOCK (0x15) -#define CPM_CR_IDMA3_SBLOCK (0x16) -#define CPM_CR_IDMA4_SBLOCK (0x17) -#define CPM_CR_IDMA1_PAGE (0x07) -#define CPM_CR_IDMA2_PAGE (0x08) -#define CPM_CR_IDMA3_PAGE (0x09) -#define CPM_CR_IDMA4_PAGE (0x0a) -#define PROFF_IDMA1_BASE ((uint)0x87fe) -#define PROFF_IDMA2_BASE ((uint)0x88fe) -#define PROFF_IDMA3_BASE ((uint)0x89fe) -#define PROFF_IDMA4_BASE ((uint)0x8afe) - -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_FLG ((ushort)0x0001) - -#define mk_cr_cmd(PG, SBC, MCN, OP) \ - ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) - - -#pragma pack(1) -typedef struct ibdbits { - unsigned b_valid:1; - unsigned b_resv1:1; - unsigned b_wrap:1; - unsigned b_interrupt:1; - unsigned b_last:1; - unsigned b_resv2:1; - unsigned b_cm:1; - unsigned b_resv3:2; - unsigned b_sdn:1; - unsigned b_ddn:1; - unsigned b_dgbl:1; - unsigned b_dbo:2; - unsigned b_resv4:1; - unsigned b_ddtb:1; - unsigned b_resv5:2; - unsigned b_sgbl:1; - unsigned b_sbo:2; - unsigned b_resv6:1; - unsigned b_sdtb:1; - unsigned b_resv7:9; -} ibdbits_t; - -#pragma pack(1) -typedef union ibdbitsu { - ibdbits_t b; - uint i; -} ibdbitsu_t; - -#pragma pack(1) -typedef struct idma_buf_desc { - ibdbitsu_t ibd_bits; /* Status and Control */ - uint ibd_datlen; /* Data length in buffer */ - uint ibd_sbuf; /* Source buffer addr in host mem */ - uint ibd_dbuf; /* Destination buffer addr in host mem */ -} ibd_t; - - -#pragma pack(1) -typedef struct dcmbits { - unsigned b_fb:1; - unsigned b_lp:1; - unsigned b_resv1:3; - unsigned b_tc2:1; - unsigned b_resv2:1; - unsigned b_wrap:3; - unsigned b_sinc:1; - unsigned b_dinc:1; - unsigned b_erm:1; - unsigned b_dt:1; - unsigned b_sd:2; -} dcmbits_t; - -#pragma pack(1) -typedef union dcmbitsu { - dcmbits_t b; - ushort i; -} dcmbitsu_t; - -#pragma pack(1) -typedef struct pram_idma { - ushort pi_ibase; - dcmbitsu_t pi_dcmbits; - ushort pi_ibdptr; - ushort pi_dprbuf; - ushort pi_bufinv; /* internal to CPM */ - ushort pi_ssmax; - ushort pi_dprinptr; /* internal to CPM */ - ushort pi_sts; - ushort pi_dproutptr; /* internal to CPM */ - ushort pi_seob; - ushort pi_deob; - ushort pi_dts; - ushort pi_retadd; - ushort pi_resv1; /* internal to CPM */ - uint pi_bdcnt; - uint pi_sptr; - uint pi_dptr; - uint pi_istate; -} pram_idma_t; - - -volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -volatile ibd_t *bdf; -volatile pram_idma_t *piptr; - -volatile int dmadone; -volatile int *dmadonep = &dmadone; -void dmadone_handler (void *); - -int idma_init (void); -void idma_start (int, int, int, uint, uint, int); -uint dpalloc (uint, uint); - - -uint dpinit_done = 0; - - -#ifdef STANDALONE -int ctrlc (void) -{ - if (tstc()) { - switch (getc ()) { - case 0x03: /* ^C - Control C */ - return 1; - default: - break; - } - } - return 0; -} -int memcmp(const void * cs,const void * ct,size_t count) -{ - const unsigned char *su1, *su2; - int res = 0; - for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) - if ((res = *su1 - *su2) != 0) - break; - return res; -} -#endif /* STANDALONE */ - -#ifdef STANDALONE -int mem_to_mem_idma2intr (int argc, char * const argv[]) -#else -int do_idma (bd_t * bd, int argc, char * const argv[]) -#endif /* STANDALONE */ -{ - int i; - - app_startup(argv); - dpinit_done = 0; - - idma_init (); - - DEBUG ("Installing dma handler\n"); - install_hdlr (7, dmadone_handler, (void *) bdf); - - memset ((void *) 0x100000, 'a', 512); - memset ((void *) 0x200000, 'b', 512); - - for (i = 0; i < 32; i++) { - printf ("Startin IDMA, iteration=%d\n", i); - idma_start (1, 1, 512, 0x100000, 0x200000, 3); - } - - DEBUG ("Uninstalling dma handler\n"); - free_hdlr (7); - - return 0; -} - -void -idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype) -{ - /* ttype is for M-M, M-P, P-M or P-P: not used for now */ - - piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */ - piptr->pi_dcmbits.b.b_resv1 = 0; - - if (sinc == 1) - piptr->pi_dcmbits.b.b_sinc = 1; - else - piptr->pi_dcmbits.b.b_sinc = 0; - - if (dinc == 1) - piptr->pi_dcmbits.b.b_dinc = 1; - else - piptr->pi_dcmbits.b.b_dinc = 0; - - piptr->pi_dcmbits.b.b_erm = 0; - piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */ - - bdf->ibd_sbuf = sbuf; - bdf->ibd_dbuf = dbuf; - bdf->ibd_bits.b.b_cm = 0; - bdf->ibd_bits.b.b_interrupt = 1; - bdf->ibd_bits.b.b_wrap = 1; - bdf->ibd_bits.b.b_last = 1; - bdf->ibd_bits.b.b_sdn = 0; - bdf->ibd_bits.b.b_ddn = 0; - bdf->ibd_bits.b.b_dgbl = 0; - bdf->ibd_bits.b.b_ddtb = 0; - bdf->ibd_bits.b.b_sgbl = 0; - bdf->ibd_bits.b.b_sdtb = 0; - bdf->ibd_bits.b.b_dbo = 1; - bdf->ibd_bits.b.b_sbo = 1; - bdf->ibd_bits.b.b_valid = 1; - bdf->ibd_datlen = 512; - - *dmadonep = 0; - - immap->im_sdma.sdma_idmr2 = (uchar) 0xf; - - immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE, - CPM_CR_IDMA2_SBLOCK, 0x0, - 0x9) | 0x00010000; - - while (*dmadonep != 1) { - if (ctrlc ()) { - DEBUG ("\nInterrupted waiting for DMA interrupt.\n"); - goto done; - } - printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n", - dmadone, bdf->ibd_bits.b.b_valid); - udelay (1000000); - } - printf ("DMA complete notification received!\n"); - - done: - DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n", - sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512)); - - return; -} - -#define MAX_INT_BUFSZ 64 -#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */ - -int idma_init (void) -{ - uint memaddr; - - immap->im_cpm.cp_rccr &= ~0x00F3FFFF; - immap->im_cpm.cp_rccr |= 0x00A00A00; - - memaddr = dpalloc (sizeof (pram_idma_t), 64); - - *(volatile u16 *)&immap->im_dprambase16 - [PROFF_IDMA2_BASE / sizeof(u16)] = memaddr; - piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr); - - piptr->pi_resv1 = 0; /* manual says: clear it */ - piptr->pi_dcmbits.b.b_fb = 0; - piptr->pi_dcmbits.b.b_lp = 1; - piptr->pi_dcmbits.b.b_erm = 0; - piptr->pi_dcmbits.b.b_dt = 0; - - memaddr = (uint) dpalloc (sizeof (ibd_t), 64); - piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr; - bdf = (volatile ibd_t *) ((uint) (immap) + memaddr); - bdf->ibd_bits.b.b_valid = 0; - - memaddr = (uint) dpalloc (64, 64); - piptr->pi_dprbuf = (volatile ushort) memaddr; - piptr->pi_dcmbits.b.b_wrap = 4; - piptr->pi_ssmax = 32; - - piptr->pi_sts = piptr->pi_ssmax; - piptr->pi_dts = piptr->pi_ssmax; - - return 1; -} - -void dmadone_handler (void *arg) -{ - immap->im_sdma.sdma_idmr2 = (uchar) 0x0; - - *dmadonep = 1; - - return; -} - - -static uint dpbase = 0; - -uint dpalloc (uint size, uint align) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - uint retloc; - uint align_mask, off; - uint savebase; - - /* Pointer to initial global data area */ - - if (dpinit_done == 0) { - dpbase = gd->arch.dp_alloc_base; - dpinit_done = 1; - } - - align_mask = align - 1; - savebase = dpbase; - - if ((off = (dpbase & align_mask)) != 0) - dpbase += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((dpbase + size) >= gd->arch.dp_alloc_top) { - dpbase = savebase; - printf ("dpalloc: ran out of dual port ram!"); - return 0; - } - - retloc = dpbase; - dpbase += size; - - memset ((void *) &immr->im_dprambase[retloc], 0, size); - - return (retloc); -} diff --git a/examples/standalone/test_burst.c b/examples/standalone/test_burst.c deleted file mode 100644 index f2fdbf1..0000000 --- a/examples/standalone/test_burst.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * The test exercises SDRAM accesses in burst mode - */ - -#include -#include - -#include -#include -#include - -#include -#include - -#include "test_burst.h" - -/* 8 MB test region of physical RAM */ -#define TEST_PADDR 0x00800000 -/* The uncached virtual region */ -#define TEST_VADDR_NC 0x00800000 -/* The cached virtual region */ -#define TEST_VADDR_C 0x01000000 -/* When an error is detected, the address where the error has been found, - and also the current and the expected data will be written to - the following flash address -*/ -#define TEST_FLASH_ADDR 0x40100000 - -static void test_prepare (void); -static int test_burst_start (unsigned long size, unsigned long pattern); -static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached); -static int test_mmu_is_on(void); -static void test_desc(unsigned long size); -static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern); -static void signal_init(void); -static void signal_start(void); -static void signal_error(void); -static void test_usage(void); - -static unsigned long test_pattern [] = { - 0x00000000, - 0xffffffff, - 0x55555555, - 0xaaaaaaaa, -}; - - -int test_burst (int argc, char * const argv[]) -{ - unsigned long size = CACHE_LINE_SIZE; - unsigned int pass = 0; - int res = 0; - int i, j; - - if (argc == 3) { - char * d; - for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) { - size *= 10; - size += *d - '0'; - } - if (size == 0 || *d) { - test_usage(); - return 1; - } - for (d = argv[2]; *d >= '0' && *d <= '9'; d++) { - pass *= 10; - pass += *d - '0'; - } - if (*d) { - test_usage(); - return 1; - } - } else if (argc > 3) { - test_usage(); - return 1; - } - - size += (CACHE_LINE_SIZE - 1); - size &= ~(CACHE_LINE_SIZE - 1); - - if (!test_mmu_is_on()) { - test_prepare(); - } - - test_desc(size); - - for (j = 0; !pass || j < pass; j++) { - for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); - i++) { - res = test_burst_start(size, test_pattern[i]); - if (res != 0) { - goto Done; - } - } - - printf ("Iteration #%d passed\n", j + 1); - - if (tstc() && 0x03 == getc()) - break; - } -Done: - return res; -} - -static void test_prepare (void) -{ - printf ("\n"); - - caches_init(); - disable_interrupts(); - mmu_init(); - - printf ("Interrupts are disabled\n"); - printf ("I-Cache is ON\n"); - printf ("D-Cache is ON\n"); - printf ("MMU is ON\n"); - - printf ("\n"); - - test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0); - test_map_8M (TEST_PADDR, TEST_VADDR_C, 1); - - test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0); - - /* Configure GPIO ports */ - signal_init(); -} - -static int test_burst_start (unsigned long size, unsigned long pattern) -{ - volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C; - volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC; - int i, n; - int res = 1; - - printf ("Test pattern %08lx ...", pattern); - - n = size / 4; - - for (i = 0; i < n; i ++) { - vaddr_c [i] = pattern; - } - signal_start(); - flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1); - - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_nc [i]; - if (tmp != pattern) { - test_error("2a", vaddr_nc + i, tmp, pattern); - goto Done; - } - } - - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_c [i]; - if (tmp != pattern) { - test_error("2b", vaddr_c + i, tmp, pattern); - goto Done; - } - } - - for (i = 0; i < n; i ++) { - vaddr_nc [i] = pattern; - } - - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_nc [i]; - if (tmp != pattern) { - test_error("3a", vaddr_nc + i, tmp, pattern); - goto Done; - } - } - - signal_start(); - for (i = 0; i < n; i ++) { - register unsigned long tmp = vaddr_c [i]; - if (tmp != pattern) { - test_error("3b", vaddr_c + i, tmp, pattern); - goto Done; - } - } - - res = 0; -Done: - printf(" %s\n", res == 0 ? "OK" : ""); - - return res; -} - -static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached) -{ - mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID); - mtspr (MD_TWC, MI_PS8MEG | MI_SVALID); - mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2)); - mtspr (MD_AP, MI_Kp); -} - -static int test_mmu_is_on(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - - return msr & MSR_DR; -} - -static void test_desc(unsigned long size) -{ - printf( - "The following tests will be conducted:\n" - "1) Map %ld-byte region of physical RAM at 0x%08x\n" - " into two virtual regions:\n" - " one cached at 0x%08x and\n" - " the the other uncached at 0x%08x.\n", - size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C); - - puts( - "2) Fill the cached region with a pattern, and flush the cache\n" - "2a) Check the uncached region to match the pattern\n" - "2b) Check the cached region to match the pattern\n" - "3) Fill the uncached region with a pattern\n" - "3a) Check the cached region to match the pattern\n" - "3b) Check the uncached region to match the pattern\n" - "2b) Change the patterns and go to step 2\n" - "\n" - ); -} - -static void test_error( - char * step, volatile void * addr, unsigned long val, unsigned long pattern) -{ - volatile unsigned long * p = (void *)TEST_FLASH_ADDR; - - signal_error(); - - p[0] = (unsigned long)addr; - p[1] = val; - p[2] = pattern; - - printf ("\nError at step %s, addr %08lx: read %08lx, pattern %08lx", - step, (unsigned long)addr, val, pattern); -} - -static void signal_init(void) -{ -#if defined(GPIO1_INIT) - GPIO1_INIT; -#endif -#if defined(GPIO2_INIT) - GPIO2_INIT; -#endif -} - -static void signal_start(void) -{ -#if defined(GPIO1_INIT) - if (GPIO1_DAT & GPIO1_BIT) { - GPIO1_DAT &= ~GPIO1_BIT; - } else { - GPIO1_DAT |= GPIO1_BIT; - } -#endif -} - -static void signal_error(void) -{ -#if defined(GPIO2_INIT) - if (GPIO2_DAT & GPIO2_BIT) { - GPIO2_DAT &= ~GPIO2_BIT; - } else { - GPIO2_DAT |= GPIO2_BIT; - } -#endif -} - -static void test_usage(void) -{ - printf("Usage: go 0x40004 [size] [count]\n"); -} diff --git a/examples/standalone/test_burst.h b/examples/standalone/test_burst.h deleted file mode 100644 index 87f5927..0000000 --- a/examples/standalone/test_burst.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEST_BURST_H -#define _TEST_BURST_H - -/* Cache line size */ -#define CACHE_LINE_SIZE 16 -/* Binary logarithm of the cache line size */ -#define LG_CACHE_LINE_SIZE 4 - -#ifndef __ASSEMBLY__ -extern void mmu_init(void); -extern void caches_init(void); -extern void flush_dcache_range(unsigned long start, unsigned long stop); -#endif - -#endif /* _TEST_BURST_H */ diff --git a/examples/standalone/test_burst_lib.S b/examples/standalone/test_burst_lib.S deleted file mode 100644 index fd3256e..0000000 --- a/examples/standalone/test_burst_lib.S +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include -#include -#include -#include -#include "test_burst.h" - - .text -/* - * void mmu_init(void); - * - * This function turns the MMU on - * - * Three 8 MByte regions are mapped 1:1, uncached - * - SDRAM lower 8 MByte - * - SDRAM higher 8 MByte - * - IMMR - */ - .global mmu_init -mmu_init: - tlbia /* Invalidate all TLB entries */ - li r8, 0 - mtspr MI_CTR, r8 /* Set instruction control to zero */ - lis r8, MD_RESETVAL@h - mtspr MD_CTR, r8 /* Set data TLB control */ - - /* Now map the lower 8 Meg into the TLBs. For this quick hack, - * we can load the instruction and data TLB registers with the - * same values. - */ - li r8, MI_EVALID /* Create EPN for address 0 */ - mtspr MI_EPN, r8 - mtspr MD_EPN, r8 - li r8, MI_PS8MEG /* Set 8M byte page */ - ori r8, r8, MI_SVALID /* Make it valid */ - mtspr MI_TWC, r8 - mtspr MD_TWC, r8 - li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */ - mtspr MI_RPN, r8 /* Store TLB entry */ - mtspr MD_RPN, r8 - lis r8, MI_Kp@h /* Set the protection mode */ - mtspr MI_AP, r8 - mtspr MD_AP, r8 - - /* Now map the higher 8 Meg into the TLBs. For this quick hack, - * we can load the instruction and data TLB registers with the - * same values. - */ - lwz r9,20(r2) /* gd->ram_size */ - addis r9,r9,-0x80 - - mr r8, r9 /* Higher 8 Meg in SDRAM */ - ori r8, r8, MI_EVALID /* Mark page valid */ - mtspr MI_EPN, r8 - mtspr MD_EPN, r8 - li r8, MI_PS8MEG /* Set 8M byte page */ - ori r8, r8, MI_SVALID /* Make it valid */ - mtspr MI_TWC, r8 - mtspr MD_TWC, r8 - mr r8, r9 - ori r8, r8, MI_BOOTINIT|0x2 - mtspr MI_RPN, r8 /* Store TLB entry */ - mtspr MD_RPN, r8 - lis r8, MI_Kp@h /* Set the protection mode */ - mtspr MI_AP, r8 - mtspr MD_AP, r8 - - /* Map another 8 MByte at the IMMR to get the processor - * internal registers (among other things). - */ - mfspr r9, 638 /* Get current IMMR */ - andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ - - mr r8, r9 /* Create vaddr for TLB */ - ori r8, r8, MD_EVALID /* Mark it valid */ - mtspr MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ - ori r8, r8, MD_SVALID /* Make it valid */ - mtspr MD_TWC, r8 - mr r8, r9 /* Create paddr for TLB */ - ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ - mtspr MD_RPN, r8 - - /* We now have the lower and higher 8 Meg mapped into TLB entries, - * and the caches ready to work. - */ - mfmsr r0 - ori r0,r0,MSR_DR|MSR_IR - mtspr SRR1,r0 - mflr r0 - mtspr SRR0,r0 - SYNC - rfi /* enables MMU */ - -/* - * void caches_init(void); - */ - .globl caches_init -caches_init: - sync - - mfspr r3, IC_CST /* Clear error bits */ - mfspr r3, DC_CST - - lis r3, IDC_UNALL@h /* Unlock all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_INVALL@h /* Invalidate all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_ENABLE@h /* Enable all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - blr - -/* - * void flush_dcache_range(unsigned long start, unsigned long stop); - */ - .global flush_dcache_range -flush_dcache_range: - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - -1: dcbf 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbf's to get to ram */ - blr - -/* - * void disable_interrupts(void); - */ - .global disable_interrupts -disable_interrupts: - mfmsr r0 - rlwinm r0,r0,0,17,15 - mtmsr r0 - blr diff --git a/examples/standalone/timer.c b/examples/standalone/timer.c deleted file mode 100644 index dbd5c16..0000000 --- a/examples/standalone/timer.c +++ /dev/null @@ -1,333 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG - -#define TIMER_PERIOD 1000000 /* 1 second clock */ - -static void timer_handler (void *arg); - - -/* Access functions for the Machine State Register */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -/* - * Definitions to access the CPM Timer registers - * See 8xx_immap.h for Internal Memory Map layout, - * and commproc.h for CPM Interrupt vectors (aka "IRQ"s) - */ - -typedef struct tid_8xx_cpmtimer_s { - int cpm_vec; /* CPM Interrupt Vector for this timer */ - ushort *tgcrp; /* Pointer to Timer Global Config Reg. */ - ushort *tmrp; /* Pointer to Timer Mode Register */ - ushort *trrp; /* Pointer to Timer Reference Register */ - ushort *tcrp; /* Pointer to Timer Capture Register */ - ushort *tcnp; /* Pointer to Timer Counter Register */ - ushort *terp; /* Pointer to Timer Event Register */ -} tid_8xx_cpmtimer_t; - -#ifndef CLOCKRATE -# define CLOCKRATE 64 -#endif - -#define CPMT_CLOCK_DIV 16 -#define CPMT_MAX_PRESCALER 256 -#define CPMT_MAX_REFERENCE 65535 /* max. unsigned short */ - -#define CPMT_MAX_TICKS (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER) -#define CPMT_MAX_TICKS_WITH_DIV (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV) -#define CPMT_MAX_INTERVAL (CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE) - -/* For now: always use max. prescaler value */ -#define CPMT_PRESCALER (CPMT_MAX_PRESCALER) - -/* CPM Timer Event Register Bits */ -#define CPMT_EVENT_CAP 0x0001 /* Capture Event */ -#define CPMT_EVENT_REF 0x0002 /* Reference Counter Event */ - -/* CPM Timer Global Config Register */ -#define CPMT_GCR_RST 0x0001 /* Reset Timer */ -#define CPMT_GCR_STP 0x0002 /* Stop Timer */ -#define CPMT_GCR_FRZ 0x0004 /* Freeze Timer */ -#define CPMT_GCR_GM_CAS 0x0008 /* Gate Mode / Cascade Timers */ -#define CPMT_GCR_MASK (CPMT_GCR_RST|CPMT_GCR_STP|CPMT_GCR_FRZ|CPMT_GCR_GM_CAS) - -/* CPM Timer Mode register */ -#define CPMT_MR_GE 0x0001 /* Gate Enable */ -#define CPMT_MR_ICLK_CASC 0x0000 /* Clock internally cascaded */ -#define CPMT_MR_ICLK_CLK 0x0002 /* Clock = system clock */ -#define CPMT_MR_ICLK_CLKDIV 0x0004 /* Clock = system clock / 16 */ -#define CPMT_MR_ICLK_TIN 0x0006 /* Clock = TINx signal */ -#define CPMT_MR_FRR 0x0008 /* Free Run / Restart */ -#define CPMT_MR_ORI 0x0010 /* Out. Reference Interrupt En. */ -#define CPMT_MR_OM 0x0020 /* Output Mode */ -#define CPMT_MR_CE_DIS 0x0000 /* Capture/Interrupt disabled */ -#define CPMT_MR_CE_RISE 0x0040 /* Capt./Interr. on rising TIN */ -#define CPMT_MR_CE_FALL 0x0080 /* Capt./Interr. on falling TIN */ -#define CPMT_MR_CE_ANY 0x00C0 /* Capt./Interr. on any TIN edge*/ - - -/* - * which CPM timer to use - index starts at 0 (= timer 1) - */ -#define TID_TIMER_ID 0 /* use CPM timer 1 */ - -void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval); - -static const char usage[] = "\n[q, b, e, ?] "; - -int timer (int argc, char * const argv[]) -{ - cpmtimer8xx_t *cpmtimerp; /* Pointer to the CPM Timer structure */ - tid_8xx_cpmtimer_t hw; - tid_8xx_cpmtimer_t *hwp = &hw; - int c; - int running; - - app_startup(argv); - - /* Pointer to CPM Timer structure */ - cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer; - - printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp); - - /* Initialize pointers depending on which timer we use */ - switch (TID_TIMER_ID) { - case 0: - hwp->tmrp = &(cpmtimerp->cpmt_tmr1); - hwp->trrp = &(cpmtimerp->cpmt_trr1); - hwp->tcrp = &(cpmtimerp->cpmt_tcr1); - hwp->tcnp = &(cpmtimerp->cpmt_tcn1); - hwp->terp = &(cpmtimerp->cpmt_ter1); - hwp->cpm_vec = CPMVEC_TIMER1; - break; - case 1: - hwp->tmrp = &(cpmtimerp->cpmt_tmr2); - hwp->trrp = &(cpmtimerp->cpmt_trr2); - hwp->tcrp = &(cpmtimerp->cpmt_tcr2); - hwp->tcnp = &(cpmtimerp->cpmt_tcn2); - hwp->terp = &(cpmtimerp->cpmt_ter2); - hwp->cpm_vec = CPMVEC_TIMER2; - break; - case 2: - hwp->tmrp = &(cpmtimerp->cpmt_tmr3); - hwp->trrp = &(cpmtimerp->cpmt_trr3); - hwp->tcrp = &(cpmtimerp->cpmt_tcr3); - hwp->tcnp = &(cpmtimerp->cpmt_tcn3); - hwp->terp = &(cpmtimerp->cpmt_ter3); - hwp->cpm_vec = CPMVEC_TIMER3; - break; - case 3: - hwp->tmrp = &(cpmtimerp->cpmt_tmr4); - hwp->trrp = &(cpmtimerp->cpmt_trr4); - hwp->tcrp = &(cpmtimerp->cpmt_tcr4); - hwp->tcnp = &(cpmtimerp->cpmt_tcn4); - hwp->terp = &(cpmtimerp->cpmt_ter4); - hwp->cpm_vec = CPMVEC_TIMER4; - break; - } - - hwp->tgcrp = &cpmtimerp->cpmt_tgcr; - - printf ("Using timer %d\n" - "tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x," - " tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n", - TID_TIMER_ID + 1, - (unsigned) hwp->tgcrp, - (unsigned) hwp->tmrp, - (unsigned) hwp->trrp, - (unsigned) hwp->tcrp, - (unsigned) hwp->tcnp, - (unsigned) hwp->terp - ); - - /* reset timer */ - *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); - - /* clear all events */ - *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF); - - puts(usage); - running = 0; - while ((c = getc()) != 'q') { - if (c == 'b') { - - setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */ - - /* Install interrupt handler (enable timer in CIMR) */ - install_hdlr (hwp->cpm_vec, timer_handler, hwp); - - printf ("Enabling timer\n"); - - /* enable timer */ - *hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID); - running = 1; - -#ifdef DEBUG - printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#endif - } else if (c == 'e') { - - printf ("Stopping timer\n"); - - *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); - running = 0; - -#ifdef DEBUG - printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#endif - /* Uninstall interrupt handler */ - free_hdlr (hwp->cpm_vec); - - } else if (c == '?') { -#ifdef DEBUG - cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic; - sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf; -#endif - - printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#ifdef DEBUG - printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx," - " SIMASK=0x%08lx, SIPEND=0x%08lx\n", - siup->sc_siumcr, - siup->sc_sypcr, - siup->sc_simask, - siup->sc_sipend - ); - - printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n", - cpm_icp->cpic_cimr, - cpm_icp->cpic_cicr, - cpm_icp->cpic_cipr - ); -#endif - } else { - printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n"); - } - puts(usage); - } - if (running) { - printf ("Stopping timer\n"); - *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); - free_hdlr (hwp->cpm_vec); - } - - return (0); -} - - -/* Set period in microseconds and start. - * Truncate to maximum period if more than this is requested - but warn about it. - */ - -void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval) -{ - unsigned short prescaler; - unsigned long ticks; - - printf ("Set interval %ld us\n", interval); - - /* Warn if requesting longer period than possible */ - if (interval > CPMT_MAX_INTERVAL) { - printf ("Truncate interval %ld to maximum (%d)\n", - interval, CPMT_MAX_INTERVAL); - interval = CPMT_MAX_INTERVAL; - } - /* - * Check if we want to use clock divider: - * Since the reference counter can be incremented only in integer steps, - * we try to keep it as big as possible to allow the resulting period to be - * as precise as possible. - */ - /* prescaler, enable interrupt, restart after ref count is reached */ - prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) | - CPMT_MR_ORI | - CPMT_MR_FRR; - - ticks = ((ulong) CLOCKRATE * interval); - - if (ticks > CPMT_MAX_TICKS) { - ticks /= CPMT_CLOCK_DIV; - prescaler |= CPMT_MR_ICLK_CLKDIV; /* use system clock divided by 16 */ - } else { - prescaler |= CPMT_MR_ICLK_CLK; /* use system clock without divider */ - } - -#ifdef DEBUG - printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n", - (ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1, - CPMT_PRESCALER, - (ticks / CPMT_PRESCALER), - ticks - ); -#endif - - /* set prescaler register */ - *hwp->tmrp = prescaler; - - /* clear timer counter */ - *hwp->tcnp = 0; - - /* set reference register */ - *hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER); - -#ifdef DEBUG - printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," - " tcr=0x%x, tcn=0x%x, ter=0x%x\n", - *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, - *hwp->tcrp, *hwp->tcnp, *hwp->terp - ); -#endif -} - -/* - * Handler for CPMVEC_TIMER1 interrupt - */ -static -void timer_handler (void *arg) -{ - tid_8xx_cpmtimer_t *hwp = (tid_8xx_cpmtimer_t *)arg; - - /* printf ("** TER1=%04x ** ", *hwp->terp); */ - - /* just for demonstration */ - printf ("."); - - /* clear all possible events: Ref. and Cap. */ - *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF); -} diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index cc397d6..db29489 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -939,7 +939,7 @@ int ubifs_load(char *filename, u32 addr, u32 size) printf("Loading file '%s' to addr 0x%08x...\n", filename, addr); - err = ubifs_read(filename, (void *)addr, 0, size, &actread); + err = ubifs_read(filename, (void *)(uintptr_t)addr, 0, size, &actread); if (err == 0) { setenv_hex("filesize", actread); printf("Done\n"); diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index 25aa6d1..f663081 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -320,7 +320,7 @@ void read_a_file(char *fn) i++; if (i > 32) { printf("\n"); - i = 0;; + i = 0; } } printf("\n"); diff --git a/include/api.h b/include/api.h new file mode 100644 index 0000000..85817f3 --- /dev/null +++ b/include/api.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __API_H +#define __API_H + +void api_init(void); + +#endif diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e6f9051..fb90be9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -110,6 +110,10 @@ typedef struct global_data { ulong video_top; /* Top of video frame buffer area */ ulong video_bottom; /* Bottom of video frame buffer area */ #endif +#ifdef CONFIG_BOOTSTAGE + struct bootstage_data *bootstage; /* Bootstage information */ + struct bootstage_data *new_bootstage; /* Relocated bootstage info */ +#endif } gd_t; #endif diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 9f3351d..95930ad 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -41,11 +41,10 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) +#if defined(CONFIG_M68K) unsigned long bi_mbar_base; /* base of internal registers */ #endif #if defined(CONFIG_MPC83xx) @@ -63,10 +62,7 @@ typedef struct bd_info { unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ unsigned long bi_vco; /* VCO Out from PLL, in MHz */ #endif -#if defined(CONFIG_MPC512X) - unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) +#if defined(CONFIG_M68K) unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif diff --git a/include/blk.h b/include/blk.h index a128ee4..ef29a07 100644 --- a/include/blk.h +++ b/include/blk.h @@ -377,6 +377,13 @@ int blk_find_max_devnum(enum if_type if_type); */ int blk_select_hwpart(struct udevice *dev, int hwpart); +/** + * blk_get_from_parent() - obtain a block device by looking up its parent + * + * All devices with + */ +int blk_get_from_parent(struct udevice *parent, struct udevice **devp); + #else #include /* diff --git a/include/bootstage.h b/include/bootstage.h index a589be6..c5d93f5 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -2,6 +2,7 @@ * This file implements recording of each stage of the boot process. It is * intended to implement timing of each stage, reporting this information * to the user and passing it to the OS for logging / further analysis. + * Note that it requires timer_get_boot_us() to be defined by the board * * Copyright (c) 2011 The Chromium OS Authors. * @@ -176,6 +177,7 @@ enum bootstage_id { */ BOOTSTAGE_ID_AWAKE, BOOTSTAGE_ID_START_SPL, + BOOTSTAGE_ID_END_SPL, BOOTSTAGE_ID_START_UBOOT_F, BOOTSTAGE_ID_START_UBOOT_R, BOOTSTAGE_ID_USB_START, @@ -198,7 +200,11 @@ enum bootstage_id { BOOTSTAGE_ID_ACCUM_SCSI, BOOTSTAGE_ID_ACCUM_SPI, BOOTSTAGE_ID_ACCUM_DECOMP, + BOOTSTAGE_ID_ACCUM_OF_LIVE, BOOTSTAGE_ID_FPGA_INIT, + BOOTSTATE_ID_ACCUM_DM_SPL, + BOOTSTATE_ID_ACCUM_DM_F, + BOOTSTATE_ID_ACCUM_DM_R, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, @@ -209,14 +215,14 @@ enum bootstage_id { /* * Return the time since boot in microseconds, This is needed for bootstage * and should be defined in CPU- or board-specific code. If undefined then - * millisecond resolution will be used (the standard get_timer()). + * you will get a link error. */ ulong timer_get_boot_us(void); #if defined(USE_HOSTCC) #define show_boot_progress(val) do {} while (0) #else -/* +/** * Board code can implement show_boot_progress() if needed. * * @param val Progress state (enum bootstage_id), or -id if an error @@ -225,8 +231,14 @@ ulong timer_get_boot_us(void); void show_boot_progress(int val); #endif -#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \ - !defined(USE_HOSTCC) +#if !defined(USE_HOSTCC) +#if CONFIG_IS_ENABLED(BOOTSTAGE) +#define ENABLE_BOOTSTAGE +#endif +#endif + +#ifdef ENABLE_BOOTSTAGE + /* This is the full bootstage implementation */ /** @@ -234,7 +246,7 @@ void show_boot_progress(int val); * * Call this after relocation has happened and after malloc has been initted. * We need to copy any pointers in bootstage records that were added pre- - * relocation, since memory can be overritten later. + * relocation, since memory can be overwritten later. * @return Always returns 0, to indicate success */ int bootstage_relocate(void); @@ -250,7 +262,7 @@ int bootstage_relocate(void); ulong bootstage_add_record(enum bootstage_id id, const char *name, int flags, ulong mark); -/* +/** * Mark a time stamp for the current boot stage. */ ulong bootstage_mark(enum bootstage_id id); @@ -309,7 +321,7 @@ void bootstage_report(void); */ int bootstage_fdt_add_report(void); -/* +/** * Stash bootstage data into memory * * @param base Base address of memory buffer @@ -326,9 +338,26 @@ int bootstage_stash(void *base, int size); * * @param base Base address of memory buffer * @param size Size of memory buffer (-1 if unknown) - * @return 0 if unstashed ok, -1 if bootstage info not found, or out of space + * @return 0 if unstashed ok, -ENOENT if bootstage info not found, -ENOSPC if + * there is not space for read the stacked data, or other error if + * something else went wrong + */ +int bootstage_unstash(const void *base, int size); + +/** + * bootstage_get_size() - Get the size of the bootstage data + * + * @return size of boostage data in bytes */ -int bootstage_unstash(void *base, int size); +int bootstage_get_size(void); + +/** + * bootstage_init() - Prepare bootstage for use + * + * @first: true if this is the first time bootstage is set up. This causes it + * to add a 'reset' record with a time of 0. + */ +int bootstage_init(bool first); #else static inline ulong bootstage_add_record(enum bootstage_id id, @@ -386,11 +415,22 @@ static inline int bootstage_stash(void *base, int size) return 0; /* Pretend to succeed */ } -static inline int bootstage_unstash(void *base, int size) +static inline int bootstage_unstash(const void *base, int size) { return 0; /* Pretend to succeed */ } -#endif /* CONFIG_BOOTSTAGE */ + +static inline int bootstage_get_size(void) +{ + return 0; +} + +static inline int bootstage_init(bool first) +{ + return 0; +} + +#endif /* ENABLE_BOOTSTAGE */ /* Helper macro for adding a bootstage to a line of code */ #define BOOTSTAGE_MARKER() \ diff --git a/include/common.h b/include/common.h index 45f190a..638c45b 100644 --- a/include/common.h +++ b/include/common.h @@ -30,61 +30,6 @@ typedef volatile unsigned char vu_char; #include #include #include -#if defined(CONFIG_PCI) && defined(CONFIG_4xx) -#include -#endif -#if defined(CONFIG_8xx) -#include -#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ - defined(CONFIG_MPC866) || \ - defined(CONFIG_MPC866P) -# define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC885) -# define CONFIG_MPC885_FAMILY 1 -#endif -#if defined(CONFIG_MPC860) \ - || defined(CONFIG_MPC860T) \ - || defined(CONFIG_MPC866_FAMILY) \ - || defined(CONFIG_MPC885_FAMILY) -# define CONFIG_MPC86x 1 -#endif -#elif defined(CONFIG_5xx) -#include -#elif defined(CONFIG_MPC5xxx) -#include -#elif defined(CONFIG_MPC512X) -#include -#elif defined(CONFIG_MPC8260) -#if defined(CONFIG_MPC8247) \ - || defined(CONFIG_MPC8272) -#define CONFIG_MPC8272_FAMILY 1 -#endif -#include -#endif -#ifdef CONFIG_MPC86xx -#include -#include -#endif -#ifdef CONFIG_MPC85xx -#include -#include -#endif -#ifdef CONFIG_MPC83xx -#include -#include -#endif -#ifdef CONFIG_4xx -#include -#endif -#ifdef CONFIG_SOC_DA8XX -#include -#endif -#ifdef CONFIG_FSL_LSCH3 -#include -#endif -#ifdef CONFIG_FSL_LSCH2 -#include -#endif #include #include @@ -166,28 +111,6 @@ typedef void (interrupt_handler_t)(void *); #include /* boot information for Linux kernel */ #include /* global data used for startup functions */ -/* - * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards - * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards - * and for the TQM885D board - */ -#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) -# ifndef CONFIG_TQM8xxM -# define CONFIG_TQM8xxM -# endif -#endif -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ - defined(CONFIG_TQM885D) -# ifndef CONFIG_TQM8xxL -# define CONFIG_TQM8xxL -# endif -#endif - #if defined(CONFIG_ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ @@ -428,29 +351,6 @@ static inline int setenv_addr(const char *varname, const void *addr) return setenv_hex(varname, (ulong)addr); } -#ifdef CONFIG_ARM -# include -# include -# include /* ARM version to be fixed! */ -#endif /* CONFIG_ARM */ -#ifdef CONFIG_X86 /* x86 version to be fixed! */ -# include -#endif /* CONFIG_X86 */ -#ifdef CONFIG_SANDBOX -# include /* TODO(sjg) what needs to be fixed? */ -#endif -#ifdef CONFIG_NDS32 -# include -# include -# include -#endif /* CONFIG_NDS32 */ -#ifdef CONFIG_MIPS -# include -#endif /* CONFIG_MIPS */ -#ifdef CONFIG_ARC -# include -#endif /* CONFIG_ARC */ - #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); #endif @@ -459,25 +359,6 @@ int get_env_id (void); void pci_init (void); void pci_init_board(void); -#if defined(CONFIG_PCI) && defined(CONFIG_4xx) - int pci_pre_init (struct pci_controller *); - int is_pci_host (struct pci_controller *); -#endif - -#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) -# if defined(CONFIG_SYS_PCI_TARGET_INIT) - void pci_target_init (struct pci_controller *); -# endif -# if defined(CONFIG_SYS_PCI_MASTER_INIT) - void pci_master_init (struct pci_controller *); -# endif -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - void pcie_setup_hoses(int busno); -#endif -#endif - int misc_init_f (void); int misc_init_r (void); @@ -487,9 +368,6 @@ void jumptable_init(void); /* common/kallsysm.c */ const char *symbol_lookup(unsigned long addr, unsigned long *caddr); -/* api/api.c */ -void api_init (void); - /* common/memsize.c */ long get_ram_size (long *, long); phys_size_t get_effective_memsize(void); @@ -545,21 +423,6 @@ int testdram(void); #endif /* CONFIG_SYS_DRAM_TEST */ /* $(CPU)/start.S */ -#if defined(CONFIG_5xx) || \ - defined(CONFIG_8xx) -uint get_immr (uint); -#endif -#if defined(CONFIG_MPC5xxx) -uint get_svr (void); -#endif -uint get_pvr (void); -uint get_svr (void); -uint rd_ic_cst (void); -void wr_ic_cst (uint); -void wr_ic_adr (uint); -uint rd_dc_cst (void); -void wr_dc_cst (uint); -void wr_dc_adr (uint); int icache_status (void); void icache_enable (void); void icache_disable(void); @@ -574,40 +437,6 @@ void relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn)); #endif ulong get_endaddr (void); void trap_init (ulong); -#if defined (CONFIG_4xx) || \ - defined (CONFIG_MPC5xxx) || \ - defined (CONFIG_MPC85xx) || \ - defined (CONFIG_MPC86xx) || \ - defined (CONFIG_MPC83xx) -unsigned char in8(unsigned int); -void out8(unsigned int, unsigned char); -unsigned short in16(unsigned int); -unsigned short in16r(unsigned int); -void out16(unsigned int, unsigned short value); -void out16r(unsigned int, unsigned short value); -unsigned long in32(unsigned int); -unsigned long in32r(unsigned int); -void out32(unsigned int, unsigned long value); -void out32r(unsigned int, unsigned long value); -void ppcDcbf(unsigned long value); -void ppcDcbi(unsigned long value); -void ppcSync(void); -void ppcDcbz(unsigned long value); -#endif -#if defined (CONFIG_MICROBLAZE) -unsigned short in16(unsigned int); -void out16(unsigned int, unsigned short value); -#endif - -#if defined (CONFIG_MPC83xx) -void ppcDWload(unsigned int *addr, unsigned int *ret); -void ppcDWstore(unsigned int *addr, unsigned int *value); -void disable_addr_trans(void); -void enable_addr_trans(void); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -void ddr_enable_ecc(unsigned int dram_size); -#endif -#endif /* $(CPU)/cpu.c */ static inline int cpumask_next(int cpu, unsigned int mask) @@ -668,76 +497,9 @@ int serial_stub_tstc(struct stdio_dev *sdev); /* $(CPU)/speed.c */ int get_clocks (void); -#if defined(CONFIG_MPC5xxx) -int prt_mpc5xxx_clks (void); -#endif -#ifdef CONFIG_4xx -ulong get_OPB_freq (void); -ulong get_PCI_freq (void); -#endif -#if defined(CONFIG_S3C24X0) || \ - defined(CONFIG_LH7A40X) || \ - defined(CONFIG_EP93XX) -ulong get_FCLK (void); -ulong get_HCLK (void); -ulong get_PCLK (void); -ulong get_UCLK (void); -#endif -#if defined(CONFIG_LH7A40X) -ulong get_PLLCLK (void); -#endif -#if defined(CONFIG_IMX) -ulong get_systemPLLCLK(void); -ulong get_FCLK(void); -ulong get_HCLK(void); -ulong get_BCLK(void); -ulong get_PERCLK1(void); -ulong get_PERCLK2(void); -ulong get_PERCLK3(void); -#endif ulong get_bus_freq (ulong); int get_serial_clock(void); -#if defined(CONFIG_MPC85xx) -typedef MPC85xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); -void ft_fixup_cpu(void *, u64); -void ft_fixup_num_cores(void *); -#endif -#if defined(CONFIG_MPC86xx) -typedef MPC86xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); -static inline ulong get_ddr_freq(ulong dummy) -{ - return get_bus_freq(dummy); -} -#else -ulong get_ddr_freq(ulong); -#endif - -#if defined(CONFIG_4xx) -# if defined(CONFIG_440) -# if defined(CONFIG_440SPE) - unsigned long determine_sysper(void); - unsigned long determine_pci_clock_per(void); -# endif -# endif -typedef PPC4xx_SYS_INFO sys_info_t; -int ppc440spe_revB(void); -void get_sys_info ( sys_info_t * ); -#endif - -/* $(CPU)/cpu_init.c */ -#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) -void cpu_init_f (volatile immap_t *immr); -#endif -#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx) -void cpu_init_f (void); -#endif -#ifdef CONFIG_MPC85xx -ulong cpu_init_f(void); -#endif - int cpu_init_r (void); /* $(CPU)/interrupts.c */ @@ -963,14 +725,6 @@ int cpu_release(int nr, int argc, char * const argv[]); #endif /* __ASSEMBLY__ */ -#ifdef CONFIG_PPC -/* - * Has to be included outside of the #ifndef __ASSEMBLY__ section. - * Otherwise might lead to compilation errors in assembler files. - */ -#include -#endif - /* Put only stuff here that the assembler can digest */ /* Declare an unsigned long constant digestable both by C and an assembler. */ diff --git a/include/commproc.h b/include/commproc.h deleted file mode 100644 index 9d4cb10..0000000 --- a/include/commproc.h +++ /dev/null @@ -1,849 +0,0 @@ -/* - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. - * This file only contains what I need for the moment, not the total - * CPM capabilities. I (or someone else) will add definitions as they - * are needed. -- Dan - * - */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((ushort)0x8000) -#define CPM_CR_OPCODE ((ushort)0x0f00) -#define CPM_CR_CHAN ((ushort)0x00f0) -#define CPM_CR_FLG ((ushort)0x0001) - -/* Some commands (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -/* Channel numbers. -*/ -#define CPM_CR_CH_SCC1 ((ushort)0x0000) -#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ -#define CPM_CR_CH_SCC2 ((ushort)0x0004) -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ -#define CPM_CR_CH_SCC3 ((ushort)0x0008) -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ -#define CPM_CR_CH_SCC4 ((ushort)0x000c) -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -/* - * DPRAM defines and allocation functions - */ -#define CPM_SERIAL_BASE 0x0800 -#define CPM_I2C_BASE 0x0820 -#define CPM_SPI_BASE 0x0840 -#define CPM_FEC_BASE 0x0860 -#define CPM_SERIAL2_BASE 0x08E0 -#define CPM_SCC_BASE 0x0900 -#define CPM_POST_BASE 0x0980 -#define CPM_WLKBD_BASE 0x0a00 - -#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR -#define CPM_POST_WORD_ADDR 0x07FC -#else -#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR -#endif - -#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) -#else -#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#endif - -#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8xx_t *cpmp; /* Pointer to comm processor */ - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ - -/* Parameter RAM offsets. -*/ -#define PROFF_SCC1 ((uint)0x0000) -#define PROFF_IIC ((uint)0x0080) -#define PROFF_REVNUM ((uint)0x00b0) -#define PROFF_SCC2 ((uint)0x0100) -#define PROFF_SPI ((uint)0x0180) -#define PROFF_SCC3 ((uint)0x0200) -#define PROFF_SMC1 ((uint)0x0280) -#define PROFF_SCC4 ((uint)0x0300) -#define PROFF_SMC2 ((uint)0x0380) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - u_char res1[8]; - ushort smc_rpbase; /* Relocation pointer */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC2 as Centronics parallel printer. It is half duplex, in that - * it can only receive or transmit. The parameter ram values for - * each direction are either unique or properly overlap, so we can - * include them in one structure. - */ -typedef struct smc_centronics { - ushort scent_rbase; - ushort scent_tbase; - u_char scent_cfcr; - u_char scent_smask; - ushort scent_mrblr; - uint scent_rstate; - uint scent_r_ptr; - ushort scent_rbptr; - ushort scent_r_cnt; - uint scent_rtemp; - uint scent_tstate; - uint scent_t_ptr; - ushort scent_tbptr; - ushort scent_t_cnt; - uint scent_ttemp; - ushort scent_max_sl; - ushort scent_sl_cnt; - ushort scent_character1; - ushort scent_character2; - ushort scent_character3; - ushort scent_character4; - ushort scent_character5; - ushort scent_character6; - ushort scent_character7; - ushort scent_character8; - ushort scent_rccm; - ushort scent_rccr; -} smc_cent_t; - -/* Centronics Status Mask Register. -*/ -#define SMC_CENT_F ((u_char)0x08) -#define SMC_CENT_PE ((u_char)0x04) -#define SMC_CENT_S ((u_char)0x02) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SI Clock Route Register -*/ -#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) -#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) -#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) -#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) -#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) -#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* Function code bits. -*/ -#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* CPM Ethernet through SCCx. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - -/********************************************************************** - * - * Board specific configuration settings. - * - * Please note that we use the presence of a #define SCC_ENET and/or - * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. - **********************************************************************/ - -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_BSEIP -/* This ENET stuff is for the MPC823 with ethernet on SCC2. - * This is unique to the BSE ip-Engine board. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* BSE uses port B and C bits for PHY control also. -*/ -#define PB_BSE_POWERUP ((uint)0x00000004) -#define PB_BSE_FDXDIS ((uint)0x00008000) -#define PC_BSE_LOOPBACK ((ushort)0x0800) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002c00) -#endif /* CONFIG_BSEIP */ - -/*** KM8XX *********************************************************/ - -/* The KM8XX Service Module uses SCC3 for Ethernet */ - -#ifdef CONFIG_KM8XX -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ -#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ -#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ -#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ - -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ -#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ - -/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00250000) -#endif /* CONFIG_KM8XX */ - -/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ - -#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ - defined(CONFIG_TQM823L) || \ - defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ -#define FEC_ENET -# endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ - -/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ - -#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ - defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ - defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) - -# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) - -# endif /* CONFIG_SCC1_ENET */ - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ - -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ - -/*********************************************************************/ - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ - uint iic_res; /* reserved */ - ushort iic_rpbase; /* Relocation pointer */ - ushort iic_res2; /* reserved */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; - ushort spi_rpbase; /* Relocation pointer */ - ushort spi_res2; -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -/* HDLC parameter RAM. -*/ - -typedef struct hdlc_pram_s { - /* - * SCC parameter RAM - */ - ushort rbase; /* Rx Buffer descriptor base address */ - ushort tbase; /* Tx Buffer descriptor base address */ - uchar rfcr; /* Rx function code */ - uchar tfcr; /* Tx function code */ - ushort mrblr; /* Rx buffer length */ - ulong rstate; /* Rx internal state */ - ulong rptr; /* Rx internal data pointer */ - ushort rbptr; /* rb BD Pointer */ - ushort rcount; /* Rx internal byte count */ - ulong rtemp; /* Rx temp */ - ulong tstate; /* Tx internal state */ - ulong tptr; /* Tx internal data pointer */ - ushort tbptr; /* Tx BD pointer */ - ushort tcount; /* Tx byte count */ - ulong ttemp; /* Tx temp */ - ulong rcrc; /* temp receive CRC */ - ulong tcrc; /* temp transmit CRC */ - /* - * HDLC specific parameter RAM - */ - uchar res[4]; /* reserved */ - ulong c_mask; /* CRC constant */ - ulong c_pres; /* CRC preset */ - ushort disfc; /* discarded frame counter */ - ushort crcec; /* CRC error counter */ - ushort abtsc; /* abort sequence counter */ - ushort nmarc; /* nonmatching address rx cnt */ - ushort retrc; /* frame retransmission cnt */ - ushort mflr; /* maximum frame length reg */ - ushort max_cnt; /* maximum length counter */ - ushort rfthr; /* received frames threshold */ - ushort rfcnt; /* received frames count */ - ushort hmask; /* user defined frm addr mask */ - ushort haddr1; /* user defined frm address 1 */ - ushort haddr2; /* user defined frm address 2 */ - ushort haddr3; /* user defined frm address 3 */ - ushort haddr4; /* user defined frm address 4 */ - ushort tmp; /* temp */ - ushort tmp_mb; /* temp */ -} hdlc_pram_t; - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -#define CPMVEC_NR 32 -#define CPMVEC_OFFSET 0x00010000 -#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) -#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) -#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) -#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) -#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) -#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) -#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) -#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) -#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) -#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) -#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) -#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) -#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) -#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) -#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) -#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) -#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) -#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) - -extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((uint)0x00000080) /* Int. enable */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ -#endif /* __CPM_8XX__ */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ab4b060..c66b26f 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -139,7 +139,6 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index b13809f..3a1d4d9 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -306,7 +306,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 9b2f836..3b62449 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -326,13 +326,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 618d537..3734055 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -206,7 +206,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -337,9 +337,9 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 4b93210..7ec36eb 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -101,7 +101,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ -#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/PATI.h b/include/configs/PATI.h deleted file mode 100644 index 1f26ac4..0000000 --- a/include/configs/PATI.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: PATI.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REGINFO - -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_PREBOOT - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ -/* - * Start addresses for the final memory configuration - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ -#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ -#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ -#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ - -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 -/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_ENV_IS_IN_EEPROM -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 2048 -#endif - -#undef CONFIG_ENV_IS_IN_FLASH -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ -#endif - -#define CONFIG_SPI 1 -#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ -#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ -#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#undef CONFIG_WATCHDOG -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ - -#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) -#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ -/* SDRAM */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ -/* PCI */ -#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) -/* config registers: */ -#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR3_PRELIM (0xffff0000) - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CONFIG_SYS_DER 0x00000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 393a02d..1f5b9f0 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -246,7 +246,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 78ce91d..b8f23d7 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -150,7 +150,6 @@ /* * IDE/ATA stuff */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h deleted file mode 100644 index e1f0445..0000000 --- a/include/configs/TQM5200.h +++ /dev/null @@ -1,626 +0,0 @@ -/* - * (C) Copyright 2003-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration with room for - * max 64 MByte Flash ROM) - * 0xFFF00000 boot high (for a backup copy of U-Boot) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -/* On a Cameron or on a FO300 board or ... */ -#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \ - && !defined(CONFIG_FO300) -#define CONFIG_STK52XX 1 /* ... on a STK52XX board */ -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_BOOTCOUNT_LIMIT 1 - -#ifdef CONFIG_FO300 -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */ -#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ -#if 0 -#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ - /* switch is closed */ -#endif - -#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ - /* switch is open */ -#endif /* CONFIG_FO300 */ - -#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -/* - * Video console - */ -#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_VIDEO_LOGO - -#ifndef CONFIG_FO300 -#else -#define CONFIG_VIDEO_BMP_LOGO -#endif - -#define CONFIG_SPLASH_SCREEN -#endif /* #ifndef CONFIG_TQM5200S */ - -/* Partitions */ - -/* USB */ -#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ - defined(CONFIG_STK52XX) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#endif - -#ifndef CONFIG_CAM5200 -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU) -#endif - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 -#endif - -#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ - defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) -#endif - -#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ - defined(CONFIG_STK52XX) - #define CONFIG_CFG_USB - #define CONFIG_CFG_FAT -#endif - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) -# define CONFIG_SYS_LOWBOOT 1 /* Boot low */ -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FFF00000 +${filesize};" \ - "erase FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 +${filesize}\0" -#else /* default lowboot configuration */ -# define ENV_UPDT \ - "update=protect off FC000000 +${filesize};" \ - "erase FC000000 +${filesize};" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 +${filesize}\0" -#endif - -#if defined(CONFIG_TQM5200) -#define CUSTOM_ENV_SETTINGS \ - "hostname=tqm5200\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" -#elif defined(CONFIG_CAM5200) -#define CUSTOM_ENV_SETTINGS \ - "bootfile=cam5200/uImage\0" \ - "u-boot=cam5200/u-boot.bin\0" \ - "setup=tftp 200000 cam5200/setup.img; source 200000\0" -#endif - -#if defined(CONFIG_TQM5200_B) -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FC100000\0" \ - "kernel_addr=FC140000\0" \ - "ramdisk_addr=FC600000\0" -#elif defined(CONFIG_CHARON) -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FDFC0000\0" \ - "kernel_addr=FC0A0000\0" \ - "ramdisk_addr=FC200000\0" -#else /* !CONFIG_TQM5200_B */ -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FC0A0000\0" \ - "kernel_addr=FC0C0000\0" \ - "ramdisk_addr=FC300000\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "console=ttyPSC0\0" \ - ENV_FLASH_LAYOUT \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "flash_self_old=sete console ttyS0; " \ - "run ramargs addip addcons addmtd; " \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons addmtd; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - CUSTOM_ENV_SETTINGS \ - "load=tftp 200000 ${u-boot}\0" \ - ENV_UPDT \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of - * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 - -#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_ADDR0 0x555 -#define CONFIG_SYS_FLASH_ADDR1 0x2AA -#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#else -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_FLASH_CFI_MTD /* with MTD support */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#if defined (CONFIG_CAM5200) -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#elif defined(CONFIG_TQM5200_B) -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) -#else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nor0=fc000000.flash" - -#if defined(CONFIG_STK52XX) -# if defined(CONFIG_TQM5200_B) -# if defined(CONFIG_SYS_LOWBOOT) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \ - "256k(dtb)," \ - "2304k(kernel)," \ - "2560k(small-fs)," \ - "2m(initrd)," \ - "8m(misc)," \ - "16m(big-fs)" -# else /* highboot */ -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\ - "3584k(small-fs)," \ - "2m(initrd)," \ - "8m(misc)," \ - "15m(big-fs)," \ - "1m(firmware)" -# endif /* CONFIG_SYS_LOWBOOT */ -# else /* !CONFIG_TQM5200_B */ -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ - "128k(dtb)," \ - "2304k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "8m(misc)," \ - "15m(big-fs)" -# endif /* CONFIG_TQM5200_B */ -#elif defined (CONFIG_CAM5200) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\ - "1792k(kernel)," \ - "5632k(rootfs)," \ - "24m(home)" -#elif defined (CONFIG_CHARON) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "24320k(big-fs)," \ - "256k(dts)" -#elif defined (CONFIG_FO300) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "8m(misc)," \ - "16m(big-fs)" -#else -# error "Unknown Carrier Board" -#endif /* CONFIG_STK52XX */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif /* CONFIG_TQM5200_B */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#if defined (CONFIG_CAM5200) -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#elif defined(CONFIG_TQM5200_B) -# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#endif - -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use CS1: Bit 0 (mask: 0x80000000): - * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * SPI on PSC3 according to PSC3 setting. Use for CAM5200. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards and FO300 boards. Do not use - * with REV100 modules (because, there I2C1 is used as I2C bus). - * use ATA: Bits 6-7 (mask 0x03000000): - * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. - * Use for CAM5200 board. - * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. - * use PSC6: Bits 9-11 (mask 0x00700000): - * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as - * UART, CODEC or IrDA. - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to - * enable extended POST tests. - * Use for MINI-FAP and TQM5200_IB boards. - * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. - * Extended POST test is not available. - * Use for STK52xx, FO300 and CAM5200 boards. - * WARNING: When the extended POST is enabled, these bits will - * be overridden by this code as GPIOs! - * use PCI_DIS: Bit 16 (mask 0x00008000): - * 1 -> disable PCI controller (on CAM5200 board). - * use USB: Bits 18-19 (mask 0x00003000): - * 10 -> two UARTs (on FO300 and CAM5200). - * use PSC3: Bits 20-23 (mask: 0x00000f00): - * 0000 -> All PSC3 pins are GPIOs. - * 1100 -> UART/SPI (on FO300 board). - * 0100 -> UART (on CAM5200 board). - * use PSC2: Bits 25:27 (mask: 0x00000030): - * 000 -> All PSC2 pins are GPIOs. - * 100 -> UART (on CAM5200 board). - * 001 -> CAN1/2 on PSC2 pins. - * Use for REV100 STK52xx boards - * 01x -> Use AC97 (on FO300 board). - * use PSC1: Bits 29-31 (mask: 0x00000007): - * 100 -> UART (on all boards). - */ -#if !defined(CONFIG_SYS_GPS_PORT_CONFIG) -#if defined (CONFIG_MINIFAP) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404 -# endif -# endif -#elif defined (CONFIG_FO300) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24 -#elif defined (CONFIG_CAM5200) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444 -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CONFIG_SYS_CS2_START 0xE5000000 -#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ -#define CONFIG_SYS_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CONFIG_SYS_CS1_START (SM501_FB_BASE) -#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CONFIG_SYS_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#if defined(CONFIG_CAM5200) -#define CONFIG_SYS_CS4_START 0xB0000000 -#define CONFIG_SYS_CS4_SIZE 0x00010000 -#define CONFIG_SYS_CS4_CFG 0x01019C10 - -#define CONFIG_SYS_CS5_START 0xD0000000 -#define CONFIG_SYS_CS5_SIZE 0x01208000 -#define CONFIG_SYS_CS5_CFG 0x1414BF10 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/* Support ATAPI devices */ -#define CONFIG_ATAPI 1 - -/*----------------------------------------------------------------------- - * Open firmware flat tree support - *----------------------------------------------------------------------- - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h deleted file mode 100644 index 74636b9..0000000 --- a/include/configs/TQM823L.h +++ /dev/null @@ -1,435 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ -#define CONFIG_LCD_INFO 1 /* ... and some board info */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823L\0" \ - "bootfile=TQM823L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM823L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h deleted file mode 100644 index 6b345c4..0000000 --- a/include/configs/TQM823M.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823M\0" \ - "bootfile=TQM823M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM823M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h deleted file mode 100644 index b4ed561..0000000 --- a/include/configs/TQM850L.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850L\0" \ - "bootfile=TQM850L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM850L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h deleted file mode 100644 index 1dc1329..0000000 --- a/include/configs/TQM850M.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850M\0" \ - "bootfile=TQM850M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM850M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h deleted file mode 100644 index b4c3a79..0000000 --- a/include/configs/TQM855L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855L\0" \ - "bootfile=TQM855L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM855L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h deleted file mode 100644 index 14b76a6..0000000 --- a/include/configs/TQM855M.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855M\0" \ - "bootfile=TQM855M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM855M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#if 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h deleted file mode 100644 index f55fe56..0000000 --- a/include/configs/TQM860L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860L\0" \ - "bootfile=TQM860L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM860L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h deleted file mode 100644 index 52c4d68..0000000 --- a/include/configs/TQM860M.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860M\0" \ - "bootfile=TQM860M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM860M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h deleted file mode 100644 index 06981c9..0000000 --- a/include/configs/TQM862L.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862L\0" \ - "bootfile=TQM862L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM862L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h deleted file mode 100644 index 3f87d8a..0000000 --- a/include/configs/TQM862M.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862M\0" \ - "bootfile=TQM862M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM862M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h deleted file mode 100644 index 975f4b7..0000000 --- a/include/configs/TQM866M.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ -#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CONFIG_SYS_MEASURE_CPUCLK -#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM866M\0" \ - "bootfile=TQM866M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM866M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 97 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h deleted file mode 100644 index 184cb62..0000000 --- a/include/configs/TQM885D.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM885D/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 128 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Network configuration - */ -#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#if defined(CONFIG_CMD_MII) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - -#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before - switching to another netwok (if the - tried network is unreachable) */ - -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index b2feccf..8579290 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -311,7 +311,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ #define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h deleted file mode 100644 index 82b9ff4..0000000 --- a/include/configs/a3m071.h +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright 2012-2013 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_A3M071 /* A3M071 board */ - -#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ - -#define CONFIG_SPL_TARGET "u-boot-img.bin" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_LOWBOOT /* Enable lowboot */ - -#ifdef CONFIG_A4M2K -#define CONFIG_HOSTNAME a4m2k -#else -#define CONFIG_HOSTNAME a3m071 -#endif - -#define CONFIG_BOOTCOUNT_LIMIT - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_MAY_FAIL -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_NET_RETRY_COUNT 3 -#define CONFIG_NETCONSOLE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS /* needed for UBI */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=fc000000.flash" -#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \ - "128k(env1)," \ - "128k(env2)," \ - "128k(hwinfo)," \ - "1M(nvramsim)," \ - "128k(dtb)," \ - "5M(kernel)," \ - "128k(sysinfo)," \ - "7552k(root)," \ - "4M(app)," \ - "5376k(data)," \ - "8M(install)" - -#define CONFIG_LZO /* needed for UBI */ -#define CONFIG_RBTREE /* needed for UBI */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_UBIFS - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* define for 66MHz speed - undef for 33MHz PCI clock speed */ -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#else -#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#endif - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -/* - * NOR flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_FLASH_VERIFY - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (4 << 20) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#ifdef CONFIG_A4M2K -#define CONFIG_PHY_ADDR 0x01 -#else -#define CONFIG_PHY_ADDR 0x00 -#endif - -/* - * GPIO configuration - */ - -/* - * GPIO-config depends on failsave-level - * failsave 0 means just MPX-config, no digiboard, no fpga - * 1 means digiboard ok - * 2 means fpga ok - */ - -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805 -#else -/* for failsave-level 0 - full failsave */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 -/* for failsave-level 1 - only digiboard ok */ -#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065 -/* for failsave-level 2 - all ok */ -#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065 -#endif - -#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 -#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */ -#endif - -/* - * Configuration matrix - * MSB LSB - * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) - * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok ) - * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok ) - * || ||| || | ||| | | | | - * || ||| || | ||| | | | | bit rev name - * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 - * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ - * ||| || | ||| | | | | 2 29 ALTs - * +++-++--+---+++-+---+---+---+- 3 28 ALTs - * ++-++--+---+++-+---+---+---+- 4 27 CS7 - * +-++--+---+++-+---+---+---+- 5 26 CS6 - * || | ||| | | | | 6 25 ATA - * ++--+---+++-+---+---+---+- 7 24 ATA - * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK - * | ||| | | | | 9 22 IRDA - * | ||| | | | | 10 21 IRDA - * +---+++-+---+---+---+- 11 20 IRDA - * ||| | | | | 12 19 Ether - * ||| | | | | 13 18 Ether - * ||| | | | | 14 17 Ether - * +++-+---+---+---+- 15 16 Ether - * ++-+---+---+---+- 16 15 PCI_DIS - * +-+---+---+---+- 17 14 USB_SE - * | | | | 18 13 USB - * +---+---+---+- 19 12 USB - * | | | 20 11 PSC3 - * | | | 21 10 PSC3 - * | | | 22 9 PSC3 - * +---+---+- 23 8 PSC3 - * | | 24 7 - - * | | 25 6 PSC2 - * | | 26 5 PSC2 - * +---+- 27 4 PSC2 - * | 28 3 - - * | 29 2 PSC1 - * | 30 1 PSC1 - * +- 31 0 PSC1 - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP - -#define CONFIG_CMDLINE_EDITING - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00f00000 - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#ifdef CONFIG_A4M2K -/* external MRAM */ -#define CONFIG_SYS_CS1_START 0xf1000000 -#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ -#endif - -#define CONFIG_SYS_CS2_START 0xe0000000 -#define CONFIG_SYS_CS2_SIZE 0x00100000 - -/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ -#define CONFIG_SYS_CS3_START 0xE9000000 -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#else -#define CONFIG_SYS_CS3_SIZE 0x00080000 -#endif -/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ -#define CONFIG_SYS_CS3_CFG 0x0032B900 - -#ifndef CONFIG_A4M2K -/* Diagnosis Interface - see ticket #63 */ -#define CONFIG_SYS_CS4_START 0xEA000000 -#define CONFIG_SYS_CS4_SIZE 0x00000001 -/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ -#define CONFIG_SYS_CS4_CFG 0x0002B900 -#endif - -/* FPGA master io (64kiB / 1MiB) - see ticket #66 */ -#define CONFIG_SYS_CS5_START 0xE8000000 -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_CS5_SIZE 0x00100000 -#else -#define CONFIG_SYS_CS5_SIZE 0x00010000 -#endif -/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ -#define CONFIG_SYS_CS5_CFG 0x0032B900 - -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ -#define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0008FD00 -#define CONFIG_SYS_CS2_CFG 0x0006F90C -#else /* for pci_clk = 33 MHz */ -#define CONFIG_SYS_BOOTCS_CFG 0x0002F900 -#define CONFIG_SYS_CS1_CFG 0x0001FB00 -#define CONFIG_SYS_CS2_CFG 0x0002F90C -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */ -/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */ -/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */ -#define CONFIG_SYS_CS_DEADCYCLE 0x33030000 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * Environment Configuration - */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_SYS_AUTOLOAD "n" - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \ - "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_SYS_FDT_BASE 0xfc1e0000 -#define CONFIG_SYS_FDT_SIZE (16<<10) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "verify=no\0" \ - "loadaddr=200000\0" \ - "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ - "fdt_addr_r=1800000\0" \ - "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ - "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ - __stringify(CONFIG_HOSTNAME) ".dtb\0" \ - "rootpath=/opt/eldk-5.2.1/powerpc/" \ - "core-image-minimal-mtdutils-dropbear-generic\0" \ - "consoledev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock8 " \ - "rootfstype=squashfs,jffs2\0" \ - "addhost=setenv bootargs ${bootargs} " \ - "hostname=${hostname}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consoledev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_mtd=run mtdargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ - "/u-boot-img.bin\0" \ - "update=protect off fc000000 fc07ffff;" \ - "era fc000000 fc07ffff;" \ - "cp.b ${loadaddr} fc000000 ${filesize}\0" \ - "upd=run load;run update\0" \ - "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \ - "run mtdargs addip addtty addmtd addhost;" \ - "fdt addr 1800000;fdt boardsetup;fdt chosen;" \ - "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \ - "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \ - "erase fc200000 fc6fffff;" \ - "cp.b 1000000 fc200000 ${filesize}" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_mtd" - -/* - * SPL related defines - */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0xfc000000 - -/* Place BSS for SPL near end of SDRAM */ -#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20) -#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) - -/* Place patched DT blob (fdt) at this address */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 - -/* Settings for real U-Boot to be loaded from NOR flash */ -#ifndef __ASSEMBLY__ -extern char __spl_flash_end[]; -#endif -#define CONFIG_SYS_UBOOT_BASE __spl_flash_end -#define CONFIG_SYS_SPL_MAX_LEN (32 << 10) -#define CONFIG_SYS_UBOOT_START 0x1000100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h deleted file mode 100644 index 6a26269..0000000 --- a/include/configs/a4m072.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2010 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_A4M072 1 /* ... on A4M072 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -/* define to enable silent console */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_SYS_XLB_PIPELINING 1 - -#undef CONFIG_EEPRO100 - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ -#define CONFIG_SYS_LOWBOOT 1 -#define CONFIG_SYS_LOWBOOT32 1 -#endif - -/* - * Autobooting - */ - -#define CONFIG_SYS_AUTOLOAD "n" - -#undef CONFIG_BOOTARGS -#define CONFIG_PREBOOT "run try_update" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \ - "cf1=diskboot 200000 0:1\0" \ - "bootcmd_cf1=run bcf1\0" \ - "bcf=setenv bootargs root=/dev/hda3\0" \ - "bootcmd_nfs=run bnfs\0" \ - "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\ - "panic=1\0" \ - "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \ - "run norargs addip; run bk\0" \ - "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \ - "run nfsargs addip ; run bk\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "try_update=usb start;sleep 2;usb start;sleep 1;" \ - "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \ - "source 2F0000\0" \ - "env_addr=FE060000\0" \ - "kernel_addr=FE100000\0" \ - "rootfs_addr=FE200000\0" \ - "add_mtd=setenv bootargs ${bootargs} mtdparts=" \ - "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \ - "bcf1=run cf1; run bcf; run addip; run bk\0" \ - "add_consolespec=setenv bootargs ${bootargs} " \ - "console=/dev/null quiet\0" \ - "addip=if test -n ${ethaddr};" \ - "then if test -n ${ipaddr};" \ - "then setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:"\ - "${netmask}:${hostname}:${netdev}:off;" \ - "fi;" \ - "else;" \ - "setenv bootargs ${bootargs} no_ethaddr;" \ - "fi\0" \ - "hostname=CPUP0\0" \ - "netdev=eth0\0" \ - "bootcmd=run bootcmd_nor\0" \ - "" -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#error "CONFIG_SYS_LOWBOOT not defined?" -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_SYS_LOWBOOT32) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif -#endif /* CONFIG_SYS_LOWBOOT */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START} -#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE} - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x1f -#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */ - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE -/* Flash at CSBoot, CS0 */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -/* External SRAM at CS1 */ -#define CONFIG_SYS_CS1_START 0x62000000 -#define CONFIG_SYS_CS1_SIZE 0x00400000 -#define CONFIG_SYS_CS1_CFG 0x00009930 -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE -/* LED display at CS7 */ -#define CONFIG_SYS_CS7_START 0x6a000000 -#define CONFIG_SYS_CS7_SIZE (64*1024) -#define CONFIG_SYS_CS7_CFG 0x0000bf30 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333003 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -/*----------------------------------------------------------------------- - * Open firmware flat tree support - *----------------------------------------------------------------------- - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -/* Support for the 7-segment display */ -#define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START -#define CONFIG_SHOW_ACTIVITY /* used for display realization */ - -#define CONFIG_SHOW_BOOT_PROGRESS - -#endif /* __CONFIG_H */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h deleted file mode 100644 index 4eb8f39..0000000 --- a/include/configs/ac14xx.h +++ /dev/null @@ -1,516 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk - * (C) Copyright 2010 DAVE Srl - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * ifm AC14xx (MPC5121e based) board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AC14XX 1 - -/* - * Memory map for the ifm AC14xx board: - * - * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) - * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) - * 0x8000_0000-0x803F_FFFF IMMR (4 MB) - * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx) - * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */ -#define SCFR1_IPS_DIV 2 -#define SCFR1_LPC_DIV 2 -#define SCFR1_NFC_DIV 2 -#define SCFR1_DIU_DIV 240 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) - -/* more aggressive 'mtest' over a wider address range */ -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x0FE00000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -/* - * DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ - -/* - * NOTE: although this board uses DDR1 only, the common source brings defaults - * for DDR2 init sequences, that's why we have to keep those here as well - */ - -/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */ -#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0)) - -#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \ - | (1 << 31) /* RST_B */ \ - | (1 << 30) /* CKE */ \ - | (1 << 29) /* CLK_ON */ \ - | (0 << 28) /* CMD_MODE */ \ - | (5 << 25) /* DRAM_ROW_SELECT */ \ - | (5 << 21) /* DRAM_BANK_SELECT */ \ - | (0 << 18) /* SELF_REF_EN */ \ - | (0 << 17) /* 16BIT_MODE */ \ - | (4 << 13) /* RDLY */ \ - | (1 << 12) /* HALF_DQS_DLY */ \ - | (0 << 11) /* QUART_DQS_DLY */ \ - | (1 << 8) /* WDLY */ \ - | (0 << 7) /* EARLY_ODT */ \ - | (0 << 6) /* ON_DIE_TERMINATE */ \ - | (0 << 5) /* FIFO_OV_CLEAR */ \ - | (0 << 4) /* FIFO_UV_CLEAR */ \ - | (0 << 1) /* FIFO_OV_EN */ \ - | (0 << 0) /* FIFO_UV_EN */ \ - ) - -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864 - -/* register address only, i.e. template without values */ -#define CONFIG_SYS_MICRON_BMODE 0x01000000 -#define CONFIG_SYS_MICRON_EMODE 0x01010000 -#define CONFIG_SYS_MICRON_EMODE2 0x01020000 -#define CONFIG_SYS_MICRON_EMODE3 0x01030000 -/* - * values for mode registers (without mode register address) - */ -/* CAS 2.5 (6), burst seq (0) and length 4 (2) */ -#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062 -#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100 -/* DLL enable, reduced drive strength */ -#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (0 << 10) | /* A10->DQS# */ \ - (0 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (0 << 2) | /* Rtt0 */ \ - (1 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) -#define CONFIG_SYS_MICRON_EMR2 0x01020000 -#define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ - (7 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (1 << 2) | /* Rtt0 */ \ - (0 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) - -/* - * Backward compatible definitions, - * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c - */ -#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { \ - CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \ - } -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * SRAM support - */ -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -/* - * CS related parameters - */ -/* CS0 Flash */ -#define CONFIG_SYS_CS0_CFG 0x00031110 -#define CONFIG_SYS_CS0_START 0xFC000000 -#define CONFIG_SYS_CS0_SIZE 0x04000000 -/* CS1 FRAM */ -#define CONFIG_SYS_CS1_CFG 0x00011000 -#define CONFIG_SYS_CS1_START 0xE0000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -/* CS2 AS-i 1 */ -#define CONFIG_SYS_CS2_CFG 0x00009100 -#define CONFIG_SYS_CS2_START 0xE0100000 -#define CONFIG_SYS_CS2_SIZE 0x00080000 -/* CS3 netX */ -#define CONFIG_SYS_CS3_CFG 0x000A1140 -#define CONFIG_SYS_CS3_START 0xE0300000 -#define CONFIG_SYS_CS3_SIZE 0x00020000 -/* CS5 safety */ -#define CONFIG_SYS_CS5_CFG 0x0011F000 -#define CONFIG_SYS_CS5_START 0xE0400000 -#define CONFIG_SYS_CS5_SIZE 0x00010000 -/* CS6 AS-i 2 */ -#define CONFIG_SYS_CS6_CFG 0x00009100 -#define CONFIG_SYS_CS6_START 0xE0200000 -#define CONFIG_SYS_CS6_SIZE 0x00080000 - -/* Don't use alternative CS timing for any CS */ -#define CONFIG_SYS_CS_ALETIMING 0x00000000 -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x00000020 -#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020 - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSC_EN(7) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -#define CONFIG_CMDLINE_EDITING 1 /* command line history */ - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1F -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the flash sector size */ -#define CONFIG_ENV_ADDR 0xFFF40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_TIMESTAMP - -/* default load addr for tftp and bootm */ -#define CONFIG_LOADADDR 400000 - - -/* the builtin environment and standard greeting */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ - "muster_nr=-00\0" \ - "fromram=run ramargs addip addtty; " \ - "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \ - "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \ - "tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; " \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ - "fromnfs=run nfsargs addip addtty; " \ - "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \ - "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fromflash=run nfsargs addip addtty; " \ - "bootm fc020000 - fc000000\0" \ - "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \ - "recovery=run mtdargsrec addip addtty; " \ - "bootm ffd20000 - ffee0000\0" \ - "production=run ramargs addip addtty; " \ - "bootm fc020000 fc400000 fc000000\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \ - "prodmtd=run mtdargs addip addtty; " \ - "bootm fc020000 - fc000000\0" \ - "" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=a00000\0" \ - "ramdisk_addr_r=b00000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FC020000\0" \ - "fdt_addr=FC000000\0" \ - "ramdisk_addr=FC400000\0" \ - "verify=n\0" \ - "ramdiskfile=ac14xx/uRamdisk\0" \ - "u-boot=ac14xx/u-boot.bin\0" \ - "bootfile=ac14xx/uImage\0" \ - "fdtfile=ac14xx/ac14xx.dtb\0" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "hostname=ac14xx\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}${muster_nr}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run production" - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -#endif /* __CONFIG_H */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index b379e08..7a42d79 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -13,6 +13,7 @@ #define __CONFIG_AM57XX_EVM_H #include +#include #ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION @@ -20,11 +21,14 @@ #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_DEVICE_AND_PART "0:1" -#define FAT_ENV_FILE "uboot.env" +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */ +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_OFFSET 0x260000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONSOLEDEV "ttyO2" #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ @@ -46,7 +50,7 @@ "partitions_android=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ + "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ diff --git a/include/configs/aria.h b/include/configs/aria.h deleted file mode 100644 index 0a7ef99..0000000 --- a/include/configs/aria.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk - * (C) Copyright 2009, DAVE Srl - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Aria board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARIA 1 - -/* - * Memory map for the ARIA board: - * - * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) - * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) - * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 - * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 - * 0x8000_0000-0x803F_FFFF IMMR (4 MB) - * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) - * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) - * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) - * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* video */ - -/* CONFIG_PCI is defined at config time */ - -#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 - -/* DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ - (1 << 30) | /* CKE */ \ - (1 << 29) | /* CLK_ON */ \ - (0 << 28) | /* CMD_MODE */ \ - (4 << 25) | /* DRAM_ROW_SELECT */ \ - (3 << 21) | /* DRAM_BANK_SELECT */ \ - (0 << 18) | /* SELF_REF_EN */ \ - (0 << 17) | /* 16BIT_MODE */ \ - (2 << 13) | /* RDLY */ \ - (0 << 12) | /* HALF_DQS_DLY */ \ - (1 << 11) | /* QUART_DQS_DLY */ \ - (2 << 8) | /* WDLY */ \ - (0 << 7) | /* EARLY_ODT */ \ - (1 << 6) | /* ON_DIE_TERMINATE */ \ - (0 << 5) | /* FIFO_OV_CLEAR */ \ - (0 << 4) | /* FIFO_UV_CLEAR */ \ - (0 << 1) | /* FIFO_OV_EN */ \ - (0 << 0) /* FIFO_UV_EN */ \ - ) - -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (0 << 10) | /* A10->DQS# */ \ - (0 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (0 << 2) | /* Rtt0 */ \ - (1 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) -#define CONFIG_SYS_MICRON_EMR2 0x01020000 -#define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ - (7 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (1 << 2) | /* Rtt0 */ \ - (0 << 1) | /* ODS (Output Drive Strength) */ \ - (0 << 0) /* DLL */ \ - ) - -/* - * Backward compatible definitions, - * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c - */ -#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND FLASH support - * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) - */ -#define CONFIG_CMD_NAND /* enable NAND support */ -#define CONFIG_JFFS2_NAND /* with JFFS2 on it */ -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE - -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -/* Make two SRAM regions contiguous */ -#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ - CONFIG_SYS_SRAM_SIZE) -#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ -#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE -#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE - -#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ - CONFIG_SYS_ARIA_SRAM_SIZE) -#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ - -#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE -#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE - -#define CONFIG_SYS_CS0_CFG 0x05059150 -#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ - (5 << 16) | \ - (1 << 15) | \ - (0 << 14) | \ - (0 << 13) | \ - (1 << 12) | \ - (0 << 10) | \ - (3 << 8) | /* 32 bit */ \ - (0 << 7) | \ - (1 << 6) | \ - (1 << 4) | \ - (0 << 3) | \ - (0 << 2) | \ - (0 << 1) | \ - (0 << 0) \ - ) -#define CONFIG_SYS_CS6_CFG 0x05059150 - -/* Use alternative CS timing for CS0 and CS2 */ -#define CONFIG_SYS_CS_ALETIMING 0x00000005 - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* FPGA */ -#define CONFIG_ARIA_FPGA 1 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -#define CONFIG_CMDLINE_EDITING 1 /* command line history */ - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ - CONFIG_SYS_PCI_MEM_SIZE) -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0x84000000 -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x17 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" - -/* - * NOR flash layout: - * - * F8000000 - FEAFFFFF 107 MiB User Data - * FEB00000 - FFAFFFFF 16 MiB Root File System - * FFB00000 - FFFEFFFF 4 MiB Linux Kernel - * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env - * FFFC0000 - FFFFFFFF 256 KiB Device Tree - * - * NAND flash layout: one big partition - */ -#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ - "16m(rootfs)," \ - "4m(kernel)," \ - "768k(u-boot)," \ - "256k(dtb);" \ - "mpc5121.nand:-(data)" - -/* - * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. - * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE - * is set to 0xFFFF, watchdog timeouts after about 64s. For details - * refer to chapter 36 of the MPC5121e Reference Manual. - */ -/* #define CONFIG_WATCHDOG */ /* enable watchdog */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - - /* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME aria -#define CONFIG_BOOTFILE "aria/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_LOADADDR 400000 /* default load addr */ - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=880000\0" \ - "ramdisk_addr_r=900000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFB00000\0" \ - "fdt_addr=FFFC0000\0" \ - "ramdisk_addr=FEB00000\0" \ - "ramdiskfile=aria/uRamdisk\0" \ - "u-boot=aria/u-boot.bin\0" \ - "fdtfile=aria/aria.dtb\0" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for IDE not supported */ - -#define CONFIG_IDE_RESET /* reset for IDE supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() - -/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define ATA_BASE_ADDR get_pata_base() - -/* - * Control register bit definitions - */ -#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 -#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 -#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 -#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 -#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 -#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 -#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 -#define FSL_ATA_CTRL_IORDY_EN 0x01000000 - -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -#endif /* __CONFIG_H */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 5814d74..f7d7369 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -16,14 +16,8 @@ #include /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD -#define CONFIG_LCD_NOSTDOUT #define LCD_BPP LCD_COLOR32 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4) -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP - /* memory */ #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) @@ -37,8 +31,6 @@ /* I2C IP block */ #define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000 -/* GPIO */ - /* MMC/SD IP block */ #define CONFIG_SUPPORT_EMMC_BOOT @@ -46,51 +38,36 @@ #define CONFIG_ENV_SIZE (64 << 10) #ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ +"autoload=0\0" \ +"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ "bootdev=cpsw(0,0)\0" \ "vx_romfsbase=0x800E0000\0" \ "vx_romfssize=0x20000\0" \ "vx_memtop=0x8FBEF000\0" \ "loadromfs=mmc read ${vx_romfsbase} 700 100\0" \ -"autoload=0\0" \ "loadaddr=0x80100000\0" \ -"logoaddr=0x82000000\0" \ -"defaultARlen=0x8000\0" \ -"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \ -"defaultAR=run loadromfs; run loaddefaultAR; bootvx ${loadaddr}\0" \ -"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \ - "bmp display ${logoaddr} 0 0\0" \ -"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \ - "bmp display ${logoaddr} 0 0\0" \ -"mmcboot=echo booting AR from eMMC-flash ...; "\ - "run logo0 || run logo1; " \ - "run loadromfs; " \ - "fatload mmc 0:1 ${loadaddr} arimg && bootvx ${loadaddr}; " \ - "run defaultAR;\0" \ -"netboot=echo booting AR from network ...; " \ - "run loadromfs; " \ - "tftp ${loadaddr} arimg && bootvx ${loadaddr}; " \ - "puts 'networkboot failed!';\0" \ -"netscript=echo running script from network (tftp) ...; " \ - "tftp 0x80000000 netscript.img && source; " \ - "puts 'netscript load failed!'\0" \ -"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \ - "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \ -"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \ - "if tftp 0x80100000 arimg.bin; " \ - "then mmc write 0x80100000 800 ${defaultARlen}; " \ - "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \ -"netupdateROMFS=echo updating romfs from network (tftp) ...; " \ - "if tftp 0x80100000 romfs.bin; " \ - "then mmc write 0x80100000 700 100; " \ - "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0" - +"startvx=run loadromfs; bootvx ${loadaddr}\0" \ +"b_break=0\0" \ +"b_tgts_std=mmc def net usb0\0" \ +"b_tgts_rcy=def net usb0\0" \ +"b_tgts_pme=net usb0 mmc\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_mmc=load mmc 1 ${loadaddr} arimg && run startvx\0" \ +"b_def=mmc read ${loadaddr} 800 8000; run startvx\0" \ +"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \ +"b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" #endif /* !CONFIG_SPL_BUILD*/ -#define CONFIG_BOOTCOMMAND \ - "run usbscript;" +#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" /* undefine command which we not need here */ #undef CONFIG_BOOTM_NETBSD @@ -113,7 +90,7 @@ BUR_COMMON_ENV \ #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 7907310..8d0e0ea 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -12,7 +12,6 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ -#define CONFIG_AM33XX #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 29d3bda..d43e331 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -316,4 +316,6 @@ int calimain_get_osc_freq(void); #endif +#include + #endif /* __CONFIG_H */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h deleted file mode 100644 index b7c74b4..0000000 --- a/include/configs/canmb.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ - -/* - * allowed and functional CONFIG_SYS_TEXT_BASE values: - * 0xfe000000 low boot at 0x00000100 (default board setting) - * 0x00100000 RAM load and test - */ -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#else -# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000" -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/canmb/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET (2*128*1024) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE (128*1024) - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x0 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047D01 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0x7f000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/charon.h b/include/configs/charon.h deleted file mode 100644 index 913b707..0000000 --- a/include/configs/charon.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_CHARON_H -#define __CONFIG_CHARON_H - -#define CONFIG_CHARON -#define CONFIG_HOSTNAME charon - -#define CONFIG_SYS_GPS_PORT_CONFIG 0x81550414 - -/* include common defines/options for TQM52xx boards */ -#include "TQM5200.h" - -/* defines special on charon board */ -#undef CONFIG_RTC_MPC5200 - -#undef CUSTOM_ENV_SETTINGS -#define CUSTOM_ENV_SETTINGS \ - "bootfile=/tftpboot/charon/uImage\0" \ - "fdt_file=/tftpboot/charon/charon.dtb\0" \ - "u-boot=/tftpboot/charon/u-boot.bin\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" - -/* additional features on charon board */ -#define CONFIG_RESET_PHY_R - -/* - * I2C configuration - */ -#define CONFIG_I2C_MULTI_BUS - -#define CONFIG_SYS_TFP410_ADDR 0x38 -#define CONFIG_SYS_TFP410_BUS 0 - -/* - * FPGA configuration - */ -#define CONFIG_SYS_CS3_START 0xE8000000 -#define CONFIG_SYS_CS3_SIZE 0x80000 /* 512 KByte */ - -/* - * CS3 Config Register Init: - * CS3 Enabled - * AddrBus: 8bits - * DataBus: 4bytes - * Multiplexed: Yes - * MuxBank: 00 - */ -#define CONFIG_SYS_CS3_CFG 0x00009310 - -#endif /* __CONFIG_CHARON_H */ diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index 96e5c9c..a04f4cd 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -42,9 +42,9 @@ #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -/* SD/MMC RAW boot */ -#undef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -#undef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION +/* SD/MMC RAW/FS boot */ +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 /* Environment */ #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */ @@ -128,8 +128,10 @@ "bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \ "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ + "emmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "emmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ "load_mmc=mmc dev ${mmcdev} && mmc rescan && " \ - "run mmcloadkernel run mmcloadfdt\0" \ + "run mmcloadkernel && run mmcloadfdt\0" \ "mmcroot=/dev/mmcblk1p2\0" \ "mmcrootfstype=ext4 rw rootwait\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ @@ -165,7 +167,7 @@ "source ${loadaddr}\0" \ "sataboot=run load_sata && run sataargs && " \ "echo Booting from SATA ... && " \ - "run bootkernel\0" \ + "run bootkernel\0" #undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h deleted file mode 100644 index 3777a0d..0000000 --- a/include/configs/cm5200.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_CM5200 1 /* ... on CM5200 platform */ - -#define CONFIG_SYS_TEXT_BASE 0xfc000000 - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Supported commands - */ -#define CONFIG_CMD_REGINFO - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ -/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - -/* - * POST support - */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU) -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) -/* List of I2C addresses to be verified by POST */ -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \ - CONFIG_SYS_I2C_IO, \ - CONFIG_SYS_I2C_EEPROM} - -/* display image timestamps */ -#define CONFIG_TIMESTAMP 1 - -/* - * Autobooting - */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ - "echo" -#undef CONFIG_BOOTARGS - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.33\0" \ - "serverip=192.168.1.1\0" \ - "gatewayip=192.168.1.1\0" \ - "console=ttyPSC0\0" \ - "u-boot_addr=100000\0" \ - "kernel_addr=200000\0" \ - "kernel_addr_flash=fc0c0000\0" \ - "fdt_addr=400000\0" \ - "fdt_addr_flash=fc0a0000\0" \ - "ramdisk_addr=500000\0" \ - "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ - "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ - "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ - "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fc000000 +${filesize}; " \ - "era fc000000 +${filesize}; " \ - "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ - "prot on fc000000 +${filesize}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "flash_flash=run flashargs addinit addip addcons;" \ - "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ - "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ - "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ - "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_flash" - -/* - * Low level configuration - */ - -/* - * Clock configuration - */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_LOWBOOT 1 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_BOARD_TYPES 1 /* we use board_type */ - -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -/* we need these despite using CFI */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#undef CONFIG_SYS_LOWBOOT -#endif - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ -/* use board_early_init_r to enable flash write in CS_BOOT */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* Flash memory addressing */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* No burst, dead cycle = 1 for CS0 (Flash) */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x00000001 - -/* - * SDRAM configuration - * settings for k4s561632E-xx75, assuming XLB = 132 MHz - */ -#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ -#define SDRAM_CONTROL 0x514F0000 -#define SDRAM_CONFIG1 0xE2333900 -#define SDRAM_CONFIG2 0x8EE70000 - -/* - * MTD configuration - */ -#define CONFIG_CMD_MTDPARTS 1 -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=cm5200-0" -#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ - "384k(uboot),128k(env)," \ - "128k(redund_env),128k(dtb)," \ - "2m(kernel),27904k(rootfs)," \ - "-(config)" - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * USB configuration - */ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 -/* Partitions (for USB) */ - -/* - * Invoke our last_stage_init function - needed by fwupdate - */ -#define CONFIG_LAST_STAGE_INIT 1 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -/* Configuration of redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Pin multiplexing configuration - */ - -/* - * CS1/GPIO_WKUP_6: GPIO (default) - * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 - * IRDA/PSC6: UART - * Ether: Ethernet 100Mbit with MD - * PCI_DIS: PCI controller disabled - * USB: USB - * PSC3: SPI with UART3 - * PSC2: UART - * PSC1: UART - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_ALT_MEMTEST 1 -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Flat Device Tree support - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 1e63098..7b5ca0d 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,6 @@ #ifndef __CONFIG_CM_T43_H #define __CONFIG_CM_T43_H -#define CONFIG_AM43XX #define CONFIG_CM_T43 #define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ @@ -21,7 +20,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#ifdef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_REG_SIZE (-4) #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f46f466..b7199bb 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -330,4 +330,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) #endif /* CONFIG_DIRECT_NOR_BOOT */ + +#include + #endif /* __CONFIG_H */ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h deleted file mode 100644 index 6710507..0000000 --- a/include/configs/digsy_mtc.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005-2007 - * Modified for InterControl digsyMTC MPC5200 board by - * Frank Bodammer, GCD Hard- & Software GmbH, - * frank.bodammer@gcd-solutions.de - * - * (C) Copyright 2009 Semihalf - * Optimized for digsyMTC by: Grzegorz Bernacki - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFE000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCI_BOOTDELAY 250 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_BZIP2 - -/* - * Video - */ - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define CONFIG_VIDEO_CORALP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ - -/* Coral-PA clock frequency, geo and other both 133MHz */ -#define CONFIG_SYS_MB862xx_CCF 0x00050000 -/* Video SDRAM parameters */ -#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72 -#endif - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) -#define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fw_image=digsyMPC.img\0" \ - "mtcb_start=mtc led diag orange; run mtcb_1\0" \ - "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \ - "do mtc led $x; done\0" \ - "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \ - "else run mtcb_fw; fi\0" \ - "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \ - "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \ - "mtcb_update=mtc led user1 orange;" \ - "while mtc key; do ; done; run mtcb_2;\0" \ - "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \ - "mtcb_usb1=if fatload usb 0 400000 script.img; " \ - "then run mtcb_doscript; else run mtcb_usb2; fi\0" \ - "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \ - "then run mtcb_dousb; else run mtcb_ide; fi\0" \ - "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \ - "run mtcb_wait_flickr mtcb_ds_1;\0" \ - "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \ - "source 400000; else run mtcb_error; fi\0" \ - "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \ - "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \ - "else run mtcb_error; fi\0" \ - "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \ - "run mtcb_checkfw\0" \ - "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \ - "else run mtcb_error; fi\0" \ - "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \ - "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \ - "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\ - "mtcb_uledflckr=mtc led user1 orange 11\0" \ - "mtcb_error=mtc led user1 red\0" \ - "mtcb_clear=erase ff000000 ff0fffff\0" \ - "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \ - "mtcb_success=mtc led user1 green\0" \ - "mtcb_ide=if fatload ide 0 400000 $fw_image;" \ - "then run mtcb_doide; else run mtcb_error; fi\0" \ - "mtcb_doide=mtc led user2 green 1;" \ - "run mtcb_wait_flickr mtcb_di_1;\0" \ - "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \ - "else run mtcb_error; fi\0" \ - "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \ - "ramdisk_num_sector=16\0" \ - "flash_base=ff000000\0" \ - "flashdisk_size=e00000\0" \ - "env_sector=fff60000\0" \ - "flashdisk_start=ff100000\0" \ - "load_cmd=tftp 400000 digsyMPC.img\0" \ - "clear_cmd=erase ff000000 ff0fffff\0" \ - "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \ - "update_cmd=run load_cmd; " \ - "iminfo 400000; " \ - "run clear_cmd flash_cmd; " \ - "iminfo ff000000\0" \ - "spi_driver=yes\0" \ - "spi_watchdog=no\0" \ - "ftps_start=yes\0" \ - "ftps_user1=admin\0" \ - "ftps_pass1=admin\0" \ - "ftps_base1=/\0" \ - "ftps_home1=/\0" \ - "plc_sio_srv=no\0" \ - "plc_sio_baud=57600\0" \ - "plc_sio_parity=no\0" \ - "plc_sio_stop=1\0" \ - "plc_sio_com=2\0" \ - "plc_eth_srv=yes\0" \ - "plc_eth_port=1200\0" \ - "plc_root=/ide/\0" \ - "diag_level=0\0" \ - "webvisu=no\0" \ - "plc_can1_routing=no\0" \ - "plc_can1_baudrate=250\0" \ - "plc_can2_routing=no\0" \ - "plc_can2_baudrate=250\0" \ - "plc_can3_routing=no\0" \ - "plc_can3_baudrate=250\0" \ - "plc_can4_routing=no\0" \ - "plc_can4_baudrate=250\0" \ - "netdev=eth0\0" \ - "console=ttyPSC0\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdt_file};" \ - "run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off FFF00000 +${filesize};" \ - "erase FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 +${filesize}\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run mtcb_start" - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 - -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_CS1} -#define CONFIG_SYS_UPDATE_FLASH_SIZE -#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE -#else -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) - -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if defined(CONFIG_LOWBOOT) -#define CONFIG_ENV_ADDR 0xFF060000 -#else /* CONFIG_LOWBOOT */ -#define CONFIG_ENV_ADDR 0xFFF60000 -#endif /* CONFIG_LOWBOOT */ -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#else -#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000 -#endif - -/* - * Use SRAM until RAM will be available - */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_PHY_ADDR 0x01 -#else -#define CONFIG_PHY_ADDR 0x00 -#endif -#define CONFIG_PHY_RESET_DELAY 1000 - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* - * GPIO configuration - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1) - * Bit 0 (mask 0x80000000) : 0x1 - * SPI on Tmr2/3/4/5 pins - * Bit 2:3 (mask 0x30000000) : 0x2 - * ATA cs0/1 on csb_4/5 - * Bit 6:7 (mask 0x03000000) : 0x2 - * Ethernet 100Mbit with MD - * Bits 12:15 (mask 0x000f0000): 0x5 - * USB - Two UARTs - * Bits 18:19 (mask 0x00003000) : 0x2 - * PSC3 - USB2 on PSC3 - * Bits 20:23 (mask 0x00000f00) : 0x1 - * PSC2 - CAN1&2 on PSC2 pins - * Bits 25:27 (mask 0x00000070) : 0x1 - * PSC1 - AC97 functionality - * Bits 29:31 (mask 0x00000007) : 0x2 - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CMDLINE_EDITING 1 - -#define CONFIG_MX_CYCLIC 1 - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000 -#define CONFIG_SYS_MEMTEST_START 0x00010000 -#define CONFIG_SYS_MEMTEST_END 0x019fffff - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_SDRAM_CS1 1 -#define CONFIG_SYS_XLB_PIPELINING 1 - -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 -#endif - -#define CONFIG_SYS_CS4_START 0x60000000 -#define CONFIG_SYS_CS4_SIZE 0x1000 -#define CONFIG_SYS_CS4_CFG 0x0008FC00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_CFG 0x0002DD00 - -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1 -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_CFG 0x0002DD00 -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x11111111 - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#else -#define CONFIG_SYS_RESET_ADDRESS 0xff000100 -#endif - -/* - * USB - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#define CONFIG_USB_CLOCK 0x00013333 -#define CONFIG_USB_CONFIG 0x00002000 - -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_CPU_INIT - -/* - * IDE/ATA - */ -#define CONFIG_IDE_RESET -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_CS_ON_I2C2 -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 -#define CONFIG_LBA48 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 17608a5..d6c4a71 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -27,7 +27,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET 0x260000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif @@ -57,7 +57,7 @@ "partitions_android=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ + "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index fc0f5e6..6fc6ec9 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -270,4 +270,6 @@ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \ "bootcmd=run net_testrfs\0" +#include + #endif /* __CONFIG_H */ diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h new file mode 100644 index 0000000..2286837 --- /dev/null +++ b/include/configs/evb_px5.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_PX5_EVB_H +#define __CONFIGS_PX5_EVB_H + +#include + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h new file mode 100644 index 0000000..ff3531b --- /dev/null +++ b/include/configs/evb_rv1108.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ipaddr=172.16.12.50\0" \ + "serverip=172.16.12.69\0" \ + "" +#define CONFIG_BOOTCOMMAND \ + "sf probe;" \ + "sf read 0x62000000 0x140800 0x500000;" \ + "dcache off;" \ + "go 0x62000000" + +#endif diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h new file mode 100644 index 0000000..6f6007e --- /dev/null +++ b/include/configs/geekbox.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_GEEKBOX_H +#define __CONFIGS_GEEKBOX_H + +#include + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h deleted file mode 100644 index d651eff..0000000 --- a/include/configs/inka4x0.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_INKA4X0 1 /* INKA4x0 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFE00000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */ -#endif -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 - -/* Partitions */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_IPADDR 192.168.100.2 -#define CONFIG_SERVERIP 192.168.100.1 -#define CONFIG_NETMASK 255.255.255.0 -#define HOSTNAME inka4x0 -#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "enable_disp=mw.l 100000 04000000 1;" \ - "cp.l 100000 f0000b20 1;" \ - "cp.l 100000 f0000b28 1\0" \ - "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ - "ide_boot=ext2load ide 0:1 200000 uImage;" \ - "run ideargs addip addcons enable_disp;bootm\0" \ - "brightness=255\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run ide_boot" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xffe00000 -#define CONFIG_SYS_FLASH_SIZE 0x00200000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* - * SDRAM controller configuration - */ -#undef CONFIG_SDR_MT48LC16M16A2 -#undef CONFIG_DDR_MT46V16M16 -#undef CONFIG_DDR_MT46V32M16 -#undef CONFIG_DDR_HYB25D512160BF -#define CONFIG_DDR_K4H511638C - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM - -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) - -#ifdef CONFIG_POST -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII - -/* - * GPIO configuration - * - * use CS1 as gpio_wkup_6 output - * Bit 0 (mask: 0x80000000): 0 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, I2C1 is used for onboard EEPROM - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard - * EEPROM - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100 - * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100 - * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101 - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* 32Mbit SRAM @0x30000000 */ -#define CONFIG_SYS_CS1_START 0x30000000 -#define CONFIG_SYS_CS1_SIZE 0x00400000 -#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ - -/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CONFIG_SYS_CS2_START 0x80000000 -#define CONFIG_SYS_CS2_SIZE 0x0001000 -#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ - -/* GPIO in @0x30400000 */ -#define CONFIG_SYS_CS3_START 0x30400000 -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_CLOCK 0x00015555 -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -#define CONFIG_ATAPI 1 - -#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 127e7e7..f78aa47 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -301,4 +301,6 @@ #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) +#include + #endif /* __CONFIG_H */ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h deleted file mode 100644 index c6390db..0000000 --- a/include/configs/ipek01.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * (C) Copyright 2006 - * MicroSys GmbH - * - * (C) Copyright 2009 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC5200 -#define CONFIG_MPX5200 1 /* MPX5200 board */ -#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ -#define CONFIG_IPEK01 /* Motherboard is ipek01 */ - -#define CONFIG_SYS_TEXT_BASE 0xfc000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * Video configuration for LIME GDC - */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ -/* Lime clock frequency */ -#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */ -/* SDRAM parameter */ -#define CONFIG_SYS_MB862xx_MMR 0x41c767e3 -#endif - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI /* pciinfo */ - -#define CONFIG_SYS_LOWBOOT 1 - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyPSC0\0" \ - "hostname=ipek01\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consoledev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdtaddr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ - "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=ipek01/uImage\0" \ - "load=tftp 100000 ipek01/u-boot.bin\0" \ - "update=protect off FC000000 +60000; era FC000000 +60000; " \ - "cp.b 100000 FC000000 ${filesize}\0" \ - "upd=run load;run update\0" \ - "fdtaddr=800000\0" \ - "loadaddr=400000\0" \ - "fdtfile=ipek01/ipek01.dtb\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */ -/* PCI clock must be 33, because board will not boot */ -#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */ - -/* - * Open firmware flat tree support - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) - -#define CONFIG_SYS_FLASH_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/* use CFI flash driver */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_SRAM_BASE 0xF1000000 -#define CONFIG_SYS_SRAM_SIZE 0x00200000 -#define CONFIG_SYS_LIME_BASE 0xE4000000 -#define CONFIG_SYS_LIME_SIZE 0x04000000 -#define CONFIG_SYS_FPGA_BASE 0xC0000000 -#define CONFIG_SYS_FPGA_SIZE 0x10000000 -#define CONFIG_SYS_MPEG_BASE 0xe2000000 -#define CONFIG_SYS_MPEG_SIZE 0x01000000 -#define CONFIG_SYS_CF_BASE 0xe1000000 -#define CONFIG_SYS_CF_SIZE 0x01000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -/* End of used area in DPRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE -#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE -#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE -#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE -#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE -#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE -#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE - -#ifdef CONFIG_SYS_PCISPEED_66 -#define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0004FB00 -#define CONFIG_SYS_CS2_CFG 0x0006F900 -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0002F900 -#define CONFIG_SYS_CS1_CFG 0x0001FB00 -#define CONFIG_SYS_CS2_CFG 0x0002F90C -#endif - -/* - * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0 - * waitstates, writeswap and readswap enabled - */ -#define CONFIG_SYS_CS3_CFG 0x00FFFB0C -#define CONFIG_SYS_CS6_CFG 0x00FFFB0C -#define CONFIG_SYS_CS7_CFG 0x4040751C - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33330000 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h deleted file mode 100644 index 4461623..0000000 --- a/include/configs/jupiter.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_JUPITER 1 /* ... on Jupiter board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_SYS_XLB_PIPELINING 1 - -#define CONFIG_MII 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -/* Partitions */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ - -#if defined(CONFIG_PCI) -#define CODFIG_CMD_PCI -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "addcons=setenv bootargs ${bootargs} console=${contyp}," \ - "${baudrate}\0" \ - "contyp=ttyS0\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/jupiter/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ - -#if 0 -/* pass open firmware flat tree */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 - -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_UPDATE_FLASH_SIZE 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST 1 - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h deleted file mode 100644 index 09c3aa9..0000000 --- a/include/configs/km82xx.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2007-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8247 -/* MGCOGE */ -#if defined(CONFIG_MGCOGE) -#define CONFIG_HOSTNAME mgcoge -#define CONFIG_KM_BOARD_EXTRA_ENV "" - -/* MGCOGE3NE */ -#elif defined(CONFIG_MGCOGE3NE) -#define CONFIG_HOSTNAME mgcoge3ne -#define CONFIG_KM_82XX -#define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0" - -#else -#error ("Board unsupported") -#endif - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_MISC_INIT_R - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 32 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -/* MGCOGE */ -#if defined(CONFIG_MGCOGE) -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -/* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 32 -#define CONFIG_SYS_FLASH_BASE_2 0x52000000 -#define CONFIG_SYS_FLASH_SIZE_2 32 - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1, \ - CONFIG_SYS_FLASH_BASE_2 } -#define MTDIDS_DEFAULT "nor3=app" - -/* - * Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - -/* SDRAM initialization values -*/ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ - ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR ( \ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* MGCOGE3NE */ -#elif defined(CONFIG_MGCOGE3NE) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* - * max num of sects on one - * chip - */ - -#define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 128 - -#define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1 } - -#define MTDIDS_DEFAULT "nor2=app" - -/* - * Bank 1 - 60x bus SDRAM - * mgcoge3ne has 256MB - * mgcoge2ne has 128MB - */ -#define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ - ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_NUMR_13 |\ - ORxS_IBID) - -#define CONFIG_SYS_PSDMR ( \ - PSDMR_PBI |\ - PSDMR_RFEN |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_SDRAM_LIST { \ - { .size = 256 << 20, \ - .or1 = ORxS_ROWST_PBI1_A4, \ - .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \ - }, \ - { .size = 128 << 20, \ - .or1 = ORxS_ROWST_PBI1_A5, \ - .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \ - }, \ -} -#endif /* defined(CONFIG_MGCOGE3NE) */ - -/* include further common stuff for all keymile 82xx boards */ -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ -#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#define CONFIG_ETHER_INDEX 4 -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 - -#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define BOOTFLASH_START 0xFE000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" - -#define MTDPARTS_DEFAULT "mtdparts=" \ - "app:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "3072k(free)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")" - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_BOARD_EXTRA_ENV \ - CONFIG_KM_DEF_ENV \ - "unlock=yes\0" \ - "newenv=" \ - "prot off 0xFE0C0000 +0x40000 && " \ - "era 0xFE0C0000 +0x40000\0" \ - "arch=ppc_82xx\0" \ - "" - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_NUM_I2C_BUSES 3 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \ - {0, {{I2C_MUX_PCA9542, 0x70, 1} } } } - -#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -#define CONFIG_KM_I2C_ABORT - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) do { \ - if (bit) \ - iop->pdat |= 0x00010000; \ - else \ - iop->pdat &= ~0x00010000; \ - } while (0) -#define I2C_SCL(bit) do { \ - if (bit) \ - iop->pdat |= 0x00020000; \ - else \ - iop->pdat &= ~0x00020000; \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#ifndef __ASSEMBLY__ -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0604b211 - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x4020c200 -#define CONFIG_SYS_SYPCR 0xFFFFFF83 -#define CONFIG_SYS_BCR 0x10000000 -#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) - -/* - *----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/* - *----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/* - *----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/* - *----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit FLASH - * 1 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit GPIO/PIGGY - * 5 60x GPCM 16 bit CFG-Flash - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -#define CONFIG_SYS_MPTPR 0x1800 - -/* - *----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x0e - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 - -/* - * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values - */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX) - -/* - * BFTICU board FPGA on CS4 initialization values - */ -#define CONFIG_SYS_FPGA_BASE 0x40000000 -#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX) - -/* - * CFG-Flash on CS5 initialization values - */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ - CONFIG_SYS_FLASH_SIZE_2) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK | ORxG_TRLX) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" - -#endif /* __CONFIG_H */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f230f40..15da407 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -214,4 +214,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 +#include + #endif /* __CONFIG_H */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index bd9b0d3..42bbc02 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -121,4 +121,6 @@ #define CONFIG_PANIC_HANG #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include + #endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 7fd3464..32f7162 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -300,4 +300,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include + #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b66b8ac..1b91676 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -237,4 +237,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include + #endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e311d0b..dbca05a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -250,4 +250,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include + #endif /* __LS2_COMMON_H */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h deleted file mode 100644 index 68874dc..0000000 --- a/include/configs/manroland/mpc5200-common.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MANROLAND_MPC52XX__COMMON_H -#define __MANROLAND_MPC52XX__COMMON_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* MPC5200 CPU */ - -/* ... running at 33.000000MHz */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ - 230400 } - -#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" -#define CONFIG_OF_IDE_FIXUP - -#endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h deleted file mode 100644 index 17a97df..0000000 --- a/include/configs/mecp5123.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk - * (C) Copyright 2009, DAVE Srl - * - * SPDX-License-Identifier: GPL-2.0+ - * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com - * - */ - -/* - * MECP5123 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MECP5123 1 - -/* - * Memory map for the MECP5123 board: - * - * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) - * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) - * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) - * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB) - * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ - -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 - -/* DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDRCMD_EM2 0x01020000 -#define CONFIG_SYS_DDRCMD_EM3 0x01030000 -#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ - -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND FLASH - * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) - */ -#define CONFIG_CMD_NAND -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS 1 - -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -/* Initialize Local Window for NOR FLASH access */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* ALE active low, data size 4bytes */ -#define CONFIG_SYS_CS0_CFG 0x05051150 - -/* Use not alternative CS timing */ -#define CONFIG_SYS_CS_ALETIMING 0x00000000 - -/* ALE active low, data size 4bytes */ -#define CONFIG_SYS_CS1_CFG 0x1f1f3090 -#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ -#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ -/* Initialize Local Window for VPC3 access */ -#define CONFIG_SYS_CS1_START CONFIG_SYS_VPC3_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_VPC3_SIZE - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */ -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_I2C_EN) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Configure on-board RTC - */ -#define CONFIG_SYS_RTC_BUS_NUM 0x01 -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#define CONFIG_RTC_RX8025 - -/* - * Environment - */ -#define CONFIG_ENV_IS_NOWHERE /* Store env in I2C EEPROM */ -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -#define CONFIG_CMD_REGINFO - -/* - * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. - * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set - * to 0xFFFF, watchdog timeouts after about 64s. For details refer - * to chapter 36 of the MPC5121e Reference Manual. - */ -/* #define CONFIG_WATCHDOG */ /* enable watchdog */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - - /* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Linux initial memory map */ - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME mecp512x -#define CONFIG_BOOTFILE "/tftpboot/mecp512x/uImage" -#define CONFIG_ROOTPATH "/tftpboot/mecp512x/target_root" - -#define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */ - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to MECP5123" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=880000\0" \ - "ramdisk_addr_r=900000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFC40000\0" \ - "fdt_addr=FFEC0000\0" \ - "ramdisk_addr=FC040000\0" \ - "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \ - "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \ - "bootfile=/tftpboot/mecp512x/uImage\0" \ - "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \ - "rootpath=/tftpboot/mecp512x/target_root\n" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -#endif /* __CONFIG_H */ diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index 12a4dfc..89e3807 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -40,6 +40,7 @@ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ + func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h deleted file mode 100644 index 75633f6..0000000 --- a/include/configs/motionpro.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -/* CPU and board */ -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_NETCONSOLE 1 /* network console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x2 -#define CONFIG_PHY_TYPE 0x79c874 -#define CONFIG_RESET_PHY_R 1 - -/* - * Autobooting - */ -#undef CONFIG_BOOTARGS - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=motionpro\0" \ - "netmask=255.255.255.0\0" \ - "ipaddr=192.168.1.106\0" \ - "serverip=192.168.1.100\0" \ - "gatewayip=192.168.1.100\0" \ - "console=ttyPSC0,115200\0" \ - "u-boot_addr=400000\0" \ - "kernel_addr=400000\0" \ - "fdt_addr=700000\0" \ - "ramdisk_addr=800000\0" \ - "multi_image_addr=800000\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ - "bootfile=/tftpboot/motionpro/uImage\0" \ - "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ - "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ - "multi_image_file=kernel+initrd+dtb.img\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fff00000 +${filesize};" \ - "era fff00000 +${filesize}; " \ - "cp.b ${u-boot_addr} fff00000 ${filesize};" \ - "prot on fff00000 +${filesize}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "fat_args=setenv bootargs root=/dev/sda rw\0" \ - "mtdids=nor0=ff000000.flash\0" \ - "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \ - "128k(env),128k(redund_env)," \ - "128k(dtb),128k(user_data)\0" \ - "addcons=setenv bootargs ${bootargs} console=${console}\0" \ - "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1 " \ - "console=${console}\0" \ - "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; " \ - "run nfsargs addip addmtd; " \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_self=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \ - "run ramargs addip addcons addmtd; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \ - "${multi_image_addr} ${multi_image_file}; " \ - "bootm ${multi_image_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run fat_multi" - -/* - * do board-specific init - */ -#define CONFIG_BOARD_EARLY_INIT_R 1 - -/* - * Low level configuration - */ - -/* - * Clock configuration: SYS_XTALIN = 33MHz - */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -/* - * Set IPB speed to 100MHz - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK - -/* - * Memory map - */ -/* - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. - * Setting MBAR to otherwise will cause system hang when using SmartDMA such - * as network commands. - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * If building for running out of SDRAM, then MBAR has been set up beforehand - * (e.g., by the BDI). Otherwise we must specify the default boot-up value of - * MBAR, as given in the doccumentation. - */ -#if CONFIG_SYS_TEXT_BASE == 0x00100000 -#define CONFIG_SYS_DEFAULT_MBAR 0xf0000000 -#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */ -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_LOWBOOT 1 -#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */ - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00045D00 - -/* Flash memory addressing */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_CFG CONFIG_SYS_BOOTCS_CFG - -/* Dual Port SRAM -- Kollmorgen Drive memory addressing */ -#define CONFIG_SYS_CS1_START 0x50000000 -#define CONFIG_SYS_CS1_SIZE 0x10000 -#define CONFIG_SYS_CS1_CFG 0x05055800 - -/* Local register access */ -#define CONFIG_SYS_CS2_START 0x50010000 -#define CONFIG_SYS_CS2_SIZE 0x10000 -#define CONFIG_SYS_CS2_CFG 0x05055800 - -/* Anybus CompactCom Module memory addressing */ -#define CONFIG_SYS_CS3_START 0x50020000 -#define CONFIG_SYS_CS3_SIZE 0x10000 -#define CONFIG_SYS_CS3_CFG 0x05055800 - -/* No burst and dead cycle = 2 for all CSs */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x22222222 - -/* - * SDRAM configuration - */ -/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ -#define SDRAM_CONFIG1 0x62322900 -#define SDRAM_CONFIG2 0x88c70000 -#define SDRAM_CONTROL 0x504f0000 -#define SDRAM_MODE 0x00cd0000 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ - -/* - * MTD configuration - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=motionpro-0" -#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ - "13m(fs),2m(kernel),384k(uboot)," \ - "128k(env),128k(redund_env)," \ - "128k(dtb),-(user_data)" - -/* - * IDE/ATA configuration - */ -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 -#define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET -#define CONFIG_SYS_ATA_STRIDE 4 - -/* - * RTC configuration - */ -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Status LED configuration - */ - -#define ENABLE_GPIO_OUT 0x00000024 -#define LED_ON 0x00000010 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* Configuration of redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Pin multiplexing configuration - */ - -/* PSC1: UART1 - * PSC2: GPIO (default) - * PSC3: GPIO (default) - * USB: 2xUART4/5 - * Ethernet: Ethernet 100Mbit with MD - * Timer: CAN2/GPIO - * PSC6/IRDA: GPIO (default) - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004 - -/* - * Motion-PRO's CPLD revision control register - */ -#define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ - -/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h deleted file mode 100644 index d252297..0000000 --- a/include/configs/mpc5121-common.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2010 DENX Software Engineering - * Anatolij Gustschin - * - * Common configuration options for MPC5121 based boards - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MPC5121_COMMON_H -#define __MPC5121_COMMON_H - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM base */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of area */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Serial console - */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_CMDLINE_EDITING 1 /* command line history */ - -#endif /* __MPC5121_COMMON_H */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h deleted file mode 100644 index e11a0e6..0000000 --- a/include/configs/mpc5121ads.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC5121ADS board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC5121ADS 1 - -/* - * Memory map for the MPC5121ADS board: - * - * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) - * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) - * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) - * 0x8200_0000 - 0x8200_001F CPLD (32 B) - * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) - * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) - * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) - * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* video */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#endif - -/* CONFIG_PCI is defined at config time */ - -#ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ -#endif - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#else -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ -#endif -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 - -/* DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 -#else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#endif -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E - -#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 -#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 -#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDRCMD_EM2 0x01020000 -#define CONFIG_SYS_DDRCMD_EM3 0x01030000 -#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 - -#define DDRCMD_EMR_OCD(pr, ohm) ( \ - (1 << 24) | /* MDDRC Command Request */ \ - (1 << 16) | /* MODE Reg BA[2:0] */ \ - (0 << 12) | /* Outputs 0=Enabled */ \ - (0 << 11) | /* RDQS */ \ - (1 << 10) | /* DQS# */ \ - (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ - /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ - ((ohm & 0x2) << 5)| /* Rtt1 */ \ - (0 << 3) | /* additive posted CAS# */ \ - ((ohm & 0x1) << 2)| /* Rtt0 */ \ - (0 << 0) | /* Output Drive Strength */ \ - (0 << 0)) /* DLL Enable 0=Normal */ - -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) -#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) - -#define DDRCMD_MODE_REG(cas, wr) ( \ - (1 << 24) | /* MDDRC Command Request */ \ - (0 << 16) | /* MODE Reg BA[2:0] */ \ - ((wr-1) << 9)| /* Write Recovery */ \ - (cas << 4) | /* CAS */ \ - (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ - (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ - -#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) -#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) -#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#undef CONFIG_BKUP_FLASH -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#ifdef CONFIG_BKUP_FLASH -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ -#else -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ -#endif -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND FLASH - * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) - */ -#define CONFIG_CMD_NAND /* enable NAND support */ -#define CONFIG_JFFS2_NAND /* with JFFS2 on it */ -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 - -#define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE - -/* - * CPLD registers area is really only 32 bytes in size, but the smallest possible LP - * window is 64KB - */ -#define CONFIG_SYS_CPLD_BASE 0x82000000 -#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ -#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE -#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE - -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ -#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ -#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN | \ - CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_USB1_EN | \ - CLOCK_SCCR2_USB2_EN) - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -/* - * General PCI - */ -#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0x84000000 -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * USB Support - */ - -#if defined(CONFIG_CMD_USB) -#define CONFIG_USB_EHCI_FSL /* On a FSL platform */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_IS_TDI -#endif - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 -#ifdef CONFIG_BKUP_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ -#else -#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" - -/* - * NOR flash layout: - * - * FC000000 - FEABFFFF 42.75 MiB User Data - * FEAC0000 - FFABFFFF 16 MiB Root File System - * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel - * FFEC0000 - FFEFFFFF 256 KiB Device Tree - * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env - * - * NAND flash layout: one big partition - */ -#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ - "16m(rootfs)," \ - "4m(kernel)," \ - "256k(dtb)," \ - "1m(u-boot);" \ - "mpc5121.nand:-(data)" - -#if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) -#define CONFIG_SUPPORT_VFAT - -#endif /* defined(CONFIG_IDE) */ - -/* - * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. - * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set - * to 0xFFFF, watchdog timeouts after about 64s. For details refer - * to chapter 36 of the MPC5121e Reference Manual. - */ -/* #define CONFIG_WATCHDOG */ /* enable watchdog */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - - /* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME mpc5121ads -#define CONFIG_BOOTFILE "mpc5121ads/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=880000\0" \ - "ramdisk_addr_r=900000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFAC0000\0" \ - "fdt_addr=FFEC0000\0" \ - "ramdisk_addr=FEAC0000\0" \ - "ramdiskfile=mpc5121ads/uRamdisk\0" \ - "u-boot=mpc5121ads/u-boot.bin\0" \ - "bootfile=mpc5121ads/uImage\0" \ - "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ - "rootpath=/opt/eldk/ppc_6xx\n" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for IDE not supported */ - -#define CONFIG_IDE_RESET /* reset for IDE supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() - -/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define ATA_BASE_ADDR get_pata_base() - -/* - * Control register bit definitions - */ -#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 -#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 -#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 -#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 -#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 -#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 -#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 -#define FSL_ATA_CTRL_IORDY_EN 0x01000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/munices.h b/include/configs/munices.h deleted file mode 100644 index ad2d69e..0000000 --- a/include/configs/munices.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ -#define CONFIG_MUNICES 1 /* ... on MUNICes board */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ -#undef CONFIG_BOOTARGS - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=5\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/munices/u-boot.bin\0" \ - "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ - "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CONFIG_SYS_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */ -#else -#undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */ -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ - -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x01 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD - no PCI */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_CMDLINE_EDITING 1 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#define OF_CPU "PowerPC,5200@0" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_SOC "soc5200@f0000000" -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/o2d.h b/include/configs/o2d.h deleted file mode 100644 index 4b36af6..0000000 --- a/include/configs/o2d.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* - * GPIO configuration: - * CS1 SDRAM activate + no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2d" -#define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT __stringify(126) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=fc060000\0" \ - "lintop=fc15ffff\0" \ - "rambot=fc160000\0" \ - "ramtop=fc55ffff\0" \ - "jffbot=fc560000\0" \ - "jfftop=fcffffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "progCram=tftp ${fileaddr} ${cramfsname};" \ - "erase ${rambot} ${ramtop};" \ - "cp.b ${fileaddr} ${rambot} ${filesize}\0" \ - "flash_for_configs=22396\0" \ - "flash_mtd=run mtd_args addip addmem;" \ - "bootm ${kernel_addr}\0" \ - "mtd_args=setenv bootargs root=/dev/mtdblock3 " \ - "rw rootfstype=cramfs\0" \ - "master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" \ - "dhcp_boot=run dhcpcmd;run flash_mtd\0" \ - "hostname=IFM_SENSOR\0" \ - "netretry=once\0" \ - "autoload=no\0" \ - "sensorType=O2D222AG\0" diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h deleted file mode 100644 index a8222d9..0000000 --- a/include/configs/o2d300.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* - * GPIO configuration: - * CS1 SDRAM activate + no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */ - -/* Use redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_BOARD_NAME "o2d300" -#define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT __stringify(126) -#define BOARD_POST_CRC32_END __stringify(0x02000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "autoload=no\0" \ - "dhcp_boot=run dhcpcmd;run flash_mtd\0" \ - "flash_mtd=run mtd_args addip addmem;" \ - "bootm ${kernel_addr}\0" \ - "mtd_args=setenv bootargs root=/dev/mtdblock4 " \ - "rw rootfstype=cramfs\0" \ - "linbot=fc080000\0" \ - "lintop=fc17ffff\0" \ - "rambot=fc180000\0" \ - "ramtop=fc57ffff\0" \ - "jffbot=fc580000\0" \ - "jfftop=fd39ffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0" \ - "halbot=fd3a0000\0" \ - "haltop=fdf9ffff\0" \ - "progHal=tftp 200000 ${halname};erase ${halbot} ${haltop};" \ - "cp.b ${fileaddr} ${halbot} ${filesize}\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" \ - "netretry=once\0" \ - "protcmd=protect on ${linbot} ${lintop};" \ - "protect on ${rambot} ${ramtop}\0" \ - "o2derror=def_env\0" \ - "sensorType=O2D300AA\0" diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h deleted file mode 100644 index 1b4200b..0000000 --- a/include/configs/o2dnt-common.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Common configuration options for ifm camera boards - * - * (C) Copyright 2005 - * Sebastien Cazaux, ifm electronic gmbh - * - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __O2D_CONFIG_H -#define __O2D_CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5200 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -/* log base 2 of the above value */ -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -/* -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_I2C) -*/ - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 - -/* Partitions */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */ - -/* - * Supported commands - */ -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000) -/* Boot low with 16 or 32 MB Flash */ -#define CONFIG_SYS_LOWBOOT 1 -#elif (CONFIG_SYS_TEXT_BASE != 0x00100000) -#error "CONFIG_SYS_TEXT_BASE value is invalid" -#endif - - -#define CONFIG_PREBOOT "run master" - -#undef CONFIG_BOOTARGS - -#if !defined(CONSOLE_DEV) -#define CONSOLE_DEV "ttyPSC1" -#endif - -/* - * Default environment for booting old and new kernel versions - */ -#define CONFIG_IFM_DEFAULT_ENV_OLD \ - "flash_self_old=run ramargs addip addmem;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs_old=run nfsargs addip addmem;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addmem;" \ - "bootm ${kernel_addr_r}\0" - -#define CONFIG_IFM_DEFAULT_ENV_NEW \ - "fdt_addr_r=900000\0" \ - "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - "IOpin=0x64\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addmem=setenv bootargs ${bootargs} ${memlimit}\0" \ - "addmisc=sete bootargs ${bootargs} ${miscargs}\0" \ - "addtty=sete bootargs ${bootargs} console=" \ - CONSOLE_DEV ",${baudrate}\0" \ - "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \ - "kernel_addr_r=600000\0" \ - "initrd_high=0x03e00000\0" \ - "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \ - "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\ - "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \ - "cp.b ${fileaddr} ${linbot} ${filesize}\0" \ - "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\ - "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \ - "cp.b ${fileaddr} ${rambot} ${filesize}\0" \ - "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \ - "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \ - "cp.b ${fileaddr} ${jffbot} ${filesize}\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "uboname=" CONFIG_BOARD_NAME \ - "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \ - "progubo=tftp 200000 ${uboname};" \ - "protect off ${ubobot} ${ubotop};" \ - "erase ${ubobot} ${ubotop};" \ - "cp.b ${fileaddr} ${ubobot} ${filesize}\0" \ - "unlock=yes\0" \ - "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \ - "setenv bootdelay 1;" \ - "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \ - BOARD_POST_CRC32_END";" \ - "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0" - -#define CONFIG_BOOTCOMMAND "run post" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * There is no write delay with FRAM, write operations are performed at bus - * speed. Thus, no status polling or write delay is needed. - */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */ -/* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 -/* "Real" (hardware) sectors protection */ -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -/* End of used area in DPRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_RESET_PHY_R - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */ -#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */ -#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */ -#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -/* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/* - * DT support - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) - -#endif /* __O2D_CONFIG_H */ diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h deleted file mode 100644 index 00a8d96..0000000 --- a/include/configs/o2dnt2.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* - * GPIO configuration: - * CS1 SDRAM activate + no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2dnt2" -#define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT __stringify(126) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=fc060000\0" \ - "lintop=fc15ffff\0" \ - "rambot=fc160000\0" \ - "ramtop=fc55ffff\0" \ - "jffbot=fc560000\0" \ - "jfftop=fce5ffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ - "calbot=fce60000\0" \ - "caltop=fcffffff\0" \ - "progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};" \ - "cp.b ${fileaddr} ${calbot} ${filesize}\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" diff --git a/include/configs/o2i.h b/include/configs/o2i.h deleted file mode 100644 index c0fceda..0000000 --- a/include/configs/o2i.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFF000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xff000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* maximum 16MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* GPIO configuration */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */ - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00087801 -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2i" -#define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT __stringify(62) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=ff060000\0" \ - "lintop=ff15ffff\0" \ - "rambot=ff160000\0" \ - "ramtop=ff55ffff\0" \ - "jffbot=ff560000\0" \ - "jfftop=ffebffff\0" \ - "kernel_addr=0xff060000\0" \ - "ramdisk_addr=0xff160000\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=ff03ffff\0" \ - "autoload=no\0" \ - "dhcp_boot=run dhcpcmd; run flash_mtd\0" \ - "hostname=IFM_SENSOR\0" \ - "flash_mtd=run mtd_args addip addmem;bootm ${kernel_addr}\0" \ - "mtd_args=setenv bootargs root=/dev/mtdblock3 " \ - "rw rootfstype=cramfs\0" \ - "sensorType=O2I100AA\0" \ - "netretry=once\0" \ - "master=mw f0000b00 0x00052006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h deleted file mode 100644 index eb63cb0..0000000 --- a/include/configs/o2mnt.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFF000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xff000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* maximum 16MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* GPIO configuration */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002004 /* no CAN */ - -/* Other board specific configs */ -#define CONFIG_NETCONSOLE - -#define CONFIG_SYS_BOOTCS_CFG 0x00087801 -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2mnt" -#define CONFIG_BOARD_BOOTCMD "${newcmd}" -#define CONFIG_BOARD_MEM_LIMIT __stringify(62) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#ifndef CONFIG_IFM_SENSOR_TYPE -#define CONFIG_IFM_SENSOR_TYPE "O2M110" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=ff060000\0" \ - "lintop=ff25ffff\0" \ - "rambot=ff260000\0" \ - "ramtop=ffc5ffff\0" \ - "jffbot=ffc60000\0" \ - "jfftop=ffffffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=ff03ffff\0" \ - "kernel_addr=0xff060000\0" \ - "ramdisk_addr=0xff260000\0" \ - "newcmd=run scrprot;run flash_ext2\0" \ - "scrprot=protect on ${linbot} ${lintop};protect on ${rambot} " \ - "${ramtop}\0" \ - "flash_ext2=run ext2args addip addmem;bootm ${kernel_addr}\0" \ - "ext2args=setenv bootargs root=/dev/mtdblock3 ro " \ - "rootfstype=ext2\0" \ - "pwm=mw f0000674 0x10006;mw f0000678 0x30000;" \ - "mw f0000678 0x30001;mw f0000670 0x3\0" \ - "master=mw f0000b00 0x00052006;mw f0000b0c $(IOpin);" \ - "mw f0000b04 $(IOpin);mw f0000b10 0x24;run pwm\0" \ - "sensortyp="CONFIG_IFM_SENSOR_TYPE"\0" \ - "srelease=0.00\0" diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h deleted file mode 100644 index f0fceda..0000000 --- a/include/configs/o3dnt.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* Additional commands */ -#define CONFIG_CMD_REGINFO - -/* - * GPIO configuration: - * no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0000A000 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o3dnt" -#define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT __stringify(62) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=fc060000\0" \ - "lintop=fc15ffff\0" \ - "rambot=fc160000\0" \ - "ramtop=fc55ffff\0" \ - "jffbot=fc560000\0" \ - "jfftop=fce5ffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ - "calbot=fce60000\0" \ - "caltop=fcffffff\0" \ - "progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};" \ - "cp.b ${fileaddr} ${calbot} ${filesize}\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "master=mw f0000b00 0x0005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d8b0c02..e7fac6d 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,7 +37,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET 0x260000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 8904cd5..5f11895 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -110,7 +110,7 @@ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT)) @@ -341,4 +341,7 @@ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) + +#include + #endif /* __CONFIG_H */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h deleted file mode 100644 index 6da17be..0000000 --- a/include/configs/pcm030.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messatechnik GmbH - * - * (C) Copyright 2009 - * Jon Smirl - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" - -/*----------------------------------------------------------------------------- -High Level Configuration Options -(easy to change) ------------------------------------------------------------------------------*/ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ -#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ - /* FEC configuration and IDE */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFF000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ - -/*----------------------------------------------------------------------------- -Serial console configuration ------------------------------------------------------------------------------*/ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ - /*define gps port conf. */ - /* register later on to */ - /*enable UART function! */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */ -#define CONFIG_SYS_LOWBOOT 1 -#endif -/* RAMBOOT will be defined automatically in memory section */ - -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ - "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" - -#undef CONFIG_BOOTARGS - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\ - "mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uimage=uImage-pcm030\0" \ - "oftree=oftree-pcm030.dtb\0" \ - "jffs2=root-pcm030.jffs2\0" \ - "uboot=u-boot-pcm030.bin\0" \ - "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ - " $(mtdparts) rw\0" \ - "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ - " rootfstype=jffs2\0" \ - "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ - " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ - "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ - " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ - "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ - "0xfff40000\0" \ - " cp.b 0x400000 0xff040000 $(filesize)\0" \ - "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ - "cp.b 0x400000 0xff200000 $(filesize)\0" \ - "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ - " cp.b 0x400000 0xfff40000 $(filesize)\0" \ - "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ - " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ - "unlock=yes\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run bcmd_flash" - -/*-------------------------------------------------------------------------- -IPB Bus clocking configuration. - ---------------------------------------------------------------------------*/ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/*------------------------------------------------------------------------- - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - * -----------------------------------------------------------------------*/ -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#define CONFIG_SYS_XLB_PIPELINING 1 - -/*--------------------------------------------------------------------------- - Flash configuration ----------------------------------------------------------------------------*/ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ - /* (= chip selects) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Use also hardware protection. This seems required, as the BDI uses - * hardware protection. Without this, U-Boot can't work with this sectors, - * as its protection is software only by default - */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/*--------------------------------------------------------------------------- - Environment settings ----------------------------------------------------------------------------*/ - -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ - /*beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 2048 - -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------------- - Memory map ------------------------------------------------------------------------------*/ -#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ - /* bootloader or debugger config */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */ - /* area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------------- - Ethernet configuration ------------------------------------------------------------------------------*/ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x01 - -/*--------------------------------------------------------------------------- - GPIO configuration - ---------------------------------------------------------------------------*/ - -/* GPIO port configuration - * - * Pin mapping: - * - * [29:31] = 01x - * PSC1_0 -> AC97 SDATA out - * PSC1_1 -> AC97 SDTA in - * PSC1_2 -> AC97 SYNC out - * PSC1_3 -> AC97 bitclock out - * PSC1_4 -> AC97 reset out - * - * [25:27] = 001 - * PSC2_0 -> CAN 1 Tx out - * PSC2_1 -> CAN 1 Rx in - * PSC2_2 -> CAN 2 Tx out - * PSC2_3 -> CAN 2 Rx in - * PSC2_4 -> GPIO (claimed for ATA reset, active low) - * - * - * [20:23] = 1100 - * PSC3_0 -> UART Tx out - * PSC3_1 -> UART Rx in - * PSC3_2 -> UART RTS (in/out FIXME) - * PSC3_3 -> UART CTS (in/out FIXME) - * PSC3_4 -> LocalPlus Bus CS6 \ - * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] - * PSC3_6 -> dedicated SPI MOSI out (master case) - * PSC3_7 -> dedicated SPI MISO in (master case) - * PSC3_8 -> dedicated SPI SS out (master case) - * PSC3_9 -> dedicated SPI CLK out (master case) - * - * [18:19] = 01 - * USB_0 -> USB OE out - * USB_1 -> USB Tx- out - * USB_2 -> USB Tx+ out - * USB_3 -> USB RxD (in/out FIXME) - * USB_4 -> USB Rx+ in - * USB_5 -> USB Rx- in - * USB_6 -> USB PortPower out - * USB_7 -> USB speed out - * USB_8 -> USB suspend (in/out FIXME) - * USB_9 -> USB overcurrent in - * - * [17] = 0 - * USB differential mode - * - * [16] = 0 - * PCI enabled - * - * [12:15] = 0101 - * ETH_0 -> ETH Txen - * ETH_1 -> ETH TxD0 - * ETH_2 -> ETH TxD1 - * ETH_3 -> ETH TxD2 - * ETH_4 -> ETH TxD3 - * ETH_5 -> ETH Txerr - * ETH_6 -> ETH MDC - * ETH_7 -> ETH MDIO - * ETH_8 -> ETH RxDv - * ETH_9 -> ETH RxCLK - * ETH_10 -> ETH Collision - * ETH_11 -> ETH TxD - * ETH_12 -> ETH RxD0 - * ETH_13 -> ETH RxD1 - * ETH_14 -> ETH RxD2 - * ETH_15 -> ETH RxD3 - * ETH_16 -> ETH Rxerr - * ETH_17 -> ETH CRS - * - * [9:11] = 101 - * PSC6_0 -> UART RxD in - * PSC6_1 -> UART CTS (in/out FIXME) - * PSC6_2 -> UART TxD out - * PSC6_3 -> UART RTS (in/out FIXME) - * - * [2:3/6:7] = 00/11 - * TMR_0 -> ATA_CS0 out - * TMR_1 -> ATA_CS1 out - * TMR_2 -> GPIO - * TMR_3 -> GPIO - * TMR_4 -> GPIO - * TMR_5 -> GPIO - * TMR_6 -> GPIO - * TMR_7 -> GPIO - * I2C_0 -> I2C 1 Clock out - * I2C_1 -> I2C 1 IO in/out - * I2C_2 -> I2C 2 Clock out - * I2C_3 -> I2C 2 IO in/out - * - * [4] = 1 - * PSC3_5 is used as CS7 - * - * [5] = 1 - * PSC3_4 is used as CS6 - * - * [1] = 0 - * gpio_wkup_7 is GPIO - * - * [0] = 0 - * gpio_wkup_6 is GPIO - * - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 - -/*----------------------------------------------------------------------------- - Miscellaneous configurable options --------------------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -/*----------------------------------------------------------------------------- - Various low-level settings ------------------------------------------------------------------------------*/ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -/* no burst access on the LPB */ -#define CONFIG_SYS_CS_BURST 0x00000000 -/* one deadcycle for the 33MHz statemachine */ -#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 -/* one additional waitstate for the 33MHz statemachine */ -#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*--------------------------------------------------------------------------- - IDE/ATA stuff Supports IDE harddisk -----------------------------------------------------------------------------*/ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_SYS_ATA_CS_ON_TIMER01 -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CONFIG_IDE_PREINIT -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 -#define CONFIG_ATAPI 1 - -/* USB */ -#define CONFIG_USB_OHCI - -/* pass open firmware flat tree */ -#define OF_CPU "PowerPC,5200@0" -#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN -#define OF_SOC "soc5200@f0000000" -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" - -#endif /* __CONFIG_H */ diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h deleted file mode 100644 index 676d55f..0000000 --- a/include/configs/pdm360ng.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * (C) Copyright 2009-2010 - * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * pdm360ng board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PDM360NG 1 - -/* - * Memory map for the PDM360NG board: - * - * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) - * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB) - * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB) - * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB) - * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) - * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB) - * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ - -#define CONFIG_SYS_TEXT_BASE 0xF0000000 - -/* Used for silent command in environment */ -#define CONFIG_SYS_DEVICE_NULLDEV - -/* Video */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_RLE8 -#endif - -#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100) - -/* - * DDR Setup - */ - -/* DDR is system memory */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000 - -/* DDR pin mux and slew rate */ -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012 - -/* Manually set all parameters as there's no SPD etc. */ -/* - * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3 - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Read Delay: 3 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Enabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 - -/* - * Alternative 1: small RAM (128 MB) configuration - */ -#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40 -#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863 - -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */ -#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */ -/* EMR with 150 ohm ODT todo: verify */ -#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040 -#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -/* EMR with 150 ohm ODT todo: verify */ -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0 -/* EMR new command with 150 ohm ODT todo: verify */ -#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440 - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */ -#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */ -/* start of FLASH-Bank1 */ -#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_FLASH_SIZE) -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE} - -#define CONFIG_SYS_SRAM_BASE 0x50000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE - -/* ALE active low, data size 4 bytes */ -#define CONFIG_SYS_CS0_CFG 0x05059350 -/* ALE active low, data size 4 bytes */ -#define CONFIG_SYS_CS1_CFG 0x05059350 - -#define CONFIG_SYS_MRAM_BASE 0x50040000 -#define CONFIG_SYS_MRAM_SIZE 0x00020000 -#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE -#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE - -/* ALE active low, data size 4 bytes */ -#define CONFIG_SYS_CS2_CFG 0x05059110 - -/* alt. CS timing for CS0, CS1, CS2 */ -#define CONFIG_SYS_CS_ALETIMING 0x00000007 - -/* - * NAND FLASH - */ -#define CONFIG_CMD_NAND /* enable NAND support */ -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE - -/* - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \ - "nand0=MPC5121 NAND" - -/* - * Flash layout - */ -#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \ - "256k(environment1)," \ - "256k(environment2)," \ - "256k(splash-factory)," \ - "2m(FIT: recovery)," \ - "4608k(fs-recovery)," \ - "256k(splash-customer),"\ - "5m(FIT: kernel+dtb)," \ - "64m(rootfs squash)ro," \ - "51m(userfs ubi);" \ - "f8000000.flash:-(unused);" \ - "MPC5121 NAND:1024m(extended-userfs)" - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */ -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ -#if CONFIG_PSC_CONSOLE != 6 -#error CONFIG_PSC_CONSOLE must be 6 -#endif - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -/* - * Used PSC UART devices - */ -#define CONFIG_SYS_PSC1 -#define CONFIG_SYS_PSC4 -#define CONFIG_SYS_PSC6 - -/* - * Co-processor communication parameters - */ -#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000 -#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400 - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Enabled only to delete "ethaddr" before testing - * "ethaddr" setting from EEPROM - */ -#define CONFIG_ENV_OVERWRITE - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1F -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMD_REGINFO - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -/* Max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* Decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -/* log base 2 of the above value */ -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_COPROC) - -/* - * Environment Configuration - */ -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME pdm360ng -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 400000 - - -#define CONFIG_PREBOOT "echo;" \ - "echo PDM360NG SAMPLE;" \ - "echo" - -#define CONFIG_BOOTCOMMAND "run env_cont" - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11600" - -/* - * Include common options for all mpc5121 boards - */ -#include "mpc5121-common.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index f778744..af1dae8 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -22,4 +22,12 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_MISC_INIT_R +#define CONFIG_SERIAL_TAG +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP + #endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 7ccbc9b..5a06244 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -59,4 +59,10 @@ #endif +/* rockchip ohci host driver */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* xhci host */ +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h new file mode 100644 index 0000000..8ebf232 --- /dev/null +++ b/include/configs/rk3368_common.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3368_COMMON_H +#define __CONFIG_RK3368_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include +#include + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00280000 + +#define CONFIG_BOUNCE_BUFFER + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x5600000\0" \ + "kernel_addr_r=0x280000\0" \ + "ramdisk_addr_r=0x5bf0000\0" + +#include + +#define BOOT_TARGET_DEVICES(func) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9d183ce..0573571 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -54,4 +54,6 @@ #define CONFIG_ENV_OFFSET (96 * 1024) #endif +#define CONFIG_DISPLAY_BOARDINFO_LATE + #endif /* _ROCKCHIP_COMMON_H_ */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h new file mode 100644 index 0000000..52750cb --- /dev/null +++ b/include/configs/rv1108_common.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RV1108_COMMON_H +#define __CONFIG_RV1108_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +/* TIMER1,initialized by ddr initialize code */ +#define CONFIG_SYS_TIMER_BASE 0x10350020 +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) + +#endif diff --git a/include/configs/sheep_rk3368.h b/include/configs/sheep_rk3368.h new file mode 100644 index 0000000..ec33565 --- /dev/null +++ b/include/configs/sheep_rk3368.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_PX5_EVB_H +#define __CONFIGS_PX5_EVB_H + +#include + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define KERNEL_LOAD_ADDR 0x280000 +#define DTB_LOAD_ADDR 0x5600000 +#define INITRD_LOAD_ADDR 0x5bf0000 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index b5705b7..21029d1 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -14,8 +14,6 @@ #ifndef __CONFIG_SIEMENS_AM33X_COMMON_H #define __CONFIG_SIEMENS_AM33X_COMMON_H -#define CONFIG_AM33XX - #include #define CONFIG_DMA_COHERENT diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 1ee5815..4e0edcb 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -10,14 +10,20 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 -#define CONFIG_SYS_TEXT_BASE 0x08000000 + +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_TEXT_BASE 0x08008000 +#define CONFIG_SYS_LOAD_ADDR 0x08008000 +#else +#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LOAD_ADDR 0xC0400000 +#define CONFIG_LOADADDR 0xC0400000 +#endif /* * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_LOAD_ADDR 0xC0400000 -#define CONFIG_LOADADDR 0xC0400000 #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -69,4 +75,23 @@ #define CONFIG_CMD_CACHE #define CONFIG_BOARD_LATE_INIT #define CONFIG_DISPLAY_BOARDINFO + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x080083FD +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) + +/* DT blob (fdt) address */ +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x1C0000) +#endif +/* For SPL ends */ + #endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c03efd8..dd72e5b 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -105,7 +105,7 @@ /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* remove I2C support */ #ifdef CONFIG_SYS_I2C_TEGRA diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index a4066a8..ea83ea2 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -16,9 +16,6 @@ #ifndef __CONFIG_TI814X_EVM_H #define __CONFIG_TI814X_EVM_H -#define CONFIG_TI81XX -#define CONFIG_TI814X - #include #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 68eb08f..defcad4 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -10,24 +10,16 @@ #ifndef __CONFIG_TI816X_EVM_H #define __CONFIG_TI816X_EVM_H -#define CONFIG_TI81XX -#define CONFIG_TI816X - -#define CONFIG_ARCH_CPU_INIT - +#include #include #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) -#define CONFIG_SYS_LONGHELP /* undef save memory */ #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG /* required for ramdisk support */ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ #define CONFIG_BOOTCOMMAND \ "mmc rescan;" \ @@ -40,41 +32,10 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - #define CONFIG_CMD_ASKENV -/* - * Only one of the following two options (DDR3/DDR2) should be enabled - * CONFIG_TI816X_EVM_DDR2 - * CONFIG_TI816X_EVM_DDR3 - */ -#define CONFIG_TI816X_EVM_DDR3 - -/* - * Supported values: 400, 531, 675 or 796 MHz - */ -#define CONFIG_TI816X_DDR_PLL_796 - -#define CONFIG_TI816X_USE_EMIF0 1 -#define CONFIG_TI816X_USE_EMIF1 1 - -#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ -#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ -#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ - #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs @@ -83,8 +44,6 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#undef CONFIG_NAND_OMAP_GPMC - /* * NS16550 Configuration */ @@ -101,28 +60,68 @@ #define CONFIG_SERIAL3 #define CONFIG_CONS_INDEX 1 -#define CONFIG_ENV_IS_NOWHERE +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* NAND: SPL related configs */ +#define CONFIG_SPL_NAND_AM33XX_BCH + +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC_PREFETCH +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ + "128k(NAND.SPL)," \ + "128k(NAND.SPL.backup1)," \ + "128k(NAND.SPL.backup2)," \ + "128k(NAND.SPL.backup3)," \ + "256k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "128k(NAND.u-boot-env)," \ + "128k(NAND.u-boot-env.backup1)," \ + "8m(NAND.kernel)," \ + "-(NAND.file-system)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #define CONFIG_SPL_TEXT_BASE 0x40400000 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SYS_TEXT_BASE 0x80800000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* Since SPL did pll and ddr initialization for us, * we don't need to do it twice. @@ -131,4 +130,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#undef CONFIG_DM_USB +#endif #endif diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 5321ed6..a4676d3 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -199,9 +199,10 @@ #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" /* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700 /* address 0x2E0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ + /* spl export command */ #define CONFIG_CMD_SPL diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index a289225..ee46d3a 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -56,7 +56,6 @@ #undef CONFIG_SF_DEFAULT_SPEED #define CONFIG_SF_DEFAULT_SPEED 108000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#undef CONFIG_SF_DUAL_FLASH #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #undef CONFIG_SPI_FLASH_WINBOND #undef CONFIG_SPI_FLASH_ISSI diff --git a/include/configs/topic_miamiplus.h b/include/configs/topic_miamiplus.h deleted file mode 100644 index 46ca6bd..0000000 --- a/include/configs/topic_miamiplus.h +++ /dev/null @@ -1,2 +0,0 @@ -#include "topic_miami.h" -#define CONFIG_SF_DUAL_FLASH diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 4ab4c65..4e99cdb 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -29,7 +29,7 @@ #define CONFIG_SYS_RTC_BUS_NUM 2 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ -#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_RTC_DS1337_NOOSC /* LED */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h deleted file mode 100644 index 2bd6cc1..0000000 --- a/include/configs/v38b.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, - * wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ...on V38B board */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ - -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ - -#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ - -#define CONFIG_NETCONSOLE 1 - -#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * DDR - */ -#define SDRAM_DDR 1 /* is DDR */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* - * PCI - no support - */ - -/* - * USB - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_SDRAM - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Boot low with 16 MB Flash - */ -#define CONFIG_SYS_LOWBOOT 1 -#define CONFIG_SYS_LOWBOOT16 1 - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootcmd=run net_nfs\0" \ - "bootdelay=3\0" \ - "baudrate=115200\0" \ - "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ - "filesystem over NFS; echo\0" \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ - "hostname=v38b\0" \ - "ethact=FEC\0" \ - "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ - "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ - "cp.b 200000 ff000000 $(filesize);" \ - "prot on ff000000 ff03ffff\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.18\0" \ - "serverip=192.168.1.1\0" \ - "bootfile=/tftpboot/v38b/uImage\0" \ - "u-boot=/tftpboot/v38b/u-boot.bin\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - use CFI driver - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * IDE/ATA (supports IDE harddisk) - */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ - -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ - -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ - -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -/* - * Status LED - */ - -#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ - else \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ - } while(0) - -#define __led_init(_msk, st) \ - do { \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ - } while(0) -#endif /* __ASSEMBLY__ */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h deleted file mode 100644 index 9f350d5..0000000 --- a/include/configs/whistler.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_UAA_UAB -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER - -/* I2C */ -#define CONFIG_SYS_I2C_TEGRA - -/* - * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes - * the user plugged the standard 8GB MoviNAND card into J29/HSMMC/POP. If - * they didn't, the boot sector layout may be different. However, use of that - * particular card is standard practice as far as I know. - */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* USB Host support */ -#define CONFIG_USB_EHCI_TEGRA - -/* USB networking support */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX - -/* General networking support */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index c56cd8c..86a4579 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -29,9 +29,6 @@ #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 1000 -/* Have release address at the end of 256MB for now */ -#define CPU_RELEASE_ADDR 0xFFFFFF0 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ @@ -292,11 +289,13 @@ # define CONFIG_ENV_MAX_ENTRIES 10 # define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000 +# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" #endif #endif +#define CONFIG_BOARD_EARLY_INIT_F + #endif /* __XILINX_ZYNQMP_H */ diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h new file mode 100644 index 0000000..9c5dd9b --- /dev/null +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2015 Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H + +/* core clocks */ +#define PLL_APLLB 1 +#define PLL_APLLL 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define ARMCLKB 7 +#define ARMCLKL 8 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_NANDC0 75 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S_8CH 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S_2CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_OTGPHY0 93 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_VOP0_PWM 100 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_PMU 125 +#define SCLK_SFC 126 +#define SCLK_MAC 127 +#define SCLK_MACREF_OUT 128 + +#define DCLK_VOP 190 +#define MCLK_CRYPTO 191 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOP 198 +#define ACLK_VOP_IEP 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_PMUGRF 324 +#define PCLK_MAILBOX 325 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM0 350 +#define PCLK_PWM1 351 +#define PCLK_TIMER0 353 +#define PCLK_TIMER1 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_CSI 358 +#define PCLK_HDCP 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO_H2P 361 +#define PCLK_BUS 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_DDRPHY 365 +#define PCLK_ISP 366 +#define PCLK_VIP 367 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_OTG0 449 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S_2CH 462 +#define HCLK_I2S_8CH 463 +#define HCLK_SPDIF 464 +#define HCLK_VOP 465 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NOC 472 +#define HCLK_VIP 473 +#define HCLK_VIO_H2P 474 +#define HCLK_VIO_HDCPMMU 475 +#define HCLK_VIDEO 476 +#define HCLK_BUS 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE_B0 0 +#define SRST_CORE_B1 1 +#define SRST_CORE_B2 2 +#define SRST_CORE_B3 3 +#define SRST_CORE_B0_PO 4 +#define SRST_CORE_B1_PO 5 +#define SRST_CORE_B2_PO 6 +#define SRST_CORE_B3_PO 7 +#define SRST_L2_B 8 +#define SRST_ADB_B 9 +#define SRST_PD_CORE_B_NIU 10 +#define SRST_PDBUS_STRSYS 11 +#define SRST_SOCDBG_B 14 +#define SRST_CORE_B_DBG 15 + +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP_24M 111 + +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_EDP 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_SYS 126 +#define SRST_GPU_MEM_NIU 127 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST1_UTMI 139 +#define SRST_USB_ADP 141 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RGA_H2P_BRG 153 +#define SRST_VIDEO 154 +#define SRST_GPU_CFG_NIU 157 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 + +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 + +#define SRST_CORE_L0 192 +#define SRST_CORE_L1 193 +#define SRST_CORE_L2 194 +#define SRST_CORE_L3 195 +#define SRST_CORE_L0_PO 195 +#define SRST_CORE_L1_PO 197 +#define SRST_CORE_L2_PO 198 +#define SRST_CORE_L3_PO 199 +#define SRST_L2_L 200 +#define SRST_ADB_L 201 +#define SRST_PD_CORE_L_NIU 202 +#define SRST_CCI_SYS 203 +#define SRST_CCI_DDR 204 +#define SRST_CCI 205 +#define SRST_SOCDBG_L 206 +#define SRST_CORE_L_DBG 207 + +#define SRST_CORE_B0_NC 208 +#define SRST_CORE_B0_PO_NC 209 +#define SRST_L2_B_NC 210 +#define SRST_ADB_B_NC 211 +#define SRST_PD_CORE_B_NIU_NC 212 +#define SRST_PDBUS_STRSYS_NC 213 +#define SRST_CORE_L0_NC 214 +#define SRST_CORE_L0_PO_NC 215 +#define SRST_L2_L_NC 216 +#define SRST_ADB_L_NC 217 +#define SRST_PD_CORE_L_NIU_NC 218 +#define SRST_CCI_SYS_NC 219 +#define SRST_CCI_DDR_NC 220 +#define SRST_CCI_NC 221 +#define SRST_TRACE_NC 222 + +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h new file mode 100644 index 0000000..d2ad3bb --- /dev/null +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Shawn Lin + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H + +/* pll id */ +#define PLL_APLL 0 +#define PLL_DPLL 1 +#define PLL_GPLL 2 +#define ARMCLK 3 + +/* sclk gates (special clocks) */ +#define SCLK_MAC 64 +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 72 +#define SCLK_UART1 73 +#define SCLK_UART2 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_TIMER0 78 +#define SCLK_TIMER1 79 +#define SCLK_SFC 80 +#define SCLK_SDMMC_DRV 81 +#define SCLK_SDIO_DRV 82 +#define SCLK_EMMC_DRV 83 +#define SCLK_SDMMC_SAMPLE 84 +#define SCLK_SDIO_SAMPLE 85 +#define SCLK_EMMC_SAMPLE 86 +#define SCLK_MAC_RX 87 +#define SCLK_MAC_TX 88 +#define SCLK_MACREF 89 +#define SCLK_MACREF_OUT 90 + + +/* aclk gates */ +#define ACLK_DMAC 192 +#define ACLK_PRE 193 +#define ACLK_CORE 194 +#define ACLK_ENMCORE 195 +#define ACLK_GMAC 196 + + +/* pclk gates */ +#define PCLK_GPIO1 256 +#define PCLK_GPIO2 257 +#define PCLK_GPIO3 258 +#define PCLK_GRF 259 +#define PCLK_I2C1 260 +#define PCLK_I2C2 261 +#define PCLK_I2C3 262 +#define PCLK_SPI 263 +#define PCLK_SFC 264 +#define PCLK_UART0 265 +#define PCLK_UART1 266 +#define PCLK_UART2 267 +#define PCLK_TSADC 268 +#define PCLK_PWM 269 +#define PCLK_TIMER 270 +#define PCLK_PERI 271 +#define PCLK_GMAC 272 + +/* hclk gates */ +#define HCLK_I2S0_8CH 320 +#define HCLK_I2S1_8CH 321 +#define HCLK_I2S2_2CH 322 +#define HCLK_NANDC 323 +#define HCLK_SDMMC 324 +#define HCLK_SDIO 325 +#define HCLK_EMMC 326 +#define HCLK_PERI 327 +#define HCLK_SFC 328 + +#define CLK_NR_CLKS (HCLK_SFC + 1) + +/* reset id */ +#define SRST_CORE_PO_AD 0 +#define SRST_CORE_AD 1 +#define SRST_L2_AD 2 +#define SRST_CPU_NIU_AD 3 +#define SRST_CORE_PO 4 +#define SRST_CORE 5 +#define SRST_L2 6 +#define SRST_CORE_DBG 8 +#define PRST_DBG 9 +#define RST_DAP 10 +#define PRST_DBG_NIU 11 +#define ARST_STRC_SYS_AD 15 + +#define SRST_DDRPHY_CLKDIV 16 +#define SRST_DDRPHY 17 +#define PRST_DDRPHY 18 +#define PRST_HDMIPHY 19 +#define PRST_VDACPHY 20 +#define PRST_VADCPHY 21 +#define PRST_MIPI_CSI_PHY 22 +#define PRST_MIPI_DSI_PHY 23 +#define PRST_ACODEC 24 +#define ARST_BUS_NIU 25 +#define PRST_TOP_NIU 26 +#define ARST_INTMEM 27 +#define HRST_ROM 28 +#define ARST_DMAC 29 +#define SRST_MSCH_NIU 30 +#define PRST_MSCH_NIU 31 + +#define PRST_DDRUPCTL 32 +#define NRST_DDRUPCTL 33 +#define PRST_DDRMON 34 +#define HRST_I2S0_8CH 35 +#define MRST_I2S0_8CH 36 +#define HRST_I2S1_2CH 37 +#define MRST_IS21_2CH 38 +#define HRST_I2S2_2CH 39 +#define MRST_I2S2_2CH 40 +#define HRST_CRYPTO 41 +#define SRST_CRYPTO 42 +#define PRST_SPI 43 +#define SRST_SPI 44 +#define PRST_UART0 45 +#define PRST_UART1 46 +#define PRST_UART2 47 + +#define SRST_UART0 48 +#define SRST_UART1 49 +#define SRST_UART2 50 +#define PRST_I2C1 51 +#define PRST_I2C2 52 +#define PRST_I2C3 53 +#define SRST_I2C1 54 +#define SRST_I2C2 55 +#define SRST_I2C3 56 +#define PRST_PWM1 58 +#define SRST_PWM1 60 +#define PRST_WDT 61 +#define PRST_GPIO1 62 +#define PRST_GPIO2 63 + +#define PRST_GPIO3 64 +#define PRST_GRF 65 +#define PRST_EFUSE 66 +#define PRST_EFUSE512 67 +#define PRST_TIMER0 68 +#define SRST_TIMER0 69 +#define SRST_TIMER1 70 +#define PRST_TSADC 71 +#define SRST_TSADC 72 +#define PRST_SARADC 73 +#define SRST_SARADC 74 +#define HRST_SYSBUS 75 +#define PRST_USBGRF 76 + +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 +#define HRST_PERIPH 83 +#define HRST_SDMMC 84 +#define HRST_SDIO 85 +#define HRST_EMMC 86 +#define HRST_NANDC 87 +#define NRST_NANDC 88 +#define HRST_SFC 89 +#define SRST_SFC 90 +#define ARST_GMAC 91 +#define HRST_OTG 92 +#define SRST_OTG 93 +#define SRST_OTG_ADP 94 +#define HRST_HOST0 95 + +#define HRST_HOST0_AUX 96 +#define HRST_HOST0_ARB 97 +#define SRST_HOST0_EHCIPHY 98 +#define SRST_HOST0_UTMI 99 +#define SRST_USBPOR 100 +#define SRST_UTMI0 101 +#define SRST_UTMI1 102 + +#define ARST_VIO0_NIU 102 +#define ARST_VIO1_NIU 103 +#define HRST_VIO_NIU 104 +#define PRST_VIO_NIU 105 +#define ARST_VOP 106 +#define HRST_VOP 107 +#define DRST_VOP 108 +#define ARST_IEP 109 +#define HRST_IEP 110 +#define ARST_RGA 111 +#define HRST_RGA 112 +#define SRST_RGA 113 +#define PRST_CVBS 114 +#define PRST_HDMI 115 +#define SRST_HDMI 116 +#define PRST_MIPI_DSI 117 + +#define ARST_ISP_NIU 118 +#define HRST_ISP_NIU 119 +#define HRST_ISP 120 +#define SRST_ISP 121 +#define ARST_VIP0 122 +#define HRST_VIP0 123 +#define PRST_VIP0 124 +#define ARST_VIP1 125 +#define HRST_VIP1 126 +#define PRST_VIP1 127 +#define ARST_VIP2 128 +#define HRST_VIP2 129 +#define PRST_VIP2 120 +#define ARST_VIP3 121 +#define HRST_VIP3 122 +#define PRST_VIP4 123 + +#define PRST_CIF1TO4 124 +#define SRST_CVBS_CLK 125 +#define HRST_CVBS 126 + +#define ARST_VPU_NIU 140 +#define HRST_VPU_NIU 141 +#define ARST_VPU 142 +#define HRST_VPU 143 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC 146 +#define HRST_RKVDEC 147 +#define SRST_RKVDEC_CABAC 148 +#define SRST_RKVDEC_CORE 149 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC 152 +#define HRST_RKVENC 153 +#define SRST_RKVENC_CORE 154 + +#define SRST_DSP_CORE 156 +#define SRST_DSP_SYS 157 +#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_OECM 159 +#define PRST_DSP_IOP_NIU 160 +#define ARST_DSP_EPP_NIU 161 +#define ARST_DSP_EDP_NIU 162 +#define PRST_DSP_DBG_NIU 163 +#define PRST_DSP_CFG_NIU 164 +#define PRST_DSP_GRF 165 +#define PRST_DSP_MAILBOX 166 +#define PRST_DSP_INTC 167 +#define PRST_DSP_PFM_MON 169 +#define SRST_DSP_PFM_MON 170 +#define ARST_DSP_EDAP_NIU 171 + +#define SRST_PMU 172 +#define SRST_PMU_I2C0 173 +#define PRST_PMU_I2C0 174 +#define PRST_PMU_GPIO0 175 +#define PRST_PMU_INTMEM 176 +#define PRST_PMU_PWM0 177 +#define SRST_PMU_PWM0 178 +#define PRST_PMU_GRF 179 +#define SRST_PMU_NIU 180 +#define SRST_PMU_PVTM 181 +#define ARST_DSP_EDP_PERF 184 +#define ARST_DSP_EPP_PERF 185 + +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/include/environment/ti/dfu.h b/include/environment/ti/dfu.h index caf71a3..c89005f 100644 --- a/include/environment/ti/dfu.h +++ b/include/environment/ti/dfu.h @@ -6,15 +6,19 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __TI_DFU_H +#define __TI_DFU_H + #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ "boot part 0 1;" \ "rootfs part 0 2;" \ "MLO fat 0 1;" \ "MLO.raw raw 0x100 0x100;" \ - "u-boot.img.raw raw 0x300 0x400;" \ - "spl-os-args.raw raw 0x80 0x80;" \ - "spl-os-image.raw raw 0x900 0x2000;" \ + "u-boot.img.raw raw 0x300 0x1000;" \ + "u-env.raw raw 0x1300 0x200;" \ + "spl-os-args.raw raw 0x1500 0x200;" \ + "spl-os-image.raw raw 0x1700 0x6900;" \ "spl-os-args fat 0 1;" \ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ @@ -28,8 +32,9 @@ "MLO fat 1 1;" \ "MLO.raw raw 0x100 0x100;" \ "u-boot.img.raw raw 0x300 0x1000;" \ - "spl-os-args.raw raw 0x80 0x80;" \ - "spl-os-image.raw raw 0x900 0x2000;" \ + "u-env.raw raw 0x1300 0x200;" \ + "spl-os-args.raw raw 0x1500 0x200;" \ + "spl-os-image.raw raw 0x1700 0x6900;" \ "spl-os-args fat 1 1;" \ "spl-os-image fat 1 1;" \ "u-boot.img fat 1 1;" \ @@ -73,3 +78,5 @@ "u-boot-env raw 0x1C0000 0x010000;" \ "u-boot-env.backup raw 0x1D0000 0x010000;" \ "kernel raw 0x1E0000 0x800000\0" + +#endif /* __TI_DFU_H */ diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index b987f71..4305ebd 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -6,6 +6,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __TI_MMC_H +#define __TI_MMC_H + #define DEFAULT_MMC_TI_ARGS \ "mmcdev=0\0" \ "mmcrootfstype=ext4 rootwait\0" \ @@ -66,3 +69,5 @@ "fi;" \ "fi;" \ "fi;\0" + +#endif /* __TI_MMC_H */ diff --git a/include/fdt.h b/include/fdt.h index 526aedb..7ead62e 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -1,111 +1 @@ -#ifndef _FDT_H -#define _FDT_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * Copyright 2012 Kim Phillips, Freescale Semiconductor. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ASSEMBLY__ - -struct fdt_header { - fdt32_t magic; /* magic word FDT_MAGIC */ - fdt32_t totalsize; /* total size of DT block */ - fdt32_t off_dt_struct; /* offset to structure */ - fdt32_t off_dt_strings; /* offset to strings */ - fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ - fdt32_t version; /* format version */ - fdt32_t last_comp_version; /* last compatible version */ - - /* version 2 fields below */ - fdt32_t boot_cpuid_phys; /* Which physical CPU id we're - booting on */ - /* version 3 fields below */ - fdt32_t size_dt_strings; /* size of the strings block */ - - /* version 17 fields below */ - fdt32_t size_dt_struct; /* size of the structure block */ -}; - -struct fdt_reserve_entry { - fdt64_t address; - fdt64_t size; -}; - -struct fdt_node_header { - fdt32_t tag; - char name[0]; -}; - -struct fdt_property { - fdt32_t tag; - fdt32_t len; - fdt32_t nameoff; - char data[0]; -}; - -#endif /* !__ASSEMBLY */ - -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ -#define FDT_TAGSIZE sizeof(fdt32_t) - -#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ -#define FDT_END_NODE 0x2 /* End node */ -#define FDT_PROP 0x3 /* Property: name off, - size, content */ -#define FDT_NOP 0x4 /* nop */ -#define FDT_END 0x9 - -#define FDT_V1_SIZE (7*sizeof(fdt32_t)) -#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) -#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) -#define FDT_V16_SIZE FDT_V3_SIZE -#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) - -#endif /* _FDT_H */ +#include <../lib/libfdt/fdt.h> diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index a86f216..29aa687 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -11,6 +11,9 @@ #ifdef CONFIG_FSL_IFC #include #include +#ifdef CONFIG_ARM +#include +#endif #define FSL_IFC_V1_1_0 0x01010000 #define FSL_IFC_V2_0_0 0x02000000 diff --git a/include/i2c.h b/include/i2c.h index 7726028..695cb76 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -660,12 +660,7 @@ extern struct i2c_bus_hose i2c_bus[]; #endif #ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - -# elif (defined(CONFIG_AT91RM9200) || \ +# if (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ defined(CONFIG_AT91SAM9263)) # define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; @@ -674,15 +669,6 @@ extern struct i2c_bus_hose i2c_bus[]; # endif #endif -#ifdef CONFIG_8xx -/* Set default value for the I2C bus speed on 8xx. In the - * future, we'll define these in all 8xx board config files. - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif -#endif - /* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real @@ -814,11 +800,6 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) { u8 buf; -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - #ifdef DEBUG printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); #endif @@ -830,11 +811,6 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) { -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - #ifdef DEBUG printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", __func__, addr, reg, val); diff --git a/include/image.h b/include/image.h index 8d380e0..fcfe730 100644 --- a/include/image.h +++ b/include/image.h @@ -785,7 +785,8 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type) } static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) { - return (image_get_arch(hdr) == arch); + return (image_get_arch(hdr) == arch) || + (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64); } static inline int image_check_os(const image_header_t *hdr, uint8_t os) { diff --git a/include/keyboard.h b/include/keyboard.h index 5cbd9f8..9b51e20 100644 --- a/include/keyboard.h +++ b/include/keyboard.h @@ -98,7 +98,7 @@ extern int kbd_init_hw(void); extern void pckbd_leds(unsigned char leds); #endif /* !CONFIG_DM_KEYBOARD */ -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \ +#if defined(CONFIG_ARCH_MPC8540) || \ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) int ps2ser_check(void); #endif diff --git a/include/lcd.h b/include/lcd.h index f76fca7..797d0b0 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -40,9 +40,7 @@ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); */ void lcd_set_flush_dcache(int flush); -#if defined CONFIG_MPC823 -#include -#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ +#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined CONFIG_CPU_MONAHANS #include #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) diff --git a/include/libfdt.h b/include/libfdt.h index e2bc2e0..10296a2 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1,2137 +1 @@ -#ifndef _LIBFDT_H -#define _LIBFDT_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#define FDT_FIRST_SUPPORTED_VERSION 0x10 -#define FDT_LAST_SUPPORTED_VERSION 0x11 - -/* Error codes: informative error codes */ -#define FDT_ERR_NOTFOUND 1 - /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ -#define FDT_ERR_EXISTS 2 - /* FDT_ERR_EXISTS: Attempted to create a node or property which - * already exists */ -#define FDT_ERR_NOSPACE 3 - /* FDT_ERR_NOSPACE: Operation needed to expand the device - * tree, but its buffer did not have sufficient space to - * contain the expanded tree. Use fdt_open_into() to move the - * device tree to a buffer with more space. */ - -/* Error codes: codes for bad parameters */ -#define FDT_ERR_BADOFFSET 4 - /* FDT_ERR_BADOFFSET: Function was passed a structure block - * offset which is out-of-bounds, or which points to an - * unsuitable part of the structure for the operation. */ -#define FDT_ERR_BADPATH 5 - /* FDT_ERR_BADPATH: Function was passed a badly formatted path - * (e.g. missing a leading / for a function which requires an - * absolute path) */ -#define FDT_ERR_BADPHANDLE 6 - /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. - * This can be caused either by an invalid phandle property - * length, or the phandle value was either 0 or -1, which are - * not permitted. */ -#define FDT_ERR_BADSTATE 7 - /* FDT_ERR_BADSTATE: Function was passed an incomplete device - * tree created by the sequential-write functions, which is - * not sufficiently complete for the requested operation. */ - -/* Error codes: codes for bad device tree blobs */ -#define FDT_ERR_TRUNCATED 8 - /* FDT_ERR_TRUNCATED: Structure block of the given device tree - * ends without an FDT_END tag. */ -#define FDT_ERR_BADMAGIC 9 - /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a - * device tree at all - it is missing the flattened device - * tree magic number. */ -#define FDT_ERR_BADVERSION 10 - /* FDT_ERR_BADVERSION: Given device tree has a version which - * can't be handled by the requested operation. For - * read-write functions, this may mean that fdt_open_into() is - * required to convert the tree to the expected version. */ -#define FDT_ERR_BADSTRUCTURE 11 - /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt - * structure block or other serious error (e.g. misnested - * nodes, or subnodes preceding properties). */ -#define FDT_ERR_BADLAYOUT 12 - /* FDT_ERR_BADLAYOUT: For read-write functions, the given - * device tree has it's sub-blocks in an order that the - * function can't handle (memory reserve map, then structure, - * then strings). Use fdt_open_into() to reorganize the tree - * into a form suitable for the read-write operations. */ - -/* "Can't happen" error indicating a bug in libfdt */ -#define FDT_ERR_INTERNAL 13 - /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. - * Should never be returned, if it is, it indicates a bug in - * libfdt itself. */ - -/* Errors in device tree content */ -#define FDT_ERR_BADNCELLS 14 - /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells - * or similar property with a bad format or value */ - -#define FDT_ERR_BADVALUE 15 - /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected - * value. For example: a property expected to contain a string list - * is not NUL-terminated within the length of its value. */ - -#define FDT_ERR_BADOVERLAY 16 - /* FDT_ERR_BADOVERLAY: The device tree overlay, while - * correctly structured, cannot be applied due to some - * unexpected or missing value, property or node. */ - -#define FDT_ERR_NOPHANDLES 17 - /* FDT_ERR_NOPHANDLES: The device tree doesn't have any - * phandle available anymore without causing an overflow */ - -#define FDT_ERR_TOODEEP 18 - /* FDT_ERR_TOODEEP: The depth of a node has exceeded the internal - * libfdt limit. This can happen if you have more than - * FDT_MAX_DEPTH nested nodes. */ - -#define FDT_ERR_MAX 18 - -/**********************************************************************/ -/* Low-level functions (you probably don't need these) */ -/**********************************************************************/ - -const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); -static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) -{ - return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); -} - -uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); - -/**********************************************************************/ -/* Traversal functions */ -/**********************************************************************/ - -int fdt_next_node(const void *fdt, int offset, int *depth); - -/** - * fdt_first_subnode() - get offset of first direct subnode - * - * @fdt: FDT blob - * @offset: Offset of node to check - * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none - */ -int fdt_first_subnode(const void *fdt, int offset); - -/** - * fdt_next_subnode() - get offset of next direct subnode - * - * After first calling fdt_first_subnode(), call this function repeatedly to - * get direct subnodes of a parent node. - * - * @fdt: FDT blob - * @offset: Offset of previous subnode - * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more - * subnodes - */ -int fdt_next_subnode(const void *fdt, int offset); - -/** - * fdt_for_each_subnode - iterate over all subnodes of a parent - * - * @node: child node (int, lvalue) - * @fdt: FDT blob (const void *) - * @parent: parent node (int) - * - * This is actually a wrapper around a for loop and would be used like so: - * - * fdt_for_each_subnode(node, fdt, parent) { - * Use node - * ... - * } - * - * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) { - * Error handling - * } - * - * Note that this is implemented as a macro and @node is used as - * iterator in the loop. The parent variable be constant or even a - * literal. - * - */ -#define fdt_for_each_subnode(node, fdt, parent) \ - for (node = fdt_first_subnode(fdt, parent); \ - node >= 0; \ - node = fdt_next_subnode(fdt, node)) - -/**********************************************************************/ -/* General functions */ -/**********************************************************************/ - -#define fdt_get_header(fdt, field) \ - (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) -#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) -#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) -#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) -#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) -#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) -#define fdt_version(fdt) (fdt_get_header(fdt, version)) -#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) -#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) -#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) -#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) - -#define __fdt_set_hdr(name) \ - static inline void fdt_set_##name(void *fdt, uint32_t val) \ - { \ - struct fdt_header *fdth = (struct fdt_header *)fdt; \ - fdth->name = cpu_to_fdt32(val); \ - } -__fdt_set_hdr(magic); -__fdt_set_hdr(totalsize); -__fdt_set_hdr(off_dt_struct); -__fdt_set_hdr(off_dt_strings); -__fdt_set_hdr(off_mem_rsvmap); -__fdt_set_hdr(version); -__fdt_set_hdr(last_comp_version); -__fdt_set_hdr(boot_cpuid_phys); -__fdt_set_hdr(size_dt_strings); -__fdt_set_hdr(size_dt_struct); -#undef __fdt_set_hdr - -/** - * fdt_check_header - sanity check a device tree or possible device tree - * @fdt: pointer to data which might be a flattened device tree - * - * fdt_check_header() checks that the given buffer contains what - * appears to be a flattened device tree with sane information in its - * header. - * - * returns: - * 0, if the buffer appears to contain a valid device tree - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings, as above - */ -int fdt_check_header(const void *fdt); - -/** - * fdt_move - move a device tree around in memory - * @fdt: pointer to the device tree to move - * @buf: pointer to memory where the device is to be moved - * @bufsize: size of the memory space at buf - * - * fdt_move() relocates, if possible, the device tree blob located at - * fdt to the buffer at buf of size bufsize. The buffer may overlap - * with the existing device tree blob at fdt. Therefore, - * fdt_move(fdt, fdt, fdt_totalsize(fdt)) - * should always succeed. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_move(const void *fdt, void *buf, int bufsize); - -/**********************************************************************/ -/* Read-only functions */ -/**********************************************************************/ - -/** - * fdt_string - retrieve a string from the strings block of a device tree - * @fdt: pointer to the device tree blob - * @stroffset: offset of the string within the strings block (native endian) - * - * fdt_string() retrieves a pointer to a single string from the - * strings block of the device tree blob at fdt. - * - * returns: - * a pointer to the string, on success - * NULL, if stroffset is out of bounds - */ -const char *fdt_string(const void *fdt, int stroffset); - -/** - * fdt_get_max_phandle - retrieves the highest phandle in a tree - * @fdt: pointer to the device tree blob - * - * fdt_get_max_phandle retrieves the highest phandle in the given - * device tree. This will ignore badly formatted phandles, or phandles - * with a value of 0 or -1. - * - * returns: - * the highest phandle on success - * 0, if no phandle was found in the device tree - * -1, if an error occurred - */ -uint32_t fdt_get_max_phandle(const void *fdt); - -/** - * fdt_num_mem_rsv - retrieve the number of memory reserve map entries - * @fdt: pointer to the device tree blob - * - * Returns the number of entries in the device tree blob's memory - * reservation map. This does not include the terminating 0,0 entry - * or any other (0,0) entries reserved for expansion. - * - * returns: - * the number of entries - */ -int fdt_num_mem_rsv(const void *fdt); - -/** - * fdt_get_mem_rsv - retrieve one memory reserve map entry - * @fdt: pointer to the device tree blob - * @address, @size: pointers to 64-bit variables - * - * On success, *address and *size will contain the address and size of - * the n-th reserve map entry from the device tree blob, in - * native-endian format. - * - * returns: - * 0, on success - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); - -/** - * fdt_subnode_offset_namelen - find a subnode based on substring - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * @namelen: number of characters of name to consider - * - * Identical to fdt_subnode_offset(), but only examine the first - * namelen characters of name for matching the subnode name. This is - * useful for finding subnodes based on a portion of a larger string, - * such as a full path. - */ -int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, - const char *name, int namelen); -/** - * fdt_subnode_offset - find a subnode of a given node - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * - * fdt_subnode_offset() finds a subnode of the node at structure block - * offset parentoffset with the given name. name may include a unit - * address, in which case fdt_subnode_offset() will find the subnode - * with that unit address, or the unit address may be omitted, in - * which case fdt_subnode_offset() will find an arbitrary subnode - * whose name excluding unit address matches the given name. - * - * returns: - * structure block offset of the requested subnode (>=0), on success - * -FDT_ERR_NOTFOUND, if the requested subnode does not exist - * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); - -/** - * fdt_path_offset_namelen - find a tree node by its full path - * @fdt: pointer to the device tree blob - * @path: full path of the node to locate - * @namelen: number of characters of path to consider - * - * Identical to fdt_path_offset(), but only consider the first namelen - * characters of path as the path name. - */ -int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); - -/** - * fdt_path_offset - find a tree node by its full path - * @fdt: pointer to the device tree blob - * @path: full path of the node to locate - * - * fdt_path_offset() finds a node of a given path in the device tree. - * Each path component may omit the unit address portion, but the - * results of this are undefined if any such path component is - * ambiguous (that is if there are multiple nodes at the relevant - * level matching the given component, differentiated only by unit - * address). - * - * returns: - * structure block offset of the node with the requested path (>=0), on - * success - * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid - * -FDT_ERR_NOTFOUND, if the requested node does not exist - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_path_offset(const void *fdt, const char *path); - -/** - * fdt_get_name - retrieve the name of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of the starting node - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_name() retrieves the name (including unit address) of the - * device tree node at structure block offset nodeoffset. If lenp is - * non-NULL, the length of this name is also returned, in the integer - * pointed to by lenp. - * - * returns: - * pointer to the node's name, on success - * If lenp is non-NULL, *lenp contains the length of that name - * (>=0) - * NULL, on error - * if lenp is non-NULL *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); - -/** - * fdt_first_property_offset - find the offset of a node's first property - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of a node - * - * fdt_first_property_offset() finds the first property of the node at - * the given structure block offset. - * - * returns: - * structure block offset of the property (>=0), on success - * -FDT_ERR_NOTFOUND, if the requested node has no properties - * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_first_property_offset(const void *fdt, int nodeoffset); - -/** - * fdt_next_property_offset - step through a node's properties - * @fdt: pointer to the device tree blob - * @offset: structure block offset of a property - * - * fdt_next_property_offset() finds the property immediately after the - * one at the given structure block offset. This will be a property - * of the same node as the given property. - * - * returns: - * structure block offset of the next property (>=0), on success - * -FDT_ERR_NOTFOUND, if the given property is the last in its node - * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_next_property_offset(const void *fdt, int offset); - -/** - * fdt_for_each_property_offset - iterate over all properties of a node - * - * @property_offset: property offset (int, lvalue) - * @fdt: FDT blob (const void *) - * @node: node offset (int) - * - * This is actually a wrapper around a for loop and would be used like so: - * - * fdt_for_each_property_offset(property, fdt, node) { - * Use property - * ... - * } - * - * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) { - * Error handling - * } - * - * Note that this is implemented as a macro and property is used as - * iterator in the loop. The node variable can be constant or even a - * literal. - */ -#define fdt_for_each_property_offset(property, fdt, node) \ - for (property = fdt_first_property_offset(fdt, node); \ - property >= 0; \ - property = fdt_next_property_offset(fdt, property)) - -/** - * fdt_get_property_by_offset - retrieve the property at a given offset - * @fdt: pointer to the device tree blob - * @offset: offset of the property to retrieve - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_property_by_offset() retrieves a pointer to the - * fdt_property structure within the device tree blob at the given - * offset. If lenp is non-NULL, the length of the property value is - * also returned, in the integer pointed to by lenp. - * - * returns: - * pointer to the structure representing the property - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const struct fdt_property *fdt_get_property_by_offset(const void *fdt, - int offset, - int *lenp); - -/** - * fdt_get_property_namelen - find a property based on substring - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @namelen: number of characters of name to consider - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * Identical to fdt_get_property(), but only examine the first namelen - * characters of name for matching the property name. - */ -const struct fdt_property *fdt_get_property_namelen(const void *fdt, - int nodeoffset, - const char *name, - int namelen, int *lenp); - -/** - * fdt_get_property - find a given property in a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_property() retrieves a pointer to the fdt_property - * structure within the device tree blob corresponding to the property - * named 'name' of the node at offset nodeoffset. If lenp is - * non-NULL, the length of the property value is also returned, in the - * integer pointed to by lenp. - * - * returns: - * pointer to the structure representing the property - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_NOTFOUND, node does not have named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, - const char *name, int *lenp); -static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, - const char *name, - int *lenp) -{ - return (struct fdt_property *)(uintptr_t) - fdt_get_property(fdt, nodeoffset, name, lenp); -} - -/** - * fdt_getprop_by_offset - retrieve the value of a property at a given offset - * @fdt: pointer to the device tree blob - * @ffset: offset of the property to read - * @namep: pointer to a string variable (will be overwritten) or NULL - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_getprop_by_offset() retrieves a pointer to the value of the - * property at structure block offset 'offset' (this will be a pointer - * to within the device blob itself, not a copy of the value). If - * lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. If namep is non-NULL, - * the property's namne will also be returned in the char * pointed to - * by namep (this will be a pointer to within the device tree's string - * block, not a new copy of the name). - * - * returns: - * pointer to the property's value - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * if namep is non-NULL *namep contiains a pointer to the property - * name. - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const void *fdt_getprop_by_offset(const void *fdt, int offset, - const char **namep, int *lenp); - -/** - * fdt_getprop_namelen - get property value based on substring - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @namelen: number of characters of name to consider - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * Identical to fdt_getprop(), but only examine the first namelen - * characters of name for matching the property name. - */ -const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, - const char *name, int namelen, int *lenp); -static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, - const char *name, int namelen, - int *lenp) -{ - return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, - namelen, lenp); -} - -/** - * fdt_getprop - retrieve the value of a given property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_getprop() retrieves a pointer to the value of the property - * named 'name' of the node at offset nodeoffset (this will be a - * pointer to within the device blob itself, not a copy of the value). - * If lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. - * - * returns: - * pointer to the property's value - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_NOTFOUND, node does not have named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const void *fdt_getprop(const void *fdt, int nodeoffset, - const char *name, int *lenp); -static inline void *fdt_getprop_w(void *fdt, int nodeoffset, - const char *name, int *lenp) -{ - return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); -} - -/** - * fdt_get_phandle - retrieve the phandle of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of the node - * - * fdt_get_phandle() retrieves the phandle of the device tree node at - * structure block offset nodeoffset. - * - * returns: - * the phandle of the node at nodeoffset, on success (!= 0, != -1) - * 0, if the node has no phandle, or another error occurs - */ -uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); - -/** - * fdt_get_alias_namelen - get alias based on substring - * @fdt: pointer to the device tree blob - * @name: name of the alias th look up - * @namelen: number of characters of name to consider - * - * Identical to fdt_get_alias(), but only examine the first namelen - * characters of name for matching the alias name. - */ -const char *fdt_get_alias_namelen(const void *fdt, - const char *name, int namelen); - -/** - * fdt_get_alias - retrieve the path referenced by a given alias - * @fdt: pointer to the device tree blob - * @name: name of the alias th look up - * - * fdt_get_alias() retrieves the value of a given alias. That is, the - * value of the property named 'name' in the node /aliases. - * - * returns: - * a pointer to the expansion of the alias named 'name', if it exists - * NULL, if the given alias or the /aliases node does not exist - */ -const char *fdt_get_alias(const void *fdt, const char *name); - -/** - * fdt_get_path - determine the full path of a node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose path to find - * @buf: character buffer to contain the returned path (will be overwritten) - * @buflen: size of the character buffer at buf - * - * fdt_get_path() computes the full path of the node at offset - * nodeoffset, and records that path in the buffer at buf. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * 0, on success - * buf contains the absolute path of the node at - * nodeoffset, as a NUL-terminated string. - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) - * characters and will not fit in the given buffer. - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); - -/** - * fdt_supernode_atdepth_offset - find a specific ancestor of a node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * @supernodedepth: depth of the ancestor to find - * @nodedepth: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_supernode_atdepth_offset() finds an ancestor of the given node - * at a specific depth from the root (where the root itself has depth - * 0, its immediate subnodes depth 1 and so forth). So - * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); - * will always return 0, the offset of the root node. If the node at - * nodeoffset has depth D, then: - * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); - * will return nodeoffset itself. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * structure block offset of the node at node offset's ancestor - * of depth supernodedepth (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of - * nodeoffset - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, - int supernodedepth, int *nodedepth); - -/** - * fdt_node_depth - find the depth of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * - * fdt_node_depth() finds the depth of a given node. The root node - * has depth 0, its immediate subnodes depth 1 and so forth. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * depth of the node at nodeoffset (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_depth(const void *fdt, int nodeoffset); - -/** - * fdt_parent_offset - find the parent of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * - * fdt_parent_offset() locates the parent node of a given node (that - * is, it finds the offset of the node which contains the node at - * nodeoffset as a subnode). - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset, *twice*. - * - * returns: - * structure block offset of the parent of the node at nodeoffset - * (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_parent_offset(const void *fdt, int nodeoffset); - -/** - * fdt_node_offset_by_prop_value - find nodes with a given property value - * @fdt: pointer to the device tree blob - * @startoffset: only find nodes after this offset - * @propname: property name to check - * @propval: property value to search for - * @proplen: length of the value in propval - * - * fdt_node_offset_by_prop_value() returns the offset of the first - * node after startoffset, which has a property named propname whose - * value is of length proplen and has value equal to propval; or if - * startoffset is -1, the very first such node in the tree. - * - * To iterate through all nodes matching the criterion, the following - * idiom can be used: - * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, - * propval, proplen); - * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here - * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, - * propval, proplen); - * } - * - * Note the -1 in the first call to the function, if 0 is used here - * instead, the function will never locate the root node, even if it - * matches the criterion. - * - * returns: - * structure block offset of the located node (>= 0, >startoffset), - * on success - * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the - * tree after startoffset - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, - const char *propname, - const void *propval, int proplen); - -/** - * fdt_node_offset_by_phandle - find the node with a given phandle - * @fdt: pointer to the device tree blob - * @phandle: phandle value - * - * fdt_node_offset_by_phandle() returns the offset of the node - * which has the given phandle value. If there is more than one node - * in the tree with the given phandle (an invalid tree), results are - * undefined. - * - * returns: - * structure block offset of the located node (>= 0), on success - * -FDT_ERR_NOTFOUND, no node with that phandle exists - * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); - -/** - * fdt_node_check_compatible: check a node's compatible property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @compatible: string to match against - * - * - * fdt_node_check_compatible() returns 0 if the given node contains a - * 'compatible' property with the given string as one of its elements, - * it returns non-zero otherwise, or on error. - * - * returns: - * 0, if the node has a 'compatible' property listing the given string - * 1, if the node has a 'compatible' property, but it does not list - * the given string - * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property - * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_check_compatible(const void *fdt, int nodeoffset, - const char *compatible); - -/** - * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value - * @fdt: pointer to the device tree blob - * @startoffset: only find nodes after this offset - * @compatible: 'compatible' string to match against - * - * fdt_node_offset_by_compatible() returns the offset of the first - * node after startoffset, which has a 'compatible' property which - * lists the given compatible string; or if startoffset is -1, the - * very first such node in the tree. - * - * To iterate through all nodes matching the criterion, the following - * idiom can be used: - * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); - * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here - * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); - * } - * - * Note the -1 in the first call to the function, if 0 is used here - * instead, the function will never locate the root node, even if it - * matches the criterion. - * - * returns: - * structure block offset of the located node (>= 0, >startoffset), - * on success - * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the - * tree after startoffset - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_compatible(const void *fdt, int startoffset, - const char *compatible); - -/** - * fdt_stringlist_contains - check a string list property for a string - * @strlist: Property containing a list of strings to check - * @listlen: Length of property - * @str: String to search for - * - * This is a utility function provided for convenience. The list contains - * one or more strings, each terminated by \0, as is found in a device tree - * "compatible" property. - * - * @return: 1 if the string is found in the list, 0 not found, or invalid list - */ -int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); - -/** - * fdt_stringlist_count - count the number of strings in a string list - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @return: - * the number of strings in the given property - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist - */ -int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); - -/** - * fdt_stringlist_search - find a string in a string list and return its index - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @string: string to look up in the string list - * - * Note that it is possible for this function to succeed on property values - * that are not NUL-terminated. That's because the function will stop after - * finding the first occurrence of @string. This can for example happen with - * small-valued cell properties, such as #address-cells, when searching for - * the empty string. - * - * @return: - * the index of the string in the list of strings - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist or does not contain - * the given string - */ -int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, - const char *string); - -/** - * fdt_stringlist_get() - obtain the string at a given index in a string list - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @index: index of the string to return - * @lenp: return location for the string length or an error code on failure - * - * Note that this will successfully extract strings from properties with - * non-NUL-terminated values. For example on small-valued cell properties - * this function will return the empty string. - * - * If non-NULL, the length of the string (on success) or a negative error-code - * (on failure) will be stored in the integer pointer to by lenp. - * - * @return: - * A pointer to the string at the given index in the string list or NULL on - * failure. On success the length of the string will be stored in the memory - * location pointed to by the lenp parameter, if non-NULL. On failure one of - * the following negative error codes will be returned in the lenp parameter - * (if non-NULL): - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist - */ -const char *fdt_stringlist_get(const void *fdt, int nodeoffset, - const char *property, int index, - int *lenp); - -/**********************************************************************/ -/* Read-only functions (addressing related) */ -/**********************************************************************/ - -/** - * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells - * - * This is the maximum value for #address-cells, #size-cells and - * similar properties that will be processed by libfdt. IEE1275 - * requires that OF implementations handle values up to 4. - * Implementations may support larger values, but in practice higher - * values aren't used. - */ -#define FDT_MAX_NCELLS 4 - -/** - * fdt_address_cells - retrieve address size for a bus represented in the tree - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to find the address size for - * - * When the node has a valid #address-cells property, returns its value. - * - * returns: - * 0 <= n < FDT_MAX_NCELLS, on success - * 2, if the node has no #address-cells property - * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid - * #address-cells property - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_address_cells(const void *fdt, int nodeoffset); - -/** - * fdt_size_cells - retrieve address range size for a bus represented in the - * tree - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to find the address range size for - * - * When the node has a valid #size-cells property, returns its value. - * - * returns: - * 0 <= n < FDT_MAX_NCELLS, on success - * 2, if the node has no #address-cells property - * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid - * #size-cells property - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_size_cells(const void *fdt, int nodeoffset); - - -/**********************************************************************/ -/* Write-in-place functions */ -/**********************************************************************/ - -/** - * fdt_setprop_inplace_namelen_partial - change a property's value, - * but not its size - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @namelen: number of characters of name to consider - * @idx: index of the property to change in the array - * @val: pointer to data to replace the property value with - * @len: length of the property value - * - * Identical to fdt_setprop_inplace(), but modifies the given property - * starting from the given index, and using only the first characters - * of the name. It is useful when you want to manipulate only one value of - * an array and you have a string that doesn't end with \0. - */ -int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, - const char *name, int namelen, - uint32_t idx, const void *val, - int len); - -/** - * fdt_setprop_inplace - change a property's value, but not its size - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: pointer to data to replace the property value with - * @len: length of the property value - * - * fdt_setprop_inplace() replaces the value of a given property with - * the data in val, of length len. This function cannot change the - * size of a property, and so will only work if len is equal to the - * current length of the property. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if len is not equal to the property's current length - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value to replace the property with - * - * fdt_setprop_inplace_u32() replaces the value of a given property - * with the 32-bit integer value in val, converting val to big-endian - * if necessary. This function cannot change the size of a property, - * and so will only work if the property already exists and has length - * 4. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value to replace the property with - * - * fdt_setprop_inplace_u64() replaces the value of a given property - * with the 64-bit integer value in val, converting val to big-endian - * if necessary. This function cannot change the size of a property, - * and so will only work if the property already exists and has length - * 8. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, - const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_inplace_cell - change the value of a single-cell property - * - * This is an alternative name for fdt_setprop_inplace_u32() - */ -static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_nop_property - replace a property with nop tags - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to nop - * @name: name of the property to nop - * - * fdt_nop_property() will replace a given property's representation - * in the blob with FDT_NOP tags, effectively removing it from the - * tree. - * - * This function will alter only the bytes in the blob which contain - * the property, and will not alter or move any other part of the - * tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_nop_property(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_nop_node - replace a node (subtree) with nop tags - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to nop - * - * fdt_nop_node() will replace a given node's representation in the - * blob, including all its subnodes, if any, with FDT_NOP tags, - * effectively removing it from the tree. - * - * This function will alter only the bytes in the blob which contain - * the node and its properties and subnodes, and will not alter or - * move any other part of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_nop_node(void *fdt, int nodeoffset); - -/**********************************************************************/ -/* Sequential write functions */ -/**********************************************************************/ - -int fdt_create(void *buf, int bufsize); -int fdt_resize(void *fdt, void *buf, int bufsize); -int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); -int fdt_finish_reservemap(void *fdt); -int fdt_begin_node(void *fdt, const char *name); -int fdt_property(void *fdt, const char *name, const void *val, int len); -static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_property(fdt, name, &tmp, sizeof(tmp)); -} -static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_property(fdt, name, &tmp, sizeof(tmp)); -} -static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) -{ - return fdt_property_u32(fdt, name, val); -} - -/** - * fdt_property_placeholder - add a new property and return a ptr to its value - * - * @fdt: pointer to the device tree blob - * @name: name of property to add - * @len: length of property value in bytes - * @valp: returns a pointer to where where the value should be placed - * - * returns: - * 0, on success - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_NOSPACE, standard meanings - */ -int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); - -#define fdt_property_string(fdt, name, str) \ - fdt_property(fdt, name, str, strlen(str)+1) -int fdt_end_node(void *fdt); -int fdt_finish(void *fdt); - -/**********************************************************************/ -/* Read-write functions */ -/**********************************************************************/ - -int fdt_create_empty_tree(void *buf, int bufsize); -int fdt_open_into(const void *fdt, void *buf, int bufsize); -int fdt_pack(void *fdt); - -/** - * fdt_add_mem_rsv - add one memory reserve map entry - * @fdt: pointer to the device tree blob - * @address, @size: 64-bit values (native endian) - * - * Adds a reserve map entry to the given blob reserving a region at - * address address of length size. - * - * This function will insert data into the reserve map and will - * therefore change the indexes of some entries in the table. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new reservation entry - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); - -/** - * fdt_del_mem_rsv - remove a memory reserve map entry - * @fdt: pointer to the device tree blob - * @n: entry to remove - * - * fdt_del_mem_rsv() removes the n-th memory reserve map entry from - * the blob. - * - * This function will delete data from the reservation table and will - * therefore change the indexes of some entries in the table. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there - * are less than n+1 reserve map entries) - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_del_mem_rsv(void *fdt, int n); - -/** - * fdt_set_name - change the name of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of a node - * @name: name to give the node - * - * fdt_set_name() replaces the name (including unit address, if any) - * of the given node with the given string. NOTE: this function can't - * efficiently check if the new name is unique amongst the given - * node's siblings; results are undefined if this function is invoked - * with a name equal to one of the given node's siblings. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob - * to contain the new name - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_set_name(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_setprop - create or change a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: pointer to data to set the property value to - * @len: length of the property value - * - * fdt_setprop() sets the value of the named property in the given - * node to the given value and length, creating the property if it - * does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_setprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_setprop_u32 - set a property to a 32-bit integer - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value for the property (native endian) - * - * fdt_setprop_u32() sets the value of the named property in the given - * node to the given 32-bit integer value (converting to big-endian if - * necessary), or creates a new property with that value if it does - * not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, - uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_u64 - set a property to a 64-bit integer - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value for the property (native endian) - * - * fdt_setprop_u64() sets the value of the named property in the given - * node to the given 64-bit integer value (converting to big-endian if - * necessary), or creates a new property with that value if it does - * not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, - uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_cell - set a property to a single cell value - * - * This is an alternative name for fdt_setprop_u32() - */ -static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, - uint32_t val) -{ - return fdt_setprop_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_setprop_string - set a property to a string value - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @str: string value for the property - * - * fdt_setprop_string() sets the value of the named property in the - * given node to the given string value (using the length of the - * string to determine the new length of the property), or creates a - * new property with that value if it does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_setprop_string(fdt, nodeoffset, name, str) \ - fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) - -/** - * fdt_appendprop - append to or create a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to append to - * @val: pointer to data to append to the property value - * @len: length of the data to append to the property value - * - * fdt_appendprop() appends the value to the named property in the - * given node, creating the property if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_appendprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_appendprop_u32 - append a 32-bit integer value to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value to append to the property (native endian) - * - * fdt_appendprop_u32() appends the given 32-bit integer value - * (converting to big-endian if necessary) to the value of the named - * property in the given node, or creates a new property with that - * value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_appendprop_u64 - append a 64-bit integer value to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value to append to the property (native endian) - * - * fdt_appendprop_u64() appends the given 64-bit integer value - * (converting to big-endian if necessary) to the value of the named - * property in the given node, or creates a new property with that - * value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, - const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_appendprop_cell - append a single cell value to a property - * - * This is an alternative name for fdt_appendprop_u32() - */ -static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - return fdt_appendprop_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_appendprop_string - append a string to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @str: string value to append to the property - * - * fdt_appendprop_string() appends the given string to the value of - * the named property in the given node, or creates a new property - * with that value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ - fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) - -/** - * fdt_delprop - delete a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to nop - * @name: name of the property to nop - * - * fdt_del_property() will delete the given property. - * - * This function will delete data from the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_delprop(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_add_subnode_namelen - creates a new node based on substring - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * @namelen: number of characters of name to consider - * - * Identical to fdt_add_subnode(), but use only the first namelen - * characters of name as the name of the new node. This is useful for - * creating subnodes based on a portion of a larger string, such as a - * full path. - */ -int fdt_add_subnode_namelen(void *fdt, int parentoffset, - const char *name, int namelen); - -/** - * fdt_add_subnode - creates a new node - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * - * fdt_add_subnode() creates a new node as a subnode of the node at - * structure block offset parentoffset, with the given name (which - * should include the unit address, if any). - * - * This function will insert data into the blob, and will therefore - * change the offsets of some existing nodes. - - * returns: - * structure block offset of the created nodeequested subnode (>=0), on - * success - * -FDT_ERR_NOTFOUND, if the requested subnode does not exist - * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE - * tag - * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of - * the given name - * -FDT_ERR_NOSPACE, if there is insufficient free space in the - * blob to contain the new node - * -FDT_ERR_NOSPACE - * -FDT_ERR_BADLAYOUT - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_add_subnode(void *fdt, int parentoffset, const char *name); - -/** - * fdt_del_node - delete a node (subtree) - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to nop - * - * fdt_del_node() will remove the given node, including all its - * subnodes if any, from the blob. - * - * This function will delete data from the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_del_node(void *fdt, int nodeoffset); - -/** - * fdt_overlay_apply - Applies a DT overlay on a base DT - * @fdt: pointer to the base device tree blob - * @fdto: pointer to the device tree overlay blob - * - * fdt_overlay_apply() will apply the given device tree overlay on the - * given base device tree. - * - * Expect the base device tree to be modified, even if the function - * returns an error. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there's not enough space in the base device tree - * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or - * properties in the base DT - * -FDT_ERR_BADPHANDLE, - * -FDT_ERR_BADOVERLAY, - * -FDT_ERR_NOPHANDLES, - * -FDT_ERR_INTERNAL, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADOFFSET, - * -FDT_ERR_BADPATH, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_overlay_apply(void *fdt, void *fdto); - -/**********************************************************************/ -/* Debugging / informational functions */ -/**********************************************************************/ - -const char *fdt_strerror(int errval); - -/** - * fdt_remove_unused_strings() - Remove any unused strings from an FDT - * - * This creates a new device tree in @new with unused strings removed. The - * called can then use fdt_pack() to minimise the space consumed. - * - * @old: Old device tree blog - * @new: Place to put new device tree blob, which must be as large as - * @old - * @return - * 0, on success - * -FDT_ERR_BADOFFSET, corrupt device tree - * -FDT_ERR_NOSPACE, out of space, which should not happen unless there - * is something very wrong with the device tree input - */ -int fdt_remove_unused_strings(const void *old, void *new); - -struct fdt_region { - int offset; - int size; -}; - -/* - * Flags for fdt_find_regions() - * - * Add a region for the string table (always the last region) - */ -#define FDT_REG_ADD_STRING_TAB (1 << 0) - -/* - * Add all supernodes of a matching node/property, useful for creating a - * valid subset tree - */ -#define FDT_REG_SUPERNODES (1 << 1) - -/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */ -#define FDT_REG_DIRECT_SUBNODES (1 << 2) - -/* Add all subnodes of a matching node */ -#define FDT_REG_ALL_SUBNODES (1 << 3) - -/* Add a region for the mem_rsvmap table (always the first region) */ -#define FDT_REG_ADD_MEM_RSVMAP (1 << 4) - -/* Indicates what an fdt part is (node, property, value) */ -#define FDT_IS_NODE (1 << 0) -#define FDT_IS_PROP (1 << 1) -#define FDT_IS_VALUE (1 << 2) /* not supported */ -#define FDT_IS_COMPAT (1 << 3) /* used internally */ -#define FDT_NODE_HAS_PROP (1 << 4) /* node contains prop */ - -#define FDT_ANY_GLOBAL (FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \ - FDT_IS_COMPAT) -#define FDT_IS_ANY 0x1f /* all the above */ - -/* We set a reasonable limit on the number of nested nodes */ -#define FDT_MAX_DEPTH 32 - -/* Decribes what we want to include from the current tag */ -enum want_t { - WANT_NOTHING, - WANT_NODES_ONLY, /* No properties */ - WANT_NODES_AND_PROPS, /* Everything for one level */ - WANT_ALL_NODES_AND_PROPS /* Everything for all levels */ -}; - -/* Keeps track of the state at parent nodes */ -struct fdt_subnode_stack { - int offset; /* Offset of node */ - enum want_t want; /* The 'want' value here */ - int included; /* 1 if we included this node, 0 if not */ -}; - -struct fdt_region_ptrs { - int depth; /* Current tree depth */ - int done; /* What we have completed scanning */ - enum want_t want; /* What we are currently including */ - char *end; /* Pointer to end of full node path */ - int nextoffset; /* Next node offset to check */ -}; - -/* The state of our finding algortihm */ -struct fdt_region_state { - struct fdt_subnode_stack stack[FDT_MAX_DEPTH]; /* node stack */ - struct fdt_region *region; /* Contains list of regions found */ - int count; /* Numnber of regions found */ - const void *fdt; /* FDT blob */ - int max_regions; /* Maximum regions to find */ - int can_merge; /* 1 if we can merge with previous region */ - int start; /* Start position of current region */ - struct fdt_region_ptrs ptrs; /* Pointers for what we are up to */ -}; - -/** - * fdt_find_regions() - find regions in device tree - * - * Given a list of nodes to include and properties to exclude, find - * the regions of the device tree which describe those included parts. - * - * The intent is to get a list of regions which will be invariant provided - * those parts are invariant. For example, if you request a list of regions - * for all nodes but exclude the property "data", then you will get the - * same region contents regardless of any change to "data" properties. - * - * This function can be used to produce a byte-stream to send to a hashing - * function to verify that critical parts of the FDT have not changed. - * - * Nodes which are given in 'inc' are included in the region list, as - * are the names of the immediate subnodes nodes (but not the properties - * or subnodes of those subnodes). - * - * For eaxample "/" means to include the root node, all root properties - * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter - * ensures that we capture the names of the subnodes. In a hashing situation - * it prevents the root node from changing at all Any change to non-excluded - * properties, names of subnodes or number of subnodes would be detected. - * - * When used with FITs this provides the ability to hash and sign parts of - * the FIT based on different configurations in the FIT. Then it is - * impossible to change anything about that configuration (include images - * attached to the configuration), but it may be possible to add new - * configurations, new images or new signatures within the existing - * framework. - * - * Adding new properties to a device tree may result in the string table - * being extended (if the new property names are different from those - * already added). This function can optionally include a region for - * the string table so that this can be part of the hash too. - * - * The device tree header is not included in the list. - * - * @fdt: Device tree to check - * @inc: List of node paths to included - * @inc_count: Number of node paths in list - * @exc_prop: List of properties names to exclude - * @exc_prop_count: Number of properties in exclude list - * @region: Returns list of regions - * @max_region: Maximum length of region list - * @path: Pointer to a temporary string for the function to use for - * building path names - * @path_len: Length of path, must be large enough to hold the longest - * path in the tree - * @add_string_tab: 1 to add a region for the string table - * @return number of regions in list. If this is >max_regions then the - * region array was exhausted. You should increase max_regions and try - * the call again. - */ -int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - char * const exc_prop[], int exc_prop_count, - struct fdt_region region[], int max_regions, - char *path, int path_len, int add_string_tab); - -/** - * fdt_first_region() - find regions in device tree - * - * Given a nodes and properties to include and properties to exclude, find - * the regions of the device tree which describe those included parts. - * - * The use for this function is twofold. Firstly it provides a convenient - * way of performing a structure-aware grep of the tree. For example it is - * possible to grep for a node and get all the properties associated with - * that node. Trees can be subsetted easily, by specifying the nodes that - * are required, and then writing out the regions returned by this function. - * This is useful for small resource-constrained systems, such as boot - * loaders, which want to use an FDT but do not need to know about all of - * it. - * - * Secondly it makes it easy to hash parts of the tree and detect changes. - * The intent is to get a list of regions which will be invariant provided - * those parts are invariant. For example, if you request a list of regions - * for all nodes but exclude the property "data", then you will get the - * same region contents regardless of any change to "data" properties. - * - * This function can be used to produce a byte-stream to send to a hashing - * function to verify that critical parts of the FDT have not changed. - * Note that semantically null changes in order could still cause false - * hash misses. Such reordering might happen if the tree is regenerated - * from source, and nodes are reordered (the bytes-stream will be emitted - * in a different order and mnay hash functions will detect this). However - * if an existing tree is modified using libfdt functions, such as - * fdt_add_subnode() and fdt_setprop(), then this problem is avoided. - * - * The nodes/properties to include/exclude are defined by a function - * provided by the caller. This function is called for each node and - * property, and must return: - * - * 0 - to exclude this part - * 1 - to include this part - * -1 - for FDT_IS_PROP only: no information is available, so include - * if its containing node is included - * - * The last case is only used to deal with properties. Often a property is - * included if its containing node is included - this is the case where - * -1 is returned.. However if the property is specifically required to be - * included/excluded, then 0 or 1 can be returned. Note that including a - * property when the FDT_REG_SUPERNODES flag is given will force its - * containing node to be included since it is not valid to have a property - * that is not in a node. - * - * Using the information provided, the inclusion of a node can be controlled - * either by a node name or its compatible string, or any other property - * that the function can determine. - * - * As an example, including node "/" means to include the root node and all - * root properties. A flag provides a way of also including supernodes (of - * which there is none for the root node), and another flag includes - * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and - * FDT_END_NODE of all subnodes of /. - * - * The subnode feature helps in a hashing situation since it prevents the - * root node from changing at all. Any change to non-excluded properties, - * names of subnodes or number of subnodes would be detected. - * - * When used with FITs this provides the ability to hash and sign parts of - * the FIT based on different configurations in the FIT. Then it is - * impossible to change anything about that configuration (include images - * attached to the configuration), but it may be possible to add new - * configurations, new images or new signatures within the existing - * framework. - * - * Adding new properties to a device tree may result in the string table - * being extended (if the new property names are different from those - * already added). This function can optionally include a region for - * the string table so that this can be part of the hash too. This is always - * the last region. - * - * The FDT also has a mem_rsvmap table which can also be included, and is - * always the first region if so. - * - * The device tree header is not included in the region list. Since the - * contents of the FDT are changing (shrinking, often), the caller will need - * to regenerate the header anyway. - * - * @fdt: Device tree to check - * @h_include: Function to call to determine whether to include a part or - * not: - * - * @priv: Private pointer as passed to fdt_find_regions() - * @fdt: Pointer to FDT blob - * @offset: Offset of this node / property - * @type: Type of this part, FDT_IS_... - * @data: Pointer to data (node name, property name, compatible - * string, value (not yet supported) - * @size: Size of data, or 0 if none - * @return 0 to exclude, 1 to include, -1 if no information is - * available - * @priv: Private pointer passed to h_include - * @region: Returns list of regions, sorted by offset - * @max_regions: Maximum length of region list - * @path: Pointer to a temporary string for the function to use for - * building path names - * @path_len: Length of path, must be large enough to hold the longest - * path in the tree - * @flags: Various flags that control the region algortihm, see - * FDT_REG_... - * @return number of regions in list. If this is >max_regions then the - * region array was exhausted. You should increase max_regions and try - * the call again. Only the first max_regions elements are available in the - * array. - * - * On error a -ve value is return, which can be: - * - * -FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags - * -FDT_ERR_BADLAYOUT - * -FDT_ERR_NOSPACE (path area is too small) - */ -int fdt_first_region(const void *fdt, - int (*h_include)(void *priv, const void *fdt, int offset, - int type, const char *data, int size), - void *priv, struct fdt_region *region, - char *path, int path_len, int flags, - struct fdt_region_state *info); - -/** fdt_next_region() - find next region - * - * See fdt_first_region() for full description. This function finds the - * next region according to the provided parameters, which must be the same - * as passed to fdt_first_region(). - * - * This function can additionally return -FDT_ERR_NOTFOUND when there are no - * more regions - */ -int fdt_next_region(const void *fdt, - int (*h_include)(void *priv, const void *fdt, int offset, - int type, const char *data, int size), - void *priv, struct fdt_region *region, - char *path, int path_len, int flags, - struct fdt_region_state *info); - -/** - * fdt_add_alias_regions() - find aliases that point to existing regions - * - * Once a device tree grep is complete some of the nodes will be present - * and some will have been dropped. This function checks all the alias nodes - * to figure out which points point to nodes which are still present. These - * aliases need to be kept, along with the nodes they reference. - * - * Given a list of regions function finds the aliases that still apply and - * adds more regions to the list for these. This function is called after - * fdt_next_region() has finished returning regions and requires the same - * state. - * - * @fdt: Device tree file to reference - * @region: List of regions that will be kept - * @count: Number of regions - * @max_regions: Number of entries that can fit in @region - * @info: Region state as returned from fdt_next_region() - * @return new number of regions in @region (i.e. count + the number added) - * or -FDT_ERR_NOSPACE if there was not enough space. - */ -int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, - int max_regions, struct fdt_region_state *info); - -#endif /* _LIBFDT_H */ +#include <../lib/libfdt/libfdt.h> diff --git a/include/linux/compat.h b/include/linux/compat.h index 03f9bef..2336b56 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -109,7 +109,7 @@ static inline void kmem_cache_destroy(struct kmem_cache *cachep) #define WARN_ON(condition) ({ \ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ - printf("WARNING in %s line %d\n", __FILE__, __LINE__);; \ + printf("WARNING in %s line %d\n", __FILE__, __LINE__); \ unlikely(__ret_warn_on); \ }) diff --git a/include/mpc5xx.h b/include/mpc5xx.h deleted file mode 100644 index 6c170dc..0000000 --- a/include/mpc5xx.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: mpc5xx.h - * - * Discription: mpc5xx specific definitions - * - */ - -#ifndef __MPC5XX_H__ -#define __MPC5XX_H__ - - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*----------------------------------------------------------------------- - * ISB bit in IMMR to set internal memory map - */ - -#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control Register - */ -#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */ -#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ -#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ -#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ -#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ -#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ -#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register - */ -#define SIUMCR_EARB 0x80000000 /* External Arbitration */ -#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ -#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ -#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ -#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ -#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ -#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ -#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ -#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ -#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ -#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ -#define SIUMCR_DBGC01 0x00200000 /* - " - */ -#define SIUMCR_DBGC10 0x00400000 /* - " - */ -#define SIUMCR_DBGC11 0x00600000 /* - " - */ -#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ -#define SIUMCR_DBPC01 0x00080000 /* - " - */ -#define SIUMCR_DBPC10 0x00100000 /* - " - */ -#define SIUMCR_DBPC11 0x00180000 /* - " - */ -#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ -#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ -#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ -#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ -#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ -#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ -#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ -#define SIUMCR_SC10 0x00004000 /* Single adress show */ -#define SIUMCR_SC11 0x00006000 /* Single adress */ -#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */ -#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ -#define SIUMCR_MLRC01 0x00000400 /* - " - */ -#define SIUMCR_MLRC10 0x00000800 /* - " - */ -#define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control Register - */ -#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */ -#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */ -#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control Register - */ -#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ -#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - */ -#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */ -#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ -#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ -#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ -#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ -#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ -#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ -#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ -#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ -#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - */ -#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ -#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ -#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ -#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ -#define SCCR_EBDF11 0x00060000 /* reserved */ -#define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ -#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ -#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ -#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ - -/*----------------------------------------------------------------------- - * MC - Memory Controller - */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ -#define BR_LBDIR 0x00000008 /* Late burst data in progess */ -#define BR_SETA 0x00000004 /* External Data Acknowledge */ -#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ -#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ -#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ -#define OR_TRLX 0x00000001 /* Timing relaxed */ -#define OR_BSCY 0x00000060 /* Burst beats length in clocks */ -#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ -#define OR_CSNT 0x00000800 /* Chip-select negotation time */ -#define OR_ETHR 0x00000100 /* Extended hold time on read */ -#define OR_ADDR_MK_FF 0xFF000000 -#define OR_ADDR_MK_FFFF 0xFFFF0000 - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */ - - -#define NR_IRQS 0 /* Place this later in a separate file */ - -/*----------------------------------------------------------------------- - * SCI - Serial communication interface - */ - -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ -#define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ -#define SCI_M_11 0x0200 /* Frame size is 11 bit */ -#define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ -#define SCI_PORT_2 ((int)2) - -#endif /* __MPC5XX_H__ */ diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h deleted file mode 100644 index 10daf09..0000000 --- a/include/mpc5xxx.h +++ /dev/null @@ -1,893 +0,0 @@ -/* - * include/asm-ppc/mpc5xxx.h - * - * Prototypes, etc. for the Motorola MPC5xxx - * embedded cpu chips - * - * 2003 (c) MontaVista, Software, Inc. - * Author: Dale Farnsworth - * - * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASMPPC_MPC5XXX_H -#define __ASMPPC_MPC5XXX_H - -#include - -/* Processor name */ -#define CPU_ID_STR "MPC5200" - -/* Exception offsets (PowerPC standard) */ -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET - -/* useful macros for manipulating CSx_START/STOP */ -#define START_REG(start) ((start) >> 16) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) - -/* Internal memory map */ - -#define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004) -#define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008) -#define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c) -#define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010) -#define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014) -#define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018) -#define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c) -#define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020) -#define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024) -#define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028) -#define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c) -#define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030) -#define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c) -#define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) -#define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) - -#define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) -#define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) -#define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) -#define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) -#define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) -#define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) - -#define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) -#define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) -#define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300) -#define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500) -#define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600) -#define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00) -#define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00) -#define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00) -#define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00) -#define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000) -#define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) -#define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) - -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) -#define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) -#define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) -#define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) - -#define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) -#define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) - -#define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) -#define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) - -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) -#define MPC5XXX_SRAM_SIZE (16*1024) - -/* SDRAM Controller */ -#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) -#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) -#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) -#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) - -/* Clock Distribution Module */ -#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) -#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) -#define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008) -#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) -#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) -#define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014) -#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) - -/* Local Plus Bus interface */ -#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) -#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) -#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) -#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) -#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) -#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) -#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG -#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) -#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) -#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) -#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) -#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) - -/* XLB Arbiter registers */ -#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) -#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) -#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) - -/* GPIO registers */ -#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) - -/* Standard GPIO registers (simple, output only and simple interrupt */ -#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) -#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) -#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) -#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) -#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) -#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) -#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) -#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) -#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) -#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) - -/* WakeUp GPIO registers */ -#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) -#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) -#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) -#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) -#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) - -/* GPIO pins, for Rev.B chip */ -#define GPIO_WKUP_7 0x80000000UL -#define GPIO_PSC6_0 0x10000000UL -#define GPIO_PSC3_9 0x04000000UL -#define GPIO_PSC1_4 0x01000000UL -#define GPIO_PSC2_4 0x02000000UL - -#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL -#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL - -#define MPC5XXX_GPIO_SINT_ETH_16 0x80 -#define MPC5XXX_GPIO_SINT_ETH_15 0x40 -#define MPC5XXX_GPIO_SINT_ETH_14 0x20 -#define MPC5XXX_GPIO_SINT_ETH_13 0x10 -#define MPC5XXX_GPIO_SINT_USB1_9 0x08 -#define MPC5XXX_GPIO_SINT_PSC3_8 0x04 -#define MPC5XXX_GPIO_SINT_PSC3_5 0x02 -#define MPC5XXX_GPIO_SINT_PSC3_4 0x01 - -#define MPC5XXX_GPIO_WKUP_7 0x80 -#define MPC5XXX_GPIO_WKUP_6 0x40 -#define MPC5XXX_GPIO_WKUP_PSC6_1 0x20 -#define MPC5XXX_GPIO_WKUP_PSC6_0 0x10 -#define MPC5XXX_GPIO_WKUP_ETH17 0x08 -#define MPC5XXX_GPIO_WKUP_PSC3_9 0x04 -#define MPC5XXX_GPIO_WKUP_PSC2_4 0x02 -#define MPC5XXX_GPIO_WKUP_PSC1_4 0x01 - -/* PCI registers */ -#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) -#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) -#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) -#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) -#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) -#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) -#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) -#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) -#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) -#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) - -/* Interrupt Controller registers */ -#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) -#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) -#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) -#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) -#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) -#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) -#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) -#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) -#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) -#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) -#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) -#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) -#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) - -#define NR_IRQS 64 - -/* IRQ mapping - these are our logical IRQ numbers */ -#define MPC5XXX_CRIT_IRQ_NUM 4 -#define MPC5XXX_MAIN_IRQ_NUM 17 -#define MPC5XXX_SDMA_IRQ_NUM 17 -#define MPC5XXX_PERP_IRQ_NUM 23 - -#define MPC5XXX_CRIT_IRQ_BASE 1 -#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) -#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) -#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) - -#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) -#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) -#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) -#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) - -#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) -#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) -#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) -#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) -#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) -#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) -#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) -#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) -#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) -#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) -#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) -#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) -#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) -#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) -#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) - -#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) -#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) -#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) -#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) -#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) -#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) -#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) -#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) -#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) -#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) -#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) -#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) -#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) -#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) -#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) -#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) -#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) -#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) -#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) -#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) -#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) -#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) -#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) -#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) - -/* General Purpose Timers registers */ -#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) -#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) -#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) -#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) -#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) -#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) -#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) -#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) -#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) -#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) -#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) -#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) -#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) -#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) -#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) -#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) -#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) -#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) -#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) -#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) -#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) -#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) -#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) -#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) - -#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) - -#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) - -/* ATA registers */ -#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) -#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) -#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) -#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -/* SPI control register 1 bits */ -#define SPI_CR_LSBFE 0x01 -#define SPI_CR_SSOE 0x02 -#define SPI_CR_CPHA 0x04 -#define SPI_CR_CPOL 0x08 -#define SPI_CR_MSTR 0x10 -#define SPI_CR_SWOM 0x20 -#define SPI_CR_SPE 0x40 -#define SPI_CR_SPIE 0x80 - -/* SPI status register bits */ -#define SPI_SR_MODF 0x10 -#define SPI_SR_WCOL 0x40 -#define SPI_SR_SPIF 0x80 - -/* SPI port data register bits */ -#define SPI_PDR_SS 0x08 - -/* Programmable Serial Controller (PSC) status register bits */ -#define PSC_SR_CDE 0x0080 -#define PSC_SR_RXRDY 0x0100 -#define PSC_SR_RXFULL 0x0200 -#define PSC_SR_TXRDY 0x0400 -#define PSC_SR_TXEMP 0x0800 -#define PSC_SR_OE 0x1000 -#define PSC_SR_PE 0x2000 -#define PSC_SR_FE 0x4000 -#define PSC_SR_RB 0x8000 - -/* PSC Command values */ -#define PSC_RX_ENABLE 0x0001 -#define PSC_RX_DISABLE 0x0002 -#define PSC_TX_ENABLE 0x0004 -#define PSC_TX_DISABLE 0x0008 -#define PSC_SEL_MODE_REG_1 0x0010 -#define PSC_RST_RX 0x0020 -#define PSC_RST_TX 0x0030 -#define PSC_RST_ERR_STAT 0x0040 -#define PSC_RST_BRK_CHG_INT 0x0050 -#define PSC_START_BRK 0x0060 -#define PSC_STOP_BRK 0x0070 - -/* PSC Rx FIFO status bits */ -#define PSC_RX_FIFO_ERR 0x0040 -#define PSC_RX_FIFO_UF 0x0020 -#define PSC_RX_FIFO_OF 0x0010 -#define PSC_RX_FIFO_FR 0x0008 -#define PSC_RX_FIFO_FULL 0x0004 -#define PSC_RX_FIFO_ALARM 0x0002 -#define PSC_RX_FIFO_EMPTY 0x0001 - -/* PSC interrupt mask bits */ -#define PSC_IMR_TXRDY 0x0100 -#define PSC_IMR_RXRDY 0x0200 -#define PSC_IMR_DB 0x0400 -#define PSC_IMR_IPC 0x8000 - -/* PSC input port change bits */ -#define PSC_IPCR_CTS 0x01 -#define PSC_IPCR_DCD 0x02 - -/* PSC mode fields */ -#define PSC_MODE_5_BITS 0x00 -#define PSC_MODE_6_BITS 0x01 -#define PSC_MODE_7_BITS 0x02 -#define PSC_MODE_8_BITS 0x03 -#define PSC_MODE_PAREVEN 0x00 -#define PSC_MODE_PARODD 0x04 -#define PSC_MODE_PARFORCE 0x08 -#define PSC_MODE_PARNONE 0x10 -#define PSC_MODE_ERR 0x20 -#define PSC_MODE_FFULL 0x40 -#define PSC_MODE_RXRTS 0x80 - -#define PSC_MODE_ONE_STOP_5_BITS 0x00 -#define PSC_MODE_ONE_STOP 0x07 -#define PSC_MODE_TWO_STOP 0x0f - -/* ATA config fields */ -#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine - reset */ -#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ -#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt - in PIO */ -#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports - IORDY protocol */ - -#ifndef __ASSEMBLY__ -/* Memory map registers */ -struct mpc5xxx_mmap_ctl { - volatile u32 mbar; - volatile u32 cs0_start; /* 0x0004 */ - volatile u32 cs0_stop; - volatile u32 cs1_start; /* 0x000c */ - volatile u32 cs1_stop; - volatile u32 cs2_start; /* 0x0014 */ - volatile u32 cs2_stop; - volatile u32 cs3_start; /* 0x001c */ - volatile u32 cs3_stop; - volatile u32 cs4_start; /* 0x0024 */ - volatile u32 cs4_stop; - volatile u32 cs5_start; /* 0x002c */ - volatile u32 cs5_stop; - volatile u32 sdram0; /* 0x0034 */ - volatile u32 sdram1; /* 0x0038 */ - volatile u32 dummy1[4]; /* 0x003c */ - volatile u32 boot_start; /* 0x004c */ - volatile u32 boot_stop; - volatile u32 ipbi_ws_ctrl; /* 0x0054 */ - volatile u32 cs6_start; /* 0x0058 */ - volatile u32 cs6_stop; - volatile u32 cs7_start; /* 0x0060 */ - volatile u32 cs7_stop; -}; - -/* Clock distribution module */ -struct mpc5xxx_cdm { - volatile u32 jtagid; /* 0x0000 */ - volatile u32 porcfg; - volatile u32 brdcrmb; /* 0x0008 */ - volatile u32 cfg; - volatile u32 fourtyeight_fdc;/* 0x0010 */ - volatile u32 clock_enable; - volatile u32 system_osc; /* 0x0018 */ - volatile u32 ccscr; - volatile u32 sreset; /* 0x0020 */ - volatile u32 pll_status; - volatile u32 psc1_mccr; /* 0x0028 */ - volatile u32 psc2_mccr; - volatile u32 psc3_mccr; /* 0x0030 */ - volatile u32 psc6_mccr; -}; - -/* SDRAM controller */ -struct mpc5xxx_sdram { - volatile u32 mode; - volatile u32 ctrl; - volatile u32 config1; - volatile u32 config2; - volatile u32 dummy[32]; - volatile u32 sdelay; -}; - -struct mpc5xxx_lpb { - volatile u32 cs0_cfg; - volatile u32 cs1_cfg; - volatile u32 cs2_cfg; - volatile u32 cs3_cfg; - volatile u32 cs4_cfg; - volatile u32 cs5_cfg; - volatile u32 cs_ctrl; - volatile u32 cs_status; - volatile u32 cs6_cfg; - volatile u32 cs7_cfg; - volatile u32 cs_burst; - volatile u32 cs_deadcycle; -}; - - -struct mpc5xxx_psc { - volatile u8 mode; /* PSC + 0x00 */ - volatile u8 reserved0[3]; - union { /* PSC + 0x04 */ - volatile u16 status; - volatile u16 clock_select; - } sr_csr; -#define psc_status sr_csr.status -#define psc_clock_select sr_csr.clock_select - volatile u16 reserved1; - volatile u8 command; /* PSC + 0x08 */ - volatile u8 reserved2[3]; - union { /* PSC + 0x0c */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } buffer; -#define psc_buffer_8 buffer.buffer_8 -#define psc_buffer_16 buffer.buffer_16 -#define psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - volatile u8 ipcr; - volatile u8 acr; - } ipcr_acr; -#define psc_ipcr ipcr_acr.ipcr -#define psc_acr ipcr_acr.acr - volatile u8 reserved3[3]; - union { /* PSC + 0x14 */ - volatile u16 isr; - volatile u16 imr; - } isr_imr; -#define psc_isr isr_imr.isr -#define psc_imr isr_imr.imr - volatile u16 reserved4; - volatile u8 ctur; /* PSC + 0x18 */ - volatile u8 reserved5[3]; - volatile u8 ctlr; /* PSC + 0x1c */ - volatile u8 reserved6[3]; - volatile u16 ccr; /* PSC + 0x20 */ - volatile u8 reserved7[14]; - volatile u8 ivr; /* PSC + 0x30 */ - volatile u8 reserved8[3]; - volatile u8 ip; /* PSC + 0x34 */ - volatile u8 reserved9[3]; - volatile u8 op1; /* PSC + 0x38 */ - volatile u8 reserved10[3]; - volatile u8 op0; /* PSC + 0x3c */ - volatile u8 reserved11[3]; - volatile u32 sicr; /* PSC + 0x40 */ - volatile u8 ircr1; /* PSC + 0x44 */ - volatile u8 reserved12[3]; - volatile u8 ircr2; /* PSC + 0x44 */ - volatile u8 reserved13[3]; - volatile u8 irsdr; /* PSC + 0x4c */ - volatile u8 reserved14[3]; - volatile u8 irmdr; /* PSC + 0x50 */ - volatile u8 reserved15[3]; - volatile u8 irfdr; /* PSC + 0x54 */ - volatile u8 reserved16[3]; - volatile u16 rfnum; /* PSC + 0x58 */ - volatile u16 reserved17; - volatile u16 tfnum; /* PSC + 0x5c */ - volatile u16 reserved18; - volatile u32 rfdata; /* PSC + 0x60 */ - volatile u16 rfstat; /* PSC + 0x64 */ - volatile u16 reserved20; - volatile u8 rfcntl; /* PSC + 0x68 */ - volatile u8 reserved21[5]; - volatile u16 rfalarm; /* PSC + 0x6e */ - volatile u16 reserved22; - volatile u16 rfrptr; /* PSC + 0x72 */ - volatile u16 reserved23; - volatile u16 rfwptr; /* PSC + 0x76 */ - volatile u16 reserved24; - volatile u16 rflrfptr; /* PSC + 0x7a */ - volatile u16 reserved25; - volatile u16 rflwfptr; /* PSC + 0x7e */ - volatile u32 tfdata; /* PSC + 0x80 */ - volatile u16 tfstat; /* PSC + 0x84 */ - volatile u16 reserved26; - volatile u8 tfcntl; /* PSC + 0x88 */ - volatile u8 reserved27[5]; - volatile u16 tfalarm; /* PSC + 0x8e */ - volatile u16 reserved28; - volatile u16 tfrptr; /* PSC + 0x92 */ - volatile u16 reserved29; - volatile u16 tfwptr; /* PSC + 0x96 */ - volatile u16 reserved30; - volatile u16 tflrfptr; /* PSC + 0x9a */ - volatile u16 reserved31; - volatile u16 tflwfptr; /* PSC + 0x9e */ -}; - -struct mpc5xxx_intr { - volatile u32 per_mask; /* INTR + 0x00 */ - volatile u32 per_pri1; /* INTR + 0x04 */ - volatile u32 per_pri2; /* INTR + 0x08 */ - volatile u32 per_pri3; /* INTR + 0x0c */ - volatile u32 ctrl; /* INTR + 0x10 */ - volatile u32 main_mask; /* INTR + 0x14 */ - volatile u32 main_pri1; /* INTR + 0x18 */ - volatile u32 main_pri2; /* INTR + 0x1c */ - volatile u32 reserved1; /* INTR + 0x20 */ - volatile u32 enc_status; /* INTR + 0x24 */ - volatile u32 crit_status; /* INTR + 0x28 */ - volatile u32 main_status; /* INTR + 0x2c */ - volatile u32 per_status; /* INTR + 0x30 */ - volatile u32 reserved2; /* INTR + 0x34 */ - volatile u32 per_error; /* INTR + 0x38 */ -}; - -struct mpc5xxx_gpio { - volatile u32 port_config; /* GPIO + 0x00 */ - volatile u32 simple_gpioe; /* GPIO + 0x04 */ - volatile u32 simple_ode; /* GPIO + 0x08 */ - volatile u32 simple_ddr; /* GPIO + 0x0c */ - volatile u32 simple_dvo; /* GPIO + 0x10 */ - volatile u32 simple_ival; /* GPIO + 0x14 */ - volatile u8 outo_gpioe; /* GPIO + 0x18 */ - volatile u8 reserved1[3]; /* GPIO + 0x19 */ - volatile u8 outo_dvo; /* GPIO + 0x1c */ - volatile u8 reserved2[3]; /* GPIO + 0x1d */ - volatile u8 sint_gpioe; /* GPIO + 0x20 */ - volatile u8 reserved3[3]; /* GPIO + 0x21 */ - volatile u8 sint_ode; /* GPIO + 0x24 */ - volatile u8 reserved4[3]; /* GPIO + 0x25 */ - volatile u8 sint_ddr; /* GPIO + 0x28 */ - volatile u8 reserved5[3]; /* GPIO + 0x29 */ - volatile u8 sint_dvo; /* GPIO + 0x2c */ - volatile u8 reserved6[3]; /* GPIO + 0x2d */ - volatile u8 sint_inten; /* GPIO + 0x30 */ - volatile u8 reserved7[3]; /* GPIO + 0x31 */ - volatile u16 sint_itype; /* GPIO + 0x34 */ - volatile u16 reserved8; /* GPIO + 0x36 */ - volatile u8 gpio_control; /* GPIO + 0x38 */ - volatile u8 reserved9[3]; /* GPIO + 0x39 */ - volatile u8 sint_istat; /* GPIO + 0x3c */ - volatile u8 sint_ival; /* GPIO + 0x3d */ - volatile u8 bus_errs; /* GPIO + 0x3e */ - volatile u8 reserved10; /* GPIO + 0x3f */ -}; - -struct mpc5xxx_wu_gpio { - volatile u8 enable; /* WU_GPIO + 0x00 */ - volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */ - volatile u8 ode; /* WU_GPIO + 0x04 */ - volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */ - volatile u8 ddr; /* WU_GPIO + 0x08 */ - volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */ - volatile u8 dvo; /* WU_GPIO + 0x0c */ - volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */ - volatile u8 inten; /* WU_GPIO + 0x10 */ - volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */ - volatile u8 iinten; /* WU_GPIO + 0x14 */ - volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */ - volatile u16 itype; /* WU_GPIO + 0x18 */ - volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */ - volatile u8 master_enable; /* WU_GPIO + 0x1c */ - volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */ - volatile u8 ival; /* WU_GPIO + 0x20 */ - volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */ - volatile u8 status; /* WU_GPIO + 0x24 */ - volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */ -}; - -struct mpc5xxx_sdma { - volatile u32 taskBar; /* SDMA + 0x00 */ - volatile u32 currentPointer; /* SDMA + 0x04 */ - volatile u32 endPointer; /* SDMA + 0x08 */ - volatile u32 variablePointer; /* SDMA + 0x0c */ - - volatile u8 IntVect1; /* SDMA + 0x10 */ - volatile u8 IntVect2; /* SDMA + 0x11 */ - volatile u16 PtdCntrl; /* SDMA + 0x12 */ - - volatile u32 IntPend; /* SDMA + 0x14 */ - volatile u32 IntMask; /* SDMA + 0x18 */ - - volatile u16 tcr_0; /* SDMA + 0x1c */ - volatile u16 tcr_1; /* SDMA + 0x1e */ - volatile u16 tcr_2; /* SDMA + 0x20 */ - volatile u16 tcr_3; /* SDMA + 0x22 */ - volatile u16 tcr_4; /* SDMA + 0x24 */ - volatile u16 tcr_5; /* SDMA + 0x26 */ - volatile u16 tcr_6; /* SDMA + 0x28 */ - volatile u16 tcr_7; /* SDMA + 0x2a */ - volatile u16 tcr_8; /* SDMA + 0x2c */ - volatile u16 tcr_9; /* SDMA + 0x2e */ - volatile u16 tcr_a; /* SDMA + 0x30 */ - volatile u16 tcr_b; /* SDMA + 0x32 */ - volatile u16 tcr_c; /* SDMA + 0x34 */ - volatile u16 tcr_d; /* SDMA + 0x36 */ - volatile u16 tcr_e; /* SDMA + 0x38 */ - volatile u16 tcr_f; /* SDMA + 0x3a */ - - volatile u8 IPR0; /* SDMA + 0x3c */ - volatile u8 IPR1; /* SDMA + 0x3d */ - volatile u8 IPR2; /* SDMA + 0x3e */ - volatile u8 IPR3; /* SDMA + 0x3f */ - volatile u8 IPR4; /* SDMA + 0x40 */ - volatile u8 IPR5; /* SDMA + 0x41 */ - volatile u8 IPR6; /* SDMA + 0x42 */ - volatile u8 IPR7; /* SDMA + 0x43 */ - volatile u8 IPR8; /* SDMA + 0x44 */ - volatile u8 IPR9; /* SDMA + 0x45 */ - volatile u8 IPR10; /* SDMA + 0x46 */ - volatile u8 IPR11; /* SDMA + 0x47 */ - volatile u8 IPR12; /* SDMA + 0x48 */ - volatile u8 IPR13; /* SDMA + 0x49 */ - volatile u8 IPR14; /* SDMA + 0x4a */ - volatile u8 IPR15; /* SDMA + 0x4b */ - volatile u8 IPR16; /* SDMA + 0x4c */ - volatile u8 IPR17; /* SDMA + 0x4d */ - volatile u8 IPR18; /* SDMA + 0x4e */ - volatile u8 IPR19; /* SDMA + 0x4f */ - volatile u8 IPR20; /* SDMA + 0x50 */ - volatile u8 IPR21; /* SDMA + 0x51 */ - volatile u8 IPR22; /* SDMA + 0x52 */ - volatile u8 IPR23; /* SDMA + 0x53 */ - volatile u8 IPR24; /* SDMA + 0x54 */ - volatile u8 IPR25; /* SDMA + 0x55 */ - volatile u8 IPR26; /* SDMA + 0x56 */ - volatile u8 IPR27; /* SDMA + 0x57 */ - volatile u8 IPR28; /* SDMA + 0x58 */ - volatile u8 IPR29; /* SDMA + 0x59 */ - volatile u8 IPR30; /* SDMA + 0x5a */ - volatile u8 IPR31; /* SDMA + 0x5b */ - - volatile u32 res1; /* SDMA + 0x5c */ - volatile u32 res2; /* SDMA + 0x60 */ - volatile u32 res3; /* SDMA + 0x64 */ - volatile u32 MDEDebug; /* SDMA + 0x68 */ - volatile u32 ADSDebug; /* SDMA + 0x6c */ - volatile u32 Value1; /* SDMA + 0x70 */ - volatile u32 Value2; /* SDMA + 0x74 */ - volatile u32 Control; /* SDMA + 0x78 */ - volatile u32 Status; /* SDMA + 0x7c */ - volatile u32 EU00; /* SDMA + 0x80 */ - volatile u32 EU01; /* SDMA + 0x84 */ - volatile u32 EU02; /* SDMA + 0x88 */ - volatile u32 EU03; /* SDMA + 0x8c */ - volatile u32 EU04; /* SDMA + 0x90 */ - volatile u32 EU05; /* SDMA + 0x94 */ - volatile u32 EU06; /* SDMA + 0x98 */ - volatile u32 EU07; /* SDMA + 0x9c */ - volatile u32 EU10; /* SDMA + 0xa0 */ - volatile u32 EU11; /* SDMA + 0xa4 */ - volatile u32 EU12; /* SDMA + 0xa8 */ - volatile u32 EU13; /* SDMA + 0xac */ - volatile u32 EU14; /* SDMA + 0xb0 */ - volatile u32 EU15; /* SDMA + 0xb4 */ - volatile u32 EU16; /* SDMA + 0xb8 */ - volatile u32 EU17; /* SDMA + 0xbc */ - volatile u32 EU20; /* SDMA + 0xc0 */ - volatile u32 EU21; /* SDMA + 0xc4 */ - volatile u32 EU22; /* SDMA + 0xc8 */ - volatile u32 EU23; /* SDMA + 0xcc */ - volatile u32 EU24; /* SDMA + 0xd0 */ - volatile u32 EU25; /* SDMA + 0xd4 */ - volatile u32 EU26; /* SDMA + 0xd8 */ - volatile u32 EU27; /* SDMA + 0xdc */ - volatile u32 EU30; /* SDMA + 0xe0 */ - volatile u32 EU31; /* SDMA + 0xe4 */ - volatile u32 EU32; /* SDMA + 0xe8 */ - volatile u32 EU33; /* SDMA + 0xec */ - volatile u32 EU34; /* SDMA + 0xf0 */ - volatile u32 EU35; /* SDMA + 0xf4 */ - volatile u32 EU36; /* SDMA + 0xf8 */ - volatile u32 EU37; /* SDMA + 0xfc */ -}; - -struct mpc5xxx_i2c { - volatile u32 madr; /* I2Cn + 0x00 */ - volatile u32 mfdr; /* I2Cn + 0x04 */ - volatile u32 mcr; /* I2Cn + 0x08 */ - volatile u32 msr; /* I2Cn + 0x0C */ - volatile u32 mdr; /* I2Cn + 0x10 */ -}; - -struct mpc5xxx_spi { - volatile u8 cr1; /* SPI + 0x0F00 */ - volatile u8 cr2; /* SPI + 0x0F01 */ - volatile u8 reserved1[2]; - volatile u8 brr; /* SPI + 0x0F04 */ - volatile u8 sr; /* SPI + 0x0F05 */ - volatile u8 reserved2[3]; - volatile u8 dr; /* SPI + 0x0F09 */ - volatile u8 reserved3[3]; - volatile u8 pdr; /* SPI + 0x0F0D */ - volatile u8 reserved4[2]; - volatile u8 ddr; /* SPI + 0x0F10 */ -}; - - -struct mpc5xxx_gpt { - volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ - volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ - volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ - volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ -}; - -struct mpc5xxx_gpt_0_7 { - struct mpc5xxx_gpt gpt0; - struct mpc5xxx_gpt gpt1; - struct mpc5xxx_gpt gpt2; - struct mpc5xxx_gpt gpt3; - struct mpc5xxx_gpt gpt4; - struct mpc5xxx_gpt gpt5; - struct mpc5xxx_gpt gpt6; - struct mpc5xxx_gpt gpt7; -}; - -struct mscan_buffer { - volatile u8 idr[0x8]; /* 0x00 */ - volatile u8 dsr[0x10]; /* 0x08 */ - volatile u8 dlr; /* 0x18 */ - volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ - volatile u16 rsrv1; /* 0x1A */ - volatile u8 tsrh; /* 0x1C */ - volatile u8 tsrl; /* 0x1D */ - volatile u16 rsrv2; /* 0x1E */ -}; - -struct mpc5xxx_mscan { - volatile u8 canctl0; /* MSCAN + 0x00 */ - volatile u8 canctl1; /* MSCAN + 0x01 */ - volatile u16 rsrv1; /* MSCAN + 0x02 */ - volatile u8 canbtr0; /* MSCAN + 0x04 */ - volatile u8 canbtr1; /* MSCAN + 0x05 */ - volatile u16 rsrv2; /* MSCAN + 0x06 */ - volatile u8 canrflg; /* MSCAN + 0x08 */ - volatile u8 canrier; /* MSCAN + 0x09 */ - volatile u16 rsrv3; /* MSCAN + 0x0A */ - volatile u8 cantflg; /* MSCAN + 0x0C */ - volatile u8 cantier; /* MSCAN + 0x0D */ - volatile u16 rsrv4; /* MSCAN + 0x0E */ - volatile u8 cantarq; /* MSCAN + 0x10 */ - volatile u8 cantaak; /* MSCAN + 0x11 */ - volatile u16 rsrv5; /* MSCAN + 0x12 */ - volatile u8 cantbsel; /* MSCAN + 0x14 */ - volatile u8 canidac; /* MSCAN + 0x15 */ - volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ - volatile u8 canrxerr; /* MSCAN + 0x1C */ - volatile u8 cantxerr; /* MSCAN + 0x1D */ - volatile u16 rsrv7; /* MSCAN + 0x1E */ - volatile u8 canidar0; /* MSCAN + 0x20 */ - volatile u8 canidar1; /* MSCAN + 0x21 */ - volatile u16 rsrv8; /* MSCAN + 0x22 */ - volatile u8 canidar2; /* MSCAN + 0x24 */ - volatile u8 canidar3; /* MSCAN + 0x25 */ - volatile u16 rsrv9; /* MSCAN + 0x26 */ - volatile u8 canidmr0; /* MSCAN + 0x28 */ - volatile u8 canidmr1; /* MSCAN + 0x29 */ - volatile u16 rsrv10; /* MSCAN + 0x2A */ - volatile u8 canidmr2; /* MSCAN + 0x2C */ - volatile u8 canidmr3; /* MSCAN + 0x2D */ - volatile u16 rsrv11; /* MSCAN + 0x2E */ - volatile u8 canidar4; /* MSCAN + 0x30 */ - volatile u8 canidar5; /* MSCAN + 0x31 */ - volatile u16 rsrv12; /* MSCAN + 0x32 */ - volatile u8 canidar6; /* MSCAN + 0x34 */ - volatile u8 canidar7; /* MSCAN + 0x35 */ - volatile u16 rsrv13; /* MSCAN + 0x36 */ - volatile u8 canidmr4; /* MSCAN + 0x38 */ - volatile u8 canidmr5; /* MSCAN + 0x39 */ - volatile u16 rsrv14; /* MSCAN + 0x3A */ - volatile u8 canidmr6; /* MSCAN + 0x3C */ - volatile u8 canidmr7; /* MSCAN + 0x3D */ - volatile u16 rsrv15; /* MSCAN + 0x3E */ - - struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ - struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ - }; - -struct mpc5xxx_xlb { - volatile u8 reserved[0x40]; /* XLB + 0x00 */ - volatile u32 config; /* XLB + 0x40 */ - volatile u32 version; /* XLB + 0x44 */ - volatile u32 status; /* XLB + 0x48 */ - volatile u32 int_enable; /* XLB + 0x4c */ - volatile u32 addr_capture; /* XLB + 0x50 */ - volatile u32 bus_sig_capture; /* XLB + 0x54 */ - volatile u32 addr_timeout; /* XLB + 0x58 */ - volatile u32 data_timeout; /* XLB + 0x5c */ - volatile u32 bus_act_timeout; /* XLB + 0x60 */ - volatile u32 master_pri_enable; /* XLB + 0x64 */ - volatile u32 master_priority; /* XLB + 0x68 */ - volatile u32 base_address; /* XLB + 0x6c */ - volatile u32 snoop_window; /* XLB + 0x70 */ -}; - -struct pci_controller; - -/* function prototypes */ -void loadtask(int basetask, int tasks); -void pci_mpc5xxx_init(struct pci_controller *); - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASMPPC_MPC5XXX_H */ diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h deleted file mode 100644 index 821ac0a..0000000 --- a/include/mpc5xxx_sdma.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - * - * odin smartdma header file - */ - -#ifndef __MPC5XXX_SDMA_H -#define __MPC5XXX_SDMA_H - -#include -#include - -/* Task number assignment */ -#define FEC_RECV_TASK_NO 0 -#define FEC_XMIT_TASK_NO 1 - -/*---------------------------------------------------------------------*/ - -/* Stuff for Ethernet Tx/Rx tasks */ - -/*---------------------------------------------------------------------*/ - -/* Layout of Ethernet controller Parameter SRAM area: ----------------------------------------------------------------- -0x00: TBD_BASE, base address of TX BD ring -0x04: TBD_NEXT, address of next TX BD to be processed -0x08: RBD_BASE, base address of RX BD ring -0x0C: RBD_NEXT, address of next RX BD to be processed ---------------------------------------------------------------- -ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). -*/ - -/* base address of SRAM area to store parameters used by Ethernet tasks */ -#define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800) - -/* base address of SRAM area for buffer descriptors */ -#define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820) - -/*---------------------------------------------------------------------*/ - -/* common shortcuts used by driver C code */ - -/*---------------------------------------------------------------------*/ - -/* Disable SmartDMA task */ -#define SDMA_TASK_DISABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) & (~0x8000); \ -} - -/* Enable SmartDMA task */ -#define SDMA_TASK_ENABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) | 0x8000; \ -} - -/* Enable interrupt */ -#define SDMA_INT_ENABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask &= ~(1 << tasknum); \ -} - -/* Disable interrupt */ -#define SDMA_INT_DISABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask |= (1 << tasknum); \ -} - - -/* Clear interrupt pending bits */ -#define SDMA_CLEAR_IEVENT(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntPend = (1 << tasknum); \ -} - -/* get interrupt pending bit of a task */ -#define SDMA_GET_PENDINGBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) - -/* get interrupt mask bit of a task */ -#define SDMA_GET_MASKBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) - -#endif /* __MPC5XXX_SDMA_H */ diff --git a/include/mpc823_lcd.h b/include/mpc823_lcd.h deleted file mode 100644 index cc72cde..0000000 --- a/include/mpc823_lcd.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * mpc823_lcd.h - MPC823 LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MPC823_LCD_H_ -#define _MPC823_LCD_H_ - -/* - * LCD controller stucture for MPC823 CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_wbl; /* Wait between lines */ - - /* Vertical control register */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_lcdac; /* LCD AC timing */ - u_char vl_wbf; /* Wait between frames */ -} vidinfo_t; - -#endif diff --git a/include/mpc8260.h b/include/mpc8260.h deleted file mode 100644 index 75f1b0c..0000000 --- a/include/mpc8260.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8260.h - * - * MPC8255 / MPC8260 specific definitions - */ - -#ifndef __MPC8260_H__ -#define __MPC8260_H__ - -#ifdef CONFIG_MPC8255 -#define CPU_ID_STR "MPC8255" -#endif -#ifndef CPU_ID_STR -#if defined(CONFIG_MPC8272_FAMILY) -#ifdef CONFIG_MPC8247 -#define CPU_ID_STR "MPC8247" -#else -#define CPU_ID_STR "MPC8272" -#endif -#else -#define CPU_ID_STR "MPC8260" -#endif -#endif /* !CPU_ID_STR */ - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration Register 4-25 - */ -#define BCR_EBM 0x80000000 /* External Bus Mode */ -#define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */ -#define BCR_L2C 0x08000000 /* Secondary Cache Controller */ -#define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */ -#define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */ -#define BCR_EAV 0x00400000 /* Enable Address Visibility */ -#define BCR_ETM 0x00080000 /* Compatibility Mode Enable */ -#define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/ -#define BCR_EPAR 0x00020000 /* Even Parity */ -#define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */ -#define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */ -#define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */ -#define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */ -#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/ -#define BCR_ISPS 0x00000010 /* Internal Space Port Size */ - - -/*----------------------------------------------------------------------- - * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28 - */ -#define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */ -#define PPC_ACR_EARB 0x10 /* External Arbitration */ -#define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */ - -#define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */ -#define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ -#define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */ -#define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */ -#define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */ -#define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */ -#define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */ - -/*----------------------------------------------------------------------- - * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28 - */ -#define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ -#define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ -#define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ -#define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ -#define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ -#define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ -#define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ -#define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ -#define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ -#define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ -#define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ -#define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ -#define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ -#define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ -#define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ -#define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ - -/*----------------------------------------------------------------------- - * LCL_ACR - Local Bus Arbiter Configuration Register 4-29 - */ -#define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */ -#define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */ - -#define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */ -#define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ -#define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */ -#define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */ - -/*----------------------------------------------------------------------- - * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30 - */ -#define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ -#define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ -#define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ -#define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ -#define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ -#define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ -#define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ -#define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ -#define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ -#define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ -#define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ -#define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ -#define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ -#define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ -#define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ -#define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register 4-31 - */ -#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ -#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ -#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ -#define SIUMCR_CDIS 0x10000000 /* Core Disable */ -#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ -#define SIUMCR_DPPC01 0x04000000 /* - " - */ -#define SIUMCR_DPPC10 0x08000000 /* - " - */ -#define SIUMCR_DPPC11 0x0c000000 /* - " - */ -#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define SIUMCR_L2CPC01 0x01000000 /* - " - */ -#define SIUMCR_L2CPC10 0x02000000 /* - " - */ -#define SIUMCR_L2CPC11 0x03000000 /* - " - */ -#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ -#define SIUMCR_LBPC01 0x00400000 /* - " - */ -#define SIUMCR_LBPC10 0x00800000 /* - " - */ -#define SIUMCR_LBPC11 0x00c00000 /* - " - */ -#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ -#define SIUMCR_APPC01 0x00100000 /* - " - */ -#define SIUMCR_APPC10 0x00200000 /* - " - */ -#define SIUMCR_APPC11 0x00300000 /* - " - */ -#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define SIUMCR_CS10PC01 0x00040000 /* - " - */ -#define SIUMCR_CS10PC10 0x00080000 /* - " - */ -#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ -#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ -#define SIUMCR_BCTLC01 0x00010000 /* - " - */ -#define SIUMCR_BCTLC10 0x00020000 /* - " - */ -#define SIUMCR_BCTLC11 0x00030000 /* - " - */ -#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ -#define SIUMCR_MMR01 0x00004000 /* - " - */ -#define SIUMCR_MMR10 0x00008000 /* - " - */ -#define SIUMCR_MMR11 0x0000c000 /* - " - */ -#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ -#define SIUMCR_ABE 0x00000400 /* Address output buffer impedance*/ - -/*----------------------------------------------------------------------- - * IMMR - Internal Memory Map Register 4-34 - */ -#define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */ -#define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */ -#define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control Register 4-35 - */ -#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/ -#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ -#define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */ -#define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */ -#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ -#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/ -#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control Register 4-40 - */ -#define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */ -#define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */ -#define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */ -#define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */ -#define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */ -#define TMCNTSC_TCE 0x0001 /* Time Counter Enable */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control Register 4-42 - */ -#if 0 /* already defined in asm/immap_8260.h */ -#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ -#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ -#define PISCR_PTF 0x0002 /* Periodic Timer Frequency */ -#define PISCR_PTE 0x0001 /* Periodic Timer Enable */ -#endif - -/*----------------------------------------------------------------------- - * RSR - Reset Status Register 5-4 - */ -#define RSR_JTRS 0x00000020 /* JTAG Reset Status */ -#define RSR_CSRS 0x00000010 /* Check Stop Reset Status */ -#define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/ -#define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */ -#define RSR_ESRS 0x00000002 /* External Soft Reset Status */ -#define RSR_EHRS 0x00000001 /* External Hard Reset Status */ - -#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS) - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - */ -#define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Word 5-8 - */ -#define HRCW_EARB 0x80000000 /* External Arbitration */ -#define HRCW_EXMC 0x40000000 /* External Memory Controller */ -#define HRCW_CDIS 0x20000000 /* Core Disable */ -#define HRCW_EBM 0x10000000 /* External Bus Mode */ -#define HRCW_BPS00 0x00000000 /* Boot Port Size */ -#define HRCW_BPS01 0x04000000 /* - " - */ -#define HRCW_BPS10 0x08000000 /* - " - */ -#define HRCW_BPS11 0x0c000000 /* - " - */ -#define HRCW_CIP 0x02000000 /* Core Initial Prefix */ -#define HRCW_ISPS 0x01000000 /* Internal Space Port Size */ -#define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define HRCW_L2CPC01 0x00400000 /* - " - */ -#define HRCW_L2CPC10 0x00800000 /* - " - */ -#define HRCW_L2CPC11 0x00c00000 /* - " - */ -#define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/ -#define HRCW_DPPC01 0x00100000 /* - " - */ -#define HRCW_DPPC10 0x00200000 /* - " - */ -#define HRCW_DPPC11 0x00300000 /* - " - */ -#define HRCW_reserved1 0x00080000 /* reserved */ -#define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */ -#define HRCW_ISB001 0x00010000 /* - " - */ -#define HRCW_ISB010 0x00020000 /* - " - */ -#define HRCW_ISB011 0x00030000 /* - " - */ -#define HRCW_ISB100 0x00040000 /* - " - */ -#define HRCW_ISB101 0x00050000 /* - " - */ -#define HRCW_ISB110 0x00060000 /* - " - */ -#define HRCW_ISB111 0x00070000 /* - " - */ -#define HRCW_BMS 0x00008000 /* Boot Memory Space */ -#define HRCW_BBD 0x00004000 /* Bus Busy Disable */ -#define HRCW_MMR00 0x00000000 /* Mask Masters Requests */ -#define HRCW_MMR01 0x00001000 /* - " - */ -#define HRCW_MMR10 0x00002000 /* - " - */ -#define HRCW_MMR11 0x00003000 /* - " - */ -#define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */ -#define HRCW_LBPC01 0x00000400 /* - " - */ -#define HRCW_LBPC10 0x00000800 /* - " - */ -#define HRCW_LBPC11 0x00000c00 /* - " - */ -#define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/ -#define HRCW_APPC01 0x00000100 /* - " - */ -#define HRCW_APPC10 0x00000200 /* - " - */ -#define HRCW_APPC11 0x00000300 /* - " - */ -#define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define HRCW_CS10PC01 0x00000040 /* - " - */ -#define HRCW_CS10PC10 0x00000080 /* - " - */ -#define HRCW_CS10PC11 0x000000c0 /* - " - */ -#define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */ -#define HRCW_MODCK_H0001 0x00000001 /* - " - */ -#define HRCW_MODCK_H0010 0x00000002 /* - " - */ -#define HRCW_MODCK_H0011 0x00000003 /* - " - */ -#define HRCW_MODCK_H0100 0x00000004 /* - " - */ -#define HRCW_MODCK_H0101 0x00000005 /* - " - */ -#define HRCW_MODCK_H0110 0x00000006 /* - " - */ -#define HRCW_MODCK_H0111 0x00000007 /* - " - */ -#define HRCW_MODCK_H1000 0x00000008 /* - " - */ -#define HRCW_MODCK_H1001 0x00000009 /* - " - */ -#define HRCW_MODCK_H1010 0x0000000a /* - " - */ -#define HRCW_MODCK_H1011 0x0000000b /* - " - */ -#define HRCW_MODCK_H1100 0x0000000c /* - " - */ -#define HRCW_MODCK_H1101 0x0000000d /* - " - */ -#define HRCW_MODCK_H1110 0x0000000e /* - " - */ -#define HRCW_MODCK_H1111 0x0000000f /* - " - */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 - */ -#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ -#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ -#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ -#define SCCR_PCIDF_SHIFT 3 -#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ -#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ -#define SCCR_DFBRG_SHIFT 0 - -#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ -#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ -#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ -#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */ - -/*----------------------------------------------------------------------- - * SCMR - System Clock Mode Register 9-9 - */ -#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */ -#define SCMR_CORECNF_SHIFT 24 -#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */ -#define SCMR_BUSDF_SHIFT 20 -#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */ -#define SCMR_CPMDF_SHIFT 16 -#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */ -#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/ -#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */ -#define SCMR_PLLMF_SHIFT 0 - - -/*----------------------------------------------------------------------- - * MxMR - Machine A/B/C Mode Registers 10-13 - */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ -#define MxMR_RFEN 0x40000000 /* Refresh Enable */ -#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ -#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ -#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ -#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ -#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ -#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ -#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ -#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ -#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ - -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_OP_RARR 0x20000000 /* Read from Array */ -#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ - -#define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ -#define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */ -#define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */ -#define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */ -#define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */ -#define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */ - -#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ -#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ - -#define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */ -#define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */ -#define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */ -#define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */ -#define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */ -#define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */ -#define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */ -#define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */ - -#define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */ -#define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/ -#define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/ -#define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/ -#define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/ -#define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/ -#define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/ -#define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/ -#define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/ -#define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/ -#define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/ -#define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/ -#define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/ -#define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/ -#define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/ -#define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/ - -#define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/ -#define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/ -#define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/ -#define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/ -#define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/ -#define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/ -#define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/ -#define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/ -#define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/ -#define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/ -#define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/ -#define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/ -#define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/ -#define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/ -#define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/ -#define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/ - -#define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/ -#define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/ -#define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/ -#define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/ -#define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/ -#define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/ -#define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/ -#define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/ -#define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/ -#define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/ -#define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/ -#define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/ -#define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/ -#define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/ -#define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/ -#define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/ - - -/*----------------------------------------------------------------------- - * BRx - Memory Controller: Base Register 10-14 - */ -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ -#define BRx_PS_MSK 0x00001800 /* Port Size Mask */ -#define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/ -#define BRx_WP 0x00000100 /* Write Protect */ -#define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */ -#define BRx_EMEMC 0x00000010 /* External MEMC Enable */ -#define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */ -#define BRx_DR 0x00000002 /* Data Pipelining */ -#define BRx_V 0x00000001 /* Bank Valid */ - -#define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/ -#define BRx_PS_8 0x00000800 /* 8 bit port size */ -#define BRx_PS_16 0x00001000 /* 16 bit port size */ -#define BRx_PS_32 0x00001800 /* 32 bit port size */ - -#define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/ -#define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */ -#define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/ -#define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */ - -#define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/ -#define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/ -#define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */ -#define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/ -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ - -#define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */ -#define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - SDRAM Mode 10-16 - */ -#define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */ -#define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/ -#define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */ -#define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */ -#define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/ -#define ORxS_PMSEL 0x00000020 /* Page Mode Select */ -#define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/ - -#define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */ -#define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */ -#define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */ - -/* ROWST values for xSDMR[PBI] = 0 */ -#define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */ -#define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */ -#define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */ -#define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */ -#define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */ -#define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */ -#define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */ - -/* ROWST values for xSDMR[PBI] = 1 */ -#define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */ -#define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */ -#define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */ -#define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */ -#define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */ -#define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */ -#define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */ -#define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */ -#define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */ -#define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */ -#define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */ -#define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */ -#define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */ - -#define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */ -#define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */ -#define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */ -#define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */ -#define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */ -#define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */ -#define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */ -#define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */ - -/* helper to determine the AM for a given size (SDRAM mode) */ -#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - GPCM Mode 10-18 - */ -#define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */ -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ -#define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/ -#define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ -#define ORxG_SETA 0x00000008 /* External Access Termination */ -#define ORxG_TRLX 0x00000004 /* Timing Relaxed */ -#define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */ - -#define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/ -#define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/ -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ - -#define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ -#define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ -#define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ -#define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ -#define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ -#define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ -#define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ -#define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ -#define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ -#define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ -#define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ -#define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ -#define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - UPM Mode 10-20 - */ -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */ -#define ORxU_BI 0x00000100 /* Burst Inhibit */ -#define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/ - -#define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */ -#define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/ -#define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/ -#define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/ - - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - - -/*----------------------------------------------------------------------- - * PSDMR - 60x SDRAM Mode Register 10-21 - */ -#define PSDMR_PBI 0x80000000 /* Page-based Interleaving */ -#define PSDMR_RFEN 0x40000000 /* Refresh Enable */ -#define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */ -#define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */ -#define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/ -#define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */ -#define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */ -#define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/ -#define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/ -#define PSDMR_BL 0x00000100 /* Burst Length */ -#define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/ -#define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */ -#define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/ -#define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/ -#define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */ - -#define PSDMR_OP_NORM 0x00000000 /* Normal Operation */ -#define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */ -#define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */ -#define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */ -#define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */ -#define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */ -#define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */ -#define PSDMR_OP_RW 0x38000000 /* Read/Write */ - -#define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */ -#define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */ -#define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */ -#define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */ -#define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */ -#define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */ - -#define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */ -#define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */ -#define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */ -#define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */ -#define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */ -#define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */ -#define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */ -#define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */ - -/* SDA10 values for xSDMR[PBI] = 0 */ -#define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */ -#define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */ -#define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */ -#define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */ -#define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */ -#define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */ -#define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */ -#define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */ - -/* SDA10 values for xSDMR[PBI] = 1 */ -#define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */ -#define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */ -#define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */ -#define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */ -#define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */ -#define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */ -#define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */ -#define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */ - -#define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */ -#define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */ -#define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */ -#define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */ -#define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */ -#define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */ -#define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */ - -#define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */ - -#define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */ - -#define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */ -#define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */ -#define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */ - -#define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */ -#define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */ -#define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */ -#define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */ - -#define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */ -#define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */ -#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ - -/*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register 10-24 - */ - -/* - * No definitions here - the LSDMR has the same fields as the PSDMR. - */ - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-32 - * See User's Manual Errata for the changed definition (matches the - * 8xx now). The wrong prescaler definition causes excessive refreshes - * (typically "divide by 2" when "divide by 32" is intended) which will - * cause unnecessary memory subsystem slowdown. - */ -#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */ -#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ -#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ -#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ -#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ -#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ -#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ - - -/*----------------------------------------------------------------------- - * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4 - */ -#define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */ -#define TGCR1_STP2 0x20 /* Stop timer 2 */ -#define TGCR1_RST2 0x10 /* Reset timer 2 */ -#define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */ -#define TGCR1_STP1 0x02 /* Stop timer 1 */ -#define TGCR1_RST1 0x01 /* Reset timer 1 */ -#define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */ -#define TGCR2_STP4 0x20 /* Stop timer 4 */ -#define TGCR2_RST4 0x10 /* Reset timer 4 */ -#define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */ -#define TGCR2_STP3 0x02 /* Stop timer 3 */ -#define TGCR2_RST3 0x01 /* Reset timer 3 */ - - -/*----------------------------------------------------------------------- - * TMR1-TMR4 - Timer Mode Registers 17-6 - */ -#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ -#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ -#define TMRx_OM 0x0020 /* Output Mode */ -#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ -#define TMRx_FRR 0x0008 /* Free Run/Restart */ -#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ -#define TMRx_GE 0x0001 /* Gate Enable */ - -#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ -#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ -#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ -#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ - -#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ -#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ -#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ -#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ - - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register 15-12 - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register 15-14 - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -/*----------------------------------------------------------------------- - * CMXSMR - CMX SMC Clock Route Register 15-17 - */ -#define CMXSMR_SMC1 0x80 /* SMC1 Connection */ -#define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */ -#define CMXSMR_SMC2 0x08 /* SMC2 Connection */ -#define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */ - -#define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */ -#define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */ -#define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */ -#define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */ - -#define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */ -#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */ -#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */ -#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */ - -/*----------------------------------------------------------------------- - * miscellaneous - */ - -#define UPMA 1 -#define UPMB 2 -#define UPMC 3 - -#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) -static __inline__ void -reset_8260_watchdog(volatile immap_t *immr) -{ - immr->im_siu_conf.sc_swsr = 0x556c; - immr->im_siu_conf.sc_swsr = 0xaa39; -} -#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */ - -#endif /* __MPC8260_H__ */ diff --git a/include/mpc8260_irq.h b/include/mpc8260_irq.h deleted file mode 100644 index 9bee9a3..0000000 --- a/include/mpc8260_irq.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _MPC8260_IRQ_H -#define _MPC8260_IRQ_H - -/****************************************************************************/ -/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */ -/* source. There was no copyright information in the file. */ - -/* - * this is the # irq's for all ppc arch's (pmac/chrp/prep) - * so it is the max of them all - * - * [let's just worry about 8260 for now - mjj] - */ -#define NR_IRQS 64 - -/* The 8260 has an internal interrupt controller with a maximum of - * 64 IRQs. We will use NR_IRQs from above since it is large enough. - * Don't be confused by the 8260 documentation where they list an - * "interrupt number" and "interrupt vector". We are only interested - * in the interrupt vector. There are "reserved" holes where the - * vector number increases, but the interrupt number in the table does not. - * (Document errata updates have fixed this...make sure you have up to - * date processor documentation -- Dan). - */ -#define NR_SIU_INTS 64 - -/* There are many more than these, we will add them as we need them. -*/ -#define SIU_INT_SMC1 ((uint)0x04) -#define SIU_INT_SMC2 ((uint)0x05) -#define SIU_INT_IRQ1 ((uint)0x13) -#define SIU_INT_IRQ2 ((uint)0x14) -#define SIU_INT_IRQ3 ((uint)0x15) -#define SIU_INT_IRQ4 ((uint)0x16) -#define SIU_INT_IRQ5 ((uint)0x17) -#define SIU_INT_IRQ6 ((uint)0x18) -#define SIU_INT_IRQ7 ((uint)0x19) -#define SIU_INT_FCC1 ((uint)0x20) -#define SIU_INT_FCC2 ((uint)0x21) -#define SIU_INT_FCC3 ((uint)0x22) -#define SIU_INT_SCC1 ((uint)0x28) -#define SIU_INT_SCC2 ((uint)0x29) -#define SIU_INT_SCC3 ((uint)0x2a) -#define SIU_INT_SCC4 ((uint)0x2b) - -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) - -#endif /* _MPC8260_IRQ_H */ diff --git a/include/nand.h b/include/nand.h index a865528..bc5dd81 100644 --- a/include/nand.h +++ b/include/nand.h @@ -132,8 +132,6 @@ void board_nand_select_device(struct nand_chip *nand, int chip); __attribute__((noreturn)) void nand_boot(void); -#endif - #ifdef CONFIG_ENV_OFFSET_OOB #define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored as block number*/ @@ -146,3 +144,5 @@ int spl_nand_erase_one(int block, int page); /* platform specific init functions */ void sunxi_nand_init(void); + +#endif /* _NAND_H_ */ diff --git a/include/net.h b/include/net.h index ed5259a..2eaa882 100644 --- a/include/net.h +++ b/include/net.h @@ -12,10 +12,6 @@ #ifndef __NET_H__ #define __NET_H__ -#if defined(CONFIG_8xx) -#include -#endif /* CONFIG_8xx */ - #include #include /* for nton* / ntoh* stuff */ diff --git a/include/netdev.h b/include/netdev.h index 8eb8b46..c06b908 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -57,9 +57,6 @@ int lpc32xx_eth_initialize(bd_t *bis); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); int mcdmafec_initialize(bd_t *bis); int mcffec_initialize(bd_t *bis); -int mpc512x_fec_initialize(bd_t *bis); -int mpc5xxx_fec_initialize(bd_t *bis); -int mpc82xx_scc_enet_initialize(bd_t *bis); int mvgbe_initialize(bd_t *bis); int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr); int natsemi_initialize(bd_t *bis); diff --git a/include/pcmcia.h b/include/pcmcia.h index aaaf651..94b54c2 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -15,18 +15,10 @@ * Allow configuration to select PCMCIA slot, * or try to generate a useful default */ -#if defined(CONFIG_CMD_PCMCIA) || \ - (defined(CONFIG_IDE) && \ - (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) +#if defined(CONFIG_CMD_PCMCIA) #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) - -#if defined(CONFIG_TQM8xxL) -# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ -#else # error "PCMCIA Slot not configured" -#endif - #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ /* Make sure exactly one slot is defined - we support only one for now */ @@ -57,17 +49,6 @@ #endif /* - * The TQM850L hardware has two pins swapped! Grrrrgh! - */ -#ifdef CONFIG_TQM850L -#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE -#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET -#else -#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET -#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE -#endif - -/* * This structure is used to address each window in the PCMCIA controller. * * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly @@ -263,13 +244,4 @@ typedef struct { #endif -#ifdef CONFIG_8xx -extern u_int *pcmcia_pgcrx[]; -#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -extern int check_ide_device(int slot); -#endif - #endif /* _PCMCIA_H */ diff --git a/include/post.h b/include/post.h index 5ebd535..b9b9c37 100644 --- a/include/post.h +++ b/include/post.h @@ -22,22 +22,7 @@ #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else -#ifdef CONFIG_MPC5xxx -#define _POST_WORD_ADDR (MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE) - -#elif defined(CONFIG_MPC512X) -#define _POST_WORD_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#elif defined(CONFIG_8xx) -#define _POST_WORD_ADDR \ - (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR) - -#elif defined(CONFIG_MPC8260) -#include -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) - -#elif defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) #include #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) @@ -164,7 +149,6 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CACHE 0x00000020 #define CONFIG_SYS_POST_UART 0x00000040 #define CONFIG_SYS_POST_ETHER 0x00000080 -#define CONFIG_SYS_POST_SPI 0x00000100 #define CONFIG_SYS_POST_USB 0x00000200 #define CONFIG_SYS_POST_SPR 0x00000400 #define CONFIG_SYS_POST_SYSMON 0x00000800 diff --git a/include/power/lp87565.h b/include/power/lp87565.h new file mode 100644 index 0000000..5160f5d --- /dev/null +++ b/include/power/lp87565.h @@ -0,0 +1,12 @@ +#define LP87565 0x0 +#define LP87565_Q1 0x1 + +#define LP87565_BUCK_NUM 6 + +/* Drivers name */ +#define LP87565_BUCK_DRIVER "lp87565_buck" + +#define LP87565_BUCK_VOLT_MASK 0xFF +#define LP87565_BUCK_VOLT_MAX_HEX 0xFF +#define LP87565_BUCK_VOLT_MAX 3360000 +#define LP87565_BUCK_MODE_MASK 0x80 diff --git a/include/power/tps65217.h b/include/power/tps65217.h index 69a49f7..cb07ea5 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -38,6 +38,7 @@ enum { TPS65217_DEFLS1, TPS65217_DEFLS2, TPS65217_ENABLE, + TPS65217_RESERVED0, /* no 0x17 register available */ TPS65217_DEFUVLO, TPS65217_SEQ1, TPS65217_SEQ2, diff --git a/include/power/tps65218.h b/include/power/tps65218.h index e3538e2..43b9c9a 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -63,6 +63,7 @@ enum { #define TPS65218_DCDC_VOLT_SEL_1200MV 0x23 #define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 +#define TPS65218_DCDC3_VOLT_SEL_1350MV 0x12 #define TPS65218_CC_STAT (BIT(0) | BIT(1)) #define TPS65218_STATE (BIT(2) | BIT(3)) diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 379c493..ce71ee9 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -81,93 +81,6 @@ #define r30 30 #define r31 31 - -#if defined(CONFIG_8xx) - -/* Some special registers */ - -#define ICR 148 /* Interrupt Cause Register (37-44) */ -#define DER 149 -#define COUNTA 150 /* Breakpoint Counter (37-44) */ -#define COUNTB 151 /* Breakpoint Counter (37-44) */ -#define LCTRL1 156 /* Load/Store Support (37-40) */ -#define LCTRL2 157 /* Load/Store Support (37-41) */ -#define ICTRL 158 - -#endif /* CONFIG_8xx */ - - -#if defined(CONFIG_5xx) -/* Some special purpose registers */ -#define DER 149 /* Debug Enable Register */ -#define COUNTA 150 /* Breakpoint Counter */ -#define COUNTB 151 /* Breakpoint Counter */ -#define LCTRL1 156 /* Load/Store Support */ -#define LCTRL2 157 /* Load/Store Support */ -#define ICTRL 158 /* I-Bus Support Control Register */ -#define EID 81 -#endif /* CONFIG_5xx */ - -#if defined(CONFIG_8xx) - -/* Registers in the processor's internal memory map that we use. -*/ -#define SYPCR 0x00000004 -#define BR0 0x00000100 -#define OR0 0x00000104 -#define BR1 0x00000108 -#define OR1 0x0000010c -#define BR2 0x00000110 -#define OR2 0x00000114 -#define BR3 0x00000118 -#define OR3 0x0000011c -#define BR4 0x00000120 -#define OR4 0x00000124 - -#define MAR 0x00000164 -#define MCR 0x00000168 -#define MAMR 0x00000170 -#define MBMR 0x00000174 -#define MSTAT 0x00000178 -#define MPTPR 0x0000017a -#define MDR 0x0000017c - -#define TBSCR 0x00000200 -#define TBREFF0 0x00000204 - -#define PLPRCR 0x00000284 - -#elif defined(CONFIG_MPC8260) - -#define HID2 1011 - -#define HID0_IFEM (1<<7) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#define IM_REGBASE 0x10000 -#define IM_SYPCR (IM_REGBASE+0x0004) -#define IM_SWSR (IM_REGBASE+0x000e) -#define IM_BR0 (IM_REGBASE+0x0100) -#define IM_OR0 (IM_REGBASE+0x0104) -#define IM_BR1 (IM_REGBASE+0x0108) -#define IM_OR1 (IM_REGBASE+0x010c) -#define IM_BR2 (IM_REGBASE+0x0110) -#define IM_OR2 (IM_REGBASE+0x0114) -#define IM_MPTPR (IM_REGBASE+0x0184) -#define IM_PSDMR (IM_REGBASE+0x0190) -#define IM_PSRT (IM_REGBASE+0x019c) -#define IM_IMMR (IM_REGBASE+0x01a8) -#define IM_SCCR (IM_REGBASE+0x0c80) - -#elif defined(CONFIG_MPC5xxx) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#endif - #define curptr r2 #define SYNC \ diff --git a/include/serial.h b/include/serial.h index 47332c5..a5b555d 100644 --- a/include/serial.h +++ b/include/serial.h @@ -29,9 +29,8 @@ extern struct serial_device *default_serial_console(void); #if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) || \ - defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ - defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ + defined(CONFIG_MPC86xx) || \ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ defined(CONFIG_MICROBLAZE) extern struct serial_device serial0_device; @@ -69,13 +68,6 @@ extern int usbtty_tstc(void); #endif /* CONFIG_USB_TTY */ -#if defined(CONFIG_MPC512X) -extern struct stdio_dev *open_port(int num, int baudrate); -extern int close_port(int num); -extern int write_port(struct stdio_dev *port, char *buf); -extern int read_port(struct stdio_dev *port, char *buf, int size); -#endif - struct udevice; /** @@ -192,10 +184,6 @@ void marvell_serial_initialize(void); void max3100_serial_initialize(void); void mcf_serial_initialize(void); void ml2_serial_initialize(void); -void mpc512x_serial_initialize(void); -void mpc5xx_serial_initialize(void); -void mpc8260_scc_serial_initialize(void); -void mpc8260_smc_serial_initialize(void); void mpc85xx_serial_initialize(void); void mpc8xx_serial_initialize(void); void mxc_serial_initialize(void); diff --git a/include/status_led.h b/include/status_led.h index f838f36..8178e93 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -40,17 +40,8 @@ void status_led_init(void); void status_led_tick (unsigned long timestamp); void status_led_set (int led, int state); -/***** TQM8xxL ********************************************************/ -#if defined(CONFIG_TQM8xxL) -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - /***** MVS v1 **********************************************************/ -#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2) +#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) # define STATUS_LED_PAR im_ioport.iop_pdpar # define STATUS_LED_DIR im_ioport.iop_pddir # undef STATUS_LED_ODR @@ -65,10 +56,6 @@ void status_led_set (int led, int state); * filling this file up with lots of custom board stuff. */ -#elif defined(CONFIG_V38B) - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - #elif defined(CONFIG_LED_STATUS_BOARD_SPECIFIC) /* led_id_t is unsigned long mask */ typedef unsigned long led_id_t; diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 7324d8a..1a370e0 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -16,7 +16,7 @@ struct dwc2_plat_otg_data { int phy_of_node; int (*phy_control)(int on); unsigned int regs_phy; - unsigned int regs_otg; + uintptr_t regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; unsigned int usb_gusbcfg; diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 8f3437a..847b698 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -156,9 +156,6 @@ #elif defined(CONFIG_MPC85xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_MPC512X) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR 0 #elif defined(CONFIG_ARCH_LS1021A) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h deleted file mode 100644 index 9906c75..0000000 --- a/include/usb/mpc8xx_udc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit - * bodonoghue@codehermit.ie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* Mode Register */ -#define USMOD_EN 0x01 -#define USMOD_HOST 0x02 -#define USMOD_TEST 0x04 -#define USMOD_SFTE 0x08 -#define USMOD_RESUME 0x40 -#define USMOD_LSS 0x80 - -/* Endpoint Registers */ -#define USEP_RHS_NORM 0x00 -#define USEP_RHS_IGNORE 0x01 -#define USEP_RHS_NAK 0x02 -#define USEP_RHS_STALL 0x03 - -#define USEP_THS_NORM 0x00 -#define USEP_THS_IGNORE 0x04 -#define USEP_THS_NAK 0x08 -#define USEP_THS_STALL 0x0C - -#define USEP_RTE 0x10 -#define USEP_MF 0x20 - -#define USEP_TM_CONTROL 0x00 -#define USEP_TM_INT 0x100 -#define USEP_TM_BULK 0x200 -#define USEP_TM_ISO 0x300 - -/* Command Register */ -#define USCOM_EP0 0x00 -#define USCOM_EP1 0x01 -#define USCOM_EP2 0x02 -#define USCOM_EP3 0x03 - -#define USCOM_FLUSH 0x40 -#define USCOM_STR 0x80 - -/* Event Register */ -#define USB_E_RXB 0x0001 -#define USB_E_TXB 0x0002 -#define USB_E_BSY 0x0004 -#define USB_E_SOF 0x0008 -#define USB_E_TXE1 0x0010 -#define USB_E_TXE2 0x0020 -#define USB_E_TXE3 0x0040 -#define USB_E_TXE4 0x0080 -#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) -#define USB_E_IDLE 0x0100 -#define USB_E_RESET 0x0200 - -/* Mask Register */ -#define USBS_IDLE 0x01 - -/* RX Buffer Descriptor */ -#define RX_BD_OV 0x02 -#define RX_BD_CR 0x04 -#define RX_BD_AB 0x08 -#define RX_BD_NO 0x10 -#define RX_BD_PID_DATA0 0x00 -#define RX_BD_PID_DATA1 0x40 -#define RX_BD_PID_SETUP 0x80 -#define RX_BD_F 0x400 -#define RX_BD_L 0x800 -#define RX_BD_I 0x1000 -#define RX_BD_W 0x2000 -#define RX_BD_E 0x8000 - -/* Useful masks */ -#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) -#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) -#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) -#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) - -/* TX Buffer Descriptor */ -#define TX_BD_UN 0x02 -#define TX_BD_TO 0x04 -#define TX_BD_NO_PID 0x00 -#define TX_BD_PID_DATA0 0x80 -#define TX_BD_PID_DATA1 0xC0 -#define TX_BD_CNF 0x200 -#define TX_BD_TC 0x400 -#define TX_BD_L 0x800 -#define TX_BD_I 0x1000 -#define TX_BD_W 0x2000 -#define TX_BD_R 0x8000 - -/* Implementation specific defines */ - -#define EP_MIN_PACKET_SIZE 0x08 -#define MAX_ENDPOINTS 0x04 -#define FIFO_SIZE 0x10 -#define EP_MAX_PKT FIFO_SIZE -#define TX_RING_SIZE 0x04 -#define RX_RING_SIZE 0x06 -#define USB_MAX_PKT 0x40 -#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 -#define TOGGLE_RX_PID(x) x^= 0x40 -#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ -#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ - -#define PROFF_USB 0x00000000 -#define CPM_USB_BASE 0x00000A00 - -/* UDC device defines */ -#define EP0_MAX_PACKET_SIZE EP_MAX_PKT - -#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE - -struct mpc8xx_ep { - struct urb * urb; - unsigned char pid; - unsigned char sc; - volatile cbd_t * prx; -}; - -typedef struct mpc8xx_usb{ - char usmod; /* Mode Register */ - char usaddr; /* Slave Address Register */ - char uscom; /* Command Register */ - char res1; /* Reserved */ - ushort usep[4]; - ulong res2; /* Reserved */ - ushort usber; /* Event Register */ - ushort res3; /* Reserved */ - ushort usbmr; /* Mask Register */ - char res4; /* Reserved */ - char usbs; /* Status Register */ - char res5[8]; /* Reserved */ -}usb_t; - -typedef struct mpc8xx_parameter_ram{ - ushort ep0ptr; /* Endpoint Pointer Register 0 */ - ushort ep1ptr; /* Endpoint Pointer Register 1 */ - ushort ep2ptr; /* Endpoint Pointer Register 2 */ - ushort ep3ptr; /* Endpoint Pointer Register 3 */ - uint rstate; /* Receive state */ - uint rptr; /* Receive internal data pointer */ - ushort frame_n; /* Frame number */ - ushort rbcnt; /* Receive byte count */ - uint rtemp; /* Receive temp cp use only */ - uint rxusb; /* Rx Data Temp */ - ushort rxuptr; /* Rx microcode return address temp */ -}usb_pram_t; - -typedef struct endpoint_parameter_block_pointer{ - ushort rbase; /* RxBD base address */ - ushort tbase; /* TxBD base address */ - char rfcr; /* Rx Function code */ - char tfcr; /* Tx Function code */ - ushort mrblr; /* Maximum Receive Buffer Length */ - ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ - ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ - ulong tstate; /* Transmit internal state */ - ulong tptr; /* Transmit internal data pointer */ - ushort tcrc; /* Transmit temp CRC */ - ushort tbcnt; /* Transmit internal bye count */ - ulong ttemp; /* Tx temp */ - ushort txuptr; /* Tx microcode return address */ - ushort res1; /* Reserved */ -}usb_epb_t; - -typedef enum mpc8xx_udc_state{ - STATE_NOT_READY, - STATE_ERROR, - STATE_READY, -}mpc8xx_udc_state_t; - diff --git a/include/watchdog.h b/include/watchdog.h index 174c894..322dda7 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -72,21 +72,6 @@ int init_func_watchdog_reset(void); * Prototypes from $(CPU)/cpu.c. */ -/* MPC 8xx */ -#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__) - void reset_8xx_watchdog(volatile immap_t *immr); -#endif - -/* MPC 5xx */ -#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__) - void reset_5xx_watchdog(volatile immap_t *immr); -#endif - -/* MPC 5xxx */ -#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__) - void reset_5xxx_watchdog(void); -#endif - /* AMCC 4xx */ #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__) void reset_4xx_watchdog(void); diff --git a/lib/bch.c b/lib/bch.c index ec53483..7a2d9d3 100644 --- a/lib/bch.c +++ b/lib/bch.c @@ -61,7 +61,11 @@ #include #else #include +#if defined(__FreeBSD__) +#include +#else #include +#endif #include #include #include @@ -113,6 +117,7 @@ struct gf_poly_deg1 { }; #ifdef USE_HOSTCC +#ifndef __BSD_VISIBLE static int fls(int x) { int r = 32; @@ -142,6 +147,7 @@ static int fls(int x) return r; } #endif +#endif /* * same as encode_bch(), but process input data one byte at a time diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5a5645a..91503b8 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1169,7 +1169,8 @@ int fdtdec_setup_memory_size(void) } gd->ram_size = (phys_size_t)(res.end - res.start + 1); - debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); + debug("%s: Initial DRAM size %llx\n", __func__, + (unsigned long long)gd->ram_size); return 0; } diff --git a/lib/libfdt/fdt.h b/lib/libfdt/fdt.h new file mode 100644 index 0000000..3134d78 --- /dev/null +++ b/lib/libfdt/fdt.h @@ -0,0 +1,67 @@ +#ifndef _FDT_H +#define _FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* _FDT_H */ diff --git a/lib/libfdt/libfdt.h b/lib/libfdt/libfdt.h new file mode 100644 index 0000000..2f7ebf8 --- /dev/null +++ b/lib/libfdt/libfdt.h @@ -0,0 +1,2144 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + */ + +#include +#include + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attempted to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. + * This can be caused either by an invalid phandle property + * length, or the phandle value was either 0 or -1, which are + * not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +/* Errors in device tree content */ +#define FDT_ERR_BADNCELLS 14 + /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells + * or similar property with a bad format or value */ + +#define FDT_ERR_BADVALUE 15 + /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected + * value. For example: a property expected to contain a string list + * is not NUL-terminated within the length of its value. */ + +#define FDT_ERR_BADOVERLAY 16 + /* FDT_ERR_BADOVERLAY: The device tree overlay, while + * correctly structured, cannot be applied due to some + * unexpected or missing value, property or node. */ + +#define FDT_ERR_NOPHANDLES 17 + /* FDT_ERR_NOPHANDLES: The device tree doesn't have any + * phandle available anymore without causing an overflow */ + +#define FDT_ERR_TOODEEP 18 + /* FDT_ERR_TOODEEP: The depth of a node has exceeded the internal + * libfdt limit. This can happen if you have more than + * FDT_MAX_DEPTH nested nodes. */ + +#define FDT_ERR_MAX 18 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +#endif +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/** + * fdt_for_each_subnode - iterate over all subnodes of a parent + * + * @node: child node (int, lvalue) + * @fdt: FDT blob (const void *) + * @parent: parent node (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_subnode(node, fdt, parent) { + * Use node + * ... + * } + * + * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and @node is used as + * iterator in the loop. The parent variable be constant or even a + * literal. + * + */ +#define fdt_for_each_subnode(node, fdt, parent) \ + for (node = fdt_first_subnode(fdt, parent); \ + node >= 0; \ + node = fdt_next_subnode(fdt, node)) + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header *)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic); +__fdt_set_hdr(totalsize); +__fdt_set_hdr(off_dt_struct); +__fdt_set_hdr(off_dt_strings); +__fdt_set_hdr(off_mem_rsvmap); +__fdt_set_hdr(version); +__fdt_set_hdr(last_comp_version); +__fdt_set_hdr(boot_cpuid_phys); +__fdt_set_hdr(size_dt_strings); +__fdt_set_hdr(size_dt_struct); +#undef __fdt_set_hdr + +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_get_max_phandle - retrieves the highest phandle in a tree + * @fdt: pointer to the device tree blob + * + * fdt_get_max_phandle retrieves the highest phandle in the given + * device tree. This will ignore badly formatted phandles, or phandles + * with a value of 0 or -1. + * + * returns: + * the highest phandle on success + * 0, if no phandle was found in the device tree + * -1, if an error occurred + */ +uint32_t fdt_get_max_phandle(const void *fdt); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +#endif +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset_namelen - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * @namelen: number of characters of path to consider + * + * Identical to fdt_path_offset(), but only consider the first namelen + * characters of path as the path name. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); +#endif + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on + * success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name + * (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_for_each_property_offset - iterate over all properties of a node + * + * @property_offset: property offset (int, lvalue) + * @fdt: FDT blob (const void *) + * @node: node offset (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_property_offset(property, fdt, node) { + * Use property + * ... + * } + * + * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and property is used as + * iterator in the loop. The node variable can be constant or even a + * literal. + */ +#define fdt_for_each_property_offset(property, fdt, node) \ + for (property = fdt_first_property_offset(fdt, node); \ + property >= 0; \ + property = fdt_next_property_offset(fdt, property)) + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); +#endif + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); +#endif + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); +static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, + const char *name, int namelen, + int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, + namelen, lenp); +} +#endif + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +#ifndef SWIG /* Not available in Python */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); +#endif + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of + * nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/** + * fdt_stringlist_count - count the number of strings in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @return: + * the number of strings in the given property + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); + +/** + * fdt_stringlist_search - find a string in a string list and return its index + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @string: string to look up in the string list + * + * Note that it is possible for this function to succeed on property values + * that are not NUL-terminated. That's because the function will stop after + * finding the first occurrence of @string. This can for example happen with + * small-valued cell properties, such as #address-cells, when searching for + * the empty string. + * + * @return: + * the index of the string in the list of strings + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist or does not contain + * the given string + */ +int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, + const char *string); + +/** + * fdt_stringlist_get() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @index: index of the string to return + * @lenp: return location for the string length or an error code on failure + * + * Note that this will successfully extract strings from properties with + * non-NUL-terminated values. For example on small-valued cell properties + * this function will return the empty string. + * + * If non-NULL, the length of the string (on success) or a negative error-code + * (on failure) will be stored in the integer pointer to by lenp. + * + * @return: + * A pointer to the string at the given index in the string list or NULL on + * failure. On success the length of the string will be stored in the memory + * location pointed to by the lenp parameter, if non-NULL. On failure one of + * the following negative error codes will be returned in the lenp parameter + * (if non-NULL): + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +const char *fdt_stringlist_get(const void *fdt, int nodeoffset, + const char *property, int index, + int *lenp); + +/**********************************************************************/ +/* Read-only functions (addressing related) */ +/**********************************************************************/ + +/** + * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells + * + * This is the maximum value for #address-cells, #size-cells and + * similar properties that will be processed by libfdt. IEE1275 + * requires that OF implementations handle values up to 4. + * Implementations may support larger values, but in practice higher + * values aren't used. + */ +#define FDT_MAX_NCELLS 4 + +/** + * fdt_address_cells - retrieve address size for a bus represented in the tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address size for + * + * When the node has a valid #address-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_address_cells(const void *fdt, int nodeoffset); + +/** + * fdt_size_cells - retrieve address range size for a bus represented in the + * tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address range size for + * + * When the node has a valid #size-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #size-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_size_cells(const void *fdt, int nodeoffset); + + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace_namelen_partial - change a property's value, + * but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @namelen: number of characters of name to consider + * @idx: index of the property to change in the array + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * Identical to fdt_setprop_inplace(), but modifies the given property + * starting from the given index, and using only the first characters + * of the name. It is useful when you want to manipulate only one value of + * an array and you have a string that doesn't end with \0. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t idx, const void *val, + int len); +#endif + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); +#endif + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_resize(void *fdt, void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} + +/** + * fdt_property_placeholder - add a new property and return a ptr to its value + * + * @fdt: pointer to the device tree blob + * @name: name of property to add + * @len: length of property value in bytes + * @valp: returns a pointer to where where the value should be placed + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_NOSPACE, standard meanings + */ +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); + +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + + +/** + * fdt_setprop_empty - set a property to an empty value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * + * fdt_setprop_empty() sets the value of the named property in the + * given node to an empty (zero length) value, or creates a new empty + * property if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_empty(fdt, nodeoffset, name) \ + fdt_setprop((fdt), (nodeoffset), (name), NULL, 0) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); +#endif + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on + * success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/** + * fdt_overlay_apply - Applies a DT overlay on a base DT + * @fdt: pointer to the base device tree blob + * @fdto: pointer to the device tree overlay blob + * + * fdt_overlay_apply() will apply the given device tree overlay on the + * given base device tree. + * + * Expect the base device tree to be modified, even if the function + * returns an error. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there's not enough space in the base device tree + * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or + * properties in the base DT + * -FDT_ERR_BADPHANDLE, + * -FDT_ERR_BADOVERLAY, + * -FDT_ERR_NOPHANDLES, + * -FDT_ERR_INTERNAL, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADOFFSET, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_overlay_apply(void *fdt, void *fdto); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +#ifndef SWIG /* Not available in Python */ +const char *fdt_strerror(int errval); + +/** + * fdt_remove_unused_strings() - Remove any unused strings from an FDT + * + * This creates a new device tree in @new with unused strings removed. The + * called can then use fdt_pack() to minimise the space consumed. + * + * @old: Old device tree blog + * @new: Place to put new device tree blob, which must be as large as + * @old + * @return + * 0, on success + * -FDT_ERR_BADOFFSET, corrupt device tree + * -FDT_ERR_NOSPACE, out of space, which should not happen unless there + * is something very wrong with the device tree input + */ +int fdt_remove_unused_strings(const void *old, void *new); + +struct fdt_region { + int offset; + int size; +}; + +/* + * Flags for fdt_find_regions() + * + * Add a region for the string table (always the last region) + */ +#define FDT_REG_ADD_STRING_TAB (1 << 0) + +/* + * Add all supernodes of a matching node/property, useful for creating a + * valid subset tree + */ +#define FDT_REG_SUPERNODES (1 << 1) + +/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */ +#define FDT_REG_DIRECT_SUBNODES (1 << 2) + +/* Add all subnodes of a matching node */ +#define FDT_REG_ALL_SUBNODES (1 << 3) + +/* Add a region for the mem_rsvmap table (always the first region) */ +#define FDT_REG_ADD_MEM_RSVMAP (1 << 4) + +/* Indicates what an fdt part is (node, property, value) */ +#define FDT_IS_NODE (1 << 0) +#define FDT_IS_PROP (1 << 1) +#define FDT_IS_VALUE (1 << 2) /* not supported */ +#define FDT_IS_COMPAT (1 << 3) /* used internally */ +#define FDT_NODE_HAS_PROP (1 << 4) /* node contains prop */ + +#define FDT_ANY_GLOBAL (FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \ + FDT_IS_COMPAT) +#define FDT_IS_ANY 0x1f /* all the above */ + +/* We set a reasonable limit on the number of nested nodes */ +#define FDT_MAX_DEPTH 32 + +/* Decribes what we want to include from the current tag */ +enum want_t { + WANT_NOTHING, + WANT_NODES_ONLY, /* No properties */ + WANT_NODES_AND_PROPS, /* Everything for one level */ + WANT_ALL_NODES_AND_PROPS /* Everything for all levels */ +}; + +/* Keeps track of the state at parent nodes */ +struct fdt_subnode_stack { + int offset; /* Offset of node */ + enum want_t want; /* The 'want' value here */ + int included; /* 1 if we included this node, 0 if not */ +}; + +struct fdt_region_ptrs { + int depth; /* Current tree depth */ + int done; /* What we have completed scanning */ + enum want_t want; /* What we are currently including */ + char *end; /* Pointer to end of full node path */ + int nextoffset; /* Next node offset to check */ +}; + +/* The state of our finding algortihm */ +struct fdt_region_state { + struct fdt_subnode_stack stack[FDT_MAX_DEPTH]; /* node stack */ + struct fdt_region *region; /* Contains list of regions found */ + int count; /* Numnber of regions found */ + const void *fdt; /* FDT blob */ + int max_regions; /* Maximum regions to find */ + int can_merge; /* 1 if we can merge with previous region */ + int start; /* Start position of current region */ + struct fdt_region_ptrs ptrs; /* Pointers for what we are up to */ +}; + +/** + * fdt_find_regions() - find regions in device tree + * + * Given a list of nodes to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * + * Nodes which are given in 'inc' are included in the region list, as + * are the names of the immediate subnodes nodes (but not the properties + * or subnodes of those subnodes). + * + * For eaxample "/" means to include the root node, all root properties + * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter + * ensures that we capture the names of the subnodes. In a hashing situation + * it prevents the root node from changing at all Any change to non-excluded + * properties, names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. + * + * The device tree header is not included in the list. + * + * @fdt: Device tree to check + * @inc: List of node paths to included + * @inc_count: Number of node paths in list + * @exc_prop: List of properties names to exclude + * @exc_prop_count: Number of properties in exclude list + * @region: Returns list of regions + * @max_region: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @add_string_tab: 1 to add a region for the string table + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. + */ +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab); + +/** + * fdt_first_region() - find regions in device tree + * + * Given a nodes and properties to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The use for this function is twofold. Firstly it provides a convenient + * way of performing a structure-aware grep of the tree. For example it is + * possible to grep for a node and get all the properties associated with + * that node. Trees can be subsetted easily, by specifying the nodes that + * are required, and then writing out the regions returned by this function. + * This is useful for small resource-constrained systems, such as boot + * loaders, which want to use an FDT but do not need to know about all of + * it. + * + * Secondly it makes it easy to hash parts of the tree and detect changes. + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * Note that semantically null changes in order could still cause false + * hash misses. Such reordering might happen if the tree is regenerated + * from source, and nodes are reordered (the bytes-stream will be emitted + * in a different order and mnay hash functions will detect this). However + * if an existing tree is modified using libfdt functions, such as + * fdt_add_subnode() and fdt_setprop(), then this problem is avoided. + * + * The nodes/properties to include/exclude are defined by a function + * provided by the caller. This function is called for each node and + * property, and must return: + * + * 0 - to exclude this part + * 1 - to include this part + * -1 - for FDT_IS_PROP only: no information is available, so include + * if its containing node is included + * + * The last case is only used to deal with properties. Often a property is + * included if its containing node is included - this is the case where + * -1 is returned.. However if the property is specifically required to be + * included/excluded, then 0 or 1 can be returned. Note that including a + * property when the FDT_REG_SUPERNODES flag is given will force its + * containing node to be included since it is not valid to have a property + * that is not in a node. + * + * Using the information provided, the inclusion of a node can be controlled + * either by a node name or its compatible string, or any other property + * that the function can determine. + * + * As an example, including node "/" means to include the root node and all + * root properties. A flag provides a way of also including supernodes (of + * which there is none for the root node), and another flag includes + * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and + * FDT_END_NODE of all subnodes of /. + * + * The subnode feature helps in a hashing situation since it prevents the + * root node from changing at all. Any change to non-excluded properties, + * names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. This is always + * the last region. + * + * The FDT also has a mem_rsvmap table which can also be included, and is + * always the first region if so. + * + * The device tree header is not included in the region list. Since the + * contents of the FDT are changing (shrinking, often), the caller will need + * to regenerate the header anyway. + * + * @fdt: Device tree to check + * @h_include: Function to call to determine whether to include a part or + * not: + * + * @priv: Private pointer as passed to fdt_find_regions() + * @fdt: Pointer to FDT blob + * @offset: Offset of this node / property + * @type: Type of this part, FDT_IS_... + * @data: Pointer to data (node name, property name, compatible + * string, value (not yet supported) + * @size: Size of data, or 0 if none + * @return 0 to exclude, 1 to include, -1 if no information is + * available + * @priv: Private pointer passed to h_include + * @region: Returns list of regions, sorted by offset + * @max_regions: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @flags: Various flags that control the region algortihm, see + * FDT_REG_... + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. Only the first max_regions elements are available in the + * array. + * + * On error a -ve value is return, which can be: + * + * -FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_NOSPACE (path area is too small) + */ +int fdt_first_region(const void *fdt, + int (*h_include)(void *priv, const void *fdt, int offset, + int type, const char *data, int size), + void *priv, struct fdt_region *region, + char *path, int path_len, int flags, + struct fdt_region_state *info); + +/** fdt_next_region() - find next region + * + * See fdt_first_region() for full description. This function finds the + * next region according to the provided parameters, which must be the same + * as passed to fdt_first_region(). + * + * This function can additionally return -FDT_ERR_NOTFOUND when there are no + * more regions + */ +int fdt_next_region(const void *fdt, + int (*h_include)(void *priv, const void *fdt, int offset, + int type, const char *data, int size), + void *priv, struct fdt_region *region, + char *path, int path_len, int flags, + struct fdt_region_state *info); + +/** + * fdt_add_alias_regions() - find aliases that point to existing regions + * + * Once a device tree grep is complete some of the nodes will be present + * and some will have been dropped. This function checks all the alias nodes + * to figure out which points point to nodes which are still present. These + * aliases need to be kept, along with the nodes they reference. + * + * Given a list of regions function finds the aliases that still apply and + * adds more regions to the list for these. This function is called after + * fdt_next_region() has finished returning regions and requires the same + * state. + * + * @fdt: Device tree file to reference + * @region: List of regions that will be kept + * @count: Number of regions + * @max_regions: Number of entries that can fit in @region + * @info: Region state as returned from fdt_next_region() + * @return new number of regions in @region (i.e. count + the number added) + * or -FDT_ERR_NOSPACE if there was not enough space. + */ +int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, + int max_regions, struct fdt_region_state *info); +#endif /* SWIG */ + +#endif /* _LIBFDT_H */ diff --git a/lib/libfdt/libfdt.swig b/lib/libfdt/libfdt.swig deleted file mode 100644 index b24c72b..0000000 --- a/lib/libfdt/libfdt.swig +++ /dev/null @@ -1,113 +0,0 @@ -/* File: libfdt.i */ -%module libfdt - -%{ -#define SWIG_FILE_WITH_INIT -#include "libfdt.h" -%} - -%pythoncode %{ -def Raise(errnum): - raise ValueError('Error %s' % fdt_strerror(errnum)) - -def Name(fdt, offset): - name, len = fdt_get_name(fdt, offset) - return name - -def String(fdt, offset): - offset = fdt32_to_cpu(offset) - name = fdt_string(fdt, offset) - return name - -def swap32(x): - return (((x << 24) & 0xFF000000) | - ((x << 8) & 0x00FF0000) | - ((x >> 8) & 0x0000FF00) | - ((x >> 24) & 0x000000FF)) - -def fdt32_to_cpu(x): - return swap32(x) - -def Data(prop): - set_prop(prop) - return get_prop_data() -%} - -%include "typemaps.i" -%include "cstring.i" - -%typemap(in) void* = char*; - -typedef int fdt32_t; - -struct fdt_property { - fdt32_t tag; - fdt32_t len; - fdt32_t nameoff; - char data[0]; -}; - -/* - * This is a work-around since I'm not sure of a better way to copy out the - * contents of a string. This is used in dtoc/GetProps(). The intent is to - * pass in a pointer to a property and access the data field at the end of - * it. Ideally the Data() function above would be able to do this directly, - * but I'm not sure how to do that. - */ -#pragma SWIG nowarn=454 -%inline %{ - static struct fdt_property *cur_prop; - - void set_prop(struct fdt_property *prop) { - cur_prop = prop; - } -%} - -%cstring_output_allocate_size(char **s, int *sz, free(*$1)); -%inline %{ - void get_prop_data(char **s, int *sz) { - *sz = fdt32_to_cpu(cur_prop->len); - *s = (char *)malloc(*sz); - if (!*s) - *sz = 0; - else - memcpy(*s, cur_prop + 1, *sz); - } -%} - -%typemap(in) (const void *) { - if (!PyByteArray_Check($input)) { - SWIG_exception_fail(SWIG_TypeError, "in method '" "$symname" "', argument " - "$argnum"" of type '" "$type""'"); - } - $1 = (void *) PyByteArray_AsString($input); -} - -const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); -int fdt_path_offset(const void *fdt, const char *path); -int fdt_first_property_offset(const void *fdt, int nodeoffset); -int fdt_next_property_offset(const void *fdt, int offset); -const char *fdt_strerror(int errval); -const struct fdt_property *fdt_get_property_by_offset(const void *fdt, - int offset, - int *OUTPUT); -const char *fdt_get_name(const void *fdt, int nodeoffset, int *OUTPUT); -const char *fdt_string(const void *fdt, int stroffset); -int fdt_first_subnode(const void *fdt, int offset); -int fdt_next_subnode(const void *fdt, int offset); - -%typemap(in) (void *) { - if (!PyByteArray_Check($input)) { - SWIG_exception_fail(SWIG_TypeError, "in method '" "$symname" "', argument " - "$argnum"" of type '" "$type""'"); - } - $1 = PyByteArray_AsString($input); -} - -int fdt_delprop(void *fdt, int nodeoffset, const char *name); - -const char *fdt_strerror(int errval); -int fdt_pack(void *fdt); - -int fdt_totalsize(const void *fdt); -int fdt_off_dt_struct(const void *fdt); diff --git a/lib/libfdt/pylibfdt/libfdt.i b/lib/libfdt/pylibfdt/libfdt.i new file mode 100644 index 0000000..3b11bb0 --- /dev/null +++ b/lib/libfdt/pylibfdt/libfdt.i @@ -0,0 +1,389 @@ +/* + * pylibfdt - Flat Device Tree manipulation in Python + * Copyright (C) 2017 Google, Inc. + * Written by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + */ + +%module libfdt + +%{ +#define SWIG_FILE_WITH_INIT +#include "libfdt.h" +%} + +%pythoncode %{ + +import struct + +# Error codes, corresponding to FDT_ERR_... in libfdt.h +(NOTFOUND, + EXISTS, + NOSPACE, + BADOFFSET, + BADPATH, + BADPHANDLE, + BADSTATE, + TRUNCATED, + BADMAGIC, + BADVERSION, + BADSTRUCTURE, + BADLAYOUT, + INTERNAL, + BADNCELLS, + BADVALUE, + BADOVERLAY, + NOPHANDLES) = QUIET_ALL = range(1, 18) +# QUIET_ALL can be passed as the 'quiet' parameter to avoid exceptions +# altogether. All # functions passed this value will return an error instead +# of raising an exception. + +# Pass this as the 'quiet' parameter to return -ENOTFOUND on NOTFOUND errors, +# instead of raising an exception. +QUIET_NOTFOUND = (NOTFOUND,) + + +class FdtException(Exception): + """An exception caused by an error such as one of the codes above""" + def __init__(self, err): + self.err = err + + def __str__(self): + return 'pylibfdt error %d: %s' % (self.err, fdt_strerror(self.err)) + +def strerror(fdt_err): + """Get the string for an error number + + Args: + fdt_err: Error number (-ve) + + Returns: + String containing the associated error + """ + return fdt_strerror(fdt_err) + +def check_err(val, quiet=()): + """Raise an error if the return value is -ve + + This is used to check for errors returned by libfdt C functions. + + Args: + val: Return value from a libfdt function + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + val if val >= 0 + + Raises + FdtException if val < 0 + """ + if val < 0: + if -val not in quiet: + raise FdtException(val) + return val + +def check_err_null(val, quiet=()): + """Raise an error if the return value is NULL + + This is used to check for a NULL return value from certain libfdt C + functions + + Args: + val: Return value from a libfdt function + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + val if val is a list, None if not + + Raises + FdtException if val indicates an error was reported and the error + is not in @quiet. + """ + # Normally a list is returned which contains the data and its length. + # If we get just an integer error code, it means the function failed. + if not isinstance(val, list): + if -val not in quiet: + raise FdtException(val) + return val + +class Fdt: + """Device tree class, supporting all operations + + The Fdt object is created is created from a device tree binary file, + e.g. with something like: + + fdt = Fdt(open("filename.dtb").read()) + + Operations can then be performed using the methods in this class. Each + method xxx(args...) corresponds to a libfdt function fdt_xxx(fdt, args...). + + All methods raise an FdtException if an error occurs. To avoid this + behaviour a 'quiet' parameter is provided for some functions. This + defaults to empty, but you can pass a list of errors that you expect. + If one of these errors occurs, the function will return an error number + (e.g. -NOTFOUND). + """ + def __init__(self, data): + self._fdt = bytearray(data) + check_err(fdt_check_header(self._fdt)); + + def path_offset(self, path, quiet=()): + """Get the offset for a given path + + Args: + path: Path to the required node, e.g. '/node@3/subnode@1' + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + Node offset + + Raises + FdtException if the path is not valid or not found + """ + return check_err(fdt_path_offset(self._fdt, path), quiet) + + def first_property_offset(self, nodeoffset, quiet=()): + """Get the offset of the first property in a node offset + + Args: + nodeoffset: Offset to the node to check + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + Offset of the first property + + Raises + FdtException if the associated node has no properties, or some + other error occurred + """ + return check_err(fdt_first_property_offset(self._fdt, nodeoffset), + quiet) + + def next_property_offset(self, prop_offset, quiet=()): + """Get the next property in a node + + Args: + prop_offset: Offset of the previous property + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + Offset of the next property + + Raises: + FdtException if the associated node has no more properties, or + some other error occurred + """ + return check_err(fdt_next_property_offset(self._fdt, prop_offset), + quiet) + + def get_name(self, nodeoffset): + """Get the name of a node + + Args: + nodeoffset: Offset of node to check + + Returns: + Node name + + Raises: + FdtException on error (e.g. nodeoffset is invalid) + """ + return check_err_null(fdt_get_name(self._fdt, nodeoffset))[0] + + def get_property_by_offset(self, prop_offset, quiet=()): + """Obtains a property that can be examined + + Args: + prop_offset: Offset of property (e.g. from first_property_offset()) + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + Property object, or None if not found + + Raises: + FdtException on error (e.g. invalid prop_offset or device + tree format) + """ + pdata = check_err_null( + fdt_get_property_by_offset(self._fdt, prop_offset), quiet) + if isinstance(pdata, (int)): + return pdata + return Property(pdata[0], pdata[1]) + + def first_subnode(self, nodeoffset, quiet=()): + """Find the first subnode of a parent node + + Args: + nodeoffset: Node offset of parent node + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + The offset of the first subnode, if any + + Raises: + FdtException if no subnode found or other error occurs + """ + return check_err(fdt_first_subnode(self._fdt, nodeoffset), quiet) + + def next_subnode(self, nodeoffset, quiet=()): + """Find the next subnode + + Args: + nodeoffset: Node offset of previous subnode + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + The offset of the next subnode, if any + + Raises: + FdtException if no more subnode found or other error occurs + """ + return check_err(fdt_next_subnode(self._fdt, nodeoffset), quiet) + + def totalsize(self): + """Return the total size of the device tree + + Returns: + Total tree size in bytes + """ + return check_err(fdt_totalsize(self._fdt)) + + def off_dt_struct(self): + """Return the start of the device tree struct area + + Returns: + Start offset of struct area + """ + return check_err(fdt_off_dt_struct(self._fdt)) + + def pack(self, quiet=()): + """Pack the device tree to remove unused space + + This adjusts the tree in place. + + Args: + quiet: Errors to ignore (empty to raise on all errors) + + Raises: + FdtException if any error occurs + """ + return check_err(fdt_pack(self._fdt), quiet) + + def delprop(self, nodeoffset, prop_name): + """Delete a property from a node + + Args: + nodeoffset: Node offset containing property to delete + prop_name: Name of property to delete + + Raises: + FdtError if the property does not exist, or another error occurs + """ + return check_err(fdt_delprop(self._fdt, nodeoffset, prop_name)) + + def getprop(self, nodeoffset, prop_name, quiet=()): + """Get a property from a node + + Args: + nodeoffset: Node offset containing property to get + prop_name: Name of property to get + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + Value of property as a bytearray, or -ve error number + + Raises: + FdtError if any error occurs (e.g. the property is not found) + """ + pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name), + quiet) + if isinstance(pdata, (int)): + return pdata + return bytearray(pdata[0]) + + +class Property: + """Holds a device tree property name and value. + + This holds a copy of a property taken from the device tree. It does not + reference the device tree, so if anything changes in the device tree, + a Property object will remain valid. + + Properties: + name: Property name + value: Proper value as a bytearray + """ + def __init__(self, name, value): + self.name = name + self.value = value +%} + +%rename(fdt_property) fdt_property_func; + +typedef int fdt32_t; + +%include "libfdt/fdt.h" + +%include "typemaps.i" + +/* Most functions don't change the device tree, so use a const void * */ +%typemap(in) (const void *)(const void *fdt) { + if (!PyByteArray_Check($input)) { + SWIG_exception_fail(SWIG_TypeError, "in method '" "$symname" + "', argument " "$argnum"" of type '" "$type""'"); + } + $1 = (void *)PyByteArray_AsString($input); + fdt = $1; + fdt = fdt; /* avoid unused variable warning */ +} + +/* Some functions do change the device tree, so use void * */ +%typemap(in) (void *)(const void *fdt) { + if (!PyByteArray_Check($input)) { + SWIG_exception_fail(SWIG_TypeError, "in method '" "$symname" + "', argument " "$argnum"" of type '" "$type""'"); + } + $1 = PyByteArray_AsString($input); + fdt = $1; + fdt = fdt; /* avoid unused variable warning */ +} + +%typemap(out) (struct fdt_property *) { + PyObject *buff; + + if ($1) { + resultobj = PyString_FromString( + fdt_string(fdt1, fdt32_to_cpu($1->nameoff))); + buff = PyByteArray_FromStringAndSize( + (const char *)($1 + 1), fdt32_to_cpu($1->len)); + resultobj = SWIG_Python_AppendOutput(resultobj, buff); + } +} + +%apply int *OUTPUT { int *lenp }; + +/* typemap used for fdt_getprop() */ +%typemap(out) (const void *) { + if (!$1) + $result = Py_None; + else + $result = Py_BuildValue("s#", $1, *arg4); +} + +/* We have both struct fdt_property and a function fdt_property() */ +%warnfilter(302) fdt_property; + +/* These are macros in the header so have to be redefined here */ +int fdt_magic(const void *fdt); +int fdt_totalsize(const void *fdt); +int fdt_off_dt_struct(const void *fdt); +int fdt_off_dt_strings(const void *fdt); +int fdt_off_mem_rsvmap(const void *fdt); +int fdt_version(const void *fdt); +int fdt_last_comp_version(const void *fdt); +int fdt_boot_cpuid_phys(const void *fdt); +int fdt_size_dt_strings(const void *fdt); +int fdt_size_dt_struct(const void *fdt); + +%include <../libfdt/libfdt.h> diff --git a/lib/libfdt/pylibfdt/setup.py b/lib/libfdt/pylibfdt/setup.py new file mode 100755 index 0000000..daf1089 --- /dev/null +++ b/lib/libfdt/pylibfdt/setup.py @@ -0,0 +1,123 @@ +#!/usr/bin/env python + +""" +setup.py file for SWIG libfdt +Copyright (C) 2017 Google, Inc. +Written by Simon Glass + +SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + +Files to be built into the extension are provided in SOURCES +C flags to use are provided in CPPFLAGS +Object file directory is provided in OBJDIR +Version is provided in VERSION + +If these variables are not given they are parsed from the Makefiles. This +allows this script to be run stand-alone, e.g.: + + ./pylibfdt/setup.py install [--prefix=...] +""" + +from distutils.core import setup, Extension +import os +import re +import sys + +# Decodes a Makefile assignment line into key and value (and plus for +=) +RE_KEY_VALUE = re.compile('(?P\w+) *(?P[+])?= *(?P.*)$') + + +def ParseMakefile(fname): + """Parse a Makefile to obtain its variables. + + This collects variable assigments of the form: + + VAR = value + VAR += more + + It does not pick out := assignments, as these are not needed here. It does + handle line continuation. + + Returns a dict: + key: Variable name (e.g. 'VAR') + value: Variable value (e.g. 'value more') + """ + makevars = {} + with open(fname) as fd: + prev_text = '' # Continuation text from previous line(s) + for line in fd.read().splitlines(): + if line and line[-1] == '\\': # Deal with line continuation + prev_text += line[:-1] + continue + elif prev_text: + line = prev_text + line + prev_text = '' # Continuation is now used up + m = RE_KEY_VALUE.match(line) + if m: + value = m.group('value') or '' + key = m.group('key') + + # Appending to a variable inserts a space beforehand + if 'plus' in m.groupdict() and key in makevars: + makevars[key] += ' ' + value + else: + makevars[key] = value + return makevars + +def GetEnvFromMakefiles(): + """Scan the Makefiles to obtain the settings we need. + + This assumes that this script is being run from the top-level directory, + not the pylibfdt directory. + + Returns: + Tuple with: + List of swig options + Version string + List of files to build + List of extra C preprocessor flags needed + Object directory to use (always '') + """ + basedir = os.path.dirname(os.path.dirname(os.path.abspath(sys.argv[0]))) + swig_opts = ['-I%s' % basedir] + makevars = ParseMakefile(os.path.join(basedir, 'Makefile')) + version = '%s.%s.%s' % (makevars['VERSION'], makevars['PATCHLEVEL'], + makevars['SUBLEVEL']) + makevars = ParseMakefile(os.path.join(basedir, 'libfdt', 'Makefile.libfdt')) + files = makevars['LIBFDT_SRCS'].split() + files = [os.path.join(basedir, 'libfdt', fname) for fname in files] + files.append('pylibfdt/libfdt.i') + cflags = ['-I%s' % basedir, '-I%s/libfdt' % basedir] + objdir = '' + return swig_opts, version, files, cflags, objdir + + +progname = sys.argv[0] +files = os.environ.get('SOURCES', '').split() +cflags = os.environ.get('CPPFLAGS', '').split() +objdir = os.environ.get('OBJDIR') +version = os.environ.get('VERSION') +swig_opts = os.environ.get('SWIG_OPTS', '').split() + +# If we were called directly rather than through our Makefile (which is often +# the case with Python module installation), read the settings from the +# Makefile. +if not all((swig_opts, version, files, cflags, objdir)): + swig_opts, version, files, cflags, objdir = GetEnvFromMakefiles() + +libfdt_module = Extension( + '_libfdt', + sources = files, + extra_compile_args = cflags, + swig_opts = swig_opts, +) + +setup( + name='libfdt', + version= version, + author='Simon Glass ', + description='Python binding for libfdt', + ext_modules=[libfdt_module], + package_dir={'': objdir}, + py_modules=['pylibfdt/libfdt'], +) diff --git a/lib/libfdt/setup.py b/lib/libfdt/setup.py deleted file mode 100644 index 845a0c2..0000000 --- a/lib/libfdt/setup.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python - -""" -setup.py file for SWIG libfdt -""" - -from distutils.core import setup, Extension -import os -import sys - -# Don't cross-compile - always use the host compiler. -del os.environ['CROSS_COMPILE'] -del os.environ['CC'] - -progname = sys.argv[0] -cflags = sys.argv[1] -files = sys.argv[2:] - -if cflags: - cflags = [flag for flag in cflags.split(' ') if flag] -else: - cflags = None - -libfdt_module = Extension( - '_libfdt', - sources = files, - extra_compile_args = cflags -) - -sys.argv = [progname, '--quiet', 'build_ext', '--inplace', '--force'] - -setup (name = 'libfdt', - version = '0.1', - author = "SWIG Docs", - description = """Simple swig libfdt from docs""", - ext_modules = [libfdt_module], - py_modules = ["libfdt"], - ) diff --git a/lib/time.c b/lib/time.c index 3c49243..aed1a09 100644 --- a/lib/time.c +++ b/lib/time.c @@ -36,6 +36,23 @@ unsigned long notrace timer_read_counter(void) return readl(CONFIG_SYS_TIMER_COUNTER); #endif } + +ulong timer_get_boot_us(void) +{ + ulong count = timer_read_counter(); + +#if CONFIG_SYS_TIMER_RATE == 1000000 + return count; +#elif CONFIG_SYS_TIMER_RATE > 1000000 + return lldiv(count, CONFIG_SYS_TIMER_RATE / 1000000); +#elif defined(CONFIG_SYS_TIMER_RATE) + return (unsigned long long)count * 1000000 / CONFIG_SYS_TIMER_RATE; +#else + /* Assume the counter is in microseconds */ + return count; +#endif +} + #else extern unsigned long __weak timer_read_counter(void); #endif diff --git a/post/Makefile b/post/Makefile index 78ede8c..09bf408 100644 --- a/post/Makefile +++ b/post/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_POST_STD_LIST) += tests.o obj-y += drivers/ obj-$(CONFIG_PPC) += lib_powerpc/ obj-$(CONFIG_MPC83xx) += cpu/mpc83xx/ -obj-$(CONFIG_8xx) += cpu/mpc8xx/ obj-$(CONFIG_4xx) += cpu/ppc4xx/ ifneq ($(filter lwmon5 pdm360ng,$(BOARD)),) obj-y += board/$(BOARD)/ diff --git a/post/board/pdm360ng/Makefile b/post/board/pdm360ng/Makefile deleted file mode 100644 index 9aa96a1..0000000 --- a/post/board/pdm360ng/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2010 DENX Software Engineering -# Anatolij Gustschin, agust@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += coproc_com.o diff --git a/post/board/pdm360ng/coproc_com.c b/post/board/pdm360ng/coproc_com.c deleted file mode 100644 index e11b69b..0000000 --- a/post/board/pdm360ng/coproc_com.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2010 DENX Software Engineering, - * Anatolij Gustschin, agust@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Co-Processor communication POST - */ -#include -#include -#include - -/* - * Actually the termination sequence of the coprocessor - * commands is "\r\n" (CR LF), but here we use a side effect of - * the putc() routine of the serial driver which checks for LF - * and sends CR before sending LF. Therefore the termination - * sequence in the command below is only "\n". - * "alive" string is the coprocessor response for ping command - * and not a command, therefore it is terminated with "\r\n". - */ -char alive[] = "$AL;38\r\n"; -char ping[] = "$PI;2C\n"; - -int coprocessor_post_test(int flags) -{ - struct stdio_dev *cop_port; - int ret; - char buf[10]; - - /* Test IO Coprocessor communication */ - cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE); - if (!cop_port) - return -1; - - write_port(cop_port, ping); - udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY); - - memset(buf, 0, sizeof(buf)); - ret = read_port(cop_port, buf, sizeof(buf)); - close_port(4); - if (ret <= 0) { - post_log("Error: Can't read IO Coprocessor port.\n"); - return -1; - } - - if (strcmp(buf, alive)) { - post_log("Error: IO-Cop. resp.: %s\n", buf); - return -1; - } - - /* Test WD Coprocessor communication */ - cop_port = open_port(1, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE); - if (!cop_port) { - post_log("Error: Can't open WD Coprocessor port.\n"); - return -1; - } - - write_port(cop_port, ping); - udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY); - - memset(buf, 0, sizeof(buf)); - ret = read_port(cop_port, buf, sizeof(buf)); - close_port(1); - if (ret <= 0) { - post_log("Error: Can't read WD Coprocessor port.\n"); - return -1; - } - - if (strcmp(buf, alive)) { - post_log("Error: WD-Cop. resp.: %s\n", buf); - return -1; - } - - return 0; -} diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile deleted file mode 100644 index f8bb6c9..0000000 --- a/post/cpu/mpc8xx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_HAS_POST) += cache_8xx.o -obj-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o diff --git a/post/cpu/mpc8xx/cache.c b/post/cpu/mpc8xx/cache.c deleted file mode 100644 index af1281b..0000000 --- a/post/cpu/mpc8xx/cache.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* Cache test - * - * This test verifies the CPU data and instruction cache using - * several test scenarios. - */ - -#include -#include - -#if CONFIG_POST & CONFIG_SYS_POST_CACHE - -#define CACHE_POST_SIZE 1024 - -extern int cache_post_test1 (char *, unsigned int); -extern int cache_post_test2 (char *, unsigned int); -extern int cache_post_test3 (char *, unsigned int); -extern int cache_post_test4 (char *, unsigned int); -extern int cache_post_test5 (void); -extern int cache_post_test6 (void); - -int cache_post_test (int flags) -{ - int ints = disable_interrupts (); - int res = 0; - static char ta[CACHE_POST_SIZE + 0xf]; - char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf); - - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test1 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test2 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test3 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test4 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test5 (); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test6 (); - - WATCHDOG_RESET (); - if (ints) - enable_interrupts (); - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */ diff --git a/post/cpu/mpc8xx/cache_8xx.S b/post/cpu/mpc8xx/cache_8xx.S deleted file mode 100644 index 43649c8..0000000 --- a/post/cpu/mpc8xx/cache_8xx.S +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright (C) 2002 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#if defined(CONFIG_MPC823) || \ - defined(CONFIG_MPC850) || \ - defined(CONFIG_MPC855) || \ - defined(CONFIG_MPC860) || \ - defined(CONFIG_MPC862) - -#include -#include -#include -#include - -#if CONFIG_POST & CONFIG_SYS_POST_CACHE - - .text - -cache_post_dinvalidate: - lis r10, IDC_INVALL@h - mtspr DC_CST, r10 - blr - -cache_post_iinvalidate: - lis r10, IDC_INVALL@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ddisable: - lis r10, IDC_DISABLE@h - mtspr DC_CST, r10 - blr - -cache_post_dwb: - lis r10, IDC_ENABLE@h - mtspr DC_CST, r10 - lis r10, DC_CFWT@h - mtspr DC_CST, r10 - blr - -cache_post_dwt: - lis r10, IDC_ENABLE@h - mtspr DC_CST, r10 - lis r10, DC_SFWT@h - mtspr DC_CST, r10 - blr - -cache_post_idisable: - lis r10, IDC_DISABLE@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ienable: - lis r10, IDC_ENABLE@h - mtspr IC_CST, r10 - isync - blr - -cache_post_iunlock: - lis r10, IDC_UNALL@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ilock: - mtspr IC_ADR, r3 - lis r10, IDC_LDLCK@h - mtspr IC_CST, r10 - isync - blr - -/* - * turn on the data cache - * switch the data cache to write-back or write-through mode - * invalidate the data cache - * write the negative pattern to a cached area - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test1 -cache_post_test1: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - bl cache_post_ddisable - bl cache_post_dinvalidate - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-back or write-through mode - * invalidate the data cache - * write the zero pattern to a cached area - * turn off the data cache - * write the negative pattern to the area - * turn on the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test2 -cache_post_test2: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwb - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - bl cache_post_ddisable - bl cache_post_dinvalidate - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-through mode - * invalidate the data cache - * write the zero pattern to a cached area - * flush the data cache - * write the negative pattern to the area - * turn off the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test3 -cache_post_test3: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwt - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-back mode - * invalidate the data cache - * write the negative pattern to a cached area - * flush the data cache - * write the zero pattern to the area - * invalidate the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test4 -cache_post_test4: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -cache_post_test5_1: - li r3, 0 -cache_post_test5_2: - li r3, -1 - -/* - * turn on the instruction cache - * unlock the entire instruction cache - * invalidate the instruction cache - * lock a branch instruction in the instruction cache - * replace the branch instruction with "nop" - * jump to the branch instruction - * check that the branch instruction was executed -*/ - .global cache_post_test5 -cache_post_test5: - mflr r0 - stw r0, 4(r1) - - bl cache_post_ienable - bl cache_post_iunlock - bl cache_post_iinvalidate - - /* Compute r9 = cache_post_test5_reloc */ - bl cache_post_test5_reloc -cache_post_test5_reloc: - mflr r9 - - /* Copy the test instruction to cache_post_test5_data */ - lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Lock the branch instruction */ - lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l - add r3, r3, r9 - bl cache_post_ilock - - /* Replace the test instruction */ - lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Execute to the test instruction */ -cache_post_test5_data: - nop - - bl cache_post_iunlock - - lwz r0, 4(r1) - mtlr r0 - blr - -cache_post_test6_1: - li r3, -1 -cache_post_test6_2: - li r3, 0 - -/* - * turn on the instruction cache - * unlock the entire instruction cache - * invalidate the instruction cache - * lock a branch instruction in the instruction cache - * replace the branch instruction with "nop" - * jump to the branch instruction - * check that the branch instruction was executed - */ - .global cache_post_test6 -cache_post_test6: - mflr r0 - stw r0, 4(r1) - - bl cache_post_ienable - bl cache_post_iunlock - bl cache_post_iinvalidate - - /* Compute r9 = cache_post_test6_reloc */ - bl cache_post_test6_reloc -cache_post_test6_reloc: - mflr r9 - - /* Copy the test instruction to cache_post_test6_data */ - lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h - ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h - ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Replace the test instruction */ - lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h - ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h - ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Execute to the test instruction */ -cache_post_test6_data: - nop - - lwz r0, 4(r1) - mtlr r0 - blr - -#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */ -#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */ diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c deleted file mode 100644 index 47f6f32..0000000 --- a/post/cpu/mpc8xx/ether.c +++ /dev/null @@ -1,532 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* - * Ethernet test - * - * The Serial Communication Controllers (SCC) listed in ctlr_list array below - * are tested in the loopback ethernet mode. - * The controllers are configured accordingly and several packets - * are transmitted. The configurable test parameters are: - * MIN_PACKET_LENGTH - minimum size of packet to transmit - * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests - */ - -#include -#if CONFIG_POST & CONFIG_SYS_POST_ETHER -#if defined(CONFIG_8xx) -#include -#elif defined(CONFIG_MPC8260) -#include -#else -#error "Apparently a bad configuration, please fix." -#endif - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MIN_PACKET_LENGTH 64 -#define MAX_PACKET_LENGTH 256 -#define TEST_NUM 1 - -#define CTLR_SCC 0 - -extern void spi_init_f (void); -extern void spi_init_r (void); - -/* The list of controllers to test */ -#if defined(CONFIG_MPC823) -static int ctlr_list[][2] = { {CTLR_SCC, 1} }; -#else -static int ctlr_list[][2] = { }; -#endif - -static struct { - void (*init) (int index); - void (*halt) (int index); - int (*send) (int index, volatile void *packet, int length); - int (*recv) (int index, void *packet, int length); -} ctlr_proc[1]; - -static char *ctlr_name[1] = { "SCC" }; - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - - /* - * SCC callbacks - */ - -static void scc_init (int scc_index) -{ - uchar ea[6]; - - static int proff[] = { - PROFF_SCC1, - PROFF_SCC2, - PROFF_SCC3, - PROFF_SCC4, - }; - static unsigned int cpm_cr[] = { - CPM_CR_CH_SCC1, - CPM_CR_CH_SCC2, - CPM_CR_CH_SCC3, - CPM_CR_CH_SCC4, - }; - - int i; - scc_enet_t *pram_ptr; - - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]); - - rxIdx = 0; - txIdx = 0; - - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); - -#if 0 - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdir |= PC_ENET_LBK; - immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; -#else - /* - * SCC2 receive clock is BRG2 - * SCC2 transmit clock is BRG3 - */ - immr->im_cpm.cp_brgc2 = 0x0001000C; - immr->im_cpm.cp_brgc3 = 0x0001000C; - - immr->im_cpm.cp_sicr &= ~0x00003F00; - immr->im_cpm.cp_sicr |= 0x00000a00; -#endif /* 0 */ - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = - (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) | - CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) - */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - - eth_getenv_enetaddr("ethaddr", ea); - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* - * Enter Command: Initialize Tx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) | - CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Mask all Events in SCCM - we use polling mode - */ - immr->im_cpm.cp_scc[scc_index].scc_sccm = 0; - - /* - * Clear Events in SCCE -- Clear bits by writing 1's - */ - - immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0); - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * LOOP = Loopback - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_DIAG_LOOP | - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * LPB = Loopback Enable (Needed when FDE is set) - */ - immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | SCC_PSMR_LPB; - - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} - -static void scc_halt (int scc_index) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); -} - -static int scc_send (int index, volatile void *packet, int length) -{ - int i, j = 0; - - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j >= TOUT_LOOP) - printf ("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= - (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j >= TOUT_LOOP) - printf ("TX timeout\n"); - i = (rtx->txbd[txIdx]. - cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ; - return i; -} - -static int scc_recv (int index, void *packet, int max_length) -{ - int length = -1; - - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - goto Done; /* nothing received */ - } - - if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) { - length = rtx->rxbd[rxIdx].cbd_datlen - 4; - memcpy (packet, - (void *)(net_rx_packets[rxIdx]), - length < max_length ? length : max_length); - } - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - -Done: - return length; -} - - /* - * Test routines - */ - -static void packet_fill (char *packet, int length) -{ - char c = (char) length; - int i; - - packet[0] = 0xFF; - packet[1] = 0xFF; - packet[2] = 0xFF; - packet[3] = 0xFF; - packet[4] = 0xFF; - packet[5] = 0xFF; - - for (i = 6; i < length; i++) { - packet[i] = c++; - } -} - -static int packet_check (char *packet, int length) -{ - char c = (char) length; - int i; - - for (i = 6; i < length; i++) { - if (packet[i] != c++) - return -1; - } - - return 0; -} - -static int test_ctlr (int ctlr, int index) -{ - int res = -1; - char packet_send[MAX_PACKET_LENGTH]; - char packet_recv[MAX_PACKET_LENGTH]; - int length; - int i; - int l; - - ctlr_proc[ctlr].init (index); - - for (i = 0; i < TEST_NUM; i++) { - for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { - packet_fill (packet_send, l); - - ctlr_proc[ctlr].send (index, packet_send, l); - - length = ctlr_proc[ctlr].recv (index, packet_recv, - MAX_PACKET_LENGTH); - - if (length != l || packet_check (packet_recv, length) < 0) { - goto Done; - } - } - } - - res = 0; - -Done: - - ctlr_proc[ctlr].halt (index); - - /* - * SCC2 Ethernet parameter RAM space overlaps - * the SPI parameter RAM space. So we need to restore - * the SPI configuration after SCC2 ethernet test. - */ -#if defined(CONFIG_SPI) - if (ctlr == CTLR_SCC && index == 1) { - spi_init_f (); - spi_init_r (); - } -#endif - - if (res != 0) { - post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr], - index + 1); - } - - return res; -} - -int ether_post_test (int flags) -{ - int res = 0; - int i; - - ctlr_proc[CTLR_SCC].init = scc_init; - ctlr_proc[CTLR_SCC].halt = scc_halt; - ctlr_proc[CTLR_SCC].send = scc_send; - ctlr_proc[CTLR_SCC].recv = scc_recv; - - for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) { - if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { - res = -1; - } - } - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */ diff --git a/post/cpu/mpc8xx/spr.c b/post/cpu/mpc8xx/spr.c deleted file mode 100644 index d20da8d..0000000 --- a/post/cpu/mpc8xx/spr.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* - * SPR test - * - * The test checks the contents of Special Purpose Registers (SPR) listed - * in the spr_test_list array below. - * Each SPR value is read using mfspr instruction, some bits are masked - * according to the table and the resulting value is compared to the - * corresponding table value. - */ - -#include - -#if CONFIG_POST & CONFIG_SYS_POST_SPR - -static struct -{ - int number; - char * name; - unsigned long mask; - unsigned long value; -} spr_test_list [] = { - /* Standard Special-Purpose Registers */ - - {1, "XER", 0x00000000, 0x00000000}, - {8, "LR", 0x00000000, 0x00000000}, - {9, "CTR", 0x00000000, 0x00000000}, - {18, "DSISR", 0x00000000, 0x00000000}, - {19, "DAR", 0x00000000, 0x00000000}, - {22, "DEC", 0x00000000, 0x00000000}, - {26, "SRR0", 0x00000000, 0x00000000}, - {27, "SRR1", 0x00000000, 0x00000000}, - {272, "SPRG0", 0x00000000, 0x00000000}, - {273, "SPRG1", 0x00000000, 0x00000000}, - {274, "SPRG2", 0x00000000, 0x00000000}, - {275, "SPRG3", 0x00000000, 0x00000000}, - {287, "PVR", 0xFFFF0000, 0x00500000}, - - /* Additional Special-Purpose Registers */ - - {144, "CMPA", 0x00000000, 0x00000000}, - {145, "CMPB", 0x00000000, 0x00000000}, - {146, "CMPC", 0x00000000, 0x00000000}, - {147, "CMPD", 0x00000000, 0x00000000}, - {148, "ICR", 0xFFFFFFFF, 0x00000000}, - {149, "DER", 0x00000000, 0x00000000}, - {150, "COUNTA", 0xFFFFFFFF, 0x00000000}, - {151, "COUNTB", 0xFFFFFFFF, 0x00000000}, - {152, "CMPE", 0x00000000, 0x00000000}, - {153, "CMPF", 0x00000000, 0x00000000}, - {154, "CMPG", 0x00000000, 0x00000000}, - {155, "CMPH", 0x00000000, 0x00000000}, - {156, "LCTRL1", 0xFFFFFFFF, 0x00000000}, - {157, "LCTRL2", 0xFFFFFFFF, 0x00000000}, - {158, "ICTRL", 0xFFFFFFFF, 0x00000007}, - {159, "BAR", 0x00000000, 0x00000000}, - {630, "DPDR", 0x00000000, 0x00000000}, - {631, "DPIR", 0x00000000, 0x00000000}, - {638, "IMMR", 0xFFFF0000, CONFIG_SYS_IMMR }, - {560, "IC_CST", 0x8E380000, 0x00000000}, - {561, "IC_ADR", 0x00000000, 0x00000000}, - {562, "IC_DAT", 0x00000000, 0x00000000}, - {568, "DC_CST", 0xEF380000, 0x00000000}, - {569, "DC_ADR", 0x00000000, 0x00000000}, - {570, "DC_DAT", 0x00000000, 0x00000000}, - {784, "MI_CTR", 0xFFFFFFFF, 0x00000000}, - {786, "MI_AP", 0x00000000, 0x00000000}, - {787, "MI_EPN", 0x00000000, 0x00000000}, - {789, "MI_TWC", 0xFFFFFE02, 0x00000000}, - {790, "MI_RPN", 0x00000000, 0x00000000}, - {816, "MI_DBCAM", 0x00000000, 0x00000000}, - {817, "MI_DBRAM0", 0x00000000, 0x00000000}, - {818, "MI_DBRAM1", 0x00000000, 0x00000000}, - {792, "MD_CTR", 0xFFFFFFFF, 0x04000000}, - {793, "M_CASID", 0xFFFFFFF0, 0x00000000}, - {794, "MD_AP", 0x00000000, 0x00000000}, - {795, "MD_EPN", 0x00000000, 0x00000000}, - {796, "M_TWB", 0x00000003, 0x00000000}, - {797, "MD_TWC", 0x00000003, 0x00000000}, - {798, "MD_RPN", 0x00000000, 0x00000000}, - {799, "M_TW", 0x00000000, 0x00000000}, - {824, "MD_DBCAM", 0x00000000, 0x00000000}, - {825, "MD_DBRAM0", 0x00000000, 0x00000000}, - {826, "MD_DBRAM1", 0x00000000, 0x00000000}, -}; - -static int spr_test_list_size = ARRAY_SIZE(spr_test_list); - -int spr_post_test (int flags) -{ - int ret = 0; - int ic = icache_status (); - int i; - - unsigned long code[] = { - 0x7c6002a6, /* mfspr r3,SPR */ - 0x4e800020 /* blr */ - }; - unsigned long (*get_spr) (void) = (void *) code; - - if (ic) - icache_disable (); - - for (i = 0; i < spr_test_list_size; i++) { - int num = spr_test_list[i].number; - - /* mfspr r3,num */ - code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); - - if ((get_spr () & spr_test_list[i].mask) != - (spr_test_list[i].value & spr_test_list[i].mask)) { - post_log ("The value of %s special register " - "is incorrect: 0x%08X\n", - spr_test_list[i].name, get_spr ()); - ret = -1; - } - } - - if (ic) - icache_enable (); - - return ret; -} -#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */ diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c deleted file mode 100644 index 64ca7e4..0000000 --- a/post/cpu/mpc8xx/uart.c +++ /dev/null @@ -1,510 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* - * UART test - * - * The Serial Management Controllers (SMC) and the Serial Communication - * Controllers (SCC) listed in ctlr_list array below are tested in - * the loopback UART mode. - * The controllers are configured accordingly and several characters - * are transmitted. The configurable test parameters are: - * MIN_PACKET_LENGTH - minimum size of packet to transmit - * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests - */ - -#include -#if CONFIG_POST & CONFIG_SYS_POST_UART -#if defined(CONFIG_8xx) -#include -#elif defined(CONFIG_MPC8260) -#include -#else -#error "Apparently a bad configuration, please fix." -#endif -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define CTLR_SMC 0 -#define CTLR_SCC 1 - -/* The list of controllers to test */ -#if defined(CONFIG_MPC823) -static int ctlr_list[][2] = - { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} }; -#else -static int ctlr_list[][2] = { }; -#endif - -static struct { - void (*init) (int index); - void (*halt) (int index); - void (*putc) (int index, const char c); - int (*getc) (int index); -} ctlr_proc[2]; - -static char *ctlr_name[2] = { "SMC", "SCC" }; - -static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 }; -static int proff_scc[] = - { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 }; - -/* - * SMC callbacks - */ - -static void smc_init (int smc_index) -{ - static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 }; - - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) & (cp->cp_smc[smc_index]); - up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - dpaddr = CPM_POST_BASE; - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf + 2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr + sizeof (cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - * Set local loopback mode. - */ - sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - cp->cp_simode = 0x00000000; - - cp->cp_brgc1 = - (((gd->cpu_clk / 16 / gd->baudrate) - - 1) << 1) | CPM_BRG_EN; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = - mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; -} - -static void smc_halt(int smc_index) -{ -} - -static void smc_putc (int smc_index, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; - - tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *) tbdf->cbd_bufaddr; -#if 0 - __asm__ ("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__ ("eieio"); -#if 1 - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif -} - -static int smc_getc (int smc_index) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - int i; - - up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; - - rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *) rbdf->cbd_bufaddr; -#if 0 - while (rbdf->cbd_sc & BD_SC_EMPTY); -#else - for (i = 100; i > 0; i--) { - if (!(rbdf->cbd_sc & BD_SC_EMPTY)) - break; - udelay (1000); - } - - if (i == 0) - return -1; -#endif - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - - /* - * SCC callbacks - */ - -static void scc_init (int scc_index) -{ - static int cpm_cr_ch[] = { - CPM_CR_CH_SCC1, - CPM_CR_CH_SCC2, - CPM_CR_CH_SCC3, - CPM_CR_CH_SCC4, - }; - - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (scc_t *) & (cp->cp_scc[scc_index]); - up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - dpaddr = CPM_POST_BASE; - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 0x0001; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - - rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf + 2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the baud rate generator. - */ - cp->cp_sicr &= ~(0x000000FF << (8 * scc_index)); - /* no |= needed, since BRG1 is 000 */ - - cp->cp_brgc1 = - (((gd->cpu_clk / 16 / gd->baudrate) - - 1) << 1) | CPM_BRG_EN; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t); - - /* Initialize Tx/Rx parameters. - */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - cp->cp_cpcr = - mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - up->scc_genscc.scc_rfcr = SCC_EB | 0x05; - up->scc_genscc.scc_tfcr = SCC_EB | 0x05; - - up->scc_genscc.scc_mrblr = 1; /* Single character receive */ - up->scc_maxidl = 0; /* disable max idle */ - up->scc_brkcr = 1; /* send one break character on stop TX */ - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = 0x8000; - up->scc_char2 = 0x8000; - up->scc_char3 = 0x8000; - up->scc_char4 = 0x8000; - up->scc_char5 = 0x8000; - up->scc_char6 = 0x8000; - up->scc_char7 = 0x8000; - up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Set low latency / small fifo. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; - - /* Set UART mode - */ - sp->scc_gsmrl &= ~0xF; - sp->scc_gsmrl |= SCC_GSMRL_MODE_UART; - - /* Set local loopback mode. - */ - sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE; - sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP; - - /* Set clock divider 16 on Tx and Rx - */ - sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - sp->scc_psmr |= SCU_PSMR_CL; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - sp->scc_dsr = 0x7e7e; - sp->scc_psmr = 0x3000; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} - -static void scc_halt(int scc_index) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]); - - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE); -} - -static void scc_putc (int scc_index, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; - - tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *) tbdf->cbd_bufaddr; -#if 0 - __asm__ ("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__ ("eieio"); -#if 1 - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif -} - -static int scc_getc (int scc_index) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - int i; - - up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; - - rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *) rbdf->cbd_bufaddr; -#if 0 - while (rbdf->cbd_sc & BD_SC_EMPTY); -#else - for (i = 100; i > 0; i--) { - if (!(rbdf->cbd_sc & BD_SC_EMPTY)) - break; - udelay (1000); - } - - if (i == 0) - return -1; -#endif - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - - /* - * Test routines - */ - -static int test_ctlr (int ctlr, int index) -{ - int res = -1; - char test_str[] = "*** UART Test String ***\r\n"; - int i; - - ctlr_proc[ctlr].init (index); - - for (i = 0; i < sizeof (test_str) - 1; i++) { - ctlr_proc[ctlr].putc (index, test_str[i]); - if (ctlr_proc[ctlr].getc (index) != test_str[i]) - goto Done; - } - - res = 0; - -Done: - ctlr_proc[ctlr].halt (index); - - if (res != 0) { - post_log ("uart %s%d test failed\n", - ctlr_name[ctlr], index + 1); - } - - return res; -} - -int uart_post_test (int flags) -{ - int res = 0; - int i; - - ctlr_proc[CTLR_SMC].init = smc_init; - ctlr_proc[CTLR_SMC].halt = smc_halt; - ctlr_proc[CTLR_SMC].putc = smc_putc; - ctlr_proc[CTLR_SMC].getc = smc_getc; - - ctlr_proc[CTLR_SCC].init = scc_init; - ctlr_proc[CTLR_SCC].halt = scc_halt; - ctlr_proc[CTLR_SCC].putc = scc_putc; - ctlr_proc[CTLR_SCC].getc = scc_getc; - - for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) { - if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { - res = -1; - } - } - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */ diff --git a/post/cpu/mpc8xx/usb.c b/post/cpu/mpc8xx/usb.c deleted file mode 100644 index 6334088..0000000 --- a/post/cpu/mpc8xx/usb.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* - * USB test - * - * The USB controller is tested in the local loopback mode. - * It is configured so that endpoint 0 operates as host and endpoint 1 - * operates as function endpoint. After that an IN token transaction - * is performed. - * Refer to MPC850 User Manual, Section 32.11.1 USB Host Controller - * Initialization Example. - */ - -#include - -#if CONFIG_POST & CONFIG_SYS_POST_USB - -#include -#include - -#define TOUT_LOOP 100 - -#define PROFF_USB ((uint)0x0000) - -#define CPM_USB_EP0_BASE 0x0a00 -#define CPM_USB_EP1_BASE 0x0a20 - -#define CPM_USB_DT0_BASE 0x0a80 -#define CPM_USB_DT1_BASE 0x0a90 -#define CPM_USB_DR0_BASE 0x0aa0 -#define CPM_USB_DR1_BASE 0x0ab0 - -#define CPM_USB_RX0_BASE 0x0b00 -#define CPM_USB_RX1_BASE 0x0b08 -#define CPM_USB_TX0_BASE 0x0b20 -#define CPM_USB_TX1_BASE 0x0b28 - -#define USB_EXPECT(x) if (!(x)) goto Done; - -typedef struct usb_param { - ushort ep0ptr; - ushort ep1ptr; - ushort ep2ptr; - ushort ep3ptr; - uint rstate; - uint rptr; - ushort frame_n; - ushort rbcnt; - ushort rtemp; -} usb_param_t; - -typedef struct usb_param_block { - ushort rbase; - ushort tbase; - uchar rfcr; - uchar tfcr; - ushort mrblr; - ushort rbptr; - ushort tbptr; - uint tstate; - uint tptr; - ushort tcrc; - ushort tbcnt; - uint res[2]; -} usb_param_block_t; - -typedef struct usb { - uchar usmod; - uchar usadr; - uchar uscom; - uchar res1; - ushort usep[4]; - uchar res2[4]; - ushort usber; - uchar res3[2]; - ushort usbmr; - uchar res4; - uchar usbs; - uchar res5[8]; -} usb_t; - -int usb_post_test (int flags) -{ - int res = -1; - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile usb_param_t *pram_ptr; - uint dpram; - ushort DPRAM; - volatile cbd_t *tx; - volatile cbd_t *rx; - volatile usb_t *usbr; - volatile usb_param_block_t *ep0; - volatile usb_param_block_t *ep1; - int j; - - pram_ptr = (usb_param_t *) & (im->im_cpm.cp_dparam[PROFF_USB]); - dpram = (uint) im->im_cpm.cp_dpmem; - DPRAM = dpram; - tx = (cbd_t *) (dpram + CPM_USB_TX0_BASE); - rx = (cbd_t *) (dpram + CPM_USB_RX0_BASE); - ep0 = (usb_param_block_t *) (dpram + CPM_USB_EP0_BASE); - ep1 = (usb_param_block_t *) (dpram + CPM_USB_EP1_BASE); - usbr = (usb_t *) & (im->im_cpm.cp_scc[0]); - - /* 01 */ - im->im_ioport.iop_padir &= ~(ushort) 0x0200; - im->im_ioport.iop_papar |= (ushort) 0x0200; - - cp->cp_sicr &= ~0x000000FF; - cp->cp_sicr |= 0x00000018; - - cp->cp_brgc4 = 0x00010001; - - /* 02 */ - im->im_ioport.iop_padir &= ~(ushort) 0x0002; - im->im_ioport.iop_padir &= ~(ushort) 0x0001; - - im->im_ioport.iop_papar |= (ushort) 0x0002; - im->im_ioport.iop_papar |= (ushort) 0x0001; - - /* 03 */ - im->im_ioport.iop_pcdir &= ~(ushort) 0x0020; - im->im_ioport.iop_pcdir &= ~(ushort) 0x0010; - - im->im_ioport.iop_pcpar &= ~(ushort) 0x0020; - im->im_ioport.iop_pcpar &= ~(ushort) 0x0010; - - im->im_ioport.iop_pcso |= (ushort) 0x0020; - im->im_ioport.iop_pcso |= (ushort) 0x0010; - - /* 04 */ - im->im_ioport.iop_pcdir |= (ushort) 0x0200; - im->im_ioport.iop_pcdir |= (ushort) 0x0100; - - im->im_ioport.iop_pcpar |= (ushort) 0x0200; - im->im_ioport.iop_pcpar |= (ushort) 0x0100; - - /* 05 */ - pram_ptr->frame_n = 0; - - /* 06 */ - pram_ptr->ep0ptr = DPRAM + CPM_USB_EP0_BASE; - pram_ptr->ep1ptr = DPRAM + CPM_USB_EP1_BASE; - - /* 07-10 */ - tx[0].cbd_sc = 0xB800; - tx[0].cbd_datlen = 3; - tx[0].cbd_bufaddr = dpram + CPM_USB_DT0_BASE; - - tx[1].cbd_sc = 0xBC80; - tx[1].cbd_datlen = 3; - tx[1].cbd_bufaddr = dpram + CPM_USB_DT1_BASE; - - rx[0].cbd_sc = 0xA000; - rx[0].cbd_datlen = 0; - rx[0].cbd_bufaddr = dpram + CPM_USB_DR0_BASE; - - rx[1].cbd_sc = 0xA000; - rx[1].cbd_datlen = 0; - rx[1].cbd_bufaddr = dpram + CPM_USB_DR1_BASE; - - /* 11-12 */ - *(volatile int *) (dpram + CPM_USB_DT0_BASE) = 0x69856000; - *(volatile int *) (dpram + CPM_USB_DT1_BASE) = 0xABCD1234; - - *(volatile int *) (dpram + CPM_USB_DR0_BASE) = 0; - *(volatile int *) (dpram + CPM_USB_DR1_BASE) = 0; - - /* 13-16 */ - ep0->rbase = DPRAM + CPM_USB_RX0_BASE; - ep0->tbase = DPRAM + CPM_USB_TX0_BASE; - ep0->rfcr = 0x18; - ep0->tfcr = 0x18; - ep0->mrblr = 0x100; - ep0->rbptr = DPRAM + CPM_USB_RX0_BASE; - ep0->tbptr = DPRAM + CPM_USB_TX0_BASE; - ep0->tstate = 0; - - /* 17-20 */ - ep1->rbase = DPRAM + CPM_USB_RX1_BASE; - ep1->tbase = DPRAM + CPM_USB_TX1_BASE; - ep1->rfcr = 0x18; - ep1->tfcr = 0x18; - ep1->mrblr = 0x100; - ep1->rbptr = DPRAM + CPM_USB_RX1_BASE; - ep1->tbptr = DPRAM + CPM_USB_TX1_BASE; - ep1->tstate = 0; - - /* 21-24 */ - usbr->usep[0] = 0x0000; - usbr->usep[1] = 0x1100; - usbr->usep[2] = 0x2200; - usbr->usep[3] = 0x3300; - - /* 25 */ - usbr->usmod = 0x06; - - /* 26 */ - usbr->usadr = 0x05; - - /* 27 */ - usbr->uscom = 0; - - /* 28 */ - usbr->usmod |= 0x01; - udelay (1); - - /* 29-30 */ - usbr->uscom = 0x80; - usbr->uscom = 0x81; - - /* Wait for the data packet to be transmitted */ - for (j = 0; j < TOUT_LOOP; j++) { - if (tx[1].cbd_sc & (ushort) 0x8000) - udelay (1); - else - break; - } - - USB_EXPECT (j < TOUT_LOOP); - - USB_EXPECT (tx[0].cbd_sc == 0x3800); - USB_EXPECT (tx[0].cbd_datlen == 3); - - USB_EXPECT (tx[1].cbd_sc == 0x3C80); - USB_EXPECT (tx[1].cbd_datlen == 3); - - USB_EXPECT (rx[0].cbd_sc == 0x2C00); - USB_EXPECT (rx[0].cbd_datlen == 5); - - USB_EXPECT (*(volatile int *) (dpram + CPM_USB_DR0_BASE) == - 0xABCD122B); - USB_EXPECT (*(volatile char *) (dpram + CPM_USB_DR0_BASE + 4) == 0x42); - - res = 0; - Done: - - return res; -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_USB */ diff --git a/post/cpu/mpc8xx/watchdog.c b/post/cpu/mpc8xx/watchdog.c deleted file mode 100644 index a070539..0000000 --- a/post/cpu/mpc8xx/watchdog.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* - * Watchdog test - * - * The test verifies the watchdog timer operation. - * On the first iteration, the test routine disables interrupts and - * makes a 10-second delay. If the system does not reboot during this delay, - * the watchdog timer is not operational and the test fails. If the system - * reboots, on the second iteration the test routine reports a success. - */ - -#include -#include - -#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG - -static ulong gettbl (void) -{ - ulong r; - - asm ("mftbl %0":"=r" (r)); - - return r; -} - -int watchdog_post_test (int flags) -{ - if (flags & POST_REBOOT) { - /* Test passed */ - - return 0; - } else { - /* 10-second delay */ - int ints = disable_interrupts (); - ulong base = gettbl (); - ulong clk = get_tbclk (); - - while ((gettbl () - base) / 10 < clk); - - if (ints) - enable_interrupts (); - - /* - * If we have reached this point, the watchdog timer - * does not work - */ - return -1; - } -} - -#endif /* CONFIG_POST & CONFIG_SYS_POST_WATCHDOG */ diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 89725fa..b410502 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -170,14 +170,7 @@ DECLARE_GLOBAL_DATA_PTR; */ static void move64(const unsigned long long *src, unsigned long long *dest) { -#if defined(CONFIG_MPC8260) - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -#else *dest = *src; -#endif } /* diff --git a/post/tests.c b/post/tests.c index d8ac54e..bc8e398 100644 --- a/post/tests.c +++ b/post/tests.c @@ -180,18 +180,6 @@ struct post_test post_list[] = CONFIG_SYS_POST_ETHER }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_SPI - { - "SPI test", - "spi", - "This test verifies the SPI operation.", - POST_RAM | POST_ALWAYS, - &spi_post_test, - NULL, - NULL, - CONFIG_SYS_POST_SPI - }, -#endif #if CONFIG_POST & CONFIG_SYS_POST_USB { "USB test", diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 774aa89..80ddb08 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -164,14 +164,12 @@ cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ ld_flags = $(LDFLAGS) $(ldflags-y) -dts_dir = $(srctree)/arch/$(ARCH)/dts - # Try these files in order to find the U-Boot-specific .dtsi include file -u_boot_dtsi_options = $(wildcard $(dts_dir)/$(basename $(notdir $<))-u-boot.dtsi) \ - $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi) \ - $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi) \ - $(wildcard $(dts_dir)/$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi) \ - $(wildcard $(dts_dir)/u-boot.dtsi) +u_boot_dtsi_options = $(wildcard $(dir $<)$(basename $(notdir $<))-u-boot.dtsi) \ + $(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi) \ + $(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi) \ + $(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi) \ + $(wildcard $(dir $<)u-boot.dtsi) # Uncomment for debugging # $(warning u_boot_dtsi_options: $(u_boot_dtsi_options)) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 135706f..ac3c2c7 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -257,14 +257,12 @@ PHONY += dts_dir dts_dir: $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) -include/generated/dt-structs.h: $(obj)/$(SPL_BIN).dtb dts_dir dtoc +include/generated/dt-structs.h: $(obj)/$(SPL_BIN).dtb dts_dir checkdtoc $(call if_changed,dtoch) -$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir dtoc +$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir checkdtoc $(call if_changed,dtocc) -dtoc: #$(objtree)/tools/_libfdt.so - ifdef CONFIG_SAMSUNG ifdef CONFIG_VAR_SIZE_SPL VAR_SIZE_PARAM = --vs @@ -357,6 +355,17 @@ ifneq ($(cmd_files),) include $(cmd_files) endif +checkdtoc: tools + @if ! ( echo 'import libfdt' | ( PYTHONPATH=tools python )); then \ + echo '*** dtoc needs the Python libfdt library. Either '; \ + echo '*** install it on your system, or try:'; \ + echo '***'; \ + echo '*** sudo apt-get install swig libpython-dev'; \ + echo '***'; \ + echo '*** to have U-Boot build its own version.'; \ + false; \ + fi + PHONY += FORCE FORCE: diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e953168..feb430f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -28,14 +28,9 @@ CONFIG_4xx_CONFIG_BLOCKSIZE CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET CONFIG_4xx_DCACHE -CONFIG_521X CONFIG_533MHZ_MODE -CONFIG_5xx_CONS_SCI1 -CONFIG_5xx_CONS_SCI2 -CONFIG_5xx_GCLK_FREQ CONFIG_64BIT_PHYS_ADDR CONFIG_66 -CONFIG_8260_CLKIN CONFIG_8349_CLKIN CONFIG_83XX CONFIG_83XX_CLKIN @@ -43,20 +38,8 @@ CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES CONFIG_83XX_PCICLK CONFIG_83XX_PCI_STREAMING CONFIG_88F5182 -CONFIG_8xx_CONS_NONE -CONFIG_8xx_CONS_SCCx -CONFIG_8xx_CONS_SMC1 -CONFIG_8xx_CONS_SMC2 -CONFIG_8xx_CONS_SMCx -CONFIG_8xx_CPUCLK_DEFAULT -CONFIG_8xx_GCLK_FREQ -CONFIG_8xx_OSCLK CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND -CONFIG_A3M071 -CONFIG_A4M072 -CONFIG_A4M2K -CONFIG_AC14XX CONFIG_ACADIA CONFIG_ACX517AKN CONFIG_ACX544AKN @@ -120,8 +103,6 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP CONFIG_ARC_MMU_VER CONFIG_ARC_SERIAL CONFIG_ARC_UART_BASE -CONFIG_ARIA -CONFIG_ARIA_FPGA CONFIG_ARIES_M28_V10 CONFIG_ARM926EJS CONFIG_ARMADA100 @@ -230,7 +211,6 @@ CONFIG_BCM_SF2_ETH_GMAC CONFIG_BD_NUM_CPUS CONFIG_BIOSEMU CONFIG_BITBANGMII_MULTI -CONFIG_BKUP_FLASH CONFIG_BL1_OFFSET CONFIG_BL1_SIZE CONFIG_BL2_OFFSET @@ -243,7 +223,6 @@ CONFIG_BOARDINFO CONFIG_BOARDNAME CONFIG_BOARDNAME_LOCAL CONFIG_BOARD_AXM -CONFIG_BOARD_BOOTCMD CONFIG_BOARD_COMMON CONFIG_BOARD_EARLY_INIT_R CONFIG_BOARD_ECC_SUPPORT @@ -252,7 +231,6 @@ CONFIG_BOARD_H2200 CONFIG_BOARD_IS_OPENRD_BASE CONFIG_BOARD_IS_OPENRD_CLIENT CONFIG_BOARD_IS_OPENRD_ULTIMATE -CONFIG_BOARD_MEM_LIMIT CONFIG_BOARD_NAME CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_RESET @@ -337,10 +315,6 @@ CONFIG_BUS_WIDTH CONFIG_BZIP2 CONFIG_CADDY2 CONFIG_CALXEDA_XGMAC -CONFIG_CAM5200 -CONFIG_CAM5200_NIOSFLASH -CONFIG_CANMB -CONFIG_CAN_DRIVER CONFIG_CDP_APPLIANCE_VLAN_TYPE CONFIG_CDP_CAPABILITIES CONFIG_CDP_DEVICE_ID @@ -351,7 +325,6 @@ CONFIG_CDP_POWER_CONSUMPTION CONFIG_CDP_TRIGGER CONFIG_CDP_VERSION CONFIG_CFG_DATA_SECTOR -CONFIG_CFG_FAT CONFIG_CFG_USB CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS CONFIG_CF_DSPI @@ -362,7 +335,6 @@ CONFIG_CF_V3 CONFIG_CF_V4 CONFIG_CF_V4E CONFIG_CHAIN_BOOT_CMD -CONFIG_CHARON CONFIG_CHIP_SELECTS_PER_CTRL CONFIG_CHIP_SELECT_QUAD_CAPABLE CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS @@ -378,7 +350,6 @@ CONFIG_CLK_DEBUG CONFIG_CLOCKS CONFIG_CLOCKS_IN_MHZ CONFIG_CLOCK_SYNTHESIZER -CONFIG_CM5200 CONFIG_CM922T_XA10 CONFIG_CMDLINE_EDITING CONFIG_CMDLINE_PS_SUPPORT @@ -443,7 +414,6 @@ CONFIG_CONS_EXTC_PINSEL CONFIG_CONS_EXTC_RATE CONFIG_CONS_NONE CONFIG_CONS_ON_SCC -CONFIG_CONS_ON_SMC CONFIG_CONS_SCIF0 CONFIG_CONS_SCIF1 CONFIG_CONS_SCIF2 @@ -547,13 +517,9 @@ CONFIG_DDR_ECC_ENABLE CONFIG_DDR_ECC_INIT_VIA_DMA CONFIG_DDR_FIXED_SIZE CONFIG_DDR_HCLK -CONFIG_DDR_HYB25D512160BF CONFIG_DDR_II -CONFIG_DDR_K4H511638C CONFIG_DDR_LOG_LEVEL CONFIG_DDR_MB -CONFIG_DDR_MT46V16M16 -CONFIG_DDR_MT46V32M16 CONFIG_DDR_MT47H128M8 CONFIG_DDR_MT47H32M16 CONFIG_DDR_MT47H64M16 @@ -592,8 +558,6 @@ CONFIG_DFU_ENV_SETTINGS CONFIG_DFU_MTD CONFIG_DHCP_MIN_EXT_LEN CONFIG_DIALOG_POWER -CONFIG_DIGSY_MTC -CONFIG_DIGSY_REV5 CONFIG_DIMM_SLOTS_PER_CTLR CONFIG_DIRECT_NOR_BOOT CONFIG_DISABLE_CONSOLE @@ -803,15 +767,11 @@ CONFIG_ETH2ADDR CONFIG_ETHADDR CONFIG_ETHBASE CONFIG_ETHER_INDEX -CONFIG_ETHER_LOOPBACK_TEST CONFIG_ETHER_NONE CONFIG_ETHER_ON_FCC CONFIG_ETHER_ON_FCC1 CONFIG_ETHER_ON_FCC2 CONFIG_ETHER_ON_FCC3 -CONFIG_ETHER_ON_FEC1 -CONFIG_ETHER_ON_FEC2 -CONFIG_ETHER_ON_SCC CONFIG_ETHPRIME CONFIG_ETH_BUFSIZE CONFIG_ETH_RXSIZE @@ -824,7 +784,6 @@ CONFIG_EXTRA_ENV_ITB CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS_COMMON -CONFIG_EXTRA_ENV_SETTINGS_DEVEL CONFIG_EXTRA_ENV_UNLOCK CONFIG_EXTRA_ENV_USBTTY CONFIG_EXT_AHB2AHB_BASE @@ -870,10 +829,6 @@ CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN CONFIG_FEATURE_SH_EXTRA_QUIET CONFIG_FEATURE_SH_FANCY_PROMPT CONFIG_FEATURE_SH_STANDALONE_SHELL -CONFIG_FEC1_PHY -CONFIG_FEC2_PHY -CONFIG_FEC_10MBIT -CONFIG_FEC_AN_TIMEOUT CONFIG_FEC_ENET CONFIG_FEC_ENET_DEV CONFIG_FEC_FIXED_SPEED @@ -908,7 +863,6 @@ CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FMAN_ENET CONFIG_FM_PLAT_CLK_DIV -CONFIG_FO300 CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 CONFIG_FORMIKE CONFIG_FPGA_COUNT @@ -948,10 +902,6 @@ CONFIG_FSL_LBC CONFIG_FSL_LINFLEXUART CONFIG_FSL_MC9SDZ60 CONFIG_FSL_MEMAC -CONFIG_FSL_NFC_CHIPS -CONFIG_FSL_NFC_SPARE_SIZE -CONFIG_FSL_NFC_WIDTH -CONFIG_FSL_NFC_WRITE_SIZE CONFIG_FSL_NGPIXIS CONFIG_FSL_PCIE_DISABLE_ASPM CONFIG_FSL_PCIE_RESET @@ -1036,7 +986,6 @@ CONFIG_FTUART010_03_BASE CONFIG_FTWDT010_BASE CONFIG_FTWDT010_WATCHDOG CONFIG_FUNC_ISRAM_ADDR -CONFIG_FWUPDATE_DEBUG CONFIG_FZOTG266HD0A_BASE CONFIG_GATEWAYIP CONFIG_GCOV_KERNEL @@ -1084,7 +1033,6 @@ CONFIG_HAS_FSL_MPH_USB CONFIG_HAS_FSL_XHCI_USB CONFIG_HAS_POST CONFIG_HAVE_ACPI_RESUME -CONFIG_HAVE_OWN_RESET CONFIG_HCLK_FREQ CONFIG_HDBOOT CONFIG_HDMI_ENCODER_I2C_ADDR @@ -1278,8 +1226,6 @@ CONFIG_IBM_EMAC4_V4 CONFIG_ICACHE CONFIG_ICON CONFIG_ICS307_REFCLK_HZ -CONFIG_IDE_8xx_DIRECT -CONFIG_IDE_8xx_PCCARD CONFIG_IDE_INIT_POSTRESET CONFIG_IDE_LED CONFIG_IDE_PCMCIA @@ -1292,10 +1238,6 @@ CONFIG_IDE_SWAP_IO CONFIG_IDS8313 CONFIG_IDT8T49N222A CONFIG_ID_EEPROM -CONFIG_IFM_DEFAULT_ENV_NEW -CONFIG_IFM_DEFAULT_ENV_OLD -CONFIG_IFM_DEFAULT_ENV_SETTINGS -CONFIG_IFM_SENSOR_TYPE CONFIG_IMA CONFIG_IMAGE_FORMAT_LEGACY CONFIG_IMX @@ -1315,7 +1257,6 @@ CONFIG_INI_CASE_INSENSITIVE CONFIG_INI_MAX_LINE CONFIG_INI_MAX_NAME CONFIG_INI_MAX_SECTION -CONFIG_INKA4X0 CONFIG_INTEGRITY CONFIG_INTEL_ICH6_GPIO CONFIG_INTERRUPTS @@ -1328,14 +1269,12 @@ CONFIG_IOMUX_LPSR CONFIG_IOMUX_SHARE_CONF_REG CONFIG_IOS CONFIG_IO_TRACE -CONFIG_IP86x CONFIG_IPADDR CONFIG_IPADDR1 CONFIG_IPADDR2 CONFIG_IPAM390_GPIO_BOOTMODE CONFIG_IPAM390_GPIO_LED_GREEN CONFIG_IPAM390_GPIO_LED_RED -CONFIG_IPEK01 CONFIG_IPROC CONFIG_IPUV3_CLK CONFIG_IP_DEFRAG @@ -1351,7 +1290,6 @@ CONFIG_IS_ENABLED CONFIG_IS_INVALID CONFIG_IS_MODULE CONFIG_IS_VALID -CONFIG_IVMS8 CONFIG_JFFS2_CMDLINE CONFIG_JFFS2_DEV CONFIG_JFFS2_LZO @@ -1361,7 +1299,6 @@ CONFIG_JFFS2_PART_SIZE CONFIG_JFFS2_SUMMARY CONFIG_JRSTARTR_JR0 CONFIG_JTAG_CONSOLE -CONFIG_JUPITER CONFIG_KASAN CONFIG_KATMAI CONFIG_KCLK_DIS @@ -1373,11 +1310,6 @@ CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_KEYSTONE_RBL_NAND CONFIG_KEY_REVOCATION CONFIG_KGDB_BAUDRATE -CONFIG_KGDB_EXTC_PINSEL -CONFIG_KGDB_EXTC_RATE -CONFIG_KGDB_INDEX -CONFIG_KGDB_ON_SCC -CONFIG_KGDB_ON_SMC CONFIG_KGDB_SER_INDEX CONFIG_KILAUEA CONFIG_KIRKWOOD_EGIGA_INIT @@ -1387,7 +1319,6 @@ CONFIG_KIRKWOOD_RGMII_PAD_1V8 CONFIG_KIRKWOOD_SPI CONFIG_KIRQ_EN CONFIG_KM8321 -CONFIG_KM8XX CONFIG_KMCOGE4 CONFIG_KMCOGE5NE CONFIG_KMETER1 @@ -1398,7 +1329,6 @@ CONFIG_KMSUPX5 CONFIG_KMTEGR1 CONFIG_KMTEPR2 CONFIG_KMVECT1 -CONFIG_KM_82XX CONFIG_KM_BOARD_EXTRA_ENV CONFIG_KM_BOARD_NAME CONFIG_KM_COGE5UN @@ -1511,7 +1441,6 @@ CONFIG_LCD_IN_PSRAM CONFIG_LCD_LOGO CONFIG_LCD_MENU CONFIG_LCD_MENU_BOARD -CONFIG_LCD_NOSTDOUT CONFIG_LCD_ROTATION CONFIG_LD9040 CONFIG_LEGACY @@ -1631,7 +1560,6 @@ CONFIG_MCFTMR CONFIG_MCFUART CONFIG_MCLK_DIS CONFIG_MDIO_TIMEOUT -CONFIG_MECP5123 CONFIG_MEMSIZE CONFIG_MEMSIZE_IN_BYTES CONFIG_MEMSIZE_MASK @@ -1650,7 +1578,6 @@ CONFIG_MIIM_ADDRESS CONFIG_MII_DEFAULT_TSEC CONFIG_MII_INIT CONFIG_MII_SUPPRESS_PREAMBLE -CONFIG_MINIFAP CONFIG_MIPS_HUGE_TLB_SUPPORT CONFIG_MIPS_MT_FPAFF CONFIG_MIRQ_EN @@ -1678,21 +1605,7 @@ CONFIG_MMC_TRACE CONFIG_MMU CONFIG_MODVERSIONS CONFIG_MONITOR_IS_IN_RAM -CONFIG_MOTIONPRO CONFIG_MP -CONFIG_MPC5121ADS -CONFIG_MPC5121ADS_REV2 -CONFIG_MPC512x_FEC -CONFIG_MPC5200 -CONFIG_MPC5200_DDR -CONFIG_MPC555 -CONFIG_MPC5xxx_FEC -CONFIG_MPC5xxx_FEC_MII10 -CONFIG_MPC5xxx_FEC_MII100 -CONFIG_MPC823 -CONFIG_MPC8247 -CONFIG_MPC8255 -CONFIG_MPC8272_FAMILY CONFIG_MPC8308 CONFIG_MPC8308RDB CONFIG_MPC8308_P1M @@ -1722,26 +1635,18 @@ CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN CONFIG_MPC83XX_GPIO_1_INIT_VALUE CONFIG_MPC83XX_PCI2 -CONFIG_MPC850 -CONFIG_MPC855 -CONFIG_MPC857 CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME CONFIG_MPC85XX_PCI2 CONFIG_MPC860 CONFIG_MPC860T -CONFIG_MPC862 CONFIG_MPC866 CONFIG_MPC866_FAMILY -CONFIG_MPC86x CONFIG_MPC885 -CONFIG_MPC885_FAMILY CONFIG_MPC8XXX_SPI -CONFIG_MPC8XX_LCD CONFIG_MPC8xxx_DISABLE_BPTR CONFIG_MPLL_FREQ CONFIG_MPR2 -CONFIG_MPX5200 CONFIG_MP_CLK_FREQ CONFIG_MS7720SE CONFIG_MS7722SE @@ -1773,7 +1678,6 @@ CONFIG_MTD_UBI_DEBUG_PARANOID CONFIG_MTD_UBI_GLUEBI CONFIG_MTD_UBI_MODULE CONFIG_MULTI_CS -CONFIG_MUNICES CONFIG_MUSB_HOST CONFIG_MVEBU_MMC CONFIG_MVGBE @@ -1846,7 +1750,6 @@ CONFIG_NAND_KMETER1 CONFIG_NAND_LPC32XX_MLC CONFIG_NAND_LPC32XX_SLC CONFIG_NAND_MODE_REG -CONFIG_NAND_MPC5121_NFC CONFIG_NAND_MXC CONFIG_NAND_MXC_V1_1 CONFIG_NAND_NDFC @@ -1910,7 +1813,6 @@ CONFIG_OF_IDE_FIXUP CONFIG_OF_SPI CONFIG_OF_SPI_FLASH CONFIG_OF_STDOUT_PATH -CONFIG_OF_SUPPORT_OLD_DEVICE_TREES CONFIG_OMAP_EHCI_PHY1_RESET_GPIO CONFIG_OMAP_EHCI_PHY2_RESET_GPIO CONFIG_OMAP_EHCI_PHY3_RESET_GPIO @@ -1932,7 +1834,6 @@ CONFIG_PALMAS_SMPS7_FPWM CONFIG_PALMAS_USB_SS_PWR CONFIG_PANIC_HANG CONFIG_PARAVIRT -CONFIG_PATI CONFIG_PB1000 CONFIG_PB1100 CONFIG_PB1500 @@ -1997,7 +1898,6 @@ CONFIG_PCMCIA_SLOT_B CONFIG_PCNET CONFIG_PCNET_79C973 CONFIG_PCNET_79C975 -CONFIG_PDM360NG CONFIG_PEN_ADDR_BIG_ENDIAN CONFIG_PERIF1_FREQ CONFIG_PERIF2_FREQ @@ -2006,7 +1906,6 @@ CONFIG_PERIF4_FREQ CONFIG_PHY1_ADDR CONFIG_PHY2_ADDR CONFIG_PHY3_ADDR -CONFIG_PHYCORE_MPC5200B_TINY CONFIG_PHYSMEM CONFIG_PHY_ADDR CONFIG_PHY_BASE_ADR @@ -2159,9 +2058,6 @@ CONFIG_PS2KBD CONFIG_PS2MULT CONFIG_PS2MULT_DELAY CONFIG_PS2SERIAL -CONFIG_PSC3_USB -CONFIG_PSC_CONSOLE -CONFIG_PSC_CONSOLE2 CONFIG_PSRAM_SCFG CONFIG_PWM CONFIG_PWM_IMX @@ -2264,9 +2160,12 @@ CONFIG_RSK7264 CONFIG_RSK7269 CONFIG_RTC_DS1307 CONFIG_RTC_DS1337 +CONFIG_RTC_DS1337_NOOSC CONFIG_RTC_DS1338 +CONFIG_RTC_DS1339_TCR_VAL CONFIG_RTC_DS1374 CONFIG_RTC_DS1388 +CONFIG_RTC_DS1388_TCR_VAL CONFIG_RTC_DS1556 CONFIG_RTC_DS174x CONFIG_RTC_DS3231 @@ -2281,8 +2180,6 @@ CONFIG_RTC_MC13XXX CONFIG_RTC_MC146818 CONFIG_RTC_MCFRRTC CONFIG_RTC_MCP79411 -CONFIG_RTC_MPC5200 -CONFIG_RTC_MPC8xx CONFIG_RTC_MV CONFIG_RTC_MXS CONFIG_RTC_PCF8563 @@ -2295,15 +2192,7 @@ CONFIG_RUN_FROM_DDR1 CONFIG_RUN_FROM_IRAM_ONLY CONFIG_RX_DESCR_NUM CONFIG_S32V234 -CONFIG_S3C2400 -CONFIG_S3C2410 -CONFIG_S3C2410_NAND_BBT -CONFIG_S3C2410_NAND_HWECC -CONFIG_S3C2440 CONFIG_S3C24X0 -CONFIG_S3C24XX_TACLS -CONFIG_S3C24XX_TWRPH0 -CONFIG_S3C24XX_TWRPH1 CONFIG_S3D2_CLK_FREQ CONFIG_S3D4_CLK_FREQ CONFIG_S5P @@ -2362,7 +2251,6 @@ CONFIG_SDRAM_PPC4xx_IBM_DDR CONFIG_SDRAM_PPC4xx_IBM_DDR2 CONFIG_SDRAM_PPC4xx_IBM_SDRAM CONFIG_SDRC -CONFIG_SDR_MT48LC16M16A2 CONFIG_SD_BOOT_QSPI CONFIG_SECBOOT CONFIG_SECURE_BL1_ONLY @@ -2396,7 +2284,6 @@ CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_MODE CONFIG_SF_DEFAULT_SPEED -CONFIG_SF_DUAL_FLASH CONFIG_SGI_IP28 CONFIG_SH4_PCI CONFIG_SH73A0 @@ -2681,8 +2568,6 @@ CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STATIC_RELA CONFIG_STD_DEVICES_SETTINGS -CONFIG_STK52XX -CONFIG_STK52XX_REV100 CONFIG_STM32F4DISCOVERY CONFIG_STM32X7_SERIAL CONFIG_STM32_FLASH @@ -2738,9 +2623,6 @@ CONFIG_SYS_64BIT_VSPRINTF CONFIG_SYS_66MHZ CONFIG_SYS_8313ERDB_BROKEN_PMC CONFIG_SYS_83XX_DDR_USES_CS0 -CONFIG_SYS_8XX_XIN -CONFIG_SYS_8xx_CPUCLK_MAX -CONFIG_SYS_8xx_CPUCLK_MIN CONFIG_SYS_ACE_BASE CONFIG_SYS_ACE_BASE_PHYS_H CONFIG_SYS_ACE_BASE_PHYS_L @@ -2771,10 +2653,6 @@ CONFIG_SYS_APP1_SIZE CONFIG_SYS_APP2_BASE CONFIG_SYS_APP2_SIZE CONFIG_SYS_ARCH_TIMER -CONFIG_SYS_ARIA_FPGA_BASE -CONFIG_SYS_ARIA_FPGA_SIZE -CONFIG_SYS_ARIA_SRAM_BASE -CONFIG_SYS_ARIA_SRAM_SIZE CONFIG_SYS_ARM_CACHE_WRITETHROUGH CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK @@ -2783,8 +2661,6 @@ CONFIG_SYS_AT91_PLLB CONFIG_SYS_AT91_SLOW_CLOCK CONFIG_SYS_ATA_ALT_OFFSET CONFIG_SYS_ATA_BASE_ADDR -CONFIG_SYS_ATA_CS_ON_I2C2 -CONFIG_SYS_ATA_CS_ON_TIMER01 CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_ATA_IDE0_OFFSET CONFIG_SYS_ATA_IDE1_OFFSET @@ -2808,9 +2684,6 @@ CONFIG_SYS_AUXCORE_BOOTDATA CONFIG_SYS_BARGSIZE CONFIG_SYS_BASE_BAUD CONFIG_SYS_BAUDRATE_TABLE -CONFIG_SYS_BCR -CONFIG_SYS_BCR_60x -CONFIG_SYS_BCR_SINGLE CONFIG_SYS_BCSR CONFIG_SYS_BCSR3_PCIE CONFIG_SYS_BCSR5_PCI66EN @@ -2843,9 +2716,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR CONFIG_SYS_BOOTCOUNT_BE CONFIG_SYS_BOOTCOUNT_LE CONFIG_SYS_BOOTCOUNT_SINGLEWORD -CONFIG_SYS_BOOTCS_CFG -CONFIG_SYS_BOOTCS_SIZE -CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTFILE CONFIG_SYS_BOOTFILE_PREFIX CONFIG_SYS_BOOTMAPSZ @@ -2861,8 +2731,6 @@ CONFIG_SYS_BOOT_RAMDISK_HIGH CONFIG_SYS_BR0_64M CONFIG_SYS_BR0_8M CONFIG_SYS_BR0_PRELIM -CONFIG_SYS_BR10_PRELIM -CONFIG_SYS_BR11_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_BR3_CAN @@ -2874,10 +2742,6 @@ CONFIG_SYS_BR6_64M CONFIG_SYS_BR6_8M CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR7_PRELIM -CONFIG_SYS_BR8_PRELIM -CONFIG_SYS_BR9_PRELIM -CONFIG_SYS_BRGCLK_PRESCALE -CONFIG_SYS_BRIGHTNESS CONFIG_SYS_BUSCLK CONFIG_SYS_CACHELINE_SHIFT CONFIG_SYS_CACHE_ACR0 @@ -2910,7 +2774,6 @@ CONFIG_SYS_CFI_FLASH_CONFIG_REGS CONFIG_SYS_CFI_FLASH_STATUS_POLL CONFIG_SYS_CF_BASE CONFIG_SYS_CF_INTC_REG1 -CONFIG_SYS_CF_SIZE CONFIG_SYS_CH7301_I2C CONFIG_SYS_CKEN CONFIG_SYS_CLK @@ -2936,7 +2799,6 @@ CONFIG_SYS_CMXFCR_MASK3 CONFIG_SYS_CMXFCR_VALUE1 CONFIG_SYS_CMXFCR_VALUE2 CONFIG_SYS_CMXFCR_VALUE3 -CONFIG_SYS_CMXSCR_VALUE CONFIG_SYS_CORE_SRAM CONFIG_SYS_CORE_SRAM_SIZE CONFIG_SYS_CORTEX_R4 @@ -2963,16 +2825,11 @@ CONFIG_SYS_CPLD_SIZE CONFIG_SYS_CPMFCR_RAMTYPE CONFIG_SYS_CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_INTERRUPT -CONFIG_SYS_CPM_POST_WORD_ADDR CONFIG_SYS_CPRI CONFIG_SYS_CPRI_CLK CONFIG_SYS_CPUSPEED CONFIG_SYS_CPU_CLK -CONFIG_SYS_CPU_PCI_IO_START -CONFIG_SYS_CPU_PCI_MEMIO_START -CONFIG_SYS_CPU_PCI_MEM_START CONFIG_SYS_CS0_BASE -CONFIG_SYS_CS0_CFG CONFIG_SYS_CS0_CTRL CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_CS0_FTIM1 @@ -2980,9 +2837,7 @@ CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_CS0_MASK CONFIG_SYS_CS0_SIZE -CONFIG_SYS_CS0_START CONFIG_SYS_CS1_BASE -CONFIG_SYS_CS1_CFG CONFIG_SYS_CS1_CTRL CONFIG_SYS_CS1_FLASH_BASE CONFIG_SYS_CS1_FTIM0 @@ -2990,10 +2845,7 @@ CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_CS1_MASK -CONFIG_SYS_CS1_SIZE -CONFIG_SYS_CS1_START CONFIG_SYS_CS2_BASE -CONFIG_SYS_CS2_CFG CONFIG_SYS_CS2_CTRL CONFIG_SYS_CS2_FLASH_BASE CONFIG_SYS_CS2_FTIM0 @@ -3001,10 +2853,7 @@ CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CS2_MASK -CONFIG_SYS_CS2_SIZE -CONFIG_SYS_CS2_START CONFIG_SYS_CS3_BASE -CONFIG_SYS_CS3_CFG CONFIG_SYS_CS3_CTRL CONFIG_SYS_CS3_FLASH_BASE CONFIG_SYS_CS3_FTIM0 @@ -3012,10 +2861,7 @@ CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_CS3_MASK -CONFIG_SYS_CS3_SIZE -CONFIG_SYS_CS3_START CONFIG_SYS_CS4_BASE -CONFIG_SYS_CS4_CFG CONFIG_SYS_CS4_CTRL CONFIG_SYS_CS4_FLASH_BASE CONFIG_SYS_CS4_FTIM0 @@ -3023,10 +2869,7 @@ CONFIG_SYS_CS4_FTIM1 CONFIG_SYS_CS4_FTIM2 CONFIG_SYS_CS4_FTIM3 CONFIG_SYS_CS4_MASK -CONFIG_SYS_CS4_SIZE -CONFIG_SYS_CS4_START CONFIG_SYS_CS5_BASE -CONFIG_SYS_CS5_CFG CONFIG_SYS_CS5_CTRL CONFIG_SYS_CS5_FLASH_BASE CONFIG_SYS_CS5_FTIM0 @@ -3034,28 +2877,20 @@ CONFIG_SYS_CS5_FTIM1 CONFIG_SYS_CS5_FTIM2 CONFIG_SYS_CS5_FTIM3 CONFIG_SYS_CS5_MASK -CONFIG_SYS_CS5_SIZE -CONFIG_SYS_CS5_START CONFIG_SYS_CS6_BASE -CONFIG_SYS_CS6_CFG CONFIG_SYS_CS6_CTRL CONFIG_SYS_CS6_FTIM0 CONFIG_SYS_CS6_FTIM1 CONFIG_SYS_CS6_FTIM2 CONFIG_SYS_CS6_FTIM3 CONFIG_SYS_CS6_MASK -CONFIG_SYS_CS6_SIZE -CONFIG_SYS_CS6_START CONFIG_SYS_CS7_BASE -CONFIG_SYS_CS7_CFG CONFIG_SYS_CS7_CTRL CONFIG_SYS_CS7_FTIM0 CONFIG_SYS_CS7_FTIM1 CONFIG_SYS_CS7_FTIM2 CONFIG_SYS_CS7_FTIM3 CONFIG_SYS_CS7_MASK -CONFIG_SYS_CS7_SIZE -CONFIG_SYS_CS7_START CONFIG_SYS_CSOR0 CONFIG_SYS_CSOR0_EXT CONFIG_SYS_CSOR1 @@ -3092,10 +2927,6 @@ CONFIG_SYS_CSPR6 CONFIG_SYS_CSPR6_EXT CONFIG_SYS_CSPR7 CONFIG_SYS_CSPR7_EXT -CONFIG_SYS_CS_ALETIMING -CONFIG_SYS_CS_BURST -CONFIG_SYS_CS_DEADCYCLE -CONFIG_SYS_CS_HOLDCYCLE CONFIG_SYS_DA850_CS2CFG CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_DDR2_DDRPHYCR @@ -3184,15 +3015,6 @@ CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDRCDR CONFIG_SYS_DDRCDR_VALUE -CONFIG_SYS_DDRCMD_EM2 -CONFIG_SYS_DDRCMD_EM3 -CONFIG_SYS_DDRCMD_EN_DLL -CONFIG_SYS_DDRCMD_NOP -CONFIG_SYS_DDRCMD_OCD_DEFAULT -CONFIG_SYS_DDRCMD_OCD_EXIT -CONFIG_SYS_DDRCMD_PCHG_ALL -CONFIG_SYS_DDRCMD_RES_DLL -CONFIG_SYS_DDRCMD_RFSH CONFIG_SYS_DDRD CONFIG_SYS_DDRTC CONFIG_SYS_DDRUA @@ -3332,13 +3154,9 @@ CONFIG_SYS_DEBUG CONFIG_SYS_DEBUG_SERVER_FW_ADDR CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DECREMENT_PATTERNS -CONFIG_SYS_DEFAULT_IMMR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -CONFIG_SYS_DEFAULT_MBAR CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR -CONFIG_SYS_DELAYED_ICACHE -CONFIG_SYS_DER CONFIG_SYS_DEVICE_NULLDEV CONFIG_SYS_DFU_DATA_BUF_SIZE CONFIG_SYS_DFU_MAX_FILE_SIZE @@ -3348,7 +3166,6 @@ CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_SYS_DIRECT_FLASH_NFS CONFIG_SYS_DIRECT_FLASH_TFTP CONFIG_SYS_DISCOVER_PHY -CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_DIU_ADDR CONFIG_SYS_DM36x_PINMUX0 CONFIG_SYS_DM36x_PINMUX1 @@ -3377,8 +3194,6 @@ CONFIG_SYS_DRAMSZ1 CONFIG_SYS_DRAM_BASE CONFIG_SYS_DRAM_SIZE CONFIG_SYS_DRAM_TEST -CONFIG_SYS_DS1339_TCR_VAL -CONFIG_SYS_DS1388_TCR_VAL CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_DSPIC_TEST_MASK CONFIG_SYS_DSPI_CS0 @@ -3425,9 +3240,6 @@ CONFIG_SYS_EHCI_USB1_ADDR CONFIG_SYS_ELBC_BASE CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELO3_DMA3 -CONFIG_SYS_ELPIDA_INIT_DEV_OP -CONFIG_SYS_ELPIDA_OCD_EXIT -CONFIG_SYS_ELPIDA_RES_DLL CONFIG_SYS_EMAC_TI_CLKDIV CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS CONFIG_SYS_ENABLE_PADS_ALL @@ -3498,7 +3310,6 @@ CONFIG_SYS_FLASH_BASE1 CONFIG_SYS_FLASH_BASE2 CONFIG_SYS_FLASH_BASE_1 CONFIG_SYS_FLASH_BASE_2 -CONFIG_SYS_FLASH_BASE_CS1 CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE_PHYS_EARLY CONFIG_SYS_FLASH_BASE_PHYS_H @@ -4027,14 +3838,11 @@ CONFIG_SYS_GPIO_CRAM_ADV CONFIG_SYS_GPIO_CRAM_CLK CONFIG_SYS_GPIO_CRAM_CRE CONFIG_SYS_GPIO_CRAM_WAIT -CONFIG_SYS_GPIO_DATADIR -CONFIG_SYS_GPIO_DATAVALUE CONFIG_SYS_GPIO_DSPIC_READY CONFIG_SYS_GPIO_EEPROM_EXT_WP CONFIG_SYS_GPIO_EEPROM_INT_WP CONFIG_SYS_GPIO_EEPROM_WP CONFIG_SYS_GPIO_EN -CONFIG_SYS_GPIO_ENABLE CONFIG_SYS_GPIO_EREADY CONFIG_SYS_GPIO_FLASH_WP CONFIG_SYS_GPIO_FUNC @@ -4052,7 +3860,6 @@ CONFIG_SYS_GPIO_LSB_ENABLE CONFIG_SYS_GPIO_M66EN CONFIG_SYS_GPIO_MONARCH_N CONFIG_SYS_GPIO_ODR -CONFIG_SYS_GPIO_OPENDRAIN CONFIG_SYS_GPIO_OR CONFIG_SYS_GPIO_OUT CONFIG_SYS_GPIO_PCIE_CLKREQ @@ -4077,9 +3884,6 @@ CONFIG_SYS_GPSR0_VAL CONFIG_SYS_GPSR1_VAL CONFIG_SYS_GPSR2_VAL CONFIG_SYS_GPSR3_VAL -CONFIG_SYS_GPS_PORT_CONFIG -CONFIG_SYS_GPS_PORT_CONFIG_1 -CONFIG_SYS_GPS_PORT_CONFIG_2 CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HELP_CMD_WIDTH CONFIG_SYS_HID0_FINAL @@ -4091,14 +3895,6 @@ CONFIG_SYS_HOSTNAME CONFIG_SYS_HRCW_HIGH CONFIG_SYS_HRCW_HIGH_BASE CONFIG_SYS_HRCW_LOW -CONFIG_SYS_HRCW_MASTER -CONFIG_SYS_HRCW_SLAVE1 -CONFIG_SYS_HRCW_SLAVE2 -CONFIG_SYS_HRCW_SLAVE3 -CONFIG_SYS_HRCW_SLAVE4 -CONFIG_SYS_HRCW_SLAVE5 -CONFIG_SYS_HRCW_SLAVE6 -CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HSDRAMC CONFIG_SYS_HWINFO_MAGIC CONFIG_SYS_HWINFO_OFFSET @@ -4130,7 +3926,6 @@ CONFIG_SYS_I2C_BUS_MAX CONFIG_SYS_I2C_CLK_OFFSET CONFIG_SYS_I2C_DAVINCI CONFIG_SYS_I2C_DIRECT_BUS -CONFIG_SYS_I2C_DPMEM_OFFSET CONFIG_SYS_I2C_DSPIC_2_ADDR CONFIG_SYS_I2C_DSPIC_ADDR CONFIG_SYS_I2C_DSPIC_IO_ADDR @@ -4188,7 +3983,6 @@ CONFIG_SYS_I2C_IHS_SPEED_2_1 CONFIG_SYS_I2C_IHS_SPEED_3 CONFIG_SYS_I2C_IHS_SPEED_3_1 CONFIG_SYS_I2C_INIT_BOARD -CONFIG_SYS_I2C_IO CONFIG_SYS_I2C_KEYBD_ADDR CONFIG_SYS_I2C_KONA CONFIG_SYS_I2C_LDI_ADDR @@ -4293,7 +4087,6 @@ CONFIG_SYS_I2C_SPEED3 CONFIG_SYS_I2C_TCA642X_ADDR CONFIG_SYS_I2C_TCA642X_BUS_NUM CONFIG_SYS_I2C_TEGRA -CONFIG_SYS_I2C_UCODE_PATCH CONFIG_SYS_I2C_W83782G_ADDR CONFIG_SYS_I2C_ZYNQ CONFIG_SYS_I2C_ZYNQ_SLAVE @@ -4369,10 +4162,8 @@ CONFIG_SYS_INTSRAM CONFIG_SYS_INTSRAMSZ CONFIG_SYS_INT_FLASH_BASE CONFIG_SYS_INT_FLASH_ENABLE -CONFIG_SYS_IOCTRL_MUX_DDR CONFIG_SYS_IO_BASE CONFIG_SYS_IPBCLK_EQUALS_XLBCLK -CONFIG_SYS_IPBSPEED_133 CONFIG_SYS_IR_REG_BASE_ADDR CONFIG_SYS_ISA_BASE CONFIG_SYS_ISA_IO @@ -4380,7 +4171,6 @@ CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_OFFSET CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_MEM -CONFIG_SYS_ISB CONFIG_SYS_ISRAM_BASE CONFIG_SYS_IVM_EEPROM_ADR CONFIG_SYS_IVM_EEPROM_MAX_LEN @@ -4490,8 +4280,6 @@ CONFIG_SYS_LOCAL_CONF_REGS CONFIG_SYS_LONGHELP CONFIG_SYS_LOW CONFIG_SYS_LOWBOOT -CONFIG_SYS_LOWBOOT16 -CONFIG_SYS_LOWBOOT32 CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LOW_RES_TIMER CONFIG_SYS_LPAE_SDRAM_BASE @@ -4536,13 +4324,11 @@ CONFIG_SYS_MARUBUN_IO CONFIG_SYS_MARUBUN_MRSHPC CONFIG_SYS_MARUBUN_MW1 CONFIG_SYS_MARUBUN_MW2 -CONFIG_SYS_MASK CONFIG_SYS_MASTER_CLOCK CONFIG_SYS_MATRIX_EBI0CSA_VAL CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_MCFG_REMAP CONFIG_SYS_MAXARGS -CONFIG_SYS_MAXIDLE CONFIG_SYS_MAX_DATAFLASH_BANKS CONFIG_SYS_MAX_DDR_BAT_SIZE CONFIG_SYS_MAX_DOC_DEVICE @@ -4554,7 +4340,6 @@ CONFIG_SYS_MAX_MTD_BANKS CONFIG_SYS_MAX_NAND_CHIPS CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SYS_MAX_PCI_EPS -CONFIG_SYS_MAX_RAM_SIZE CONFIG_SYS_MB862xx_CCF CONFIG_SYS_MB862xx_MMR CONFIG_SYS_MBAR @@ -4579,48 +4364,12 @@ CONFIG_SYS_MCMEM1_VAL CONFIG_SYS_MDC1_PIN CONFIG_SYS_MDCNFG_VAL CONFIG_SYS_MDC_PIN -CONFIG_SYS_MDDRCGRP_HIPRIO_CFG -CONFIG_SYS_MDDRCGRP_LUT0_AL -CONFIG_SYS_MDDRCGRP_LUT0_AU -CONFIG_SYS_MDDRCGRP_LUT0_ML -CONFIG_SYS_MDDRCGRP_LUT0_MU -CONFIG_SYS_MDDRCGRP_LUT1_AL -CONFIG_SYS_MDDRCGRP_LUT1_AU -CONFIG_SYS_MDDRCGRP_LUT1_ML -CONFIG_SYS_MDDRCGRP_LUT1_MU -CONFIG_SYS_MDDRCGRP_LUT2_AL -CONFIG_SYS_MDDRCGRP_LUT2_AU -CONFIG_SYS_MDDRCGRP_LUT2_ML -CONFIG_SYS_MDDRCGRP_LUT2_MU -CONFIG_SYS_MDDRCGRP_LUT3_AL -CONFIG_SYS_MDDRCGRP_LUT3_AU -CONFIG_SYS_MDDRCGRP_LUT3_ML -CONFIG_SYS_MDDRCGRP_LUT3_MU -CONFIG_SYS_MDDRCGRP_LUT4_AL -CONFIG_SYS_MDDRCGRP_LUT4_AU -CONFIG_SYS_MDDRCGRP_LUT4_ML -CONFIG_SYS_MDDRCGRP_LUT4_MU -CONFIG_SYS_MDDRCGRP_PM_CFG1 -CONFIG_SYS_MDDRCGRP_PM_CFG2 -CONFIG_SYS_MDDRC_SYS_CFG -CONFIG_SYS_MDDRC_SYS_CFG_ALT1 -CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA -CONFIG_SYS_MDDRC_SYS_CFG_EN -CONFIG_SYS_MDDRC_TIME_CFG0 -CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 -CONFIG_SYS_MDDRC_TIME_CFG1 -CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 -CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA -CONFIG_SYS_MDDRC_TIME_CFG2 -CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 -CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA CONFIG_SYS_MDIO1_OFFSET CONFIG_SYS_MDIO1_PIN CONFIG_SYS_MDIO_BASE_ADDR CONFIG_SYS_MDIO_PIN CONFIG_SYS_MDMRS_VAL CONFIG_SYS_MDREFR_VAL -CONFIG_SYS_MEASURE_CPUCLK CONFIG_SYS_MECR_VAL CONFIG_SYS_MEMAC_LITTLE_ENDIAN CONFIG_SYS_MEMORY_BASE @@ -4635,18 +4384,6 @@ CONFIG_SYS_MEM_SIZE CONFIG_SYS_MEM_TOP_HIDE CONFIG_SYS_MFD CONFIG_SYS_MHZ -CONFIG_SYS_MICRON_BMODE -CONFIG_SYS_MICRON_BMODE_PARAM -CONFIG_SYS_MICRON_BMODE_RSTDLL -CONFIG_SYS_MICRON_EMODE -CONFIG_SYS_MICRON_EMODE2 -CONFIG_SYS_MICRON_EMODE3 -CONFIG_SYS_MICRON_EMODE_PARAM -CONFIG_SYS_MICRON_EMR -CONFIG_SYS_MICRON_EMR2 -CONFIG_SYS_MICRON_EMR3 -CONFIG_SYS_MICRON_EMR_OCD -CONFIG_SYS_MICRON_INIT_DEV_OP CONFIG_SYS_MII_MODE CONFIG_SYS_MIPS_CACHE_MODE CONFIG_SYS_MIPS_TIMER_FREQ @@ -4673,10 +4410,6 @@ CONFIG_SYS_MONITOR_BASE_EARLY CONFIG_SYS_MONITOR_LEN CONFIG_SYS_MONITOR_SEC CONFIG_SYS_MOR_VAL -CONFIG_SYS_MPC512X_CLKIN -CONFIG_SYS_MPC512x_USB1_ADDR -CONFIG_SYS_MPC512x_USB1_OFFSET -CONFIG_SYS_MPC5XXX_CLKIN CONFIG_SYS_MPC83xx_DMA_ADDR CONFIG_SYS_MPC83xx_DMA_OFFSET CONFIG_SYS_MPC83xx_ESDHC_ADDR @@ -4756,15 +4489,6 @@ CONFIG_SYS_MPC8xxx_DDR_OFFSET CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC8xxx_PIC_ADDR CONFIG_SYS_MPC92469AC -CONFIG_SYS_MPEG_BASE -CONFIG_SYS_MPEG_SIZE -CONFIG_SYS_MPTPR -CONFIG_SYS_MPTPR_1BK_2K -CONFIG_SYS_MPTPR_1BK_4K -CONFIG_SYS_MPTPR_1BK_8K -CONFIG_SYS_MPTPR_2BK_2K -CONFIG_SYS_MPTPR_2BK_4K -CONFIG_SYS_MPTPR_2BK_8K CONFIG_SYS_MRAM_BASE CONFIG_SYS_MRAM_SIZE CONFIG_SYS_MRS_OFFS @@ -4980,8 +4704,6 @@ CONFIG_SYS_OR0_8M CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_REMAP CONFIG_SYS_OR1 -CONFIG_SYS_OR10_PRELIM -CONFIG_SYS_OR11_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR2_PRELIM @@ -4995,8 +4717,6 @@ CONFIG_SYS_OR6_64M CONFIG_SYS_OR6_8M CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR7_PRELIM -CONFIG_SYS_OR8_PRELIM -CONFIG_SYS_OR9_PRELIM CONFIG_SYS_OR_TIMING_FLASH CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ CONFIG_SYS_OR_TIMING_MRAM @@ -5004,7 +4724,6 @@ CONFIG_SYS_OR_TIMING_SDRAM CONFIG_SYS_OSC0_HZ CONFIG_SYS_OSC1_HZ CONFIG_SYS_OSCIN_FREQ -CONFIG_SYS_OSC_CLK CONFIG_SYS_OSD_DH CONFIG_SYS_OSD_SCREENS CONFIG_SYS_OSPR_OFFSET @@ -5121,7 +4840,6 @@ CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_SIZE CONFIG_SYS_PCI64_MEMORY_BUS CONFIG_SYS_PCI9054_IOBASE -CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 CONFIG_SYS_PCIE CONFIG_SYS_PCIE0_CFGBASE CONFIG_SYS_PCIE0_CFGMASK @@ -5219,9 +4937,6 @@ CONFIG_SYS_PCIE_MMAP_SIZE CONFIG_SYS_PCIE_NR_PORTS CONFIG_SYS_PCIE_PHYS CONFIG_SYS_PCIE_VIRT -CONFIG_SYS_PCIMSK0_MASK -CONFIG_SYS_PCIMSK1_MASK -CONFIG_SYS_PCISPEED_66 CONFIG_SYS_PCI_64BIT CONFIG_SYS_PCI_BAR0 CONFIG_SYS_PCI_BAR1 @@ -5264,17 +4979,6 @@ CONFIG_SYS_PCI_MEM_SIZE CONFIG_SYS_PCI_MMIO_BASE CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_SIZE -CONFIG_SYS_PCI_MSTR0_LOCAL -CONFIG_SYS_PCI_MSTR1_LOCAL -CONFIG_SYS_PCI_MSTR_IO_BUS -CONFIG_SYS_PCI_MSTR_IO_LOCAL -CONFIG_SYS_PCI_MSTR_IO_SIZE -CONFIG_SYS_PCI_MSTR_MEMIO_BUS -CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL -CONFIG_SYS_PCI_MSTR_MEMIO_SIZE -CONFIG_SYS_PCI_MSTR_MEM_BUS -CONFIG_SYS_PCI_MSTR_MEM_LOCAL -CONFIG_SYS_PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_NR_INBOUND_WIN CONFIG_SYS_PCI_PHYS CONFIG_SYS_PCI_PTM1LA @@ -5334,10 +5038,7 @@ CONFIG_SYS_PCMCIA_POR4 CONFIG_SYS_PCMCIA_POR5 CONFIG_SYS_PCMCIA_POR6 CONFIG_SYS_PCMCIA_POR7 -CONFIG_SYS_PCMCIA_TIMING CONFIG_SYS_PDCNT -CONFIG_SYS_PDM360NG_COPROC_BAUDRATE -CONFIG_SYS_PDM360NG_COPROC_READ_DELAY CONFIG_SYS_PEHLPAR CONFIG_SYS_PEPAR CONFIG_SYS_PERIPHERAL_BASE @@ -5347,7 +5048,6 @@ CONFIG_SYS_PHYS_ADDR_HIGH CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_PIB_BASE CONFIG_SYS_PIB_WINDOW_SIZE -CONFIG_SYS_PICMR0_MASK_ATTRIB CONFIG_SYS_PIOC_ASR_VAL CONFIG_SYS_PIOC_BSR_VAL CONFIG_SYS_PIOC_PDR_VAL @@ -5356,7 +5056,6 @@ CONFIG_SYS_PIOC_PPUDR_VAL CONFIG_SYS_PIOD_PDR_VAL1 CONFIG_SYS_PIOD_PPUDR_VAL CONFIG_SYS_PIO_MODE -CONFIG_SYS_PISCR CONFIG_SYS_PIT_BASE CONFIG_SYS_PIT_PRESCALE CONFIG_SYS_PIXIS_VBOOT_ENABLE @@ -5379,15 +5078,11 @@ CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_RECONFIG CONFIG_SYS_PLL_SETTLING_TIME -CONFIG_SYS_PLPRCR CONFIG_SYS_PLUG_BASE CONFIG_SYS_PMAN CONFIG_SYS_PMC_BASE CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PME_CLK -CONFIG_SYS_POCMR0_MASK_ATTRIB -CONFIG_SYS_POCMR1_MASK_ATTRIB -CONFIG_SYS_POCMR2_MASK_ATTRIB CONFIG_SYS_PORTTC CONFIG_SYS_POST_BSPEC1 CONFIG_SYS_POST_BSPEC2 @@ -5420,7 +5115,6 @@ CONFIG_SYS_POST_MEM_REGIONS CONFIG_SYS_POST_OCM CONFIG_SYS_POST_PREREL CONFIG_SYS_POST_RTC -CONFIG_SYS_POST_SPI CONFIG_SYS_POST_SPR CONFIG_SYS_POST_SYSMON CONFIG_SYS_POST_UART @@ -5434,15 +5128,8 @@ CONFIG_SYS_PPC_DDR_WIMGE CONFIG_SYS_PQSPAR CONFIG_SYS_PRELIM_OR_AM CONFIG_SYS_PROMPT_HUSH_PS2 -CONFIG_SYS_PSC1 -CONFIG_SYS_PSC3 -CONFIG_SYS_PSC4 -CONFIG_SYS_PSC6 -CONFIG_SYS_PSDMR CONFIG_SYS_PSDPAR -CONFIG_SYS_PSRT CONFIG_SYS_PSSR_VAL -CONFIG_SYS_PTA_PER_CLK CONFIG_SYS_PTCPAR CONFIG_SYS_PTDPAR CONFIG_SYS_PTL2_BITS @@ -5484,7 +5171,6 @@ CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C2_SPEED CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_RCAR_I2C3_SPEED -CONFIG_SYS_RCCR CONFIG_SYS_RCWH_PCIHOST CONFIG_SYS_READ_SPD CONFIG_SYS_REDUNDAND_ENVIRONMENT @@ -5501,17 +5187,11 @@ CONFIG_SYS_RIO_MEM_BUS CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_SIZE CONFIG_SYS_RIO_MEM_VIRT -CONFIG_SYS_RMDS -CONFIG_SYS_RMR CONFIG_SYS_ROM_BASE CONFIG_SYS_ROOTPATH CONFIG_SYS_RSTC_RMR_VAL -CONFIG_SYS_RTCSC CONFIG_SYS_RTC_BUS_NUM CONFIG_SYS_RTC_CNT -CONFIG_SYS_RTC_DS1337 -CONFIG_SYS_RTC_DS1337_NOOSC -CONFIG_SYS_RTC_DS1388 CONFIG_SYS_RTC_OSCILLATOR CONFIG_SYS_RTC_PL031_BASE CONFIG_SYS_RTC_REG_BASE_ADDR @@ -5543,7 +5223,6 @@ CONFIG_SYS_SCCR_TSEC2ON CONFIG_SYS_SCCR_TSECCM CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_USBMPHCM -CONFIG_SYS_SCC_TOUT_LOOP CONFIG_SYS_SCR CONFIG_SYS_SCRATCH_VA CONFIG_SYS_SCSI_MAXDEVICE @@ -5566,7 +5245,6 @@ CONFIG_SYS_SDIO_BASE0 CONFIG_SYS_SDIO_BASE1 CONFIG_SYS_SDIO_BASE2 CONFIG_SYS_SDIO_BASE3 -CONFIG_SYS_SDMR CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM0_CFG0 CONFIG_SYS_SDRAM0_CLKTR @@ -5627,7 +5305,6 @@ CONFIG_SYS_SDRAM_CL CONFIG_SYS_SDRAM_CONF1HB CONFIG_SYS_SDRAM_CONF1LL CONFIG_SYS_SDRAM_CONFPATHB -CONFIG_SYS_SDRAM_CS1 CONFIG_SYS_SDRAM_CTP CONFIG_SYS_SDRAM_CTRL CONFIG_SYS_SDRAM_DRVSTRENGTH @@ -5681,7 +5358,6 @@ CONFIG_SYS_SDRC_MR_VAL5 CONFIG_SYS_SDRC_TR_VAL CONFIG_SYS_SDRC_TR_VAL1 CONFIG_SYS_SDRC_TR_VAL2 -CONFIG_SYS_SDSR CONFIG_SYS_SD_VOLTAGE CONFIG_SYS_SEC_MON_ADDR CONFIG_SYS_SEC_MON_OFFSET @@ -5710,9 +5386,6 @@ CONFIG_SYS_SICRH CONFIG_SYS_SICRL CONFIG_SYS_SIL1178_I2C CONFIG_SYS_SIMULATE_SPD_EEPROM -CONFIG_SYS_SIUMCR -CONFIG_SYS_SIUMCR_HIGH -CONFIG_SYS_SIUMCR_LOW CONFIG_SYS_SJA1000_BASE CONFIG_SYS_SMALL_FLASH CONFIG_SYS_SMC0_CYCLE0_VAL @@ -5720,14 +5393,9 @@ CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL -CONFIG_SYS_SMC_DPMEM_OFFSET -CONFIG_SYS_SMC_RXBUFLEN -CONFIG_SYS_SMC_UCODE_PATCH CONFIG_SYS_SMI_BASE CONFIG_SYS_SPANSION_BASE CONFIG_SYS_SPANSION_BOOT -CONFIG_SYS_SPC1920_PLD_BASE -CONFIG_SYS_SPC1920_SMC1_CLK4 CONFIG_SYS_SPCR_OPT CONFIG_SYS_SPCR_TSEC1EP CONFIG_SYS_SPCR_TSEC2EP @@ -5746,20 +5414,14 @@ CONFIG_SYS_SPI_ARGS_OFFS CONFIG_SYS_SPI_ARGS_SIZE CONFIG_SYS_SPI_BASE CONFIG_SYS_SPI_CLK -CONFIG_SYS_SPI_CS_ACT -CONFIG_SYS_SPI_CS_BASE -CONFIG_SYS_SPI_CS_USED -CONFIG_SYS_SPI_DPMEM_OFFSET CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE CONFIG_SYS_SPI_FLASH_U_BOOT_START -CONFIG_SYS_SPI_INIT_OFFSET CONFIG_SYS_SPI_KERNEL_OFFS CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_RTC_DEVID CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -CONFIG_SYS_SPI_UCODE_PATCH CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_SPI_WRITE_TOUT @@ -5801,18 +5463,14 @@ CONFIG_SYS_STATUS_OK CONFIG_SYS_STMICRO_BOOT CONFIG_SYS_SUPPORT_64BIT_DATA CONFIG_SYS_SXCNFG_VAL -CONFIG_SYS_SYPCR CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_SYSTEMACE_WIDTH CONFIG_SYS_TBIPA_VALUE -CONFIG_SYS_TBSCR CONFIG_SYS_TCLK CONFIG_SYS_TEMP_STACK_OCM CONFIG_SYS_TEXT_ADDR CONFIG_SYS_TEXT_BASE_NOR CONFIG_SYS_TEXT_BASE_SPL -CONFIG_SYS_TFP410_ADDR -CONFIG_SYS_TFP410_BUS CONFIG_SYS_TIMERBASE CONFIG_SYS_TIMER_BASE CONFIG_SYS_TIMER_COUNTER @@ -5820,7 +5478,6 @@ CONFIG_SYS_TIMER_COUNTS_DOWN CONFIG_SYS_TIMER_PRESCALER CONFIG_SYS_TIMER_RATE CONFIG_SYS_TLB_FOR_BOOT_FLASH -CONFIG_SYS_TMCNTSC CONFIG_SYS_TMPVIRT CONFIG_SYS_TMRINTR_MASK CONFIG_SYS_TMRINTR_NO @@ -5902,7 +5559,6 @@ CONFIG_SYS_UECx_PHY_ADDR CONFIG_SYS_UHC0_EHCI_BASE CONFIG_SYS_UHC1_EHCI_BASE CONFIG_SYS_ULB_CLK -CONFIG_SYS_UMCR CONFIG_SYS_UNIFY_CACHE CONFIG_SYS_UNSPEC_PHYID CONFIG_SYS_UNSPEC_STRID @@ -5970,8 +5626,6 @@ CONFIG_SYS_VCXK_RESET_PORT CONFIG_SYS_VGA_RAM_EN CONFIG_SYS_VIDEO CONFIG_SYS_VIDEO_LOGO_MAX_SIZE -CONFIG_SYS_VPC3_BASE -CONFIG_SYS_VPC3_SIZE CONFIG_SYS_VSC7385_BASE CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BR_PRELIM @@ -5995,7 +5649,6 @@ CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR CONFIG_SYS_XILINX_SPI_LIST CONFIG_SYS_XIMG_LEN -CONFIG_SYS_XLB_PIPELINING CONFIG_SYS_XSVF_DEFAULT_ADDR CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT @@ -6034,29 +5687,16 @@ CONFIG_TFTP_TSIZE CONFIG_THOR_RESET_OFF CONFIG_THUMB2_KERNEL CONFIG_THUNDERX -CONFIG_TI814X -CONFIG_TI816X -CONFIG_TI816X_DDR_PLL_796 -CONFIG_TI816X_EVM_DDR2 -CONFIG_TI816X_EVM_DDR3 -CONFIG_TI816X_USE_EMIF0 -CONFIG_TI816X_USE_EMIF1 -CONFIG_TI81XX CONFIG_TIMESTAMP CONFIG_TIZEN CONFIG_TI_KEYSTONE_SERDES CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP CONFIG_TMU_TIMER -CONFIG_TOTAL5200 CONFIG_TPL_DRIVERS_MISC_SUPPORT CONFIG_TPL_PAD_TO CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER -CONFIG_TQM5200 -CONFIG_TQM5200S -CONFIG_TQM5200_B -CONFIG_TQM5200_REV100 CONFIG_TQM823L CONFIG_TQM823M CONFIG_TQM834X @@ -6068,10 +5708,6 @@ CONFIG_TQM860L CONFIG_TQM860M CONFIG_TQM862L CONFIG_TQM862M -CONFIG_TQM866M -CONFIG_TQM885D -CONFIG_TQM8xxL -CONFIG_TQM8xxM CONFIG_TRACE CONFIG_TRACE_BUFFER_SIZE CONFIG_TRACE_EARLY @@ -6186,8 +5822,6 @@ CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_BIN_FIXUP CONFIG_USB_BOOTING CONFIG_USB_CABLE_CHECK -CONFIG_USB_CLOCK -CONFIG_USB_CONFIG CONFIG_USB_DEVICE CONFIG_USB_DEV_BASE CONFIG_USB_DEV_PULLUP_GPIO @@ -6241,7 +5875,6 @@ CONFIG_USB_GADGET_GOKU CONFIG_USB_GADGET_IMX CONFIG_USB_GADGET_M66592 CONFIG_USB_GADGET_MASS_STORAGE -CONFIG_USB_GADGET_MPC8272 CONFIG_USB_GADGET_MQ11XX CONFIG_USB_GADGET_MUSBHSFC CONFIG_USB_GADGET_N9604 @@ -6249,7 +5882,6 @@ CONFIG_USB_GADGET_NET2280 CONFIG_USB_GADGET_OMAP CONFIG_USB_GADGET_PXA27X CONFIG_USB_GADGET_PXA2XX -CONFIG_USB_GADGET_S3C2410 CONFIG_USB_GADGET_SA1100 CONFIG_USB_GADGET_SUPERH CONFIG_USB_GADGET_SX2 @@ -6362,7 +5994,6 @@ CONFIG_WATCHDOG_PRESC CONFIG_WATCHDOG_RC CONFIG_WATCHDOG_TIMEOUT CONFIG_WATCHDOG_TIMEOUT_MSECS -CONFIG_WDOG_GPIO_PIN CONFIG_WD_MAX_RATE CONFIG_WD_PERIOD CONFIG_X600 diff --git a/test/README b/test/README index 1142e9c..873a4e1 100644 --- a/test/README +++ b/test/README @@ -46,7 +46,7 @@ tbot Tbot provides a way to execute tests on target hardware. It is intended for trying out both U-Boot and Linux (and potentially other software) on a number of boards automatically. It can be used to create a continuous test -environment. See tools/tbot/README for more information. +environment. See http://www.tbot.tools for more information. Ad-hoc tests diff --git a/test/dm/blk.c b/test/dm/blk.c index 5c5eb82..923e8d9 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -150,3 +150,21 @@ static int dm_test_blk_devnum(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_blk_devnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we can get a block from its parent */ +static int dm_test_blk_get_from_parent(struct unit_test_state *uts) +{ + struct udevice *dev, *blk; + + ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev)); + ut_assertok(blk_get_from_parent(dev, &blk)); + + ut_assertok(uclass_get_device(UCLASS_I2C, 0, &dev)); + ut_asserteq(-ENOTBLK, blk_get_from_parent(dev, &blk)); + + ut_assertok(uclass_get_device(UCLASS_GPIO, 0, &dev)); + ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk)); + + return 0; +} +DM_TEST(dm_test_blk_get_from_parent, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/bus.c b/test/dm/bus.c index 8ba75d4..7006d41 100644 --- a/test/dm/bus.c +++ b/test/dm/bus.c @@ -171,13 +171,16 @@ static int dm_test_bus_children_of_offset(struct unit_test_state *uts) int node; ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + ut_assertnonnull(bus); /* Find a valid child */ node = fdt_path_offset(blob, "/some-bus/c-test@1"); ut_assert(node > 0); ut_assertok(device_find_child_by_of_offset(bus, node, &dev)); + ut_assertnonnull(dev); ut_assert(!(dev->flags & DM_FLAG_ACTIVATED)); ut_assertok(device_get_child_by_of_offset(bus, node, &dev)); + ut_assertnonnull(dev); ut_assert(dev->flags & DM_FLAG_ACTIVATED); return 0; diff --git a/test/dm/pwm.c b/test/dm/pwm.c index f1e38c7..6b2dedf 100644 --- a/test/dm/pwm.c +++ b/test/dm/pwm.c @@ -18,6 +18,7 @@ static int dm_test_pwm_base(struct unit_test_state *uts) struct udevice *dev; ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev)); + ut_assertnonnull(dev); ut_assertok(pwm_set_config(dev, 0, 100, 50)); ut_assertok(pwm_set_enable(dev, 0, true)); ut_assertok(pwm_set_enable(dev, 1, true)); diff --git a/test/dm/wdt.c b/test/dm/wdt.c index 2ecfcea..0116502 100644 --- a/test/dm/wdt.c +++ b/test/dm/wdt.c @@ -20,6 +20,7 @@ static int dm_test_wdt_base(struct unit_test_state *uts) const u64 timeout = 42; ut_assertok(uclass_get_device(UCLASS_WDT, 0, &dev)); + ut_assertnonnull(dev); ut_asserteq(0, state->wdt.counter); ut_asserteq(false, state->wdt.running); diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py index b572538..c8f4208 100644 --- a/test/py/tests/test_hush_if_test.py +++ b/test/py/tests/test_hush_if_test.py @@ -8,6 +8,8 @@ import os import os.path import pytest +pytestmark = pytest.mark.buildconfigspec('hush_parser') + # The list of "if test" conditions to test. subtests = ( # Base if functionality. @@ -109,29 +111,27 @@ def exec_hush_if(u_boot_console, expr, result): response = u_boot_console.run_command(cmd) assert response.strip() == str(result).lower() -@pytest.mark.buildconfigspec('hush_parser') def test_hush_if_test_setup(u_boot_console): """Set up environment variables used during the "if" tests.""" u_boot_console.run_command('setenv ut_var_nonexistent') u_boot_console.run_command('setenv ut_var_exists 1') -@pytest.mark.buildconfigspec('hush_parser') +@pytest.mark.buildconfigspec('cmd_echo') @pytest.mark.parametrize('expr,result', subtests) def test_hush_if_test(u_boot_console, expr, result): """Test a single "if test" condition.""" exec_hush_if(u_boot_console, expr, result) -@pytest.mark.buildconfigspec('hush_parser') def test_hush_if_test_teardown(u_boot_console): """Clean up environment variables used during the "if" tests.""" u_boot_console.run_command('setenv ut_var_exists') -@pytest.mark.buildconfigspec('hush_parser') # We might test this on real filesystems via UMS, DFU, 'save', etc. # Of those, only UMS currently allows file removal though. +@pytest.mark.buildconfigspec('cmd_echo') @pytest.mark.boardspec('sandbox') def test_hush_if_test_host_file_exists(u_boot_console): """Test the "if test -e" shell command.""" diff --git a/tools/Makefile b/tools/Makefile index 2fc4a58..cb1683e 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -60,9 +60,21 @@ hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o # Flattened device tree objects -LIBFDT_OBJS := $(addprefix lib/libfdt/, \ - fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o \ - fdt_region.o fdt_sw.o) +LIBFDT_CSRCS := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c \ + fdt_empty_tree.c fdt_addresses.c fdt_overlay.c \ + fdt_region.c + +# Unfortunately setup.py below cannot handle srctree being ".." which it often +# is. It fails with an error like: +# Fatal error: can't create build/temp.linux-x86_64-2.7/../lib/libfdt/fdt.o: +# No such file or directory +# To fix this, use an absolute path. +libfdt_tree := $(shell readlink -f $(srctree)/lib/libfdt) + +LIBFDT_SRCS := $(addprefix $(libfdt_tree)/, $(LIBFDT_CSRCS)) +LIBFDT_SWIG := $(addprefix $(libfdt_tree)/, pylibfdt/libfdt.i) +LIBFDT_OBJS := $(addprefix lib/libfdt/, $(patsubst %.c, %.o, $(LIBFDT_CSRCS))) + RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \ rsa-sign.o rsa-verify.o rsa-checksum.o \ rsa-mod-exp.o) @@ -112,22 +124,22 @@ mkimage-objs := $(dumpimage-mkimage-objs) mkimage.o fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o -# Build a libfdt Python module if swig is available -# Use 'sudo apt-get install swig libpython-dev' to enable this -hostprogs-y += \ - $(if $(shell which swig 2> /dev/null),_libfdt.so) -_libfdt.so-sharedobjs += $(LIBFDT_OBJS) -libfdt: - -tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c - LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= ${PYTHON} $(srctree)/lib/libfdt/setup.py \ - "$(_hostc_flags)" $^ - mv _libfdt.so $@ - -tools/libfdt_wrap.c: $(srctree)/lib/libfdt/libfdt.swig - swig -python -o $@ $< - -# TODO(sjg@chromium.org): Is this correct on Mac OS? +# Unfortunately setup.py (or actually the Python distutil implementation) +# puts files into the same directory as the .i file. We cannot touch the source +# directory, so we copy the .i file into the tools/ build subdirectory before +# calling setup. This directory is safe to write to. This ensures that we get +# all three files in $(obj)/tools: _libfdt.so, libfdt.py and libfdt_wrap.c +# The latter is a temporary file which we could actually remove. +tools/_libfdt.so: $(LIBFDT_SRCS) $(LIBFDT_SWIG) + cp $(LIBFDT_SWIG) tools/. + unset CC; \ + unset CROSS_COMPILE; \ + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= VERSION="u-boot-$(UBOOTVERSION)" \ + CPPFLAGS="$(_hostc_flags)" OBJDIR=tools \ + SOURCES="$(LIBFDT_SRCS) tools/libfdt.i" \ + SWIG_OPTS="-I$(srctree)/lib/libfdt -I$(srctree)/lib" \ + $(libfdt_tree)/pylibfdt/setup.py --quiet build_ext \ + --build-lib tools ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register @@ -216,6 +228,10 @@ clean-dirs := lib common always := $(hostprogs-y) +# Build a libfdt Python module if swig is available +# Use 'sudo apt-get install swig libpython-dev' to enable this +always += $(if $(shell which swig 2> /dev/null),_libfdt.so) + # Generated LCD/video logo LOGO_H = $(objtree)/include/bmp_logo.h LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h diff --git a/tools/binman/binman.py b/tools/binman/binman.py index 857d698..95d3a048 100755 --- a/tools/binman/binman.py +++ b/tools/binman/binman.py @@ -21,6 +21,9 @@ sys.path.append(os.path.join(our_path, '../patman')) sys.path.append(os.path.join(our_path, '../dtoc')) sys.path.append(os.path.join(our_path, '../')) +# Bring in the libfdt module +sys.path.append('tools') + # Also allow entry-type modules to be brought in from the etype directory. sys.path.append(os.path.join(our_path, 'etype')) diff --git a/tools/binman/control.py b/tools/binman/control.py index e909678..e9d48df 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -12,7 +12,7 @@ import sys import tools import command -import fdt_select +import fdt import fdt_util from image import Image import tout @@ -40,15 +40,15 @@ def _ReadImageDesc(binman_node): images['image'] = Image('image', binman_node) return images -def _FindBinmanNode(fdt): +def _FindBinmanNode(dtb): """Find the 'binman' node in the device tree Args: - fdt: Fdt object to scan + dtb: Fdt object to scan Returns: Node object of /binman node, or None if not found """ - for node in fdt.GetRoot().subnodes: + for node in dtb.GetRoot().subnodes: if node.name == 'binman': return node return None @@ -92,8 +92,8 @@ def Binman(options, args): try: tools.SetInputDirs(options.indir) tools.PrepareOutputDir(options.outdir, options.preserve) - fdt = fdt_select.FdtScan(dtb_fname) - node = _FindBinmanNode(fdt) + dtb = fdt.FdtScan(dtb_fname) + node = _FindBinmanNode(dtb) if not node: raise ValueError("Device tree '%s' does not have a 'binman' " "node" % dtb_fname) diff --git a/tools/binman/etype/u_boot_dtb_with_ucode.py b/tools/binman/etype/u_boot_dtb_with_ucode.py index fc02c67..a384a75 100644 --- a/tools/binman/etype/u_boot_dtb_with_ucode.py +++ b/tools/binman/etype/u_boot_dtb_with_ucode.py @@ -6,7 +6,7 @@ # Entry-type module for U-Boot device tree with the microcode removed # -import fdt_select +import fdt from entry import Entry from blob import Entry_blob import tools @@ -44,9 +44,8 @@ class Entry_u_boot_dtb_with_ucode(Entry_blob): fd.write(self.data) # Remove the microcode - fdt = fdt_select.FdtScan(fname) - fdt.Scan() - ucode = fdt.GetNode('/microcode') + dtb = fdt.FdtScan(fname) + ucode = dtb.GetNode('/microcode') if not ucode: raise self.Raise("No /microcode node found in '%s'" % fname) @@ -57,20 +56,15 @@ class Entry_u_boot_dtb_with_ucode(Entry_blob): data_prop = node.props.get('data') if data_prop: self.ucode_data += ''.join(data_prop.bytes) - if not self.collate: - poffset = data_prop.GetOffset() - if poffset is None: - # We cannot obtain a property offset. Collate instead. - self.collate = True - else: - # Find the offset in the device tree of the ucode data - self.ucode_offset = poffset + 12 - self.ucode_size = len(data_prop.bytes) if self.collate: prop = node.DeleteProp('data') + else: + # Find the offset in the device tree of the ucode data + self.ucode_offset = data_prop.GetOffset() + 12 + self.ucode_size = len(data_prop.bytes) if self.collate: - fdt.Pack() - fdt.Flush() + dtb.Pack() + dtb.Flush() # Make this file the contents of this entry self._pathname = fname diff --git a/tools/binman/fdt_test.py b/tools/binman/fdt_test.py index 1d9494e..249a9ea 100644 --- a/tools/binman/fdt_test.py +++ b/tools/binman/fdt_test.py @@ -11,7 +11,8 @@ import sys import tempfile import unittest -from fdt_select import FdtScan +import fdt +from fdt import FdtScan import fdt_util import tools @@ -28,21 +29,56 @@ class TestFdt(unittest.TestCase): def GetCompiled(self, fname): return fdt_util.EnsureCompiled(self.TestFile(fname)) - def _DeleteProp(self, fdt): - node = fdt.GetNode('/microcode/update@0') + def _DeleteProp(self, dt): + node = dt.GetNode('/microcode/update@0') node.DeleteProp('data') def testFdtNormal(self): fname = self.GetCompiled('34_x86_ucode.dts') - fdt = FdtScan(fname) - self._DeleteProp(fdt) + dt = FdtScan(fname) + self._DeleteProp(dt) - def testFdtFallback(self): - fname = self.GetCompiled('34_x86_ucode.dts') - fdt = FdtScan(fname, True) - fdt.GetProp('/microcode/update@0', 'data') - self.assertEqual('fred', - fdt.GetProp('/microcode/update@0', 'none', default='fred')) - self.assertEqual('12345678 12345679', - fdt.GetProp('/microcode/update@0', 'data', typespec='x')) - self._DeleteProp(fdt) + def testFdtNormalProp(self): + fname = self.GetCompiled('45_prop_test.dts') + dt = FdtScan(fname) + node = dt.GetNode('/binman/intel-me') + self.assertEquals('intel-me', node.name) + val = fdt_util.GetString(node, 'filename') + self.assertEquals(str, type(val)) + self.assertEquals('me.bin', val) + + prop = node.props['intval'] + self.assertEquals(fdt.TYPE_INT, prop.type) + self.assertEquals(3, fdt_util.GetInt(node, 'intval')) + + prop = node.props['intarray'] + self.assertEquals(fdt.TYPE_INT, prop.type) + self.assertEquals(list, type(prop.value)) + self.assertEquals(2, len(prop.value)) + self.assertEquals([5, 6], + [fdt_util.fdt32_to_cpu(val) for val in prop.value]) + + prop = node.props['byteval'] + self.assertEquals(fdt.TYPE_BYTE, prop.type) + self.assertEquals(chr(8), prop.value) + + prop = node.props['bytearray'] + self.assertEquals(fdt.TYPE_BYTE, prop.type) + self.assertEquals(list, type(prop.value)) + self.assertEquals(str, type(prop.value[0])) + self.assertEquals(3, len(prop.value)) + self.assertEquals([chr(1), '#', '4'], prop.value) + + prop = node.props['longbytearray'] + self.assertEquals(fdt.TYPE_INT, prop.type) + self.assertEquals(0x090a0b0c, fdt_util.GetInt(node, 'longbytearray')) + + prop = node.props['stringval'] + self.assertEquals(fdt.TYPE_STRING, prop.type) + self.assertEquals('message2', fdt_util.GetString(node, 'stringval')) + + prop = node.props['stringarray'] + self.assertEquals(fdt.TYPE_STRING, prop.type) + self.assertEquals(list, type(prop.value)) + self.assertEquals(3, len(prop.value)) + self.assertEquals(['another', 'multi-word', 'message'], prop.value) diff --git a/tools/binman/func_test.py b/tools/binman/func_test.py index 740fa9e..8b4db41 100644 --- a/tools/binman/func_test.py +++ b/tools/binman/func_test.py @@ -21,7 +21,7 @@ import cmdline import command import control import entry -import fdt_select +import fdt import fdt_util import tools import tout @@ -658,8 +658,8 @@ class TestFunctional(unittest.TestCase): fname = tools.GetOutputFilename('test.dtb') with open(fname, 'wb') as fd: fd.write(second) - fdt = fdt_select.FdtScan(fname) - ucode = fdt.GetNode('/microcode') + dtb = fdt.FdtScan(fname) + ucode = dtb.GetNode('/microcode') self.assertTrue(ucode) for node in ucode.subnodes: self.assertFalse(node.props.get('data')) @@ -683,7 +683,7 @@ class TestFunctional(unittest.TestCase): self.assertEqual('nodtb with microcode' + pos_and_size + ' somewhere in here', first) - def _RunPackUbootSingleMicrocode(self, collate): + def _RunPackUbootSingleMicrocode(self): """Test that x86 microcode can be handled correctly We expect to see the following in the image, in order: @@ -695,8 +695,6 @@ class TestFunctional(unittest.TestCase): # We need the libfdt library to run this test since only that allows # finding the offset of a property. This is required by # Entry_u_boot_dtb_with_ucode.ObtainContents(). - if not fdt_select.have_libfdt: - return data = self._DoReadFile('35_x86_single_ucode.dts', True) second = data[len(U_BOOT_NODTB_DATA):] @@ -705,34 +703,22 @@ class TestFunctional(unittest.TestCase): third = second[fdt_len:] second = second[:fdt_len] - if not collate: - ucode_data = struct.pack('>2L', 0x12345678, 0x12345679) - self.assertIn(ucode_data, second) - ucode_pos = second.find(ucode_data) + len(U_BOOT_NODTB_DATA) + ucode_data = struct.pack('>2L', 0x12345678, 0x12345679) + self.assertIn(ucode_data, second) + ucode_pos = second.find(ucode_data) + len(U_BOOT_NODTB_DATA) - # Check that the microcode pointer was inserted. It should match the - # expected position and size - pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos, - len(ucode_data)) - first = data[:len(U_BOOT_NODTB_DATA)] - self.assertEqual('nodtb with microcode' + pos_and_size + - ' somewhere in here', first) + # Check that the microcode pointer was inserted. It should match the + # expected position and size + pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos, + len(ucode_data)) + first = data[:len(U_BOOT_NODTB_DATA)] + self.assertEqual('nodtb with microcode' + pos_and_size + + ' somewhere in here', first) def testPackUbootSingleMicrocode(self): """Test that x86 microcode can be handled correctly with fdt_normal. """ - self._RunPackUbootSingleMicrocode(False) - - def testPackUbootSingleMicrocodeFallback(self): - """Test that x86 microcode can be handled correctly with fdt_fallback. - - This only supports collating the microcode. - """ - try: - old_val = fdt_select.UseFallback(True) - self._RunPackUbootSingleMicrocode(True) - finally: - fdt_select.UseFallback(old_val) + self._RunPackUbootSingleMicrocode() def testUBootImg(self): """Test that u-boot.img can be put in a file""" @@ -763,14 +749,12 @@ class TestFunctional(unittest.TestCase): def testMicrocodeWithoutPtrInElf(self): """Test that a U-Boot binary without the microcode symbol is detected""" # ELF file without a '_dt_ucode_base_size' symbol - if not fdt_select.have_libfdt: - return try: with open(self.TestFile('u_boot_no_ucode_ptr')) as fd: TestFunctional._MakeInputFile('u-boot', fd.read()) with self.assertRaises(ValueError) as e: - self._RunPackUbootSingleMicrocode(False) + self._RunPackUbootSingleMicrocode() self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Cannot locate " "_dt_ucode_base_size symbol in u-boot", str(e.exception)) diff --git a/tools/binman/test/45_prop_test.dts b/tools/binman/test/45_prop_test.dts new file mode 100644 index 0000000..d22e460 --- /dev/null +++ b/tools/binman/test/45_prop_test.dts @@ -0,0 +1,23 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + sort-by-pos; + end-at-4gb; + size = <16>; + intel-me { + filename = "me.bin"; + pos-unset; + intval = <3>; + intarray = <5 6>; + byteval = [08]; + bytearray = [01 23 34]; + longbytearray = [09 0a 0b 0c]; + stringval = "message2"; + stringarray = "another", "multi-word", "message"; + }; + }; +}; diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index b0ea57e..acb0810 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -847,7 +847,7 @@ class Builder: delta.reverse() args = [add, -remove, grow, -shrink, up, -down, up - down] - if max(args) == 0: + if max(args) == 0 and min(args) == 0: return args = [self.ColourNum(x) for x in args] indent = ' ' * 15 diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index acaf500..9e8ca80 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -280,13 +280,15 @@ class BuilderThread(threading.Thread): outfile = os.path.join(build_dir, 'log') with open(outfile, 'w') as fd: if result.stdout: - fd.write(result.stdout.encode('latin-1', 'ignore')) + # We don't want unicode characters in log files + fd.write(result.stdout.decode('UTF-8').encode('ASCII', 'replace')) errfile = self.builder.GetErrFile(result.commit_upto, result.brd.target) if result.stderr: with open(errfile, 'w') as fd: - fd.write(result.stderr.encode('latin-1', 'ignore')) + # We don't want unicode characters in log files + fd.write(result.stderr.decode('UTF-8').encode('ASCII', 'replace')) elif os.path.exists(errfile): os.remove(errfile) diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py index d439e17..bc32f61 100644 --- a/tools/buildman/func_test.py +++ b/tools/buildman/func_test.py @@ -39,7 +39,6 @@ boards = [ ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board0', ''], ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 2', 'board1', ''], ['Active', 'powerpc', 'powerpc', '', 'Tester', 'PowerPC board 1', 'board2', ''], - ['Active', 'powerpc', 'mpc5xx', '', 'Tester', 'PowerPC board 2', 'board3', ''], ['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''], ] diff --git a/tools/buildman/test.py b/tools/buildman/test.py index ed2a3a8..53ebc37 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -89,7 +89,6 @@ boards = [ ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 1', 'board0', ''], ['Active', 'arm', 'armv7', '', 'Tester', 'ARM Board 2', 'board1', ''], ['Active', 'powerpc', 'powerpc', '', 'Tester', 'PowerPC board 1', 'board2', ''], - ['Active', 'powerpc', 'mpc5xx', '', 'Tester', 'PowerPC board 2', 'board3', ''], ['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''], ] diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 5cf97ac..2076323 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -144,7 +144,9 @@ class Toolchain: """Returns an environment for using the toolchain. Thie takes the current environment and adds CROSS_COMPILE so that - the tool chain will operate correctly. + the tool chain will operate correctly. This also disables localized + output and possibly unicode encoded output of all build tools by + adding LC_ALL=C. Args: full_path: Return the full path in CROSS_COMPILE and don't set @@ -159,6 +161,8 @@ class Toolchain: env['CROSS_COMPILE'] = wrapper + self.cross env['PATH'] = self.path + ':' + env['PATH'] + env['LC_ALL'] = 'C' + return env diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 2e0b9c0..08e35f1 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -17,7 +17,6 @@ our_path = os.path.dirname(os.path.realpath(__file__)) sys.path.append(os.path.join(our_path, '../patman')) import fdt -import fdt_select import fdt_util # When we see these properties we ignore them - i.e. do not create a structure member @@ -170,7 +169,7 @@ class DtbPlatdata: Once this is done, self.fdt.GetRoot() can be called to obtain the device tree root node, and progress from there. """ - self.fdt = fdt_select.FdtScan(self._dtb_fname) + self.fdt = fdt.FdtScan(self._dtb_fname) def ScanNode(self, root): for node in root.subnodes: diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py index 816fdbe..63a32ea 100644 --- a/tools/dtoc/fdt.py +++ b/tools/dtoc/fdt.py @@ -10,12 +10,15 @@ import struct import sys import fdt_util +import libfdt # This deals with a device tree, presenting it as an assortment of Node and # Prop objects, representing nodes and properties, respectively. This file -# contains the base classes and defines the high-level API. Most of the -# implementation is in the FdtFallback and FdtNormal subclasses. See -# fdt_select.py for how to create an Fdt object. +# contains the base classes and defines the high-level API. You can use +# FdtScan() as a convenience function to create and scan an Fdt. + +# This implementation uses a libfdt Python library to access the device tree, +# so it is fairly efficient. # A list of types we support (TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL) = range(4) @@ -25,7 +28,7 @@ def CheckErr(errnum, msg): raise ValueError('Error %d: %s: %s' % (errnum, libfdt.fdt_strerror(errnum), msg)) -class PropBase: +class Prop: """A device tree property Properties: @@ -34,11 +37,17 @@ class PropBase: bytes type: Value type """ - def __init__(self, node, offset, name): + def __init__(self, node, offset, name, bytes): self._node = node self._offset = offset self.name = name self.value = None + self.bytes = str(bytes) + if not bytes: + self.type = TYPE_BOOL + self.value = True + return + self.type, self.value = self.BytesToValue(bytes) def GetPhandle(self): """Get a (single) phandle value from a property @@ -96,6 +105,7 @@ class PropBase: TYPE_INT: a byte-swapped integer stored as a 4-byte string TYPE_BYTE: a byte stored as a single-byte string """ + bytes = str(bytes) size = len(bytes) strings = bytes.split('\0') is_string = True @@ -147,15 +157,12 @@ class PropBase: def GetOffset(self): """Get the offset of a property - This can be implemented by subclasses. - Returns: - The offset of the property (struct fdt_property) within the - file, or None if not known. + The offset of the property (struct fdt_property) within the file """ - return None + return self._node._fdt.GetStructOffset(self._offset) -class NodeBase: +class Node: """A device tree node Properties: @@ -188,25 +195,65 @@ class NodeBase: return subnode return None + def Offset(self): + """Returns the offset of a node, after checking the cache + + This should be used instead of self._offset directly, to ensure that + the cache does not contain invalid offsets. + """ + self._fdt.CheckCache() + return self._offset + def Scan(self): - """Scan the subnodes of a node + """Scan a node's properties and subnodes - This should be implemented by subclasses + This fills in the props and subnodes properties, recursively + searching into subnodes so that the entire tree is built. """ - raise NotImplementedError() + self.props = self._fdt.GetProps(self) + + offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.Offset()) + while offset >= 0: + sep = '' if self.path[-1] == '/' else '/' + name = self._fdt._fdt_obj.get_name(offset) + path = self.path + sep + name + node = Node(self._fdt, offset, name, path) + self.subnodes.append(node) + + node.Scan() + offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset) + + def Refresh(self, my_offset): + """Fix up the _offset for each node, recursively + + Note: This does not take account of property offsets - these will not + be updated. + """ + if self._offset != my_offset: + #print '%s: %d -> %d\n' % (self.path, self._offset, my_offset) + self._offset = my_offset + offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self._offset) + for subnode in self.subnodes: + subnode.Refresh(offset) + offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset) def DeleteProp(self, prop_name): """Delete a property of a node - This should be implemented by subclasses + The property is deleted and the offset cache is invalidated. Args: prop_name: Name of the property to delete + Raises: + ValueError if the property does not exist """ - raise NotImplementedError() + CheckErr(libfdt.fdt_delprop(self._fdt.GetFdt(), self.Offset(), prop_name), + "Node '%s': delete property: '%s'" % (self.path, prop_name)) + del self.props[prop_name] + self._fdt.Invalidate() class Fdt: - """Provides simple access to a flat device tree blob. + """Provides simple access to a flat device tree blob using libfdts. Properties: fname: Filename of fdt @@ -214,6 +261,13 @@ class Fdt: """ def __init__(self, fname): self._fname = fname + self._cached_offsets = False + if self._fname: + self._fname = fdt_util.EnsureCompiled(self._fname) + + with open(self._fname) as fd: + self._fdt = bytearray(fd.read()) + self._fdt_obj = libfdt.Fdt(self._fdt) def Scan(self, root='/'): """Scan a device tree, building up a tree of Node objects @@ -255,15 +309,100 @@ class Fdt: """Flush device tree changes back to the file If the device tree has changed in memory, write it back to the file. - Subclasses can implement this if needed. """ - pass + with open(self._fname, 'wb') as fd: + fd.write(self._fdt) def Pack(self): """Pack the device tree down to its minimum size When nodes and properties shrink or are deleted, wasted space can - build up in the device tree binary. Subclasses can implement this - to remove that spare space. + build up in the device tree binary. """ - pass + CheckErr(libfdt.fdt_pack(self._fdt), 'pack') + fdt_len = libfdt.fdt_totalsize(self._fdt) + del self._fdt[fdt_len:] + + def GetFdt(self): + """Get the contents of the FDT + + Returns: + The FDT contents as a string of bytes + """ + return self._fdt + + def CheckErr(errnum, msg): + if errnum: + raise ValueError('Error %d: %s: %s' % + (errnum, libfdt.fdt_strerror(errnum), msg)) + + + def GetProps(self, node): + """Get all properties from a node. + + Args: + node: Full path to node name to look in. + + Returns: + A dictionary containing all the properties, indexed by node name. + The entries are Prop objects. + + Raises: + ValueError: if the node does not exist. + """ + props_dict = {} + poffset = libfdt.fdt_first_property_offset(self._fdt, node._offset) + while poffset >= 0: + p = self._fdt_obj.get_property_by_offset(poffset) + prop = Prop(node, poffset, p.name, p.value) + props_dict[prop.name] = prop + + poffset = libfdt.fdt_next_property_offset(self._fdt, poffset) + return props_dict + + def Invalidate(self): + """Mark our offset cache as invalid""" + self._cached_offsets = False + + def CheckCache(self): + """Refresh the offset cache if needed""" + if self._cached_offsets: + return + self.Refresh() + self._cached_offsets = True + + def Refresh(self): + """Refresh the offset cache""" + self._root.Refresh(0) + + def GetStructOffset(self, offset): + """Get the file offset of a given struct offset + + Args: + offset: Offset within the 'struct' region of the device tree + Returns: + Position of @offset within the device tree binary + """ + return libfdt.fdt_off_dt_struct(self._fdt) + offset + + @classmethod + def Node(self, fdt, offset, name, path): + """Create a new node + + This is used by Fdt.Scan() to create a new node using the correct + class. + + Args: + fdt: Fdt object + offset: Offset of node + name: Node name + path: Full path to node + """ + node = Node(fdt, offset, name, path) + return node + +def FdtScan(fname): + """Returns a new Fdt object from the implementation we are using""" + dtb = Fdt(fname) + dtb.Scan() + return dtb diff --git a/tools/dtoc/fdt_fallback.py b/tools/dtoc/fdt_fallback.py deleted file mode 100644 index 23e2679..0000000 --- a/tools/dtoc/fdt_fallback.py +++ /dev/null @@ -1,181 +0,0 @@ -#!/usr/bin/python -# -# Copyright (C) 2016 Google, Inc -# Written by Simon Glass -# -# SPDX-License-Identifier: GPL-2.0+ -# - -import command -import fdt -from fdt import Fdt, NodeBase, PropBase -import fdt_util -import sys - -# This deals with a device tree, presenting it as a list of Node and Prop -# objects, representing nodes and properties, respectively. -# -# This implementation uses the fdtget tool to access the device tree, so it -# is not very efficient for larger trees. The tool is called once for each -# node and property in the tree. - -class Prop(PropBase): - """A device tree property - - Properties: - name: Property name (as per the device tree) - value: Property value as a string of bytes, or a list of strings of - bytes - type: Value type - """ - def __init__(self, node, name, byte_list_str): - PropBase.__init__(self, node, 0, name) - if not byte_list_str.strip(): - self.type = fdt.TYPE_BOOL - return - self.bytes = [chr(int(byte, 16)) - for byte in byte_list_str.strip().split(' ')] - self.type, self.value = self.BytesToValue(''.join(self.bytes)) - - -class Node(NodeBase): - """A device tree node - - Properties: - name: Device tree node tname - path: Full path to node, along with the node name itself - _fdt: Device tree object - subnodes: A list of subnodes for this node, each a Node object - props: A dict of properties for this node, each a Prop object. - Keyed by property name - """ - def __init__(self, fdt, offset, name, path): - NodeBase.__init__(self, fdt, offset, name, path) - - def Scan(self): - """Scan a node's properties and subnodes - - This fills in the props and subnodes properties, recursively - searching into subnodes so that the entire tree is built. - """ - for name, byte_list_str in self._fdt.GetProps(self.path).items(): - prop = Prop(self, name, byte_list_str) - self.props[name] = prop - - for name in self._fdt.GetSubNodes(self.path): - sep = '' if self.path[-1] == '/' else '/' - path = self.path + sep + name - node = Node(self._fdt, 0, name, path) - self.subnodes.append(node) - - node.Scan() - - def DeleteProp(self, prop_name): - """Delete a property of a node - - The property is deleted using fdtput. - - Args: - prop_name: Name of the property to delete - Raises: - CommandError if the property does not exist - """ - args = [self._fdt._fname, '-d', self.path, prop_name] - command.Output('fdtput', *args) - del self.props[prop_name] - -class FdtFallback(Fdt): - """Provides simple access to a flat device tree blob using fdtget/fdtput - - Properties: - See superclass - """ - - def __init__(self, fname): - Fdt.__init__(self, fname) - if self._fname: - self._fname = fdt_util.EnsureCompiled(self._fname) - - def GetSubNodes(self, node): - """Returns a list of sub-nodes of a given node - - Args: - node: Node name to return children from - - Returns: - List of children in the node (each a string node name) - - Raises: - CmdError: if the node does not exist. - """ - out = command.Output('fdtget', self._fname, '-l', node) - return out.strip().splitlines() - - def GetProps(self, node): - """Get all properties from a node - - Args: - node: full path to node name to look in - - Returns: - A dictionary containing all the properties, indexed by node name. - The entries are simply strings - no decoding of lists or numbers - is done. - - Raises: - CmdError: if the node does not exist. - """ - out = command.Output('fdtget', self._fname, node, '-p') - props = out.strip().splitlines() - props_dict = {} - for prop in props: - name = prop - props_dict[prop] = self.GetProp(node, name) - return props_dict - - def GetProp(self, node, prop, default=None, typespec=None): - """Get a property from a device tree. - - This looks up the given node and property, and returns the value as a - string, - - If the node or property does not exist, this will return the default - value. - - Args: - node: Full path to node to look up. - prop: Property name to look up. - default: Default value to return if nothing is present in the fdt, - or None to raise in this case. This will be converted to a - string. - typespec: Type character to use (None for default, 's' for string) - - Returns: - string containing the property value. - - Raises: - CmdError: if the property does not exist and no default is provided. - """ - args = [self._fname, node, prop, '-t', 'bx'] - if default is not None: - args += ['-d', str(default)] - if typespec is not None: - args += ['-t', typespec] - out = command.Output('fdtget', *args) - return out.strip() - - @classmethod - def Node(self, fdt, offset, name, path): - """Create a new node - - This is used by Fdt.Scan() to create a new node using the correct - class. - - Args: - fdt: Fdt object - offset: Offset of node - name: Node name - path: Full path to node - """ - node = Node(fdt, offset, name, path) - return node diff --git a/tools/dtoc/fdt_normal.py b/tools/dtoc/fdt_normal.py deleted file mode 100644 index cce5c06..0000000 --- a/tools/dtoc/fdt_normal.py +++ /dev/null @@ -1,225 +0,0 @@ -#!/usr/bin/python -# -# Copyright (C) 2016 Google, Inc -# Written by Simon Glass -# -# SPDX-License-Identifier: GPL-2.0+ -# - -import struct -import sys - -import fdt -from fdt import Fdt, NodeBase, PropBase -import fdt_util -import libfdt - -# This deals with a device tree, presenting it as a list of Node and Prop -# objects, representing nodes and properties, respectively. -# -# This implementation uses a libfdt Python library to access the device tree, -# so it is fairly efficient. - -def CheckErr(errnum, msg): - if errnum: - raise ValueError('Error %d: %s: %s' % - (errnum, libfdt.fdt_strerror(errnum), msg)) - -class Prop(PropBase): - """A device tree property - - Properties: - name: Property name (as per the device tree) - value: Property value as a string of bytes, or a list of strings of - bytes - type: Value type - """ - def __init__(self, node, offset, name, bytes): - PropBase.__init__(self, node, offset, name) - self.bytes = bytes - if not bytes: - self.type = fdt.TYPE_BOOL - self.value = True - return - self.type, self.value = self.BytesToValue(bytes) - - def GetOffset(self): - """Get the offset of a property - - Returns: - The offset of the property (struct fdt_property) within the file - """ - return self._node._fdt.GetStructOffset(self._offset) - -class Node(NodeBase): - """A device tree node - - Properties: - offset: Integer offset in the device tree - name: Device tree node tname - path: Full path to node, along with the node name itself - _fdt: Device tree object - subnodes: A list of subnodes for this node, each a Node object - props: A dict of properties for this node, each a Prop object. - Keyed by property name - """ - def __init__(self, fdt, offset, name, path): - NodeBase.__init__(self, fdt, offset, name, path) - - def Offset(self): - """Returns the offset of a node, after checking the cache - - This should be used instead of self._offset directly, to ensure that - the cache does not contain invalid offsets. - """ - self._fdt.CheckCache() - return self._offset - - def Scan(self): - """Scan a node's properties and subnodes - - This fills in the props and subnodes properties, recursively - searching into subnodes so that the entire tree is built. - """ - self.props = self._fdt.GetProps(self) - - offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.Offset()) - while offset >= 0: - sep = '' if self.path[-1] == '/' else '/' - name = libfdt.Name(self._fdt.GetFdt(), offset) - path = self.path + sep + name - node = Node(self._fdt, offset, name, path) - self.subnodes.append(node) - - node.Scan() - offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset) - - def Refresh(self, my_offset): - """Fix up the _offset for each node, recursively - - Note: This does not take account of property offsets - these will not - be updated. - """ - if self._offset != my_offset: - #print '%s: %d -> %d\n' % (self.path, self._offset, my_offset) - self._offset = my_offset - offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self._offset) - for subnode in self.subnodes: - subnode.Refresh(offset) - offset = libfdt.fdt_next_subnode(self._fdt.GetFdt(), offset) - - def DeleteProp(self, prop_name): - """Delete a property of a node - - The property is deleted and the offset cache is invalidated. - - Args: - prop_name: Name of the property to delete - Raises: - ValueError if the property does not exist - """ - CheckErr(libfdt.fdt_delprop(self._fdt.GetFdt(), self.Offset(), prop_name), - "Node '%s': delete property: '%s'" % (self.path, prop_name)) - del self.props[prop_name] - self._fdt.Invalidate() - -class FdtNormal(Fdt): - """Provides simple access to a flat device tree blob using libfdt. - - Properties: - _fdt: Device tree contents (bytearray) - _cached_offsets: True if all the nodes have a valid _offset property, - False if something has changed to invalidate the offsets - """ - def __init__(self, fname): - Fdt.__init__(self, fname) - self._cached_offsets = False - if self._fname: - self._fname = fdt_util.EnsureCompiled(self._fname) - - with open(self._fname) as fd: - self._fdt = bytearray(fd.read()) - - def GetFdt(self): - """Get the contents of the FDT - - Returns: - The FDT contents as a string of bytes - """ - return self._fdt - - def Flush(self): - """Flush device tree changes back to the file""" - with open(self._fname, 'wb') as fd: - fd.write(self._fdt) - - def Pack(self): - """Pack the device tree down to its minimum size""" - CheckErr(libfdt.fdt_pack(self._fdt), 'pack') - fdt_len = libfdt.fdt_totalsize(self._fdt) - del self._fdt[fdt_len:] - - def GetProps(self, node): - """Get all properties from a node. - - Args: - node: Full path to node name to look in. - - Returns: - A dictionary containing all the properties, indexed by node name. - The entries are Prop objects. - - Raises: - ValueError: if the node does not exist. - """ - props_dict = {} - poffset = libfdt.fdt_first_property_offset(self._fdt, node._offset) - while poffset >= 0: - dprop, plen = libfdt.fdt_get_property_by_offset(self._fdt, poffset) - prop = Prop(node, poffset, libfdt.String(self._fdt, dprop.nameoff), - libfdt.Data(dprop)) - props_dict[prop.name] = prop - - poffset = libfdt.fdt_next_property_offset(self._fdt, poffset) - return props_dict - - def Invalidate(self): - """Mark our offset cache as invalid""" - self._cached_offsets = False - - def CheckCache(self): - """Refresh the offset cache if needed""" - if self._cached_offsets: - return - self.Refresh() - self._cached_offsets = True - - def Refresh(self): - """Refresh the offset cache""" - self._root.Refresh(0) - - def GetStructOffset(self, offset): - """Get the file offset of a given struct offset - - Args: - offset: Offset within the 'struct' region of the device tree - Returns: - Position of @offset within the device tree binary - """ - return libfdt.fdt_off_dt_struct(self._fdt) + offset - - @classmethod - def Node(self, fdt, offset, name, path): - """Create a new node - - This is used by Fdt.Scan() to create a new node using the correct - class. - - Args: - fdt: Fdt object - offset: Offset of node - name: Node name - path: Full path to node - """ - node = Node(fdt, offset, name, path) - return node diff --git a/tools/dtoc/fdt_select.py b/tools/dtoc/fdt_select.py deleted file mode 100644 index ea78c52..0000000 --- a/tools/dtoc/fdt_select.py +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/python -# -# Copyright (C) 2016 Google, Inc -# Written by Simon Glass -# -# SPDX-License-Identifier: GPL-2.0+ -# - -import fdt_fallback - -# Bring in either the normal fdt library (which relies on libfdt) or the -# fallback one (which uses fdtget and is slower). Both provide the same -# interface for this file to use. -try: - import fdt_normal - have_libfdt = True -except ImportError: - have_libfdt = False - -force_fallback = False - -def FdtScan(fname, _force_fallback=False): - """Returns a new Fdt object from the implementation we are using""" - if have_libfdt and not force_fallback and not _force_fallback: - dtb = fdt_normal.FdtNormal(fname) - else: - dtb = fdt_fallback.FdtFallback(fname) - dtb.Scan() - return dtb - -def UseFallback(fallback): - global force_fallback - - old_val = force_fallback - force_fallback = fallback - return old_val diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index e373c43..f51f5f1 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -522,18 +522,21 @@ static int check_type_include(void *priv, int type, const char *data, int size) * return 1 at the first match. For exclusive conditions, we must * check that there are no matches. */ - for (val = disp->value_head; val; val = val->next) { - if (!(type & val->type)) - continue; - match = fdt_stringlist_contains(data, size, val->string); - debug(" - val->type=%x, str='%s', match=%d\n", - val->type, val->string, match); - if (match && val->include) { - debug(" - match inc %s\n", val->string); - return 1; + if (data) { + for (val = disp->value_head; val; val = val->next) { + if (!(type & val->type)) + continue; + match = fdt_stringlist_contains(data, size, + val->string); + debug(" - val->type=%x, str='%s', match=%d\n", + val->type, val->string, match); + if (match && val->include) { + debug(" - match inc %s\n", val->string); + return 1; + } + if (match) + none_match &= ~val->type; } - if (match) - none_match &= ~val->type; } /* diff --git a/tools/img2srec.c b/tools/img2srec.c index ec76964..75efd76 100644 --- a/tools/img2srec.c +++ b/tools/img2srec.c @@ -112,7 +112,7 @@ static char* ExtractDecimal (uint32_t* value, char* getPtr) static void ExtractNumber (uint32_t* value, char* getPtr) { - bool neg = false;; + bool neg = false; while (*getPtr == ' ') getPtr++; if (*getPtr == '-') { diff --git a/tools/kwbimage.c b/tools/kwbimage.c index edef560..5830549 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -24,7 +24,7 @@ #include #include -#if OPENSSL_VERSION_NUMBER < 0x10100000L +#if OPENSSL_VERSION_NUMBER < 0x10100000L || defined(LIBRESSL_VERSION_NUMBER) static void RSA_get0_key(const RSA *r, const BIGNUM **n, const BIGNUM **e, const BIGNUM **d) { diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py index 7c76014..ebd4300 100644 --- a/tools/patman/cros_subprocess.py +++ b/tools/patman/cros_subprocess.py @@ -190,8 +190,6 @@ class Popen(subprocess.Popen): # We will get an error on read if the pty is closed try: data = os.read(self.stdout.fileno(), 1024) - if isinstance(data, bytes): - data = data.decode('utf-8') except OSError: pass if data == "": @@ -207,8 +205,6 @@ class Popen(subprocess.Popen): # We will get an error on read if the pty is closed try: data = os.read(self.stderr.fileno(), 1024) - if isinstance(data, bytes): - data = data.decode('utf-8') except OSError: pass if data == "": diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py new file mode 100644 index 0000000..2c0da84 --- /dev/null +++ b/tools/patman/func_test.py @@ -0,0 +1,242 @@ +# -*- coding: utf-8 -*- +# +# Copyright 2017 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +import contextlib +import os +import re +import shutil +import sys +import tempfile +import unittest + +import gitutil +import patchstream +import settings + + +@contextlib.contextmanager +def capture(): + import sys + from cStringIO import StringIO + oldout,olderr = sys.stdout, sys.stderr + try: + out=[StringIO(), StringIO()] + sys.stdout,sys.stderr = out + yield out + finally: + sys.stdout,sys.stderr = oldout, olderr + out[0] = out[0].getvalue() + out[1] = out[1].getvalue() + + +class TestFunctional(unittest.TestCase): + def setUp(self): + self.tmpdir = tempfile.mkdtemp(prefix='patman.') + + def tearDown(self): + shutil.rmtree(self.tmpdir) + + @staticmethod + def GetPath(fname): + return os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), + 'test', fname) + + @classmethod + def GetText(self, fname): + return open(self.GetPath(fname)).read() + + @classmethod + def GetPatchName(self, subject): + fname = re.sub('[ :]', '-', subject) + return fname.replace('--', '-') + + def CreatePatchesForTest(self, series): + cover_fname = None + fname_list = [] + for i, commit in enumerate(series.commits): + clean_subject = self.GetPatchName(commit.subject) + src_fname = '%04d-%s.patch' % (i + 1, clean_subject[:52]) + fname = os.path.join(self.tmpdir, src_fname) + shutil.copy(self.GetPath(src_fname), fname) + fname_list.append(fname) + if series.get('cover'): + src_fname = '0000-cover-letter.patch' + cover_fname = os.path.join(self.tmpdir, src_fname) + fname = os.path.join(self.tmpdir, src_fname) + shutil.copy(self.GetPath(src_fname), fname) + + return cover_fname, fname_list + + def testBasic(self): + """Tests the basic flow of patman + + This creates a series from some hard-coded patches build from a simple + tree with the following metadata in the top commit: + + Series-to: u-boot + Series-prefix: RFC + Series-cc: Stefan Brüns + Cover-letter-cc: Lord Mëlchett + Series-version: 2 + Series-changes: 4 + - Some changes + + Cover-letter: + test: A test patch series + This is a test of how the cover + leter + works + END + + and this in the first commit: + + Series-notes: + some notes + about some things + from the first commit + END + + Commit-notes: + Some notes about + the first commit + END + + with the following commands: + + git log -n2 --reverse >/path/to/tools/patman/test/test01.txt + git format-patch --subject-prefix RFC --cover-letter HEAD~2 + mv 00* /path/to/tools/patman/test + + It checks these aspects: + - git log can be processed by patchstream + - emailing patches uses the correct command + - CC file has information on each commit + - cover letter has the expected text and subject + - each patch has the correct subject + - dry-run information prints out correctly + - unicode is handled correctly + - Series-to, Series-cc, Series-prefix, Cover-letter + - Cover-letter-cc, Series-version, Series-changes, Series-notes + - Commit-notes + """ + process_tags = True + ignore_bad_tags = True + stefan = u'Stefan Brüns ' + rick = 'Richard III ' + mel = u'Lord Mëlchett ' + ed = u'Lond Edmund Blackaddër 0x80: - self.warn.append("Line %d/%d ('%s') has funny ascii char" % - (self.linenum, pos, line)) - pos += 1 - # Look for space before tab m = re_space_before_tab.match(line) if m: @@ -433,6 +424,19 @@ def GetMetaData(start, count): """ return GetMetaDataForList('HEAD~%d' % start, None, count) +def GetMetaDataForTest(text): + """Process metadata from a file containing a git log. Used for tests + + Args: + text: + """ + series = Series() + ps = PatchStream(series, is_log=True) + for line in text.splitlines(): + ps.ProcessLine(line) + ps.Finalize() + return series + def FixPatch(backup_dir, fname, series, commit): """Fix up a patch file, by adding/removing as required. @@ -486,7 +490,6 @@ def FixPatches(series, fnames): print count += 1 print('Cleaned %d patches' % count) - return series def InsertCoverLetter(fname, series, count): """Inserts a cover letter with the required info into patch 0 diff --git a/tools/patman/patman.py b/tools/patman/patman.py index fdbee67..4b3bc78 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -82,11 +82,13 @@ if __name__ != "__main__": # Run our meagre tests elif options.test: import doctest + import func_test sys.argv = [sys.argv[0]] - suite = unittest.TestLoader().loadTestsFromTestCase(test.TestPatch) result = unittest.TestResult() - suite.run(result) + for module in (test.TestPatch, func_test.TestFunctional): + suite = unittest.TestLoader().loadTestsFromTestCase(module) + suite.run(result) for module in ['gitutil', 'settings']: suite = doctest.DocTestSuite(module) @@ -141,8 +143,8 @@ else: series) # Fix up the patch files to our liking, and insert the cover letter - series = patchstream.FixPatches(series, args) - if series and cover_fname and series.get('cover'): + patchstream.FixPatches(series, args) + if cover_fname and series.get('cover'): patchstream.InsertCoverLetter(cover_fname, series, options.count) # Do a few checks on the series diff --git a/tools/patman/series.py b/tools/patman/series.py index c1b8652..d3947a7 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -212,7 +212,9 @@ class Series(dict): cover_fname: If non-None the name of the cover letter. raise_on_error: True to raise an error when an alias fails to match, False to just print a message. - add_maintainers: Call the get_maintainers to CC maintainers + add_maintainers: Either: + True/False to call the get_maintainers to CC maintainers + List of maintainers to include (for testing) Return: Filename of temp file created """ @@ -221,21 +223,27 @@ class Series(dict): fd = open(fname, 'w') all_ccs = [] for commit in self.commits: - list = [] + cc = [] if process_tags: - list += gitutil.BuildEmailList(commit.tags, + cc += gitutil.BuildEmailList(commit.tags, raise_on_error=raise_on_error) - list += gitutil.BuildEmailList(commit.cc_list, + cc += gitutil.BuildEmailList(commit.cc_list, raise_on_error=raise_on_error) - if add_maintainers: - list += get_maintainer.GetMaintainer(commit.patch) - all_ccs += list - print(commit.patch, ', '.join(set(list)), file=fd) - self._generated_cc[commit.patch] = list + if type(add_maintainers) == type(cc): + cc += add_maintainers + elif add_maintainers: + cc += get_maintainer.GetMaintainer(commit.patch) + cc = [m.encode('utf-8') if type(m) != str else m for m in cc] + all_ccs += cc + print(commit.patch, ', '.join(set(cc)), file=fd) + self._generated_cc[commit.patch] = cc if cover_fname: cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) - cc_list = ', '.join([x.decode('utf-8') for x in set(cover_cc + all_ccs)]) + cover_cc = [m.encode('utf-8') if type(m) != str else m + for m in cover_cc] + cc_list = ', '.join([x.decode('utf-8') + for x in set(cover_cc + all_ccs)]) print(cover_fname, cc_list.encode('utf-8'), file=fd) fd.close() diff --git a/tools/patman/test.py b/tools/patman/test.py index 8c39f66..20dc9c1 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -1,3 +1,4 @@ +# -*- coding: utf-8 -*- # # Copyright (c) 2011 The Chromium OS Authors. # @@ -31,6 +32,10 @@ Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support This adds functions to enable/disable clocks and reset to on-chip peripherals. +cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + BUG=chromium-os:13875 TEST=build U-Boot for Seaboard, boot @@ -53,6 +58,10 @@ Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support This adds functions to enable/disable clocks and reset to on-chip peripherals. +cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + Signed-off-by: Simon Glass --- diff --git a/tools/patman/test/0000-cover-letter.patch b/tools/patman/test/0000-cover-letter.patch new file mode 100644 index 0000000..2906201 --- /dev/null +++ b/tools/patman/test/0000-cover-letter.patch @@ -0,0 +1,23 @@ +From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 +From: Simon Glass +Date: Sat, 27 May 2017 20:52:11 -0600 +Subject: [RFC 0/2] *** SUBJECT HERE *** +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +*** BLURB HERE *** + +Simon Glass (2): + pci: Correct cast for sandbox + fdt: Correct cast for sandbox in fdtdec_setup_memory_size() + + cmd/pci.c | 3 ++- + fs/fat/fat.c | 1 + + lib/efi_loader/efi_memory.c | 1 + + lib/fdtdec.c | 3 ++- + 4 files changed, 6 insertions(+), 2 deletions(-) + +-- +2.7.4 + diff --git a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch new file mode 100644 index 0000000..7191176 --- /dev/null +++ b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch @@ -0,0 +1,48 @@ +From b9da5f937bd5ea4931ea17459bf79b2905d9594d Mon Sep 17 00:00:00 2001 +From: Simon Glass +Date: Sat, 15 Apr 2017 15:39:08 -0600 +Subject: [RFC 1/2] pci: Correct cast for sandbox +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This gives a warning with some native compilers: + +cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + +Fix it with a cast. + +Signed-off-by: Simon Glass +Series-notes: +some notes +about some things +from the first commit +END + +Commit-notes: +Some notes about +the first commit +END +--- + cmd/pci.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/cmd/pci.c b/cmd/pci.c +index 41b4fff..fe27b4f 100644 +--- a/cmd/pci.c ++++ b/cmd/pci.c +@@ -150,7 +150,8 @@ int pci_bar_show(struct udevice *dev) + if ((!is_64 && size_low) || (is_64 && size)) { + size = ~size + 1; + printf(" %d %#016llx %#016llx %d %s %s\n", +- bar_id, base, size, is_64 ? 64 : 32, ++ bar_id, (unsigned long long)base, ++ (unsigned long long)size, is_64 ? 64 : 32, + is_io ? "I/O" : "MEM", + prefetchable ? "Prefetchable" : ""); + } +-- +2.7.4 + diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch new file mode 100644 index 0000000..e328497 --- /dev/null +++ b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch @@ -0,0 +1,73 @@ +From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 +From: Simon Glass +Date: Sat, 15 Apr 2017 15:39:08 -0600 +Subject: [RFC 2/2] fdt: Correct cast for sandbox in fdtdec_setup_memory_size() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This gives a warning with some native compilers: + +lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘long unsigned int’ [-Wformat=] + +Fix it with a cast. + +Signed-off-by: Simon Glass +Series-to: u-boot +Series-prefix: RFC +Series-cc: Stefan Brüns +Cover-letter-cc: Lord Mëlchett +Series-version: 3 +Patch-cc: fred +Series-changes: 4 +- Some changes + +Cover-letter: +test: A test patch series +This is a test of how the cover +leter +works +END +--- + fs/fat/fat.c | 1 + + lib/efi_loader/efi_memory.c | 1 + + lib/fdtdec.c | 3 ++- + 3 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/fs/fat/fat.c b/fs/fat/fat.c +index a71bad1..ba169dc 100644 +--- a/fs/fat/fat.c ++++ b/fs/fat/fat.c +@@ -1,3 +1,4 @@ ++ + /* + * fat.c + * +diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c +index db2ae19..05f75d1 100644 +--- a/lib/efi_loader/efi_memory.c ++++ b/lib/efi_loader/efi_memory.c +@@ -1,3 +1,4 @@ ++ + /* + * EFI application memory management + * +diff --git a/lib/fdtdec.c b/lib/fdtdec.c +index c072e54..942244f 100644 +--- a/lib/fdtdec.c ++++ b/lib/fdtdec.c +@@ -1200,7 +1200,8 @@ int fdtdec_setup_memory_size(void) + } + + gd->ram_size = (phys_size_t)(res.end - res.start + 1); +- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); ++ debug("%s: Initial DRAM size %llx\n", __func__, ++ (unsigned long long)gd->ram_size); + + return 0; + } +-- +2.7.4 + diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt new file mode 100644 index 0000000..8ad9587 --- /dev/null +++ b/tools/patman/test/test01.txt @@ -0,0 +1,56 @@ +commit b9da5f937bd5ea4931ea17459bf79b2905d9594d +Author: Simon Glass +Date: Sat Apr 15 15:39:08 2017 -0600 + + pci: Correct cast for sandbox + + This gives a warning with some native compilers: + + cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + + Fix it with a cast. + + Signed-off-by: Simon Glass + Series-notes: + some notes + about some things + from the first commit + END + + Commit-notes: + Some notes about + the first commit + END + +commit 5ab48490f03051875ab13d288a4bf32b507d76fd +Author: Simon Glass +Date: Sat Apr 15 15:39:08 2017 -0600 + + fdt: Correct cast for sandbox in fdtdec_setup_memory_size() + + This gives a warning with some native compilers: + + lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘long unsigned int’ [-Wformat=] + + Fix it with a cast. + + Signed-off-by: Simon Glass + Series-to: u-boot + Series-prefix: RFC + Series-cc: Stefan Brüns + Cover-letter-cc: Lord Mëlchett + Series-version: 3 + Patch-cc: fred + Series-changes: 4 + - Some changes + + Cover-letter: + test: A test patch series + This is a test of how the cover + leter + works + END diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 8283a74..a583c0c 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -2,6 +2,8 @@ * (C) Copyright 2015 Google, Inc * Written by Simon Glass * + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * * SPDX-License-Identifier: GPL-2.0+ * * Helper functions for Rockchip images @@ -75,6 +77,7 @@ static struct spl_info spl_infos[] = { { "rk3288", "RK32", 0x8000, false, false }, { "rk3328", "RK32", 0x8000 - 0x1000, false, false }, { "rk3399", "RK33", 0x20000, false, true }, + { "rv1108", "RK11", 0x1800, false, false}, }; static unsigned char rc4_key[16] = { @@ -182,11 +185,14 @@ static void rkcommon_set_header0(void *buf, uint file_size, */ hdr->init_size = ROUND(hdr->init_size, 4); /* - * The images we create do not contain the stage following the SPL as - * part of the SPL image, so the init_boot_size (which might have been - * read by Rockchip's miniloder) should be the same as the init_size. + * init_boot_size needs to be set, as it is read by the BootROM + * to determine the size of the next-stage bootloader (e.g. U-Boot + * proper), when used with the back-to-bootrom functionality. + * + * see https://lists.denx.de/pipermail/u-boot/2017-May/293267.html + * for a more detailed explanation by Andy Yan */ - hdr->init_boot_size = hdr->init_size; + hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; rc4_encode(buf, RK_BLK_SIZE, rc4_key); } @@ -201,7 +207,7 @@ int rkcommon_set_header(void *buf, uint file_size, rkcommon_set_header0(buf, file_size, params); - /* Set up the SPL name */ + /* Set up the SPL name (i.e. copy spl_hdr over) */ memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); if (rkcommon_need_rc4_spl(params)) @@ -211,6 +217,121 @@ int rkcommon_set_header(void *buf, uint file_size, return 0; } +static inline unsigned rkcommon_offset_to_spi(unsigned offset) +{ + /* + * While SD/MMC images use a flat addressing, SPI images are padded + * to use the first 2K of every 4K sector only. + */ + return ((offset & ~0x7ff) << 1) + (offset & 0x7ff); +} + +static inline unsigned rkcommon_spi_to_offset(unsigned offset) +{ + return ((offset & ~0x7ff) >> 1) + (offset & 0x7ff); +} + +static int rkcommon_parse_header(const void *buf, struct header0_info *header0, + struct spl_info **spl_info) +{ + unsigned hdr1_offset; + struct header1_info *hdr1_sdmmc, *hdr1_spi; + int i; + + if (spl_info) + *spl_info = NULL; + + /* + * The first header (hdr0) is always RC4 encoded, so try to decrypt + * with the well-known key. + */ + memcpy((void *)header0, buf, sizeof(struct header0_info)); + rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key); + + if (header0->signature != RK_SIGNATURE) + return -EPROTO; + + /* We don't support RC4 encoded image payloads here, yet... */ + if (header0->disable_rc4 == 0) + return -ENOSYS; + + hdr1_offset = header0->init_offset * RK_BLK_SIZE; + hdr1_sdmmc = (struct header1_info *)(buf + hdr1_offset); + hdr1_spi = (struct header1_info *)(buf + + rkcommon_offset_to_spi(hdr1_offset)); + + for (i = 0; i < ARRAY_SIZE(spl_infos); i++) { + if (!memcmp(&hdr1_sdmmc->magic, spl_infos[i].spl_hdr, 4)) { + if (spl_info) + *spl_info = &spl_infos[i]; + return IH_TYPE_RKSD; + } else if (!memcmp(&hdr1_spi->magic, spl_infos[i].spl_hdr, 4)) { + if (spl_info) + *spl_info = &spl_infos[i]; + return IH_TYPE_RKSPI; + } + } + + return -1; +} + +int rkcommon_verify_header(unsigned char *buf, int size, + struct image_tool_params *params) +{ + struct header0_info header0; + struct spl_info *img_spl_info, *spl_info; + int ret; + + ret = rkcommon_parse_header(buf, &header0, &img_spl_info); + + /* If this is the (unimplemented) RC4 case, then rewrite the result */ + if (ret == -ENOSYS) + return 0; + + if (ret < 0) + return ret; + + /* + * If no 'imagename' is specified via the commandline (e.g. if this is + * 'dumpimage -l' w/o any further constraints), we accept any spl_info. + */ + if (params->imagename == NULL) + return 0; + + /* Match the 'imagename' against the 'spl_hdr' found */ + spl_info = rkcommon_get_spl_info(params->imagename); + if (spl_info && img_spl_info) + return strcmp(spl_info->spl_hdr, img_spl_info->spl_hdr); + + return -ENOENT; +} + +void rkcommon_print_header(const void *buf) +{ + struct header0_info header0; + struct spl_info *spl_info; + uint8_t image_type; + int ret; + + ret = rkcommon_parse_header(buf, &header0, &spl_info); + + /* If this is the (unimplemented) RC4 case, then fail silently */ + if (ret == -ENOSYS) + return; + + if (ret < 0) { + fprintf(stderr, "Error: image verification failed\n"); + return; + } + + image_type = ret; + + printf("Image Type: Rockchip %s (%s) boot image\n", + spl_info->spl_hdr, + (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI"); + printf("Data Size: %d bytes\n", header0.init_size * RK_BLK_SIZE); +} + void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size) { unsigned int remaining = size; @@ -259,8 +380,9 @@ int rkcommon_vrec_header(struct image_tool_params *params, /* Allocate, clear and install the header */ tparams->hdr = malloc(tparams->header_size); + if (!tparams->hdr) + return -ENOMEM; memset(tparams->hdr, 0, tparams->header_size); - tparams->header_size = tparams->header_size; /* * If someone passed in 0 for the alignment, we'd better handle diff --git a/tools/rkcommon.h b/tools/rkcommon.h index a21321f..8790f1c 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -10,6 +10,7 @@ enum { RK_BLK_SIZE = 512, + RK_INIT_SIZE_ALIGN = 2048, RK_INIT_OFFSET = 4, RK_MAX_BOOT_SIZE = 512 << 10, RK_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE, @@ -56,6 +57,25 @@ int rkcommon_set_header(void *buf, uint file_size, struct image_tool_params *params); /** + * rkcommon_verify_header() - verify the header for a Rockchip boot image + * + * @buf: Pointer to the image file + * @file_size: Size of entire bootable image file (incl. all padding) + * @return 0 if OK + */ +int rkcommon_verify_header(unsigned char *buf, int size, + struct image_tool_params *params); + +/** + * rkcommon_print_header() - print the header for a Rockchip boot image + * + * This prints the header, spl_name and whether this is a SD/MMC or SPI image. + * + * @buf: Pointer to the image (can be a read-only file-mapping) + */ +void rkcommon_print_header(const void *buf); + +/** * rkcommon_need_rc4_spl() - check if rc4 encoded spl is required * * Some socs cannot disable the rc4-encryption of the spl binary. diff --git a/tools/rksd.c b/tools/rksd.c index 8627b6d..c56153d 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -13,29 +13,17 @@ #include "mkimage.h" #include "rkcommon.h" -static int rksd_verify_header(unsigned char *buf, int size, - struct image_tool_params *params) -{ - return 0; -} - -static void rksd_print_header(const void *buf) -{ -} - static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, - struct image_tool_params *params) + struct image_tool_params *params) { unsigned int size; int ret; - printf("params->file_size %d\n", params->file_size); - printf("params->orig_file_size %d\n", params->orig_file_size); - /* * We need to calculate this using 'RK_SPL_HDR_START' and not using * 'tparams->header_size', as the additional byte inserted when - * 'is_boot0' is true counts towards the payload. + * 'is_boot0' is true counts towards the payload (and not towards the + * header). */ size = params->file_size - RK_SPL_HDR_START; ret = rkcommon_set_header(buf, size, params); @@ -46,11 +34,6 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, } } -static int rksd_extract_subimage(void *buf, struct image_tool_params *params) -{ - return 0; -} - static int rksd_check_image_type(uint8_t type) { if (type == IH_TYPE_RKSD) @@ -63,10 +46,10 @@ static int rksd_vrec_header(struct image_tool_params *params, struct image_type_params *tparams) { /* - * Pad to the RK_BLK_SIZE (512 bytes) to be consistent with init_size - * being encoded in RK_BLK_SIZE units in header0 (see rkcommon.c). + * Pad to a 2KB alignment, as required for init_size by the ROM + * (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html) */ - return rkcommon_vrec_header(params, tparams, RK_BLK_SIZE); + return rkcommon_vrec_header(params, tparams, RK_INIT_SIZE_ALIGN); } /* @@ -78,10 +61,10 @@ U_BOOT_IMAGE_TYPE( 0, NULL, rkcommon_check_params, - rksd_verify_header, - rksd_print_header, + rkcommon_verify_header, + rkcommon_print_header, rksd_set_header, - rksd_extract_subimage, + NULL, rksd_check_image_type, NULL, rksd_vrec_header diff --git a/tools/rkspi.c b/tools/rkspi.c index 87bd1a9..4332ce1 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -17,16 +17,6 @@ enum { RKSPI_SECT_LEN = RK_BLK_SIZE * 4, }; -static int rkspi_verify_header(unsigned char *buf, int size, - struct image_tool_params *params) -{ - return 0; -} - -static void rkspi_print_header(const void *buf) -{ -} - static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, struct image_tool_params *params) { @@ -58,11 +48,6 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, } } -static int rkspi_extract_subimage(void *buf, struct image_tool_params *params) -{ - return 0; -} - static int rkspi_check_image_type(uint8_t type) { if (type == IH_TYPE_RKSPI) @@ -78,7 +63,7 @@ static int rkspi_check_image_type(uint8_t type) static int rkspi_vrec_header(struct image_tool_params *params, struct image_type_params *tparams) { - int padding = rkcommon_vrec_header(params, tparams, 2048); + int padding = rkcommon_vrec_header(params, tparams, RK_INIT_SIZE_ALIGN); /* * The file size has not been adjusted at this point (our caller will * eventually add the header/padding to the file_size), so we need to @@ -112,10 +97,10 @@ U_BOOT_IMAGE_TYPE( 0, NULL, rkcommon_check_params, - rkspi_verify_header, - rkspi_print_header, + rkcommon_verify_header, + rkcommon_print_header, rkspi_set_header, - rkspi_extract_subimage, + NULL, rkspi_check_image_type, NULL, rkspi_vrec_header diff --git a/tools/tbot/README b/tools/tbot/README deleted file mode 100644 index 49b9e95..0000000 --- a/tools/tbot/README +++ /dev/null @@ -1,195 +0,0 @@ -# Copyright (c) 2016 DENX Software Engineering GmbH -# Heiko Schocher -# -# SPDX-License-Identifier: GPL-2.0+ -# - -What is tbot ? -============== - -tbot is a tool for executing testcases on boards. -Source code found on [1] -Based on DUTS [2] -written in python - -Basic Ideas of tbot -=================== -(see also the figure: -https://github.com/hsdenx/tbot/blob/master/doc/tbot_structure.png ) - -- Virtual laboratory (VL) - VL is the basic environment that groups: - - [a number of] boards - target devices on which tbot executes testcases. - - one Lab PC - -- Test case (TC): - A piece of python code, which uses the tbot class from [1]. - Tbot provides functions for sending shell commands and parsing the - shell commands output. - Tbot waits endless for a shell commands end (detected through reading - the consoles prompt). - A TC can also call other TC-es. - - remark: - Tbot not really waits endless, for a shell commands end, instead - tbot starts a watchdog in the background, and if it triggers, tbot - ends the TC as failed. In the tbot beginning there was a lot of - timeouts / retry cases, but it turned out, that waiting endless - is robust and easy ... - -- Host PC (where tbot runs, currently only linux host tested) - must not a powerful machine (For example [3], I use a - raspberry pi for running tbot and buildbot) - -- Lab PC: - - Host PC connects through ssh to the Lab PC - -> so it is possible to test boards, which - are not at the same place as the Host PC. - (Lab PC and Host PC can be the same of course) - -> maybe we can setup a Testsystem, which does nightly - U-Boot/Linux builds and test from current mainline U-Boot - on boards wherever they are accessible. - - - necessary tasks a Lab PC must deliver: - - connect to boards console through a shell command. - - power on/off boards through a shell command - - detect the current power state of a board through - a shell command - - - optional tasks: - - tftp server (for example loading images) - - nfs server (used as rootfs for linux kernels) - - Internet access for example for downloading - U-Boot source with git. - - toolchains installed for compiling source code - - -> a linux machine is preffered. - - - currently only Lab PC with an installed linux supported/tested. - -- Boards(s): - the boards on which shell commands are executed. - -- Board state: - equals to the software, the board is currently running. - - Currently tbot supports 2 board states: - - "u-boot", if the board is running U-Boot - - "linux", if the board is running a linux kernel - - It should be easy to add other board states to tbot, see - https://github.com/hsdenx/tbot/tree/master/src/lab_api/state_[u-boot/linux].py - - A board state is detected through analysing the boards - shell prompt. In linux, tbot sets a special tbot prompt, - in U-Boot the prompt is static, and configurable in tbot through - a board config file. - - A TC can say in which board state it want to send shell commands. - Tbot tries to detect the current board state, if board is not in - the requested board state, tbot tries to switch into the correct - state. If this fails, the TC fails. - - It is possible to switch in a single TC between board states. - -- Events - tbot creates while executing testcases so called events. - After tbot ended with the testcase it can call event_backends, - which convert the events to different formats. more info: - - https://github.com/hsdenx/tbot/blob/master/doc/README.event - - demo for a event backend: - http://xeidos.ddns.net/tests/test_db_auslesen.php - -- tbot cmdline parameters: - -$ python2.7 src/common/tbot.py --help -Usage: tbot.py [options] - -Options: - -h, --help show this help message and exit - -c CFGFILE, --cfgfile=CFGFILE - the tbot common configfilename - -l LOGFILE, --logfile=LOGFILE - the tbot logfilename, if default, tbot creates a - defaultnamelogfile - -t TC, --testcase=TC the testcase which should be run - -v, --verbose be verbose, print all read/write to stdout - -w WORKDIR, --workdir=WORKDIR - set workdir, default os.getcwd() -$ - -tbot needs the following files for proper execution: - - - tbot board configuration file (option -c): - A board configuration file contains settings tbot needs to - connect to the Lab PC and board specific variable settings - for testcases. - - - name of the logfile tbot creates (option -l) - defaultname: 'log/' + now.strftime("%Y-%m-%d-%H-%M") + '.log' - - - tbots working directory (option -w) - - - the testcasename tbot executes (option -t) - -You are interested and want to use tbot? -If so, please read on the file: -tools/tbot/README.install - -If not read [3] ;-) - -Heiko Schocher -v1 2016.01.22 - --------------- -[1] https://github.com/hsdenx/tbot -[2] http://www.denx.de/wiki/DUTS/DUTSDocs -[3] automated Testsetup with buildbot and tbot doing cyclic tests - (buildbot used for starting tbot TC and web presentation of the - results, all testing done through tbot): - http://xeidos.ddns.net/buildbot/tgrid - Host PC in Letkes/hungary - VL in munich/germany - - Fancy things are done here, for example: - - http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/43/steps/shell/logs/tbotlog - (I try to cleanup the logfile soon, so it is not so filled with crap ;-) - A first step see here: - http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/45/steps/shell/logs/tbotlog - (same TC now with the new loglevel = 'CON' ... not yet perfect) - Executed steps: - - clone u-boot.git - - set toolchain - - get a list of patchwork patches from my U-Boots ToDo list - - download all of them, and check them with checkpatch - and apply them to u-boot.git - - compile U-Boot for the smartweb board - - install the resulting images on the smartweb board - - boot U-boot - - test DFU - - more TC should be added here for testing U-Boot - - - automatic "git bisect" - https://github.com/hsdenx/tbot/blob/master/src/tc/tc_board_git_bisect.py - http://xeidos.ddns.net/buildbot/builders/tqm5200s/builds/3/steps/shell/logs/tbotlog - - If a current U-Boot image not works on the tqm5200 board - this TC can be started. It starts a "git bisect" session, - and compiles for each step U-Boot, install it on the tqm5200 - board, and tests if U-Boot works ! - - At the end, it detects the commit, which breaks the board - - This TC is not dependend on U-Boot nor on a special board. It - needs only 3 variables: - tb.board_git_bisect_get_source_tc: TC which gets the source tree, in which - "git bisect" should be executed - tb.board_git_bisect_call_tc: TC which gets called every "git bisect" step, - which executes commands for detecting if current source code is OK or not. - This could be a TC which compiles U-Boot, install it on the board and - executes TC on the new booted U-Boot image. ! Board maybe gets borken, - as not all U-Boot images work, so you must have a TC which install U-Boot - image for example through a debugger. - tb.board_git_bisect_good_commit: last nown good commit id diff --git a/tools/tbot/README-ToDo b/tools/tbot/README-ToDo deleted file mode 100644 index daf1af1..0000000 --- a/tools/tbot/README-ToDo +++ /dev/null @@ -1,62 +0,0 @@ -# Copyright (c) 2016 DENX Software Engineering GmbH -# Heiko Schocher -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ToDo list for tbot -================== - -please look also into the tbot ToDo list. -https://github.com/hsdenx/tbot/blob/master/ToDo - -- cleanup tbot code: - - remove all retry / timeout pieces of code - - clean up tbot function names, as I am not good in - giving function a understandable name ;-) - - as I am not a python programmer, cleanup whole tbot code - -- introduce a "layering" like yocto do, so U-Boot TC can integrated - into U-Boot source code. - - Proposal: - introduce subdirs in "src/tc" - - lab: all lab specific stuff - lab/common: common lab stuff (for example ssh handling) - lab/ssh_std: ssh_std specific stuff - - u-boot: all u-boot tests - u-boot/common: common u-boot tc - u-boot/duts: DUTS tc - u-boot-dxr2: all u-boot dxr2 board specific tc - - board: board tc - board/common: common board tc - board/dxr2: all tc for dxr2 board - - linux: all linux tc - linux/common: common linux tc - linux/dxr2 - - - move U-Boot special TC to U-Boot source - -> need a mechanism in tbot, how it gets automatically for example - U-Boot TC from U-Boot source... - -> add a consistency checker - -- simplify tbot log output (seperate a lot of output which is currently - in INFO logging level, to another logging level) - started (new loglevel "CON", whih prints read/write from console only), see: - https://github.com/hsdenx/tbot/commit/b4ab2567ad8c19ad53f785203159d3c8465a21c6 - - make the timestamp configurable - -- Open more than 2 filehandles ? - Do we need for more complex TC more than 2 filehandles? - -- Find a way to document all TC and document all variables they use in an - automated way. - -- write a lot of more TC - -- get U-Boot configuration settings from current U-Boot code and use - them in U-Boot TC-es diff --git a/tools/tbot/README.create_a_new_testcase b/tools/tbot/README.create_a_new_testcase deleted file mode 100644 index fbf8ae8..0000000 --- a/tools/tbot/README.create_a_new_testcase +++ /dev/null @@ -1,117 +0,0 @@ -# Copyright (c) 2016 DENX Software Engineering GmbH -# Heiko Schocher -# -# SPDX-License-Identifier: GPL-2.0+ -# - -write a new testcase -===================== - -A TC is written in python, so you can use python as usual. For accessing -the boards console, use functions from the tbotlib, therefore - -First import the tbotlib with the line: - - from tbotlib import tbot - -If your TC uses variables, please add a line which adds them to -the log file (for debugging purposes): - - logging.info("args: %s ...", tb.varname, ...) - -Say tbot, for which board state your TC is valid with: - - tb.set_board_state("u-boot") - -Then you are ready ... and you can use the tbotlib funtions -for writting/reading to the boards console. - -Big fat warning: - -A TC must worry about to end only if a board has finished the shell -command! - -Not following this rule, will end in unpredictable behaviour. - -(hopefully) useful tbotlib functions -==================================== -- set the board state, you want to test - tb.set_board_state(state) - states are: "u-boot" or "linux" - If tbot could not set the board state, tbot ends with failure. - -- write a command to the boards console: - tb.eof_write_con(command): - write the command to the boards console. If this - fails, tbot ends with failure - -- write a command to boards console and wait for prompt: - tb.eof_write_cmd(fd, command): - fd: filedescriptor which is used, use tb.channel_con for boards console - command: command which is written to fd - - Wait endless for board prompt - -- write a list of commands to boards console: - tb.eof_write_cmd_list(fd, cmdlist): - fd: filedescriptor which is used, use tb.channel_con for boards console - cmdlist: python list of commandstrings which is written to fd - -- wait for boards prompt: - tb.eof_read_end_state_con(retry): - retry: deprecated, not used anymore, cleanup needed here... - tbot waits endless for the boards prompt - -- write a command, wait for prompt and check, if a string is read - tb.write_cmd_check(fd, cmd, string): - fd: filedescriptor which is used, use tb.channel_con for boards console - cmd: command, which is send to fd - string: string which should be read from fd - - return value: - True, if string is read and tbot got back boards prompt - False, else - - tb.eof_write_cmd_check(fd, cmd, string): - same as tb.write_cmd_check(fd, cmd, string) except, that tbot - ends immediately with Failure, if string is not read. - -- read until prompt and search strings: - tb.readline_and_search_strings(fd, strings): - fd: filedescriptor which is used, use tb.channel_con for boards console - strings: python list of strings, which can be read - If one of this strings is read, this function return the index, which - string is read. This function shoud be called in a while loop, - until this function returns 'prompt' - -- read a line from filedescriptor: - not recommended to use, as the TC must check, if tprompt is read for every - readen line. Also TC must ensure, that it ends only, if prompt is read. - tb.read_line(fd, retry) - fd: filedescriptor which is used, use tb.channel_con for boards console - retry: retry of trying to reead a line - - return values: - True, if a line is read. Readen line in tb.buf[fd] - False, if something read, but not a complete line - None, if nothing is read - - check if string contains prompt with: - tb.is_end_fd(fd, string) - fd: filedescriptor which is used, use tb.channel_con for boards console - string: buffer, in which a prompt gets searched. - -- calling other TC: - eof_call_tc(name): - call another TC from "src/tc" - if the called TC fails with failure, tbot ends with failure - - call_tc(name): - call another TC from "src/tc" - if the TC which call_tc calls fails, call_tc() returns False, else True - -There are more functions, but for writting TC this should be enough. But -its software, so new useful functions can always pop up. - -Heiko Schocher -v1 2016.01.23 diff --git a/tools/tbot/README.install b/tools/tbot/README.install deleted file mode 100644 index a68e705..0000000 --- a/tools/tbot/README.install +++ /dev/null @@ -1,310 +0,0 @@ -# Copyright (c) 2016 DENX Software Engineering GmbH -# Heiko Schocher -# -# SPDX-License-Identifier: GPL-2.0+ -# - -install tbot on your PC (linux only tested): -============================================ - -- get the source code: - -$ git clone https://github.com/hsdenx/tbot.git -[...] -$ - - cd into the tbot directory. - -- you need the for running tbot the python paramiko module, see: - http://www.paramiko.org/installing.html - - paramiko is used for handling ssh sessions, and open filedescriptors - on a ssh connection. Tbot open a ssh connection to a "lab PC" and - opens on that connection 2 filehandles, one for control functions - and one for the connection to the boards console. May it is worth - to think about to open more filehandles and use them in tbot, but - thats a point in the Todo list ... - - See [1] for more infos about tbot principles. - -- prepare a directory for storing the logfiles - and pass it with the commandline option "-l" - to tbot. Default is the directory "log" in the tbot - root (don;t forget to create it, if you want to use it) - -- If your VL is not yet in tbot source, integrate it - (This task has only to be done once for your VL): - - A VL has, as described in [2] "necessary tasks for a Lab PC" explained, - 3 tasks: - - a) power on/off the board - b) get power state of the board - c) connect to the boards console - - As tbot sends only shell commands (also to the Lab PC) - this tasks must be executable through shell commands on your - Lab PC: - - Task a) power on/off board: - default TC for this task is: - https://github.com/hsdenx/tbot/blob/master/src/tc/tc_lab_denx_power.py - - - now copy this file to for example - cp src/tc/tc_lab_denx_power.py src/tc/tc_lab_denx_power_XXX.py - (replace XXX to a proper value) - and adapt the "remote_power" command from the denx lab to your needs. - - As this TC powers on the board for all your boards in your VL, - you can differ between the boards through the tbot class - variable "tb.boardlabpowername" (which is in the default case the - same as "tb.boardname"), but you may need to name the power target - with an other name than boardname, so you can configure this case. - The power state "tb.power_state" which the TC has to set - is "on" for power on, or "off" for power off. - - If switching on the power is successful, call "tb.end_tc(True)" - else "tb.end_tc(False)" - - - set in your board config file: - self.tc_lab_denx_power_tc = 'tc_lab_denx_power_XXX.py' - - Task b) power on/off board: - default TC for this task is: - https://github.com/hsdenx/tbot/blob/master/src/tc/tc_lab_denx_get_power_state.py - - - now copy this file to for example - (replace XXX to a proper value) - cp src/tc/tc_lab_denx_get_power_state.py src/tc/tc_lab_denx_get_power_state_XXX.py - and adapt the commands to your needs. - - If the power of the board is on, call "tb.end_tc(True)" - else "tb.end_tc(False)" - - - set in your board config file: - self.tc_lab_denx_get_power_state_tc = 'tc_lab_denx_get_power_state_XXX.py' - - Task c) connect to the boards console: - default TC for this task is: - https://github.com/hsdenx/tbot/blob/master/src/tc/tc_lab_denx_connect_to_board.py - - - now copy this file to for example - (replace XXX to a proper value) - cp src/tc/tc_lab_denx_connect_to_board.py src/tc/tc_lab_denx_connect_to_board_XXX.py - and adapt the commands to your needs. - - If connect fails end this TC with "tb.end_tc(False)" - else call "tb.end_tc(True)" - - If you want to use kermit for connecting to the boards console, you - can use: - - https://github.com/hsdenx/tbot/blob/master/src/tc/tc_workfd_connect_with_kermit.py - - Example for such a board in the VL from denx: - self.tc_lab_denx_connect_to_board_tc = 'tc_workfd_connect_with_kermit.py' - https://github.com/hsdenx/tbot/blob/master/tbot_dxr2.cfg#L24 - - Hopefully this works for you too. - - - set in your board config file: - self.tc_lab_denx_connect_to_board_tc = 'tc_lab_denx_connect_to_board_XXX.py' - - remarks while writting this: - - Currently there is only the denx VL. Original idea was to include - other VL through a seperate class/file in - https://github.com/hsdenx/tbot/tree/master/src/lab_api - but it turned out, that if we say "ssh" is the standard way to connect - to a VL, we can integrate the VL specific tasks through testcases, see - above, so we should do: - - rename the "denx" API to a more general name. - This is a point on my ToDo list ... done, renamed to 'ssh_std' - - - the VL specific configuration may moved from the board config files - and should be collected in VL specific config files, which boards - config file simple include. - -- prepare password.py file: - This file contains all passwords tbot needs (for example for - linux login on the boards) - tbot searches this file in the tbot root directory. - It is a simple python file, for example: - - # passwords for the lab - if (board == 'lab'): - if (user == 'hs'): - password = 'passwordforuserhs' - if (user == 'root'): - password = 'passwordforrootuser' - # passwords for the boards - elif (board == 'mcx'): - if (user == 'root'): - password = 'passwordformcxrootfs' - else: - if (user == 'root'): - password = '' - -- prepare board config file - Each board which is found in the VL needs a tbot configuration file - pass the config file name with the option '-c' to tbot, tbot searches - in the root dir for them. - - board Example (dxr2 board): - https://github.com/hsdenx/tbot/blob/master/tbot_dxr2.cfg - - Necessary variables: - - line 3: boardname, here it is the "etamin" board - no default value, must be set. - line 4: boardlabname: name used for connecting to the board - may differ from tb.boardname, default tb.boardname - line 5: boardlabpowername: name used for power on/off - may differ from tb.boardname, default tb.boardname - line 6: tftpboardname: name used for tftp subdir (from where - U-Boot loads images for example). - may differ from tb.boardname, default tb.boardname - line 7: labprompt: linux prompt tbot sets - no defaultvalue, must be set (maybe we should introduce - "ttbott" as default ... - line 8: debug: If True, adds debug output on the tbot shell - line 9: debugstatus: enable status debug output on the shell - line 10: ip: Where tbot finds the Lab PC - line 11: user: As which user does tbot logs into the Lab PC - line 12: accept_all: passed to paramiko, accept all connections - line 13: keepalivetimout: passed to paramiko, timeout for sending - keepalive message. - line 14: channel_timeout: passed to paramiko - line 15: loglevel: tbots loglevel for adding entries into the logfile. - line 17: wdt_timeout: timeout in seconds for tbots watchdog. - Watchdog gets triggered if prompt get read. - line 24: tc_lab_denx_connect_to_board_tc: Which TC is used for - connecting to the boards console the TC, here: - https://github.com/hsdenx/tbot/blob/master/src/tc/tc_workfd_connect_with_kermit.py - line 27: uboot_prompt: boards U-Boot prompt - line 28: linux_prompt: boards linux prompt - - Now comes a list of variables TC needs, this vary from which TC - you start on the board. - -Thats it ... you now can call tbot and hopefully, it works ;-) -Find an example log [3] for calling simple U-Boot TC for setting -an U-Boot Environmentvariable. - -If you have problems in setting tbot up, please contact me -(and may give me ssh access to your Lab PC ;-) - -If you have running your first TC [3], you may want to write now your own -TC (and hopefully share them), so continue with: -u-boot:tools/tbot/README.create_a_new_testcase - -Heiko Schocher -v2 2016.04.26 - --------------- - -[1] tbot Dokumentation: - [2] u-boot:/tools/tbot/README - https://github.com/hsdenx/tbot/blob/master/README.md - tbot-devel@googlegroups.com - -[3] Example for a first U-Boot TC which should always work: - (with commandline option "-v" for verbose output): -hs@localhost:tbot [event-devel] $ python2.7 src/common/tbot.py -c tbot_dxr2.cfg -t tc_ub_setenv.py -v -l log/tbot.log -**** option cfg: tbot_dxr2.cfg log: log/tbot.log tc: tc_ub_setenv.py v 1 -('CUR WORK PATH: ', '/home/hs/data/Entwicklung/tbot') -('CFGFILE ', 'tbot_dxr2.cfg') -('LOGFILE ', '/home/hs/data/Entwicklung/tbot/log/tbot.log') -tb_ctrl: Last login: Mon Apr 25 14:52:42 2016 from 87.97.29.27 -************************************************************* -BDI2000 Assignment: (last updated: 2015-11-20 12:30 MET) -bdi1 => techem bdi2 => cetec_mx25 bdi3 => lpc3250 -bdi4 => - bdi5 => --Rev.B!-- bdi6 => tqm5200s -bdi7 => [stefano] bdi8 => smartweb bdi9 => sigmatek-nand -bdi10 => pcm052 bdi11 => socrates bdi12 => aristainetos -bdi13 => imx53 bdi14 => ib8315 bdi15 => cairo -bdi16 => g2c1 bdi17 => lwe090 bdi18 => symphony -bdi19 => dxr2 bdi20 => ima3-mx6 bdi21 => sama5d3 -bdi98 => - bdi99 => - bdi0 => - -Please power off unused systems when you leave! Thanks, wd. -************************************************************* -tb_ctrl: pollux:~ hs $ -tb_ctrl: export PS1=ttbott -ttbott -tb_ctrl: stty cols 200 -ttbott -tb_ctrl: export TERM=vt200 -ttbott -tb_ctrl: echo $COLUMNS -200 -ttbott -tb_con: Last login: Tue Apr 26 06:28:59 2016 from 87.97.29.27 -************************************************************* -BDI2000 Assignment: (last updated: 2015-11-20 12:30 MET) -bdi1 => techem bdi2 => cetec_mx25 bdi3 => lpc3250 -bdi4 => - bdi5 => --Rev.B!-- bdi6 => tqm5200s -bdi7 => [stefano] bdi8 => smartweb bdi9 => sigmatek-nand -bdi10 => pcm052 bdi11 => socrates bdi12 => aristainetos -bdi13 => imx53 bdi14 => ib8315 bdi15 => cairo -bdi16 => g2c1 bdi17 => lwe090 bdi18 => symphony -bdi19 => dxr2 bdi20 => ima3-mx6 bdi21 => sama5d3 -bdi98 => - bdi99 => - bdi0 => - -Please power off unused systems when you leave! Thanks, wd. -************************************************************* -tb_con: pollux:~ hs $ -tb_con: export PS1=ttbot -tb_con: t -ttbott -tb_con: stty cols 200 -ttbott -tb_con: export TERM=vt200 -ttbott -tb_con: echo $COLUMNS -200 -ttbott -tb_con: ssh hs@lena -tb_con: hs@lena's password: -tb_con: -tb_con: Last login: Mon Apr 25 07:03:29 2016 from 192.168.1.1 -tb_con: [hs@lena ~]$ -tb_con: export PS1=ttbott -ttbott -tb_con: stty cols 200 -ttbott -tb_con: export TERM=vt200 -ttbott -tb_con: echo $COLUMNS -200 -ttbott -tb_con: kermit -C-Kermit 8.0.211, 10 Apr 2004, for Linux - Copyright (C) 1985, 2004, - Trustees of Columbia University in the City of New York. -Type ? or HELP for help. -(/home/hs/) C-Kermit> -tb_con: set line /dev/ttyUSB0 -(/home/hs/) C-Kermit> -tb_con: set speed 115200 -/dev/ttyUSB0, 115200 bps -(/home/hs/) C-Kermit> -tb_con: set flow-control none -(/home/hs/) C-Kermit> -tb_con: set carrier-watch off -(/home/hs/) C-Kermit> -tb_con: connect -Connecting to /dev/ttyUSB0, speed 115200 - Escape character: Ctrl-\ (ASCII 28, FS): enabled -Type the escape character followed by C to get back, -or followed by ? to see other options. ----------------------------------------------------- -tb_con: -U-Boot# -tb_con: U-Boot# -U-Boot# -tb_con: setenv Heiko Schocher -U-Boot# -tb_con: printenv Heiko -Heiko=Schocher -U-Boot# -[('tc_workfd_ssh.py', 1, 0), ('tc_workfd_connect_with_kermit.py', 1, 0), ('tc_ub_setenv.py', 1, 0)] -End of TBOT: success -hs@localhost:tbot [event-devel] $