From: Devin Heitmueller Date: Thu, 20 Nov 2008 12:53:05 +0000 (-0300) Subject: V4L/DVB (9658): em28xx: use em28xx_write_reg() for i2c clock setup X-Git-Tag: v3.12-rc1~16854^2~378 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=23159a0bfcfb329cf68c7a7259e688494273bb7f;p=kernel%2Fkernel-generic.git V4L/DVB (9658): em28xx: use em28xx_write_reg() for i2c clock setup Convert the calls that write the i2c clock register over to the new em28xx_write_reg() function that allows for or'ing bits Signed-off-by: Devin Heitmueller Signed-off-by: Mauro Carvalho Chehab --- diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c index d73d661..1b4488a 100644 --- a/drivers/media/video/em28xx/em28xx-cards.c +++ b/drivers/media/video/em28xx/em28xx-cards.c @@ -1400,7 +1400,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2883_BOARD_KWORLD_HYBRID_A316: case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); msleep(50); /* Sets GPO/GPIO sequences for this device */ @@ -1412,7 +1414,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2882_BOARD_TERRATEC_HYBRID_XS: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); msleep(50); /* should be added ir_codes here */ @@ -1432,7 +1436,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2870_BOARD_KWORLD_350U: case EM2881_BOARD_DNT_DA2_HYBRID: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); msleep(50); /* NOTE: EM2881_DNT_DA2_HYBRID spend 140 msleep for digital @@ -1449,7 +1455,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2880_BOARD_MSI_DIGIVOX_AD: case EM2880_BOARD_MSI_DIGIVOX_AD_II: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); msleep(50); /* Sets GPO/GPIO sequences for this device */ @@ -1466,7 +1474,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2861_BOARD_PLEXTOR_PX_TV100U: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); /* FIXME guess */ /* Turn on analog audio output */ em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1); @@ -1475,7 +1485,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2861_BOARD_KWORLD_PVRTV_300U: case EM2880_BOARD_KWORLD_DVB_305U: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x4c", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); msleep(10); em28xx_write_regs(dev, 0x08, "\x6d", 1); msleep(10); @@ -1485,7 +1497,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2870_BOARD_KWORLD_355U: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); msleep(50); /* Sets GPO/GPIO sequences for this device */ @@ -1494,7 +1508,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2870_BOARD_COMPRO_VIDEOMATE: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); /* TODO: someone can do some cleanup here... not everything's needed */ em28xx_write_regs(dev, 0x04, "\x00", 1); @@ -1513,7 +1529,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2870_BOARD_TERRATEC_XS_MT2060: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); /* this device needs some gpio writes to get the DVB-T demod work */ em28xx_write_regs(dev, 0x08, "\xfe", 1); @@ -1525,7 +1543,10 @@ void em28xx_pre_card_setup(struct em28xx *dev) break; case EM2870_BOARD_PINNACLE_PCTV_DVB: - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); + /* this device needs some gpio writes to get the DVB-T demod work */ em28xx_write_regs(dev, 0x08, "\xfe", 1); @@ -1541,7 +1562,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2820_BOARD_GADMEI_UTV310: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); /* Turn on analog audio output */ em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1); break; @@ -1549,20 +1572,27 @@ void em28xx_pre_card_setup(struct em28xx *dev) case EM2860_BOARD_GADMEI_UTV330: /* Turn on IR */ em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x07", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); /* should be added ir_codes here */ break; case EM2820_BOARD_MSI_VOX_USB_2: em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1); - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1); + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_100_KHZ); /* enables audio for that device */ em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1); break; case EM2874_BOARD_PINNACLE_PCTV_80E: - /* Set 400 KHz clock */ - em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x45", 1); + /* Set 400 KHz clock and select secondary i2c bus */ + em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, + EM28XX_I2C_CLK_WAIT_ENABLE | + EM2874_I2C_SECONDARY_BUS_SELECT | + EM28XX_I2C_FREQ_400_KHZ); dev->digital_gpio = em2874_pinnacle_80e_digital; break; diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h index 9727f38..98e9505 100644 --- a/drivers/media/video/em28xx/em28xx-reg.h +++ b/drivers/media/video/em28xx/em28xx-reg.h @@ -32,6 +32,19 @@ #define EM28XX_R08_GPIO 0x08 /* em2820 or upper */ #define EM28XX_R06_I2C_CLK 0x06 + +/* em28xx I2C Clock Register (0x06) */ +#define EM28XX_I2C_CLK_ACK_LAST_READ 0x80 +#define EM28XX_I2C_CLK_WAIT_ENABLE 0x40 +#define EM28XX_I2C_EEPROM_ON_BOARD 0x08 +#define EM28XX_I2C_EEPROM_KEY_VALID 0x04 +#define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */ +#define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */ +#define EM28XX_I2C_FREQ_25_KHZ 0x02 +#define EM28XX_I2C_FREQ_400_KHZ 0x01 +#define EM28XX_I2C_FREQ_100_KHZ 0x00 + + #define EM28XX_R0A_CHIPID 0x0a #define EM28XX_R0C_USBSUSP 0x0c /* */