From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 8 May 2023 13:01:37 +0000 (+0200)
Subject: freedreno: Add some A6/7xx registers
X-Git-Tag: upstream/23.3.3~8358
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=22fb6e3906e9c20b6a0bba3c72c0f2478b9e7a26;p=platform%2Fupstream%2Fmesa.git

freedreno: Add some A6/7xx registers

Can be found in recent downstream kernels.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22901>
---

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index fecc903..c4af1b8 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -1875,13 +1875,13 @@ registers-gmu:
 	00000000	GMU_HOST2GMU_INTR_INFO_2: 0
 	00000000	GMU_HOST2GMU_INTR_INFO_3: 0
 	10010000	0x51c0: 10010000
-	babeface	0x51c5: babeface
+	babeface	GMU_GENERAL_0: 0xbabeface
 	00000000	GMU_GENERAL_1: 0
 	00000000	0x51c7: 00000000
 	00000000	0x51c8: 00000000
 	60005018	0x51c9: 60005018
 	60005048	0x51ca: 60005048
-	00000000	0x51cb: 00000000
+	00000000	GMU_GENERAL_6: 0
 	00000001	GMU_GENERAL_7: 0x1
 	00000000	0x51e0: 00000000
 	00000000	0x51e1: 00000000
@@ -2171,7 +2171,7 @@ registers-gmu:
 	802800a0	GMU_AHB_FENCE_RANGE_0: 0x802800a0
 	00000000	GMU_AHB_FENCE_RANGE_1: 0
 	00000000	GMU_AHB_FENCE_STATUS: 0
-	00000000	0x9314: 00000000
+	00000000	GMU_AHB_FENCE_STATUS_CLR: 0
 	00000001	GMU_RBBM_INT_UNMASKED_STATUS: 0x1
 	00000000	GMU_AO_SPARE_CNTL: 0
 	00000000	0x9400: 00000000
diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
index 99c8712..b2f1fbe 100644
--- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
@@ -13309,13 +13309,13 @@ registers-gmu:
 	00000000	GMU_HOST2GMU_INTR_INFO_2: 0
 	00000000	GMU_HOST2GMU_INTR_INFO_3: 0
 	10010000	0x51c0: 10010000
-	babeface	0x51c5: babeface
+	babeface	GMU_GENERAL_0: 0xbabeface
 	00000000	GMU_GENERAL_1: 0
 	00000000	0x51c7: 00000000
 	00000000	0x51c8: 00000000
 	60005018	0x51c9: 60005018
 	60005048	0x51ca: 60005048
-	00000000	0x51cb: 00000000
+	00000000	GMU_GENERAL_6: 0
 	00000001	GMU_GENERAL_7: 0x1
 	00000000	0x51e0: 00000000
 	00000000	0x51e1: 00000000
@@ -13343,7 +13343,7 @@ registers-gmu:
 	802800a0	GMU_AHB_FENCE_RANGE_0: 0x802800a0
 	00000000	GMU_AHB_FENCE_RANGE_1: 0
 	00000000	GMU_AHB_FENCE_STATUS: 0
-	00000000	0x9314: 00000000
+	00000000	GMU_AHB_FENCE_STATUS_CLR: 0
 	00000001	GMU_RBBM_INT_UNMASKED_STATUS: 0x1
 	00000000	GMU_AO_SPARE_CNTL: 0
 	00000000	0x9400: 00000000
diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
index b337741..94127b4 100644
--- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log
+++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
@@ -147511,13 +147511,13 @@ registers-gmu:
 	00000000	GMU_HOST2GMU_INTR_INFO_2: 0
 	00000000	GMU_HOST2GMU_INTR_INFO_3: 0
 	10010000	0x51c0: 10010000
-	babeface	0x51c5: babeface
+	babeface	GMU_GENERAL_0: 0xbabeface
 	00000000	GMU_GENERAL_1: 0
 	00000000	0x51c7: 00000000
 	00000000	0x51c8: 00000000
 	60005018	0x51c9: 60005018
 	60005048	0x51ca: 60005048
-	00000000	0x51cb: 00000000
+	00000000	GMU_GENERAL_6: 0
 	00000001	GMU_GENERAL_7: 0x1
 	00000000	0x51e0: 00000000
 	00000000	0x51e1: 00000000
@@ -147545,7 +147545,7 @@ registers-gmu:
 	802800a0	GMU_AHB_FENCE_RANGE_0: 0x802800a0
 	00000000	GMU_AHB_FENCE_RANGE_1: 0
 	00000000	GMU_AHB_FENCE_STATUS: 0
-	00000000	0x9314: 00000000
+	00000000	GMU_AHB_FENCE_STATUS_CLR: 0
 	00000001	GMU_RBBM_INT_UNMASKED_STATUS: 0x1
 	00000000	GMU_AO_SPARE_CNTL: 0
 	00000000	0x9400: 00000000
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 9969741..002c5ad 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1031,7 +1031,23 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0825" name="CP_STATUS_1"/>
 	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
 	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
-	<reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
+	<reg32 offset="0x0844" name="CP_APRIV_CNTL">
+		<!-- Crashdumper writes -->
+		<bitfield pos="6" name="CDWRITE" type="boolean"/>
+		<!-- Crashdumper reads -->
+		<bitfield pos="5" name="CDREAD" type="boolean"/>
+
+		<!-- 4 is unknown -->
+
+		<!-- RPTR shadow writes -->
+		<bitfield pos="3" name="RBRPWB" type="boolean"/>
+		<!-- Memory accesses from PM4 packets in the ringbuffer -->
+		<bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>
+		<!-- Ringbuffer reads -->
+		<bitfield pos="1" name="RBFETCH" type="boolean"/>
+		<!-- Instruction cache fetches -->
+		<bitfield pos="0" name="ICACHE" type="boolean"/>
+	</reg32>
 	<!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
 	<reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
 	<!-- all the threshold values seem to be in units of quad-dwords: -->
@@ -1460,6 +1476,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
 	<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
 	<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
+	<reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX"/>
 	<reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>
 
 	<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
@@ -4385,9 +4402,10 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
 </domain>
 
-<domain name="A6XX_CX_MISC" width="32">
+<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">
 	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
 	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
+	<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX"/>
 </domain>
 
 </database>
diff --git a/src/freedreno/registers/adreno/a6xx_gmu.xml b/src/freedreno/registers/adreno/a6xx_gmu.xml
index 3e3acb0..1defe31 100644
--- a/src/freedreno/registers/adreno/a6xx_gmu.xml
+++ b/src/freedreno/registers/adreno/a6xx_gmu.xml
@@ -147,8 +147,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
 	<reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
 	<reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
+	<reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
 	<reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
+	<reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
 	<reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
+	<reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
+	<reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
+	<reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
 	<reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
 	<reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
 	<reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
@@ -187,6 +192,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
 	<reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
 	<reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
+	<reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
 	<reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
 	<reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
 	<reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
@@ -211,6 +217,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/>
 	<reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/>
 	<reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/>
+	<reg32 offset="0x0154" name="RSCC_SEQ_MEM_0_DRV0_A740" variants="A7XX"/>
 	<reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/>
 	<reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/>
 	<reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>