From: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Date: Wed, 25 Sep 2013 13:33:10 +0000 (+0400)
Subject: net: designware: Respect "bus mode" register contents on SW reset
X-Git-Tag: v2014.01-rc1~2^2~20
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=227ad7b2b6fab024fff6f60613b0e90c9e3a6724;p=platform%2Fkernel%2Fu-boot.git

net: designware: Respect "bus mode" register contents on SW reset

"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
---

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 8413d57..22155b4 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -96,7 +96,7 @@ static int mac_reset(struct eth_device *dev)
 	ulong start;
 	int timeout = CONFIG_MACRESET_TIMEOUT;
 
-	writel(DMAMAC_SRST, &dma_p->busmode);
+	writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
 
 	if (priv->interface != PHY_INTERFACE_MODE_RGMII)
 		writel(MII_PORTSELECT, &mac_p->conf);