From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Thu, 16 Jul 2015 20:48:50 +0000 (-0500)
Subject: ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache
X-Git-Tag: v4.3-rc1~120^2~38^2~6
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2211a658620a35f3b3eabdfa2587f46b7abf3ee7;p=platform%2Fkernel%2Flinux-exynos.git

ARM: dts: socfpga: enable the data and instruction prefetch for the l2 cache

Just in case the firmware did not enable data and instruction prefetch in
the L2 cache controller, we enable it in the kernel.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 80f924d..1e3c833 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -639,6 +639,8 @@
 			cache-level = <2>;
 			arm,tag-latency = <1 1 1>;
 			arm,data-latency = <2 1 1>;
+			prefetch-data = <1>;
+			prefetch-instr = <1>;
 		};
 
 		mmc: dwmmc0@ff704000 {