From: Nicholas Piggin <npiggin@gmail.com>
Date: Wed, 6 Mar 2019 21:28:31 +0000 (+0800)
Subject: nios2: Fix update_mmu_cache preload the TLB with the new PTE
X-Git-Tag: v5.4-rc1~1448^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=21e6bff5e0ef0033d776e64c40e6873d7c75e74b;p=platform%2Fkernel%2Flinux-rpi.git

nios2: Fix update_mmu_cache preload the TLB with the new PTE

There is a bug in the TLB preload caused by the pid not being
shifted to the correct location in tlbmisc register.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
---

diff --git a/arch/nios2/mm/tlb.c b/arch/nios2/mm/tlb.c
index af871188..7fea59e 100644
--- a/arch/nios2/mm/tlb.c
+++ b/arch/nios2/mm/tlb.c
@@ -70,7 +70,8 @@ static void replace_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, unsig
 		if (pid != mmu_pid)
 			continue;
 
-		tlbmisc = mmu_pid | TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
+		tlbmisc = (mmu_pid << TLBMISC_PID_SHIFT) | TLBMISC_WE |
+			  (way << TLBMISC_WAY_SHIFT);
 		WRCTL(CTL_TLBMISC, tlbmisc);
 		if (tlbacc == 0)
 			WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));