From: Romain Perier Date: Mon, 4 Sep 2017 08:51:17 +0000 (+0200) Subject: clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs X-Git-Tag: v4.19~2132^2~17^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=216ac5297a8083ac4a27a6cbc3d20d13dd17984d;p=platform%2Fkernel%2Flinux-rpi.git clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs This exports the clock for the pclk gate of the eFuse that is part of the RK3368 SoCs. So we can use it from the dt-bindings. Signed-off-by: Romain Perier Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index fc56565..7c4d242 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS), GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS), GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS), - GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS), + GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS), GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS), /*