From: Neil Armstrong Date: Wed, 21 Nov 2018 11:19:22 +0000 (+0100) Subject: clk: meson: Fix GXL HDMI PLL fractional bits width X-Git-Tag: v5.4-rc1~1882^2~7^5^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=21310c39ec01e82ef3ef9bf8ac385b53ccdc158c;p=platform%2Fkernel%2Flinux-rpi.git clk: meson: Fix GXL HDMI PLL fractional bits width The GXL Documentation specifies 12 bits for the Fractional bit field, bit the last bits have a different purpose that we cannot handle right now, so update the bitwidth to have correct fractional calculations. Signed-off-by: Neil Armstrong [narmstrong: added comment on GXL HHI_HDMI_PLL_CNTL register shift] Acked-by: Martin Blumenstingl Link: https://lkml.kernel.org/r/20181121111922.1277-1-narmstrong@baylibre.com --- diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 30fbf8f..794f649 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -216,10 +216,16 @@ static struct clk_regmap gxl_hdmi_pll_dco = { .shift = 9, .width = 5, }, + /* + * On gxl, there is a register shift due to + * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, + * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB + * instead which is defined at the same offset. + */ .frac = { .reg_off = HHI_HDMI_PLL_CNTL2, .shift = 0, - .width = 12, + .width = 10, }, .l = { .reg_off = HHI_HDMI_PLL_CNTL,