From: samin Date: Wed, 5 Jan 2022 06:27:50 +0000 (+0800) Subject: dt-bingings:reset:jh7110: Add isp/vout domain reset define. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=20c26454af1dd9f777f551d00fe9c62a0085a91d;p=platform%2Fkernel%2Flinux-starfive.git dt-bingings:reset:jh7110: Add isp/vout domain reset define. isp/vout domain are independent of other CRGS. Signed-off-by: samin --- diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h index b8cddb2..8b5e121 100644 --- a/include/dt-bindings/reset/starfive-jh7110.h +++ b/include/dt-bindings/reset/starfive-jh7110.h @@ -181,7 +181,37 @@ #define RSTN_U0_RTC_HMS_APB 165 #define RSTN_U0_RTC_HMS_CAL 166 #define RSTN_U0_RTC_HMS_OSC32K 167 +/* + * group[6]: ispcrg + */ +#define RSTN_U0_ISPV2_TOP_WRAPPER_P 192 +#define RSTN_U0_ISPV2_TOP_WRAPPER_C 193 +#define RSTN_U0_M31DPHY_HW 194 +#define RSTN_U0_M31DPHY_B09_ALWAYS_ON 195 +#define RSTN_U0_VIN_N_PCLK 196 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF0 197 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF1 198 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF2 199 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF3 200 +#define RSTN_U0_VIN_N_SYS_CLK 201 +#define RSTN_U0_VIN_P_AXIRD 202 +#define RSTN_U0_VIN_P_AXIWR 203 +/* + * group[7]: voutcrg + */ +#define RSTN_U0_DC8200_AXI 224 +#define RSTN_U0_DC8200_AHB 225 +#define RSTN_U0_DC8200_CORE 226 +#define RSTN_U0_CDNS_DSITX_DPI 227 +#define RSTN_U0_CDNS_DSITX_APB 228 +#define RSTN_U0_CDNS_DSITX_RXESC 229 +#define RSTN_U0_CDNS_DSITX_SYS 230 +#define RSTN_U0_CDNS_DSITX_TXBYTEHS 231 +#define RSTN_U0_CDNS_DSITX_TXESC 232 +#define RSTN_U0_HDMI_TX_HDMI 233 +#define RSTN_U0_MIPITX_DPHY_SYS 234 +#define RSTN_U0_MIPITX_DPHY_TXBYTEHS 235 -#define RSTN_JH7110_RESET_END 168 +#define RSTN_JH7110_RESET_END 236 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */