From: Andy Shevchenko Date: Mon, 19 Dec 2022 12:32:29 +0000 (+0200) Subject: pinctrl: intel: Use same order of bit fields for PADCFG2 X-Git-Tag: v6.6.7~3483^2~16^2~11 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=203a1c3ecae70076e14a652ca44b7ad9302eecd3;p=platform%2Fkernel%2Flinux-starfive.git pinctrl: intel: Use same order of bit fields for PADCFG2 PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. No functional changes intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index ad32e3c..038a572 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -88,9 +88,9 @@ #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) #define PADCFG2 0x008 -#define PADCFG2_DEBEN BIT(0) #define PADCFG2_DEBOUNCE_SHIFT 1 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) +#define PADCFG2_DEBEN BIT(0) #define DEBOUNCE_PERIOD_NSEC 31250