From: Marek Olšák Date: Sun, 29 Jan 2012 04:22:00 +0000 (+0100) Subject: r600g: don't add PA_SC_LINE_STIPPLE to rasterizer_state X-Git-Tag: 062012170305~1759 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=2000086fcd5174f121f61dd6df5948c67101e148;p=profile%2Fivi%2Fmesa.git r600g: don't add PA_SC_LINE_STIPPLE to rasterizer_state It's always emitted in draw_vbo. Reviewed-by: Dave Airlie Reviewed-by: Alex Deucher --- diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 9f9a6a1..a5a443c 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -889,6 +889,9 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, rs->sprite_coord_enable = state->sprite_coord_enable; rs->two_side = state->light_twoside; rs->clip_plane_enable = state->clip_plane_enable; + rs->pa_sc_line_stipple = state->line_stipple_enable ? + S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | + S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; clip_rule = state->scissor ? 0xAAAA : 0xFFFF; @@ -946,14 +949,6 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, tmp = (unsigned)state->line_width * 8; r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0); - - if (state->line_stipple_enable) { - r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, - S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | - S_028A0C_REPEAT_COUNT(state->line_stipple_factor), - 0x9FFFFFFF, NULL, 0); - } - r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable), 0xFFFFFFFF, NULL, 0); diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index b7c5e55..d4578bd 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -109,6 +109,7 @@ struct r600_pipe_rasterizer { boolean two_side; unsigned sprite_coord_enable; unsigned clip_plane_enable; + unsigned pa_sc_line_stipple; float offset_units; float offset_scale; }; @@ -209,6 +210,7 @@ struct r600_pipe_context { struct pipe_framebuffer_state framebuffer; unsigned cb_target_mask; unsigned cb_color_control; + unsigned pa_sc_line_stipple; /* for saving when using blitter */ struct pipe_stencil_ref stencil_ref; struct pipe_viewport_state viewport; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index e1d8ab3..ae9f797 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -943,6 +943,9 @@ static void *r600_create_rs_state(struct pipe_context *ctx, rs->sprite_coord_enable = state->sprite_coord_enable; rs->two_side = state->light_twoside; rs->clip_plane_enable = state->clip_plane_enable; + rs->pa_sc_line_stipple = state->line_stipple_enable ? + S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | + S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; clip_rule = state->scissor ? 0xAAAA : 0xFFFF; /* offset */ @@ -1000,13 +1003,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx, tmp = (unsigned)state->line_width * 8; r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0); - if (state->line_stipple_enable) { - r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, - S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | - S_028A0C_REPEAT_COUNT(state->line_stipple_factor), - 0x9FFFFFFF, NULL, 0); - } - if (rctx->chip_class >= R700) sc_mode_cntl = 0x514002; else diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 9833de0..84ccd5e 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -166,6 +166,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state) rctx->sprite_coord_enable = rs->sprite_coord_enable; rctx->two_side = rs->two_side; + rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; rctx->rasterizer = rs; @@ -752,9 +753,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0); - r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, - 0, - S_028A0C_AUTO_RESET_CNTL(3), NULL, 0); + r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0xFFFFFFFF, NULL, 0); r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, S_028814_PROVOKING_VTX_LAST(1), NULL, 0); @@ -777,7 +776,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) ls_mask = 1; else if (prim == V_008958_DI_PT_LINESTRIP) ls_mask = 2; - r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask)); + r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple); if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) { r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));