From: Conor Dooley <conor.dooley@microchip.com>
Date: Thu, 15 Jun 2023 22:50:15 +0000 (+0100)
Subject: dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
X-Git-Tag: v6.6.7~2493^2^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1ffe6ddc5c64f88b1ec2e250327defb5446a7904;p=platform%2Fkernel%2Flinux-starfive.git

dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

To permit validation of cpu nodes, swap "additionalProperties: true"
out for "unevaluatedProperties: false".

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230615-viper-stoic-1ff8efd7d51d@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e89a10d..144da86 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -143,7 +143,7 @@ required:
   - riscv,isa
   - interrupt-controller
 
-additionalProperties: true
+unevaluatedProperties: false
 
 examples:
   - |