From: James Hogan <james.hogan@imgtec.com>
Date: Wed, 27 Feb 2013 21:54:51 +0000 (+0000)
Subject: metag: perf: don't reset TXTACTCYC
X-Git-Tag: upstream/snapshot3+hdmi~5254^2~11
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1fb4dc5c39af941d3abc597337e0ea776bfce0f2;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git

metag: perf: don't reset TXTACTCYC

The thread active cycle counter TXTACTCYC is used in __delay so it
shouldn't really be reset to zero by perf. Fix perf to just read the
value, and instead of clearing it, record the prev_count value in
enable_counter so that the delta calculations know about the previous
value.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
---

diff --git a/arch/metag/kernel/perf/perf_event.c b/arch/metag/kernel/perf/perf_event.c
index 54fde35..a1eff36 100644
--- a/arch/metag/kernel/perf/perf_event.c
+++ b/arch/metag/kernel/perf/perf_event.c
@@ -617,9 +617,7 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
 		WARN_ONCE((config != 0x100),
 			"invalid configuration (%d) for counter (%d)\n",
 			config, idx);
-
-		/* Reset the cycle count */
-		__core_reg_set(TXTACTCYC, 0);
+		local64_set(&event->prev_count, __core_reg_get(TXTACTCYC));
 		goto unlock;
 	}
 
@@ -708,9 +706,8 @@ static u64 metag_pmu_read_counter(int idx)
 {
 	u32 tmp = 0;
 
-	/* The act of reading the cycle counter also clears it */
 	if (METAG_INST_COUNTER == idx) {
-		__core_reg_swap(TXTACTCYC, tmp);
+		tmp = __core_reg_get(TXTACTCYC);
 		goto out;
 	}