From: Tom Musta Date: Tue, 12 Aug 2014 13:45:06 +0000 (-0500) Subject: target-ppc: Bug Fix: mullw X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~604^2~22 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1fa74845f2bab36bfa37108b9054b53c1b8264b9;p=sdk%2Femulator%2Fqemu.git target-ppc: Bug Fix: mullw For 64-bit implementations, the mullw result is the 64 bit product of the sign-extended least significant 32 bits of the source registers. Fix the code to properly sign extend the source operands and produce a 64 bit product. Example: R3 00000000002F37A0 R4 41C33D242F816715 mullw 3,3,4 R3 expected : 0008C3146AE0F020 R3 actual : 000000006AE0F020 (without this patch) Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- diff --git a/target-ppc/translate.c b/target-ppc/translate.c index dc80b02..b19eb14 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1128,9 +1128,20 @@ static void gen_mulhwu(DisasContext *ctx) /* mullw mullw. */ static void gen_mullw(DisasContext *ctx) { +#if defined(TARGET_PPC64) + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); + tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); +#else tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); +#endif if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); }