From: Michael S. Tsirkin <mst@redhat.com>
Date: Wed, 25 Nov 2009 10:00:10 +0000 (+0200)
Subject: msix: fix reset value for enable bit
X-Git-Tag: Tizen_Studio_1.3_Release_p2.3.1~1405^2~17^2~6023^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1f944c661a821774e7b8cfbf5560a238795f2a60;p=sdk%2Femulator%2Fqemu.git

msix: fix reset value for enable bit

On reset, we currently clear all bits in msix control register *except*
enable bit.  This is wrong: the spec says we should clear writeable
bits: function mask and enable bit.
Correct this.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---

diff --git a/hw/msix.c b/hw/msix.c
index 45f83dd716..785e097d80 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -361,7 +361,8 @@ void msix_reset(PCIDevice *dev)
     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
         return;
     msix_free_irq_entries(dev);
-    dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
+    dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &=
+	    ~dev->wmask[dev->msix_cap + MSIX_ENABLE_OFFSET];
     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
     msix_mask_all(dev, dev->msix_entries_nr);
 }