From: Bastian Koppelmann Date: Mon, 21 Mar 2016 08:03:01 +0000 (+0100) Subject: target-tricore: add missing break in insn decode switch stmt X-Git-Tag: TizenStudio_2.0_p2.4~27^2~6^2~8^2~95^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1f75cba8f8e0acb079b196e73874595b9523094f;p=sdk%2Femulator%2Fqemu.git target-tricore: add missing break in insn decode switch stmt After decoding/translating a RRR_DIVIDE/RRRR_EXTRACT_INSERT type instruction we would simply fall through and would decode/translate another unintended RRR2_MADD/RRRW_EXTRACT_INSERT instruction. Signed-off-by: Bastian Koppelmann Message-Id: <1458547383-23102-2-git-send-email-kbastian@mail.uni-paderborn.de> --- diff --git a/target-tricore/translate.c b/target-tricore/translate.c index d13e5c8..66f798a 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8632,6 +8632,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; case OPCM_32_RRR_DIVIDE: decode_rrr_divide(env, ctx); + break; /* RRR2 Format */ case OPCM_32_RRR2_MADD: decode_rrr2_madd(env, ctx); @@ -8661,6 +8662,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) /* RRRR format */ case OPCM_32_RRRR_EXTRACT_INSERT: decode_rrrr_extract_insert(env, ctx); + break; /* RRRW format */ case OPCM_32_RRRW_EXTRACT_INSERT: decode_rrrw_extract_insert(env, ctx);