From: James Greenhalgh <james.greenhalgh@arm.com>
Date: Mon, 20 Jun 2016 13:40:07 +0000 (+0000)
Subject: [Patch AArch64] Fixup to fcvt patterns added in r237200
X-Git-Tag: upstream/12.2.0~46302
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1f0e9e34f557ca2e184e91720429a2fda1988b69;p=platform%2Fupstream%2Fgcc.git

[Patch AArch64] Fixup to fcvt patterns added in r237200

gcc/

	* config/aarch64/aarch64.md
	(<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3): Add attributes to
	iterators.
	(<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Likewise.  Correct
	attributes.
	* config/aarch64/aarch64-builtins.c
	(aarch64_types_binop_uss_qualifiers): Delete.
	(TYPES_BINOP_USS): Likewise.
	(aarch64_types_binop_sus_qualifiers): Likewise.
	(TYPES_BINOP_SUS): Likewise.
	(aarch64_types_fcvt_from_unsigned_qualifiers): New.
	(TYPES_FCVTIMM_SUS): Likewise.
	* config/aarch64/aarch64-simd-builtins.def (scvtf): Use SHIFTIMM
	rather than BINOP.
	(ucvtf): Use FCVTIMM_SUS rather than BINOP_SUS.
	(fcvtzs): Use SHIFTIMM rather than BINOP.
	(fcvtzu): Use SHIFTIMM_USS rather than BINOP_USS.

From-SVN: r237602
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e6f7e9e..1e01322 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,25 @@
 2016-06-20  James Greenhalgh  <james.greenhalgh@arm.com>
 
+	* config/aarch64/aarch64.md
+	(<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3): Add attributes to
+	iterators.
+	(<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3): Likewise.  Correct
+	attributes.
+	* config/aarch64/aarch64-builtins.c
+	(aarch64_types_binop_uss_qualifiers): Delete.
+	(TYPES_BINOP_USS): Likewise.
+	(aarch64_types_binop_sus_qualifiers): Likewise.
+	(TYPES_BINOP_SUS): Likewise.
+	(aarch64_types_fcvt_from_unsigned_qualifiers): New.
+	(TYPES_FCVTIMM_SUS): Likewise.
+	* config/aarch64/aarch64-simd-builtins.def (scvtf): Use SHIFTIMM
+	rather than BINOP.
+	(ucvtf): Use FCVTIMM_SUS rather than BINOP_SUS.
+	(fcvtzs): Use SHIFTIMM rather than BINOP.
+	(fcvtzu): Use SHIFTIMM_USS rather than BINOP_USS.
+
+2016-06-20  James Greenhalgh  <james.greenhalgh@arm.com>
+
 	* config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Make FP
 	costs relative to the cost of a register move.
 
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 262ea1c..6b90b2a 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -139,14 +139,6 @@ aarch64_types_binop_ssu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_unsigned };
 #define TYPES_BINOP_SSU (aarch64_types_binop_ssu_qualifiers)
 static enum aarch64_type_qualifiers
-aarch64_types_binop_uss_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-  = { qualifier_unsigned, qualifier_none, qualifier_none };
-#define TYPES_BINOP_USS (aarch64_types_binop_uss_qualifiers)
-static enum aarch64_type_qualifiers
-aarch64_types_binop_sus_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-  = { qualifier_none, qualifier_unsigned, qualifier_none };
-#define TYPES_BINOP_SUS (aarch64_types_binop_sus_qualifiers)
-static enum aarch64_type_qualifiers
 aarch64_types_binopp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_poly, qualifier_poly, qualifier_poly };
 #define TYPES_BINOPP (aarch64_types_binopp_qualifiers)
@@ -181,6 +173,10 @@ aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_none, qualifier_immediate };
 #define TYPES_SHIFTIMM_USS (aarch64_types_shift_to_unsigned_qualifiers)
 static enum aarch64_type_qualifiers
+aarch64_types_fcvt_from_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+  = { qualifier_none, qualifier_unsigned, qualifier_immediate };
+#define TYPES_FCVTIMM_SUS (aarch64_types_fcvt_from_unsigned_qualifiers)
+static enum aarch64_type_qualifiers
 aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate };
 #define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers)
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 1332734..02d465b 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -447,10 +447,10 @@
   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
 
   /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3.  */
-  BUILTIN_VSDQ_SDI (BINOP, scvtf, 3)
-  BUILTIN_VSDQ_SDI (BINOP_SUS, ucvtf, 3)
-  BUILTIN_VALLF (BINOP, fcvtzs, 3)
-  BUILTIN_VALLF (BINOP_USS, fcvtzu, 3)
+  BUILTIN_VSDQ_SDI (SHIFTIMM, scvtf, 3)
+  BUILTIN_VSDQ_SDI (FCVTIMM_SUS, ucvtf, 3)
+  BUILTIN_VALLF (SHIFTIMM, fcvtzs, 3)
+  BUILTIN_VALLF (SHIFTIMM_USS, fcvtzu, 3)
 
   /* Implemented by aarch64_rsqrte<mode>.  */
   BUILTIN_VALLF (UNOP, rsqrte, 0)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b4e6ba0..bcb7db0 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4638,8 +4638,8 @@
 	 FCVT_F2FIXED))]
   ""
   "@
-   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<w1>0, %<s>1, #%2
-   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<s>0, %<s>1, #%2"
+   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:w1>0, %<GPF:s>1, #%2
+   <FCVT_F2FIXED:fcvt_fixed_insn>\t%<GPF:s>0, %<GPF:s>1, #%2"
   [(set_attr "type" "f_cvtf2i, neon_fp_to_int_<GPF:Vetype>")
    (set_attr "fp" "yes, *")
    (set_attr "simd" "*, yes")]
@@ -4652,8 +4652,8 @@
 	 FCVT_FIXED2F))]
   ""
   "@
-   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<s>0, %<w1>1, #%2
-   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<s>0, %<s>1, #%2"
+   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:w>1, #%2
+   <FCVT_FIXED2F:fcvt_fixed_insn>\t%<GPI:v>0, %<GPI:v>1, #%2"
   [(set_attr "type" "f_cvti2f, neon_int_to_fp_<GPI:Vetype>")
    (set_attr "fp" "yes, *")
    (set_attr "simd" "*, yes")]