From: Arnd Bergmann Date: Mon, 21 Nov 2022 10:56:08 +0000 (+0100) Subject: Merge tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel... X-Git-Tag: v6.6.7~4018^2~29 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1e9629820ab333a26353477863e494f95fec8fc0;p=platform%2Fkernel%2Flinux-starfive.git Merge tag 'renesas-arm-dt-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt Renesas ARM DT updates for v6.2 (take two) - Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for the R-Car V4H SoC, - Watchdog, L2 cache, and system controller support for the RZ/V2M SoC on the RZ/V2M Evaluation Kit 2.0, - Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the Spider development board, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits) arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes arm64: dts: renesas: r9a09g011: Add system controller node arm64: dts: renesas: r8a779g0: Add CA76 operating points arm64: dts: renesas: r8a779g0: Add CPU core clocks arm64: dts: renesas: r8a779g0: Add CPUIdle support arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores arm64: dts: renesas: r8a779g0: Add L3 cache controller arm64: dts: renesas: r9a09g011: Add L2 Cache node arm64: dts: renesas: rzv2mevk2: Enable watchdog arm64: dts: renesas: r9a09g011: Add watchdog node arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0 arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings arm64: dts: renesas: rzg2l: Add missing cache-level properties arm64: dts: renesas: r8a779g0: Add CMT node arm64: dts: renesas: r9a09g011: Fix unit address format error arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctly arm64: dts: renesas: r8a779g0: Add TMU nodes arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock ... Link: https://lore.kernel.org/r/cover.1668788921.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann --- 1e9629820ab333a26353477863e494f95fec8fc0