From: Conor Dooley Date: Wed, 7 Jun 2023 20:28:30 +0000 (+0100) Subject: dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support X-Git-Tag: v6.6.7~2493^2~3^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1e5cae98e46d15f4dc7c675e1bd0ed2172ea181c;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support Similar to commit 41ebfc91f785 ("dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm extensions also used to be part of the base ISA but were removed after the bindings were merged. Document the assumption of their presence in the base ISA. Suggested-by: Palmer Dabbelt Signed-off-by: Conor Dooley Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230607-rerun-retinal-5e8ba89e98f1@spud Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a..d520888 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -89,8 +89,8 @@ properties: Due to revisions of the ISA specification, some deviations have arisen over time. Notably, riscv,isa was defined prior to the creation of the - Zicsr and Zifencei extensions and thus "i" implies - "zicsr_zifencei". + Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" + implies "zicntr_zicsr_zifencei_zihpm". While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all