From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu, 20 Apr 2017 00:16:49 +0000 (-0700)
Subject: anv/query: Use genxml for MI_MATH
X-Git-Tag: upstream/18.1.0~10563
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1e21d4227e27c4e2a5446b47bbe122713d26cb33;p=platform%2Fupstream%2Fmesa.git

anv/query: Use genxml for MI_MATH

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed by: Iago Toral Quiroga <itoral@igalia.com>
---

diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 2c70b4f..126431b 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -500,35 +500,20 @@ void genX(CmdWriteTimestamp)(
 
 #if GEN_GEN > 7 || GEN_IS_HASWELL
 
-#define alu_opcode(v)   __gen_uint((v),  20, 31)
-#define alu_operand1(v) __gen_uint((v),  10, 19)
-#define alu_operand2(v) __gen_uint((v),   0,  9)
-#define alu(opcode, operand1, operand2) \
-   alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
-
-#define OPCODE_NOOP      0x000
-#define OPCODE_LOAD      0x080
-#define OPCODE_LOADINV   0x480
-#define OPCODE_LOAD0     0x081
-#define OPCODE_LOAD1     0x481
-#define OPCODE_ADD       0x100
-#define OPCODE_SUB       0x101
-#define OPCODE_AND       0x102
-#define OPCODE_OR        0x103
-#define OPCODE_XOR       0x104
-#define OPCODE_STORE     0x180
-#define OPCODE_STOREINV  0x580
-
-#define OPERAND_R0   0x00
-#define OPERAND_R1   0x01
-#define OPERAND_R2   0x02
-#define OPERAND_R3   0x03
-#define OPERAND_R4   0x04
-#define OPERAND_SRCA 0x20
-#define OPERAND_SRCB 0x21
-#define OPERAND_ACCU 0x31
-#define OPERAND_ZF   0x32
-#define OPERAND_CF   0x33
+static inline uint32_t
+mi_alu(uint32_t opcode, uint32_t operand1, uint32_t operand2)
+{
+   struct GENX(MI_MATH_ALU_INSTRUCTION) instr = {
+      .ALUOpcode = opcode,
+      .Operand1 = operand1,
+      .Operand2 = operand2,
+   };
+
+   uint32_t dw;
+   GENX(MI_MATH_ALU_INSTRUCTION_pack)(NULL, &dw, &instr);
+
+   return dw;
+}
 
 #define CS_GPR(n) (0x2600 + (n) * 8)
 
@@ -581,10 +566,10 @@ keep_gpr0_lower_n_bits(struct anv_batch *batch, uint32_t n)
    emit_load_alu_reg_imm64(batch, CS_GPR(1), (1ull << n) - 1);
 
    uint32_t *dw = anv_batch_emitn(batch, 5, GENX(MI_MATH));
-   dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R0);
-   dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R1);
-   dw[3] = alu(OPCODE_AND, 0, 0);
-   dw[4] = alu(OPCODE_STORE, OPERAND_R0, OPERAND_ACCU);
+   dw[1] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCA, MI_ALU_REG0);
+   dw[2] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCB, MI_ALU_REG1);
+   dw[3] = mi_alu(MI_ALU_AND, 0, 0);
+   dw[4] = mi_alu(MI_ALU_STORE, MI_ALU_REG0, MI_ALU_ACCU);
 }
 
 /*
@@ -609,10 +594,10 @@ shl_gpr0_by_30_bits(struct anv_batch *batch)
       uint32_t *dw = anv_batch_emitn(batch, cmd_len, GENX(MI_MATH));
       dw++;
       for (int i = 0; i < inner_count; i++, dw += 4) {
-         dw[0] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R0);
-         dw[1] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
-         dw[2] = alu(OPCODE_ADD, 0, 0);
-         dw[3] = alu(OPCODE_STORE, OPERAND_R0, OPERAND_ACCU);
+         dw[0] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCA, MI_ALU_REG0);
+         dw[1] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCB, MI_ALU_REG0);
+         dw[2] = mi_alu(MI_ALU_ADD, 0, 0);
+         dw[3] = mi_alu(MI_ALU_STORE, MI_ALU_REG0, MI_ALU_ACCU);
       }
    }
 }
@@ -675,10 +660,10 @@ compute_query_result(struct anv_batch *batch, uint32_t dst_reg,
       return;
    }
 
-   dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
-   dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
-   dw[3] = alu(OPCODE_SUB, 0, 0);
-   dw[4] = alu(OPCODE_STORE, dst_reg, OPERAND_ACCU);
+   dw[1] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCA, MI_ALU_REG1);
+   dw[2] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCB, MI_ALU_REG0);
+   dw[3] = mi_alu(MI_ALU_SUB, 0, 0);
+   dw[4] = mi_alu(MI_ALU_STORE, dst_reg, MI_ALU_ACCU);
 }
 
 void genX(CmdCopyQueryPoolResults)(
@@ -707,7 +692,7 @@ void genX(CmdCopyQueryPoolResults)(
       slot_offset = (firstQuery + i) * pool->stride;
       switch (pool->type) {
       case VK_QUERY_TYPE_OCCLUSION:
-         compute_query_result(&cmd_buffer->batch, OPERAND_R2,
+         compute_query_result(&cmd_buffer->batch, MI_ALU_REG2,
                               &pool->bo, slot_offset + 8);
          gpu_write_query_result(&cmd_buffer->batch, buffer, destOffset,
                                 flags, 0, CS_GPR(2));
@@ -719,7 +704,7 @@ void genX(CmdCopyQueryPoolResults)(
          while (statistics) {
             uint32_t stat = u_bit_scan(&statistics);
 
-            compute_query_result(&cmd_buffer->batch, OPERAND_R0,
+            compute_query_result(&cmd_buffer->batch, MI_ALU_REG0,
                                  &pool->bo, slot_offset + idx * 16 + 8);
 
             /* WaDividePSInvocationCountBy4:HSW,BDW */