From: Daniel Schürmann <daniel@schuermann.dev>
Date: Fri, 15 Nov 2019 07:20:06 +0000 (+0100)
Subject: aco: implement 64bit i2b for SI /CI
X-Git-Tag: upstream/20.1.8~5344
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1e1356b2ad2500e8aeefb8c3b64575ccac685eca;p=platform%2Fupstream%2Fmesa.git

aco: implement 64bit i2b for SI /CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
---

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 85ed7b3..82b6989 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -2115,8 +2115,13 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
       } else {
          assert(src.regClass() == s1 || src.regClass() == s2);
-         Temp tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
-                             bld.scc(bld.def(s1)), Operand(0u), src);
+         Temp tmp;
+         if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
+            tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
+         } else {
+            tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
+                           bld.scc(bld.def(s1)), Operand(0u), src);
+         }
          bool_to_vector_condition(ctx, tmp, dst);
       }
       break;