From: Gurchetan Singh Date: Fri, 11 Jan 2019 23:37:15 +0000 (-0800) Subject: virgl: add ability to do finer grain dirty tracking X-Git-Tag: upstream/19.3.0~9793 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1d294ad264dc85e716bec5b6d0286cc3e10ce224;p=platform%2Fupstream%2Fmesa.git virgl: add ability to do finer grain dirty tracking There are levels to cleanliness. Reviewed-by: Gert Wollny --- diff --git a/src/gallium/drivers/virgl/virgl_buffer.c b/src/gallium/drivers/virgl/virgl_buffer.c index 4d30c6c..6762011 100644 --- a/src/gallium/drivers/virgl/virgl_buffer.c +++ b/src/gallium/drivers/virgl/virgl_buffer.c @@ -120,7 +120,7 @@ static void virgl_buffer_transfer_flush_region(struct pipe_context *ctx, * We'll end up flushing 25 --> 70. */ util_range_add(&trans->range, box->x, box->x + box->width); - vbuf->clean = FALSE; + vbuf->clean[0] = FALSE; } static const struct u_resource_vtbl virgl_buffer_vtbl = diff --git a/src/gallium/drivers/virgl/virgl_context.c b/src/gallium/drivers/virgl/virgl_context.c index 08f85f8..0e4fd5b 100644 --- a/src/gallium/drivers/virgl/virgl_context.c +++ b/src/gallium/drivers/virgl/virgl_context.c @@ -234,7 +234,7 @@ static struct pipe_surface *virgl_create_surface(struct pipe_context *ctx, (util_format_is_srgb(templ->format) == util_format_is_srgb(resource->format))); - res->clean = FALSE; + res->clean[0] = FALSE; handle = virgl_object_assign_handle(); pipe_reference_init(&surf->base.reference, 1); pipe_resource_reference(&surf->base.texture, resource); @@ -521,7 +521,7 @@ void virgl_transfer_inline_write(struct pipe_context *ctx, struct virgl_screen *vs = virgl_screen(ctx->screen); struct virgl_resource *grres = virgl_resource(res); - grres->clean = FALSE; + grres->clean[0] = FALSE; if (virgl_res_needs_flush_wait(vctx, grres, usage)) { ctx->flush(ctx, NULL, 0); @@ -975,7 +975,7 @@ static void virgl_resource_copy_region(struct pipe_context *ctx, struct virgl_resource *dres = virgl_resource(dst); struct virgl_resource *sres = virgl_resource(src); - dres->clean = FALSE; + dres->clean[0] = FALSE; virgl_encode_resource_copy_region(vctx, dres, dst_level, dstx, dsty, dstz, sres, src_level, @@ -1000,7 +1000,7 @@ static void virgl_blit(struct pipe_context *ctx, (util_format_is_srgb(blit->dst.resource->format) == util_format_is_srgb(blit->dst.format))); - dres->clean = FALSE; + dres->clean[0] = FALSE; virgl_encode_blit(vctx, dres, sres, blit); } diff --git a/src/gallium/drivers/virgl/virgl_encode.c b/src/gallium/drivers/virgl/virgl_encode.c index 5b85756..b7fa317 100644 --- a/src/gallium/drivers/virgl/virgl_encode.c +++ b/src/gallium/drivers/virgl/virgl_encode.c @@ -64,7 +64,7 @@ static void virgl_encoder_write_res(struct virgl_context *ctx, static void virgl_dirty_res(struct virgl_resource *res) { if (res) - res->clean = FALSE; + res->clean[0] = FALSE; } int virgl_encode_bind_object(struct virgl_context *ctx, diff --git a/src/gallium/drivers/virgl/virgl_query.c b/src/gallium/drivers/virgl/virgl_query.c index 23e24c5..0085cc5 100644 --- a/src/gallium/drivers/virgl/virgl_query.c +++ b/src/gallium/drivers/virgl/virgl_query.c @@ -113,7 +113,7 @@ static struct pipe_query *virgl_create_query(struct pipe_context *ctx, query->type = pipe_to_virgl_query(query_type); query->index = index; query->handle = handle; - query->buf->clean = FALSE; + query->buf->clean[0] = FALSE; virgl_encoder_create_query(vctx, handle, query->type, index, query->buf, 0); return (struct pipe_query *)query; @@ -137,7 +137,7 @@ static boolean virgl_begin_query(struct pipe_context *ctx, struct virgl_context *vctx = virgl_context(ctx); struct virgl_query *query = virgl_query(q); - query->buf->clean = FALSE; + query->buf->clean[0] = FALSE; virgl_encoder_begin_query(vctx, query->handle); return true; } diff --git a/src/gallium/drivers/virgl/virgl_resource.c b/src/gallium/drivers/virgl/virgl_resource.c index 26d14d6..b7dfcac 100644 --- a/src/gallium/drivers/virgl/virgl_resource.c +++ b/src/gallium/drivers/virgl/virgl_resource.c @@ -44,7 +44,7 @@ bool virgl_res_needs_readback(struct virgl_context *vctx, unsigned usage) { bool readback = true; - if (res->clean) + if (res->clean[0]) readback = false; else if (usage & PIPE_TRANSFER_DISCARD_RANGE) readback = false; @@ -61,7 +61,6 @@ static struct pipe_resource *virgl_resource_create(struct pipe_screen *screen, struct virgl_screen *vs = virgl_screen(screen); struct virgl_resource *res = CALLOC_STRUCT(virgl_resource); - res->clean = TRUE; res->u.b = *templ; res->u.b.screen = &vs->base; pipe_reference_init(&res->u.b.reference, 1); @@ -81,6 +80,9 @@ static struct pipe_resource *virgl_resource_create(struct pipe_screen *screen, return NULL; } + for (uint32_t i = 0; i < VR_MAX_TEXTURE_2D_LEVELS; i++) + res->clean[i] = TRUE; + if (templ->target == PIPE_BUFFER) virgl_buffer_init(res); else diff --git a/src/gallium/drivers/virgl/virgl_resource.h b/src/gallium/drivers/virgl/virgl_resource.h index 1dc789c..fee630b 100644 --- a/src/gallium/drivers/virgl/virgl_resource.h +++ b/src/gallium/drivers/virgl/virgl_resource.h @@ -46,7 +46,7 @@ struct virgl_resource_metadata struct virgl_resource { struct u_resource u; - boolean clean; + boolean clean[VR_MAX_TEXTURE_2D_LEVELS]; struct virgl_hw_res *hw_res; struct virgl_resource_metadata metadata; }; diff --git a/src/gallium/drivers/virgl/virgl_streamout.c b/src/gallium/drivers/virgl/virgl_streamout.c index 0fc3af6..a3465e5 100644 --- a/src/gallium/drivers/virgl/virgl_streamout.c +++ b/src/gallium/drivers/virgl/virgl_streamout.c @@ -48,7 +48,7 @@ static struct pipe_stream_output_target *virgl_create_so_target( t->base.buffer_offset = buffer_offset; t->base.buffer_size = buffer_size; t->handle = handle; - res->clean = FALSE; + res->clean[0] = FALSE; virgl_encoder_create_so_target(vctx, handle, res, buffer_offset, buffer_size); return &t->base; } diff --git a/src/gallium/drivers/virgl/virgl_texture.c b/src/gallium/drivers/virgl/virgl_texture.c index df419db..59dbd15 100644 --- a/src/gallium/drivers/virgl/virgl_texture.c +++ b/src/gallium/drivers/virgl/virgl_texture.c @@ -165,7 +165,7 @@ static void virgl_texture_transfer_unmap(struct pipe_context *ctx, if (trans->base.usage & PIPE_TRANSFER_WRITE) { if (!(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) { struct virgl_screen *vs = virgl_screen(ctx->screen); - vtex->clean = FALSE; + vtex->clean[0] = FALSE; vctx->num_transfers++; vs->vws->transfer_put(vs->vws, vtex->hw_res, &transfer->box, trans->base.stride,