From: Krzysztof Parzyszek Date: Tue, 16 Aug 2016 18:08:40 +0000 (+0000) Subject: [Hexagon] Standardize next batch of pseudo instructions X-Git-Tag: llvmorg-4.0.0-rc1~12304 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1d01a793042d3d0566b009915529ab4559ea72a9;p=platform%2Fupstream%2Fllvm.git [Hexagon] Standardize next batch of pseudo instructions ALIGNA PS_aligna ALLOCA PS_alloca TFR_FI PS_fi TFR_FIA PS_fia TFR_PdFalse PS_false TFR_PdTrue PS_true VMULW PS_vmulw VMULW_ACC PS_vmulw_acc llvm-svn: 278832 --- diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 76dcc61..1bca47f 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1351,8 +1351,8 @@ bool ConstGeneration::isTfrConst(const MachineInstr &MI) { case Hexagon::A4_combineii: case Hexagon::A2_tfrsi: case Hexagon::A2_tfrpi: - case Hexagon::TFR_PdTrue: - case Hexagon::TFR_PdFalse: + case Hexagon::PS_true: + case Hexagon::PS_false: case Hexagon::CONST32: case Hexagon::CONST64: return true; @@ -1397,9 +1397,9 @@ unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, if (RC == &Hexagon::PredRegsRegClass) { unsigned Opc; if (C == 0) - Opc = Hexagon::TFR_PdFalse; + Opc = Hexagon::PS_false; else if ((C & 0xFF) == 0xFF) - Opc = Hexagon::TFR_PdTrue; + Opc = Hexagon::PS_true; else return 0; BuildMI(B, At, DL, HII.get(Opc), Reg); @@ -2173,7 +2173,7 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI, } } else if (V.is(0) || V.is(1)) { unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); - unsigned NewOpc = V.is(0) ? Hexagon::TFR_PdFalse : Hexagon::TFR_PdTrue; + unsigned NewOpc = V.is(0) ? Hexagon::PS_false : Hexagon::PS_true; BuildMI(B, At, DL, HII.get(NewOpc), NewR); HBS::replaceReg(RD.Reg, NewR, MRI); return true; diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp index 1f45acc..6833d7d 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -260,11 +260,11 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, case CONST32: case CONST64: return rr0(eIMM(im(1), W0), Outputs); - case TFR_PdFalse: + case PS_false: return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); - case TFR_PdTrue: + case PS_true: return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); - case TFR_FI: { + case PS_fi: { int FI = op(1).getIndex(); int Off = op(2).getImm(); unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off); diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index c4a0a62..b475213 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -1994,11 +1994,11 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, break; } - case Hexagon::TFR_PdTrue: - case Hexagon::TFR_PdFalse: + case Hexagon::PS_true: + case Hexagon::PS_false: { LatticeCell RC = Outputs.get(DefR.Reg); - bool NonZero = (Opc == Hexagon::TFR_PdTrue); + bool NonZero = (Opc == Hexagon::PS_true); uint32_t P = NonZero ? ConstantProperties::NonZero : ConstantProperties::Zero; RC.add(P); @@ -2328,8 +2328,8 @@ bool HexagonConstEvaluator::rewrite(MachineInstr &MI, const CellMap &Inputs) { case Hexagon::A2_tfrpi: case Hexagon::CONST32: case Hexagon::CONST64: - case Hexagon::TFR_PdTrue: - case Hexagon::TFR_PdFalse: + case Hexagon::PS_true: + case Hexagon::PS_false: return false; } @@ -2874,8 +2874,8 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, if (RC != PredRC) continue; const MCInstrDesc *NewD = (Ps & P::Zero) ? - &HII.get(Hexagon::TFR_PdFalse) : - &HII.get(Hexagon::TFR_PdTrue); + &HII.get(Hexagon::PS_false) : + &HII.get(Hexagon::PS_true); unsigned NewR = MRI->createVirtualRegister(PredRC); const MachineInstrBuilder &MIB = BuildMI(B, At, DL, *NewD, NewR); (void)MIB; diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 537715b..cc1fdd4 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -99,20 +99,20 @@ // cated (reserved) register, it needs to be kept live throughout the function // to be available as the base register for local object accesses. // Normally, an address of a stack objects is obtained by a pseudo-instruction -// TFR_FI. To access local objects with the AP register present, a different -// pseudo-instruction needs to be used: TFR_FIA. The TFR_FIA takes one extra -// argument compared to TFR_FI: the first input register is the AP register. +// PS_fi. To access local objects with the AP register present, a different +// pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra +// argument compared to PS_fi: the first input register is the AP register. // This keeps the register live between its definition and its uses. -// The AP register is originally set up using pseudo-instruction ALIGNA: -// AP = ALIGNA A +// The AP register is originally set up using pseudo-instruction PS_aligna: +// AP = PS_aligna A // where // A - required stack alignment // The alignment value must be the maximum of all alignments required by // any stack object. -// The dynamic allocation uses a pseudo-instruction ALLOCA: -// Rd = ALLOCA Rs, A +// The dynamic allocation uses a pseudo-instruction PS_alloca: +// Rd = PS_alloca Rs, A // where // Rd - address of the allocated space // Rs - minimum size (the actual allocated can be larger to accommodate @@ -256,8 +256,8 @@ namespace { return true; unsigned Opc = MI->getOpcode(); switch (Opc) { - case Hexagon::ALLOCA: - case Hexagon::ALIGNA: + case Hexagon::PS_alloca: + case Hexagon::PS_aligna: return true; default: break; @@ -536,7 +536,7 @@ void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB, auto &AdjustRegs = FuncInfo->getAllocaAdjustInsts(); for (auto MI : AdjustRegs) { - assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca"); + assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca"); expandAlloca(MI, HII, SP, MaxCF); MI->eraseFromParent(); } @@ -2322,7 +2322,7 @@ const MachineInstr *HexagonFrameLowering::getAlignaInstr( const MachineFunction &MF) const { for (auto &B : MF) for (auto &I : B) - if (I.getOpcode() == Hexagon::ALIGNA) + if (I.getOpcode() == Hexagon::PS_aligna) return &I; return nullptr; } diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index d6faa47..52f3280 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -934,22 +934,16 @@ void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) { } // -// Map predicate true (encoded as -1 in LLVM) to a XOR. +// Map boolean values. // void HexagonDAGToDAGISel::SelectConstant(SDNode *N) { - SDLoc dl(N); if (N->getValueType(0) == MVT::i1) { - SDNode* Result = 0; - int32_t Val = cast(N)->getSExtValue(); - if (Val == -1) { - Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1); - } else if (Val == 0) { - Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1); - } - if (Result) { - ReplaceNode(N, Result); - return; - } + assert(!(cast(N)->getZExtValue() >> 1)); + unsigned Opc = (cast(N)->getSExtValue() != 0) + ? Hexagon::PS_true + : Hexagon::PS_false; + ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i1)); + return; } SelectCode(N); @@ -1141,19 +1135,19 @@ void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) { SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); SDNode *R = nullptr; - // Use TFR_FI when: + // Use PS_fi when: // - the object is fixed, or // - there are no objects with higher-than-default alignment, or // - there are no dynamically allocated objects. - // Otherwise, use TFR_FIA. + // Otherwise, use PS_fia. if (FX < 0 || MaxA <= StkA || !MFI.hasVarSizedObjects()) { - R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero); + R = CurDAG->getMachineNode(Hexagon::PS_fi, DL, MVT::i32, FI, Zero); } else { auto &HMFI = *MF->getInfo(); unsigned AR = HMFI.getStackAlignBaseVReg(); SDValue CH = CurDAG->getEntryNode(); SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero }; - R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops); + R = CurDAG->getMachineNode(Hexagon::PS_fia, DL, MVT::i32, Ops); } ReplaceNode(N, R); @@ -1388,7 +1382,7 @@ void HexagonDAGToDAGISel::EmitFunctionEntryCode() { MachineBasicBlock *EntryBB = &MF->front(); unsigned AR = FuncInfo->CreateReg(MVT::i32); unsigned MaxA = MFI.getMaxAlignment(); - BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::ALIGNA), AR) + BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR) .addImm(MaxA); MF->getInfo()->setStackAlignBaseVReg(AR); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index d3a5ce1..ef45217 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2954,7 +2954,7 @@ HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table, MachineBasicBlock *HexagonTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *BB) const { switch (MI.getOpcode()) { - case Hexagon::ALLOCA: { + case Hexagon::PS_alloca: { MachineFunction *MF = BB->getParent(); auto *FuncInfo = MF->getInfo(); FuncInfo->addAllocaAdjustInst(&MI); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index d36303f..d3c038a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1007,7 +1007,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MBBI); return true; } - case Hexagon::ALIGNA: + case Hexagon::PS_aligna: BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg()) .addReg(HRI.getFrameRegister()) .addImm(-MI.getOperand(1).getImm()); @@ -1113,7 +1113,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } - case Hexagon::TFR_PdTrue: { + case Hexagon::PS_true: { unsigned Reg = MI.getOperand(0).getReg(); BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg) .addReg(Reg, RegState::Undef) @@ -1121,7 +1121,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } - case Hexagon::TFR_PdFalse: { + case Hexagon::PS_false: { unsigned Reg = MI.getOperand(0).getReg(); BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg) .addReg(Reg, RegState::Undef) @@ -1129,7 +1129,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } - case Hexagon::VMULW: { + case Hexagon::PS_vmulw: { // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies. unsigned DstReg = MI.getOperand(0).getReg(); unsigned Src1Reg = MI.getOperand(1).getReg(); @@ -1153,7 +1153,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MRI.clearKillFlags(Src2SubLo); return true; } - case Hexagon::VMULW_ACC: { + case Hexagon::PS_vmulw_acc: { // Expand 64-bit vector multiply with addition into 2 scalar multiplies. unsigned DstReg = MI.getOperand(0).getReg(); unsigned Src1Reg = MI.getOperand(1).getReg(); @@ -2063,8 +2063,9 @@ bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const { // TODO: This is largely obsolete now. Will need to be removed // in consecutive patches. switch (MI.getOpcode()) { - // TFR_FI Remains a special case. - case Hexagon::TFR_FI: + // PS_fi and PS_fia remain special cases. + case Hexagon::PS_fi: + case Hexagon::PS_fia: return true; default: return false; @@ -2762,8 +2763,8 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset, case Hexagon::LDriw_mod: return true; - case Hexagon::TFR_FI: - case Hexagon::TFR_FIA: + case Hexagon::PS_fi: + case Hexagon::PS_fia: case Hexagon::INLINEASM: return true; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 719f0a0..911dc11 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -4517,14 +4517,14 @@ def Y2_barrier : SYSInst<(outs), (ins), // let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { - def TFR_FI : ALU32_ri<(outs IntRegs:$Rd), - (ins IntRegs:$fi, s32Imm:$off), "">; - def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">; + def PS_fi : ALU32_ri<(outs IntRegs:$Rd), + (ins IntRegs:$fi, s32Imm:$off), "">; + def PS_fia : ALU32_ri<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">; } -def: Pat<(i32 (orisadd (i32 AddrFI:$Rs), s32ImmPred:$off)), - (i32 (TFR_FI (i32 AddrFI:$Rs), s32ImmPred:$off))>; +def: Pat<(orisadd (i32 AddrFI:$Rs), s32ImmPred:$off), + (PS_fi (i32 AddrFI:$Rs), s32ImmPred:$off)>; //===----------------------------------------------------------------------===// // CRUSER - Type. @@ -4778,13 +4778,13 @@ def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>; let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, isCodeGenOnly = 1 in -def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "", - [(set (i1 PredRegs:$dst), 1)]>; +def PS_true : SInst<(outs PredRegs:$dst), (ins), "", + [(set (i1 PredRegs:$dst), 1)]>; let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, isCodeGenOnly = 1 in -def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "", - [(set (i1 PredRegs:$dst), 0)]>; +def PS_false : SInst<(outs PredRegs:$dst), (ins), "", + [(set (i1 PredRegs:$dst), 0)]>; // Pseudo instructions. def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; @@ -5073,13 +5073,13 @@ def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, // in MachineFunctionInfo. let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1, usesCustomInserter = 1 in -def ALLOCA: ALU32Inst<(outs IntRegs:$Rd), +def PS_alloca: ALU32Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u32Imm:$A), "", [(set (i32 IntRegs:$Rd), (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>; let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in -def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>; +def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>; def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td index 0277d5e..cd87052 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td @@ -238,15 +238,13 @@ def: vcmp_vi1_pat; // scalar MPYI instructions. // This is expanded by ExpandPostRAPseudos. let isPseudo = 1 in -def VMULW : PseudoM<(outs DoubleRegs:$Rd), - (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - ".error \"Should never try to emit VMULW\"", +def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd), + (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", [(set V2I32:$Rd, (mul V2I32:$Rs, V2I32:$Rt))]>; let isPseudo = 1 in -def VMULW_ACC : PseudoM<(outs DoubleRegs:$Rd), - (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), - ".error \"Should never try to emit VMULW_ACC\"", +def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd), + (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [(set V2I32:$Rd, (add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)))], "$Rd = $Rx">; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 23ebfd4..6a45e7b 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -180,12 +180,12 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned Opc = MI.getOpcode(); switch (Opc) { - case Hexagon::TFR_FIA: + case Hexagon::PS_fia: MI.setDesc(HII.get(Hexagon::A2_addi)); MI.getOperand(FIOp).ChangeToImmediate(RealOffset); MI.RemoveOperand(FIOp+1); return; - case Hexagon::TFR_FI: + case Hexagon::PS_fi: // Set up the instruction for updating below. MI.setDesc(HII.get(Hexagon::A2_addi)); break;