From: H.J. Lu <hjl.tools@gmail.com>
Date: Tue, 2 Jul 2013 15:03:29 +0000 (-0700)
Subject: Enable static 32-bit SSE4.2 strcasecmp/strncasecmp
X-Git-Tag: upstream/2.20~1881
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1c81621c5bbecb223c9d1262c05175608c47add5;p=platform%2Fupstream%2Flinaro-glibc.git

Enable static 32-bit SSE4.2 strcasecmp/strncasecmp
---

diff --git a/ChangeLog b/ChangeLog
index 4a2d19a..0b37552 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2013-07-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Enable
+	SSE4.2 strcasecmp for libc.a.
+	* sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
+
 2013-07-02  Joseph Myers  <joseph@codesourcery.com>
 
 	[BZ #13304]
diff --git a/sysdeps/i386/i686/multiarch/strcasecmp.S b/sysdeps/i386/i686/multiarch/strcasecmp.S
index 3b38214..2444af2 100644
--- a/sysdeps/i386/i686/multiarch/strcasecmp.S
+++ b/sysdeps/i386/i686/multiarch/strcasecmp.S
@@ -54,12 +54,9 @@ ENTRY(__strcasecmp)
 	testl	$bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features
 	jz	2f
 	leal	__strcasecmp_ssse3, %eax
-#if 0
-	// XXX Temporarily
 	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	__strcasecmp_sse4_2, %eax
-#endif
 2:	ret
 END(__strcasecmp)
 #endif
diff --git a/sysdeps/i386/i686/multiarch/strncase.S b/sysdeps/i386/i686/multiarch/strncase.S
index 51c6d72..939cd96 100644
--- a/sysdeps/i386/i686/multiarch/strncase.S
+++ b/sysdeps/i386/i686/multiarch/strncase.S
@@ -54,12 +54,9 @@ ENTRY(__strncasecmp)
 	testl	$bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features
 	jz	2f
 	leal	__strncasecmp_ssse3, %eax
-#if 0
-	// XXX Temporarily
 	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	__strncasecmp_sse4_2, %eax
-#endif
 2:	ret
 END(__strncasecmp)
 #endif