From: Hyeongseok Oh <hseok82.oh@samsung.com>
Date: Mon, 3 Apr 2017 06:16:43 +0000 (+0900)
Subject: [RyuJIT/ARM32] [ReadyToRun] Fix target register for invocation to Thunk
X-Git-Tag: submit/tizen/20210909.063632~11030^2~7368^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1be1521315e3043779ad859b89bf2c84c48fd38e;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

[RyuJIT/ARM32] [ReadyToRun] Fix target register for invocation to Thunk

Fix target register for invocation to Thunk code from generated by ReadyToRun
Target register: REG_VIRTUAL_STUB_PARAM (R4, same as LegacyJIT)


Commit migrated from https://github.com/dotnet/coreclr/commit/9c2213765abc56f98dcb59d4567912dc5ac1e137
---

diff --git a/src/coreclr/src/jit/gentree.cpp b/src/coreclr/src/jit/gentree.cpp
index 4e42f4f..4f1b724 100644
--- a/src/coreclr/src/jit/gentree.cpp
+++ b/src/coreclr/src/jit/gentree.cpp
@@ -5524,11 +5524,16 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
             }
 
 #ifdef FEATURE_READYTORUN_COMPILER
-#ifdef _TARGET_ARM64_
+#if defined(_TARGET_ARM64_)
             if (tree->gtCall.IsR2RRelativeIndir())
             {
                 ftreg |= RBM_R2R_INDIRECT_PARAM;
             }
+#elif defined(_TARGET_ARM_)
+            if (tree->gtCall.IsR2RRelativeIndir())
+            {
+                ftreg |= RBM_JUMP_THUNK_PARAM;
+            }
 #endif
 #endif
 
diff --git a/src/coreclr/src/jit/lower.cpp b/src/coreclr/src/jit/lower.cpp
index 5aad06a..487054e 100644
--- a/src/coreclr/src/jit/lower.cpp
+++ b/src/coreclr/src/jit/lower.cpp
@@ -2554,6 +2554,7 @@ GenTree* Lowering::LowerDirectCall(GenTreeCall* call)
             if (call->IsR2RRelativeIndir())
             {
                 cellAddr->gtRegNum = REG_JUMP_THUNK_PARAM;
+                indir->gtRegNum    = REG_VIRTUAL_STUB_PARAM;
             }
 #endif
 #endif