From: Yassine Oudjana <y.oudjana@protonmail.com>
Date: Tue, 21 Jun 2022 16:06:16 +0000 (+0400)
Subject: clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX
X-Git-Tag: v6.1-rc5~153^2~7^6~4^2~52
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1ba0a3bbd5ed5a1bb8d0165912d9904b812af74b;p=platform%2Fkernel%2Flinux-starfive.git

clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX

The parent at this index is the secondary mux, which can connect
not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX
to better reflect the parent.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-2-y.oudjana@protonmail.com
---

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 4a4fde8..5dc68dc 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -61,7 +61,7 @@
 #include "clk-regmap.h"
 
 enum _pmux_input {
-	DIV_2_INDEX = 0,
+	SMUX_INDEX = 0,
 	PLL_INDEX,
 	ACD_INDEX,
 	ALT_INDEX,
@@ -468,7 +468,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
 	case POST_RATE_CHANGE:
 		if (cnd->new_rate < DIV_2_THRESHOLD)
 			ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
-							  DIV_2_INDEX);
+							  SMUX_INDEX);
 		else
 			ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
 							  ACD_INDEX);