From: Dave Liu <daveliu@freescale.com>
Date: Fri, 27 Mar 2009 06:32:43 +0000 (+0800)
Subject: 85xx: Fix the clock adjust of mpc8569mds board
X-Git-Tag: v2009.06-rc3~9
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1b5291dddf5f16c7ae10e3cb165882fa96038b26;p=platform%2Fkernel%2Fu-boot.git

85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---

diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index 4b4533e..e938788 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -54,7 +54,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 *	0110	3/4 cycle late
 	 *	0111	7/8 cycle late
 	 */
-	popts->clk_adjust = 6;
+	popts->clk_adjust = 4;
 
 	/*
 	 * Factors to consider for CPO: