From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Thu, 10 Nov 2022 14:40:48 +0000 (+0100)
Subject: freedreno,tu,ir3: DCE ij_pix
X-Git-Tag: upstream/23.3.3~16550
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1b492d503103fac8ef9467ced09db3e92b0fba77;p=platform%2Fupstream%2Fmesa.git

freedreno,tu,ir3: DCE ij_pix

SP_FS_PREFETCH_CNTL.IJ_WRITE_DISABLE allows disabling ij write, so
now we could DCE it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19652>
---

diff --git a/src/freedreno/ir3/ir3_dce.c b/src/freedreno/ir3/ir3_dce.c
index 02cd29b..6e0654c 100644
--- a/src/freedreno/ir3/ir3_dce.c
+++ b/src/freedreno/ir3/ir3_dce.c
@@ -112,13 +112,6 @@ find_and_remove_unused(struct ir3 *ir, struct ir3_shader_variant *so)
    foreach_block (block, &ir->block_list) {
       foreach_instr (instr, &block->instr_list) {
          if (instr->opc == OPC_META_INPUT) {
-            /* special case, if pre-fs texture fetch used, we cannot
-             * eliminate the barycentric i/j input
-             */
-            if (so->num_sampler_prefetch &&
-                instr->input.sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
-               continue;
-
             /* Without GS header geometry shader is never invoked. */
             if (instr->input.sysval == SYSTEM_VALUE_GS_HEADER_IR3)
                continue;
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index ec249d3..91e54bc 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1498,9 +1498,9 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
       ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
 
    if (fs->num_sampler_prefetch > 0) {
-      assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
-      /* also, it seems like ij_pix is *required* to be r0.x */
-      assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
+      /* It seems like ij_pix is *required* to be r0.x */
+      assert(!VALIDREG(ij_regid[IJ_PERSP_PIXEL]) ||
+             ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
    }
 
    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index f75f427..a5dd118 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -526,13 +526,10 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
       ij_regid[i] =
          ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
 
-   /* If we have pre-dispatch texture fetches, then ij_pix should not
-    * be DCE'd, even if not actually used in the shader itself:
-    */
    if (fs->num_sampler_prefetch > 0) {
-      assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
-      /* also, it seems like ij_pix is *required* to be r0.x */
-      assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
+      /* It seems like ij_pix is *required* to be r0.x */
+      assert(!VALIDREG(ij_regid[IJ_PERSP_PIXEL]) ||
+             ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
    }
 
    /* we can't write gl_SampleMask for !msaa..  if b0 is zero then we