From: Qiang Yu Date: Mon, 6 Jun 2022 08:37:16 +0000 (+0800) Subject: nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd X-Git-Tag: upstream/22.3.5~4236 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1aef9c831873ef384b6f25e2eb8579505a8dbec1;p=platform%2Fupstream%2Fmesa.git nir,ac/llvm: add nir_intrinsic_load_half_line_width_amd Used by AMD GPU NGG line culling. We could use nir load line width and viewport scale to calculate this in shader, but this way needs expensive divide ops. Acked-by: Marek Olšák Reviewed-by: Timur Kristóf Signed-off-by: Qiang Yu Part-of: --- diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 587bc5e..8ec5674 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3581,6 +3581,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_tcs_num_patches_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd: + case nir_intrinsic_load_clip_half_line_width_amd: result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic); break; case nir_intrinsic_load_vertex_id_zero_base: { diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index c40c14c..084ceaa 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -181,6 +181,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_ray_num_dss_rt_stacks_intel: case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd: + case nir_intrinsic_load_clip_half_line_width_amd: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 81066ad..aee5e5c 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1416,6 +1416,9 @@ system_value("lshs_vertex_stride_amd", 1) # Per patch data offset in HS VRAM output buffer system_value("hs_out_patch_data_offset_amd", 1) +# line_width * 0.5 / abs(viewport_scale[2]) +system_value("clip_half_line_width_amd", 2) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel