From: Jason Molenda Date: Wed, 13 Mar 2013 00:14:30 +0000 (+0000) Subject: Various fixes for armv7 floating point/vector register support. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1ad66dbae4e402cdce3e8dd433927f143be72692;p=platform%2Fupstream%2Fllvm.git Various fixes for armv7 floating point/vector register support. Drop the old f registers from debugserver's register list. Add the NEON 128-bit q registers to debugserver, support reading and writing. Add the new contains / invalidates mappings for the s, d, and q registers so lldb will know what registers overlay what other registers. Change the default format of s and d registers to be floating point instead of hex. Remove some UTF-8 hyphen chars in comments in the ARM register number definition headers. llvm-svn: 176915 --- diff --git a/lldb/source/Utility/ARM_DWARF_Registers.cpp b/lldb/source/Utility/ARM_DWARF_Registers.cpp index 5e59c33..491ba04 100644 --- a/lldb/source/Utility/ARM_DWARF_Registers.cpp +++ b/lldb/source/Utility/ARM_DWARF_Registers.cpp @@ -81,8 +81,8 @@ GetARMDWARFRegisterName (unsigned reg_num) case dwarf_f6: return "f6"; case dwarf_f7: return "f7"; - // Intel wireless MMX general purpose registers 0–7 - // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7) + // Intel wireless MMX general purpose registers 0 - 7 + // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7) case dwarf_wCGR0: return "wCGR0/ACC0"; case dwarf_wCGR1: return "wCGR1/ACC1"; case dwarf_wCGR2: return "wCGR2/ACC2"; @@ -92,7 +92,7 @@ GetARMDWARFRegisterName (unsigned reg_num) case dwarf_wCGR6: return "wCGR6/ACC6"; case dwarf_wCGR7: return "wCGR7/ACC7"; - // Intel wireless MMX data registers 0–15 + // Intel wireless MMX data registers 0 - 15 case dwarf_wR0: return "wR0"; case dwarf_wR1: return "wR1"; case dwarf_wR2: return "wR2"; @@ -140,7 +140,7 @@ GetARMDWARFRegisterName (unsigned reg_num) case dwarf_r13_svc: return "r13_svc"; case dwarf_r14_svc: return "r14_svc"; - // Intel wireless MMX control register in co-processor 0–7 + // Intel wireless MMX control register in co-processor 0 - 7 case dwarf_wC0: return "wC0"; case dwarf_wC1: return "wC1"; case dwarf_wC2: return "wC2"; @@ -183,6 +183,24 @@ GetARMDWARFRegisterName (unsigned reg_num) case dwarf_d29: return "d29"; case dwarf_d30: return "d30"; case dwarf_d31: return "d31"; + + // NEON 128-bit vector registers (overlays the d registers) + case dwarf_q0: return "q0"; + case dwarf_q1: return "q1"; + case dwarf_q2: return "q2"; + case dwarf_q3: return "q3"; + case dwarf_q4: return "q4"; + case dwarf_q5: return "q5"; + case dwarf_q6: return "q6"; + case dwarf_q7: return "q7"; + case dwarf_q8: return "q8"; + case dwarf_q9: return "q9"; + case dwarf_q10: return "q10"; + case dwarf_q11: return "q11"; + case dwarf_q12: return "q12"; + case dwarf_q13: return "q13"; + case dwarf_q14: return "q14"; + case dwarf_q15: return "q15"; } return 0; } @@ -192,6 +210,13 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) { ::memset (®_info, 0, sizeof(RegisterInfo)); ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); + + if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) + { + reg_info.byte_size = 16; + reg_info.format = eFormatVectorOfUInt8; + reg_info.encoding = eEncodingVector; + } if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) { @@ -273,7 +298,7 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) case dwarf_s30: reg_info.name = "s30"; break; case dwarf_s31: reg_info.name = "s31"; break; - // FPA Registers 0-7 + // FPA Registers 0-7 case dwarf_f0: reg_info.name = "f0"; break; case dwarf_f1: reg_info.name = "f1"; break; case dwarf_f2: reg_info.name = "f2"; break; @@ -283,8 +308,8 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) case dwarf_f6: reg_info.name = "f6"; break; case dwarf_f7: reg_info.name = "f7"; break; - // Intel wireless MMX general purpose registers 0–7 - // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7) + // Intel wireless MMX general purpose registers 0 - 7 + // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7) case dwarf_wCGR0: reg_info.name = "wCGR0/ACC0"; break; case dwarf_wCGR1: reg_info.name = "wCGR1/ACC1"; break; case dwarf_wCGR2: reg_info.name = "wCGR2/ACC2"; break; @@ -294,7 +319,7 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) case dwarf_wCGR6: reg_info.name = "wCGR6/ACC6"; break; case dwarf_wCGR7: reg_info.name = "wCGR7/ACC7"; break; - // Intel wireless MMX data registers 0–15 + // Intel wireless MMX data registers 0 - 15 case dwarf_wR0: reg_info.name = "wR0"; break; case dwarf_wR1: reg_info.name = "wR1"; break; case dwarf_wR2: reg_info.name = "wR2"; break; @@ -342,7 +367,7 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) case dwarf_r13_svc: reg_info.name = "r13_svc"; break; case dwarf_r14_svc: reg_info.name = "r14_svc"; break; - // Intel wireless MMX control register in co-processor 0–7 + // Intel wireless MMX control register in co-processor 0 - 7 case dwarf_wC0: reg_info.name = "wC0"; break; case dwarf_wC1: reg_info.name = "wC1"; break; case dwarf_wC2: reg_info.name = "wC2"; break; @@ -352,7 +377,7 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) case dwarf_wC6: reg_info.name = "wC6"; break; case dwarf_wC7: reg_info.name = "wC7"; break; - // VFP-v3/Neon + // VFP-v3/Neon case dwarf_d0: reg_info.name = "d0"; break; case dwarf_d1: reg_info.name = "d1"; break; case dwarf_d2: reg_info.name = "d2"; break; @@ -385,6 +410,25 @@ GetARMDWARFRegisterInfo (unsigned reg_num, RegisterInfo ®_info) case dwarf_d29: reg_info.name = "d29"; break; case dwarf_d30: reg_info.name = "d30"; break; case dwarf_d31: reg_info.name = "d31"; break; + + // NEON 128-bit vector registers (overlays the d registers) + case dwarf_q0: reg_info.name = "q0"; break; + case dwarf_q1: reg_info.name = "q1"; break; + case dwarf_q2: reg_info.name = "q2"; break; + case dwarf_q3: reg_info.name = "q3"; break; + case dwarf_q4: reg_info.name = "q4"; break; + case dwarf_q5: reg_info.name = "q5"; break; + case dwarf_q6: reg_info.name = "q6"; break; + case dwarf_q7: reg_info.name = "q7"; break; + case dwarf_q8: reg_info.name = "q8"; break; + case dwarf_q9: reg_info.name = "q9"; break; + case dwarf_q10: reg_info.name = "q10"; break; + case dwarf_q11: reg_info.name = "q11"; break; + case dwarf_q12: reg_info.name = "q12"; break; + case dwarf_q13: reg_info.name = "q13"; break; + case dwarf_q14: reg_info.name = "q14"; break; + case dwarf_q15: reg_info.name = "q15"; break; + default: return false; } return true; diff --git a/lldb/source/Utility/ARM_DWARF_Registers.h b/lldb/source/Utility/ARM_DWARF_Registers.h index b5bad8b..6850d3e 100644 --- a/lldb/source/Utility/ARM_DWARF_Registers.h +++ b/lldb/source/Utility/ARM_DWARF_Registers.h @@ -75,7 +75,7 @@ enum dwarf_f6, dwarf_f7, - // Intel wireless MMX general purpose registers 0–7 + // Intel wireless MMX general purpose registers 0 - 7 dwarf_wCGR0 = 104, dwarf_wCGR1, dwarf_wCGR2, @@ -85,7 +85,7 @@ enum dwarf_wCGR6, dwarf_wCGR7, - // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7) + // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7) dwarf_ACC0 = 104, dwarf_ACC1, dwarf_ACC2, @@ -95,7 +95,7 @@ enum dwarf_ACC6, dwarf_ACC7, - // Intel wireless MMX data registers 0–15 + // Intel wireless MMX data registers 0 - 15 dwarf_wR0 = 112, dwarf_wR1, dwarf_wR2, @@ -143,7 +143,7 @@ enum dwarf_r13_svc, dwarf_r14_svc, - // Intel wireless MMX control register in co-processor 0–7 + // Intel wireless MMX control register in co-processor 0 - 7 dwarf_wC0 = 192, dwarf_wC1, dwarf_wC2, diff --git a/lldb/tools/debugserver/source/ARM_DWARF_Registers.h b/lldb/tools/debugserver/source/ARM_DWARF_Registers.h index c94579d..845260b 100644 --- a/lldb/tools/debugserver/source/ARM_DWARF_Registers.h +++ b/lldb/tools/debugserver/source/ARM_DWARF_Registers.h @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// -#ifndef utility_ARM_DWARF_Registers_h_ -#define utility_ARM_DWARF_Registers_h_ +#ifndef ARM_DWARF_Registers_h_ +#define ARM_DWARF_Registers_h_ + enum { @@ -73,7 +74,7 @@ enum dwarf_f6, dwarf_f7, - // Intel wireless MMX general purpose registers 0–7 + // Intel wireless MMX general purpose registers 0 - 7 dwarf_wCGR0 = 104, dwarf_wCGR1, dwarf_wCGR2, @@ -93,7 +94,7 @@ enum dwarf_ACC6, dwarf_ACC7, - // Intel wireless MMX data registers 0–15 + // Intel wireless MMX data registers 0 - 15 dwarf_wR0 = 112, dwarf_wR1, dwarf_wR2, @@ -141,7 +142,7 @@ enum dwarf_r13_svc, dwarf_r14_svc, - // Intel wireless MMX control register in co-processor 0–7 + // Intel wireless MMX control register in co-processor 0 - 7 dwarf_wC0 = 192, dwarf_wC1, dwarf_wC2, @@ -183,8 +184,26 @@ enum dwarf_d28, dwarf_d29, dwarf_d30, - dwarf_d31 + dwarf_d31, + + // Neon quadword registers + dwarf_q0 = 288, + dwarf_q1, + dwarf_q2, + dwarf_q3, + dwarf_q4, + dwarf_q5, + dwarf_q6, + dwarf_q7, + dwarf_q8, + dwarf_q9, + dwarf_q10, + dwarf_q11, + dwarf_q12, + dwarf_q13, + dwarf_q14, + dwarf_q15 }; -#endif // utility_ARM_DWARF_Registers_h_ +#endif // ARM_DWARF_Registers_h_ diff --git a/lldb/tools/debugserver/source/ARM_GCC_Registers.h b/lldb/tools/debugserver/source/ARM_GCC_Registers.h index e315b69..974d01b 100644 --- a/lldb/tools/debugserver/source/ARM_GCC_Registers.h +++ b/lldb/tools/debugserver/source/ARM_GCC_Registers.h @@ -31,5 +31,116 @@ enum gcc_cpsr }; +enum +{ +// Name Nr Rel Offset Size Type Raw value + gdb_arm_r0 = 0, // 0 0 4 int32_t + gdb_arm_r1 = 1, // 1 4 4 int32_t + gdb_arm_r2 = 2, // 2 8 4 int32_t + gdb_arm_r3 = 3, // 3 12 4 int32_t + gdb_arm_r4 = 4, // 4 16 4 int32_t + gdb_arm_r5 = 5, // 5 20 4 int32_t + gdb_arm_r6 = 6, // 6 24 4 int32_t + gdb_arm_r7 = 7, // 7 28 4 int32_t + gdb_arm_r8 = 8, // 8 32 4 int32_t + gdb_arm_r9 = 9, // 9 36 4 int32_t + gdb_arm_r10 = 10, // 10 40 4 int32_t + gdb_arm_r11 = 11, // 11 44 4 int32_t + gdb_arm_r12 = 12, // 12 48 4 int32_t + gdb_arm_sp = 13, // 13 52 4 int32_t + gdb_arm_lr = 14, // 14 56 4 int32_t + gdb_arm_pc = 15, // 15 60 4 int32_t + gdb_arm_f0 = 16, // 16 64 12 _arm_ext_littlebyte_bigword + gdb_arm_f1 = 17, // 17 76 12 _arm_ext_littlebyte_bigword + gdb_arm_f2 = 18, // 18 88 12 _arm_ext_littlebyte_bigword + gdb_arm_f3 = 19, // 19 100 12 _arm_ext_littlebyte_bigword + gdb_arm_f4 = 20, // 20 112 12 _arm_ext_littlebyte_bigword + gdb_arm_f5 = 21, // 21 124 12 _arm_ext_littlebyte_bigword + gdb_arm_f6 = 22, // 22 136 12 _arm_ext_littlebyte_bigword + gdb_arm_f7 = 23, // 23 148 12 _arm_ext_littlebyte_bigword + gdb_arm_f8 = 24, // 24 160 12 _arm_ext_littlebyte_bigword + gdb_arm_cpsr = 25, // 25 172 4 int32_t + gdb_arm_s0 = 26, // 26 176 4 _ieee_single_little + gdb_arm_s1 = 27, // 27 180 4 _ieee_single_little + gdb_arm_s2 = 28, // 28 184 4 _ieee_single_little + gdb_arm_s3 = 29, // 29 188 4 _ieee_single_little + gdb_arm_s4 = 30, // 30 192 4 _ieee_single_little + gdb_arm_s5 = 31, // 31 196 4 _ieee_single_little + gdb_arm_s6 = 32, // 32 200 4 _ieee_single_little + gdb_arm_s7 = 33, // 33 204 4 _ieee_single_little + gdb_arm_s8 = 34, // 34 208 4 _ieee_single_little + gdb_arm_s9 = 35, // 35 212 4 _ieee_single_little + gdb_arm_s10 = 36, // 36 216 4 _ieee_single_little + gdb_arm_s11 = 37, // 37 220 4 _ieee_single_little + gdb_arm_s12 = 38, // 38 224 4 _ieee_single_little + gdb_arm_s13 = 39, // 39 228 4 _ieee_single_little + gdb_arm_s14 = 40, // 40 232 4 _ieee_single_little + gdb_arm_s15 = 41, // 41 236 4 _ieee_single_little + gdb_arm_s16 = 42, // 42 240 4 _ieee_single_little + gdb_arm_s17 = 43, // 43 244 4 _ieee_single_little + gdb_arm_s18 = 44, // 44 248 4 _ieee_single_little + gdb_arm_s19 = 45, // 45 252 4 _ieee_single_little + gdb_arm_s20 = 46, // 46 256 4 _ieee_single_little + gdb_arm_s21 = 47, // 47 260 4 _ieee_single_little + gdb_arm_s22 = 48, // 48 264 4 _ieee_single_little + gdb_arm_s23 = 49, // 49 268 4 _ieee_single_little + gdb_arm_s24 = 50, // 50 272 4 _ieee_single_little + gdb_arm_s25 = 51, // 51 276 4 _ieee_single_little + gdb_arm_s26 = 52, // 52 280 4 _ieee_single_little + gdb_arm_s27 = 53, // 53 284 4 _ieee_single_little + gdb_arm_s28 = 54, // 54 288 4 _ieee_single_little + gdb_arm_s29 = 55, // 55 292 4 _ieee_single_little + gdb_arm_s30 = 56, // 56 296 4 _ieee_single_little + gdb_arm_s31 = 57, // 57 300 4 _ieee_single_little + gdb_arm_fpscr = 58, // 58 304 4 int32_t + gdb_arm_d16 = 59, // 59 308 8 _ieee_double_little + gdb_arm_d17 = 60, // 60 316 8 _ieee_double_little + gdb_arm_d18 = 61, // 61 324 8 _ieee_double_little + gdb_arm_d19 = 62, // 62 332 8 _ieee_double_little + gdb_arm_d20 = 63, // 63 340 8 _ieee_double_little + gdb_arm_d21 = 64, // 64 348 8 _ieee_double_little + gdb_arm_d22 = 65, // 65 356 8 _ieee_double_little + gdb_arm_d23 = 66, // 66 364 8 _ieee_double_little + gdb_arm_d24 = 67, // 67 372 8 _ieee_double_little + gdb_arm_d25 = 68, // 68 380 8 _ieee_double_little + gdb_arm_d26 = 69, // 69 388 8 _ieee_double_little + gdb_arm_d27 = 70, // 70 396 8 _ieee_double_little + gdb_arm_d28 = 71, // 71 404 8 _ieee_double_little + gdb_arm_d29 = 72, // 72 412 8 _ieee_double_little + gdb_arm_d30 = 73, // 73 420 8 _ieee_double_little + gdb_arm_d31 = 74, // 74 428 8 _ieee_double_little + gdb_arm_d0 = 75, // 0 436 8 _ieee_double_little + gdb_arm_d1 = 76, // 1 444 8 _ieee_double_little + gdb_arm_d2 = 77, // 2 452 8 _ieee_double_little + gdb_arm_d3 = 78, // 3 460 8 _ieee_double_little + gdb_arm_d4 = 79, // 4 468 8 _ieee_double_little + gdb_arm_d5 = 80, // 5 476 8 _ieee_double_little + gdb_arm_d6 = 81, // 6 484 8 _ieee_double_little + gdb_arm_d7 = 82, // 7 492 8 _ieee_double_little + gdb_arm_d8 = 83, // 8 500 8 _ieee_double_little + gdb_arm_d9 = 84, // 9 508 8 _ieee_double_little + gdb_arm_d10 = 85, // 10 516 8 _ieee_double_little + gdb_arm_d11 = 86, // 11 524 8 _ieee_double_little + gdb_arm_d12 = 87, // 12 532 8 _ieee_double_little + gdb_arm_d13 = 88, // 13 540 8 _ieee_double_little + gdb_arm_d14 = 89, // 14 548 8 _ieee_double_little + gdb_arm_d15 = 90, // 15 556 8 _ieee_double_little + gdb_arm_q0 = 91, // 16 564 16 _vec128 + gdb_arm_q1 = 92, // 17 580 16 _vec128 + gdb_arm_q2 = 93, // 18 596 16 _vec128 + gdb_arm_q3 = 94, // 19 612 16 _vec128 + gdb_arm_q4 = 95, // 20 628 16 _vec128 + gdb_arm_q5 = 96, // 21 644 16 _vec128 + gdb_arm_q6 = 97, // 22 660 16 _vec128 + gdb_arm_q7 = 98, // 23 676 16 _vec128 + gdb_arm_q8 = 99, // 24 692 16 _vec128 + gdb_arm_q9 = 100, // 25 708 16 _vec128 + gdb_arm_q10 = 101, // 26 724 16 _vec128 + gdb_arm_q11 = 102, // 27 740 16 _vec128 + gdb_arm_q12 = 103, // 28 756 16 _vec128 + gdb_arm_q13 = 104, // 29 772 16 _vec128 + gdb_arm_q14 = 105, // 30 788 16 _vec128 + gdb_arm_q15 = 106 // 31 804 16 _vec128 +}; #endif // utility_ARM_GCC_Registers_h_ diff --git a/lldb/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp b/lldb/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp index a3a867b..a2fb437 100644 --- a/lldb/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp +++ b/lldb/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp @@ -1230,7 +1230,7 @@ DNBArchMachARM::GetWatchAddress(const DBG &debug_state, uint32_t hw_index) } //---------------------------------------------------------------------- -// Register information defintions for 32 bit ARMV6. +// Register information defintions for 32 bit ARMV7. //---------------------------------------------------------------------- enum gpr_regnums { @@ -1255,7 +1255,7 @@ enum gpr_regnums enum { - vfp_s0 = 0, + vfp_s0 = 17, // match the g_gdb_register_map_arm table in RNBRemote.cpp vfp_s1, vfp_s2, vfp_s3, @@ -1286,8 +1286,12 @@ enum vfp_s28, vfp_s29, vfp_s30, - vfp_s31, - vfp_d0, + vfp_s31 +}; + +enum +{ + vfp_d0 = 49, // match the g_gdb_register_map_arm table in RNBRemote.cpp vfp_d1, vfp_d2, vfp_d3, @@ -1318,114 +1322,48 @@ enum vfp_d28, vfp_d29, vfp_d30, - vfp_d31, - vfp_fpscr + vfp_d31 }; enum { - exc_exception, - exc_fsr, - exc_far, + vfp_q0 = 81, // match the g_gdb_register_map_arm table in RNBRemote.cpp + vfp_q1, + vfp_q2, + vfp_q3, + vfp_q4, + vfp_q5, + vfp_q6, + vfp_q7, + vfp_q8, + vfp_q9, + vfp_q10, + vfp_q11, + vfp_q12, + vfp_q13, + vfp_q14, + vfp_q15, + vfp_fpscr }; enum { - gdb_r0 = 0, - gdb_r1, - gdb_r2, - gdb_r3, - gdb_r4, - gdb_r5, - gdb_r6, - gdb_r7, - gdb_r8, - gdb_r9, - gdb_r10, - gdb_r11, - gdb_r12, - gdb_sp, - gdb_lr, - gdb_pc, - gdb_f0, - gdb_f1, - gdb_f2, - gdb_f3, - gdb_f4, - gdb_f5, - gdb_f6, - gdb_f7, - gdb_f8, - gdb_cpsr, - gdb_s0, - gdb_s1, - gdb_s2, - gdb_s3, - gdb_s4, - gdb_s5, - gdb_s6, - gdb_s7, - gdb_s8, - gdb_s9, - gdb_s10, - gdb_s11, - gdb_s12, - gdb_s13, - gdb_s14, - gdb_s15, - gdb_s16, - gdb_s17, - gdb_s18, - gdb_s19, - gdb_s20, - gdb_s21, - gdb_s22, - gdb_s23, - gdb_s24, - gdb_s25, - gdb_s26, - gdb_s27, - gdb_s28, - gdb_s29, - gdb_s30, - gdb_s31, - gdb_fpscr, - gdb_d0, - gdb_d1, - gdb_d2, - gdb_d3, - gdb_d4, - gdb_d5, - gdb_d6, - gdb_d7, - gdb_d8, - gdb_d9, - gdb_d10, - gdb_d11, - gdb_d12, - gdb_d13, - gdb_d14, - gdb_d15 + exc_exception, + exc_fsr, + exc_far, }; #define GPR_OFFSET_IDX(idx) (offsetof (DNBArchMachARM::GPR, __r[idx])) #define GPR_OFFSET_NAME(reg) (offsetof (DNBArchMachARM::GPR, __##reg)) -#define VFP_S_OFFSET_IDX(idx) (offsetof (DNBArchMachARM::FPU, __r[(idx)]) + offsetof (DNBArchMachARM::Context, vfp)) -#define VFP_D_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX ((idx) * 2)) -#define VFP_OFFSET_NAME(reg) (offsetof (DNBArchMachARM::FPU, __##reg) + offsetof (DNBArchMachARM::Context, vfp)) + #define EXC_OFFSET(reg) (offsetof (DNBArchMachARM::EXC, __##reg) + offsetof (DNBArchMachARM::Context, exc)) // These macros will auto define the register name, alt name, register size, // register offset, encoding, format and native register. This ensures that // the register state structures are defined correctly and have the correct // sizes and offsets. -#define DEFINE_GPR_IDX(idx, reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), gcc_##reg, dwarf_##reg, gen, gdb_##reg, NULL, NULL} -#define DEFINE_GPR_NAME(reg, alt, gen, inval) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), gcc_##reg, dwarf_##reg, gen, gdb_##reg, NULL, inval} -//#define FLOAT_FORMAT Float -#define FLOAT_FORMAT Hex -#define DEFINE_VFP_S_IDX(idx) { e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, gdb_s##idx, NULL, NULL} -//#define DEFINE_VFP_D_IDX(idx) { e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, Float, 8, VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, gdb_d##idx } -#define DEFINE_VFP_D_IDX(idx) { e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL } +#define DEFINE_GPR_IDX(idx, reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), gcc_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL} +#define DEFINE_GPR_NAME(reg, alt, gen, inval) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), gcc_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, inval} // In case we are debugging to a debug target that the ability to // change into the protected modes with folded registers (ABT, IRQ, @@ -1465,75 +1403,140 @@ DNBArchMachARM::g_gpr_registers[] = DEFINE_GPR_NAME (cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr) }; +uint32_t g_contained_q0[] {vfp_q0, INVALID_NUB_REGNUM }; +uint32_t g_contained_q1[] {vfp_q1, INVALID_NUB_REGNUM }; +uint32_t g_contained_q2[] {vfp_q2, INVALID_NUB_REGNUM }; +uint32_t g_contained_q3[] {vfp_q3, INVALID_NUB_REGNUM }; +uint32_t g_contained_q4[] {vfp_q4, INVALID_NUB_REGNUM }; +uint32_t g_contained_q5[] {vfp_q5, INVALID_NUB_REGNUM }; +uint32_t g_contained_q6[] {vfp_q6, INVALID_NUB_REGNUM }; +uint32_t g_contained_q7[] {vfp_q7, INVALID_NUB_REGNUM }; +uint32_t g_contained_q8[] {vfp_q8, INVALID_NUB_REGNUM }; +uint32_t g_contained_q9[] {vfp_q9, INVALID_NUB_REGNUM }; +uint32_t g_contained_q10[] {vfp_q10, INVALID_NUB_REGNUM }; +uint32_t g_contained_q11[] {vfp_q11, INVALID_NUB_REGNUM }; +uint32_t g_contained_q12[] {vfp_q12, INVALID_NUB_REGNUM }; +uint32_t g_contained_q13[] {vfp_q13, INVALID_NUB_REGNUM }; +uint32_t g_contained_q14[] {vfp_q14, INVALID_NUB_REGNUM }; +uint32_t g_contained_q15[] {vfp_q15, INVALID_NUB_REGNUM }; + +uint32_t g_invalidate_q0[] {vfp_q0, vfp_d0, vfp_d1, vfp_s0, vfp_s1, vfp_s2, vfp_s3, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q1[] {vfp_q1, vfp_d2, vfp_d3, vfp_s4, vfp_s5, vfp_s6, vfp_s7, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q2[] {vfp_q2, vfp_d4, vfp_d5, vfp_s8, vfp_s9, vfp_s10, vfp_s11, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q3[] {vfp_q3, vfp_d6, vfp_d7, vfp_s12, vfp_s13, vfp_s14, vfp_s15, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q4[] {vfp_q4, vfp_d8, vfp_d9, vfp_s16, vfp_s17, vfp_s18, vfp_s19, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q5[] {vfp_q5, vfp_d10, vfp_d11, vfp_s20, vfp_s21, vfp_s22, vfp_s23, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q6[] {vfp_q6, vfp_d12, vfp_d13, vfp_s24, vfp_s25, vfp_s26, vfp_s27, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q7[] {vfp_q7, vfp_d14, vfp_d15, vfp_s28, vfp_s29, vfp_s30, vfp_s31, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q8[] {vfp_q8, vfp_d16, vfp_d17, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q9[] {vfp_q9, vfp_d18, vfp_d19, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q10[] {vfp_q10, vfp_d20, vfp_d21, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q11[] {vfp_q11, vfp_d22, vfp_d23, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q12[] {vfp_q12, vfp_d24, vfp_d25, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q13[] {vfp_q13, vfp_d26, vfp_d27, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q14[] {vfp_q14, vfp_d28, vfp_d29, INVALID_NUB_REGNUM }; +uint32_t g_invalidate_q15[] {vfp_q15, vfp_d30, vfp_d31, INVALID_NUB_REGNUM }; + +#define VFP_S_OFFSET_IDX(idx) (offsetof (DNBArchMachARM::FPU, __r[(idx)]) + offsetof (DNBArchMachARM::Context, vfp)) +#define VFP_D_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX ((idx) * 2)) +#define VFP_Q_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX ((idx) * 4)) + +#define VFP_OFFSET_NAME(reg) (offsetof (DNBArchMachARM::FPU, __##reg) + offsetof (DNBArchMachARM::Context, vfp)) + +#define FLOAT_FORMAT Float + +#define DEFINE_VFP_S_IDX(idx) e_regSetVFP, vfp_s##idx - vfp_s0, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM +#define DEFINE_VFP_D_IDX(idx) e_regSetVFP, vfp_d##idx - vfp_s0, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM +#define DEFINE_VFP_Q_IDX(idx) e_regSetVFP, vfp_q##idx - vfp_s0, "q" #idx, NULL, Vector, VectorOfUInt8, 16, VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM + // Floating point registers const DNBRegisterInfo DNBArchMachARM::g_vfp_registers[] = { - DEFINE_VFP_S_IDX ( 0), - DEFINE_VFP_S_IDX ( 1), - DEFINE_VFP_S_IDX ( 2), - DEFINE_VFP_S_IDX ( 3), - DEFINE_VFP_S_IDX ( 4), - DEFINE_VFP_S_IDX ( 5), - DEFINE_VFP_S_IDX ( 6), - DEFINE_VFP_S_IDX ( 7), - DEFINE_VFP_S_IDX ( 8), - DEFINE_VFP_S_IDX ( 9), - DEFINE_VFP_S_IDX (10), - DEFINE_VFP_S_IDX (11), - DEFINE_VFP_S_IDX (12), - DEFINE_VFP_S_IDX (13), - DEFINE_VFP_S_IDX (14), - DEFINE_VFP_S_IDX (15), - DEFINE_VFP_S_IDX (16), - DEFINE_VFP_S_IDX (17), - DEFINE_VFP_S_IDX (18), - DEFINE_VFP_S_IDX (19), - DEFINE_VFP_S_IDX (20), - DEFINE_VFP_S_IDX (21), - DEFINE_VFP_S_IDX (22), - DEFINE_VFP_S_IDX (23), - DEFINE_VFP_S_IDX (24), - DEFINE_VFP_S_IDX (25), - DEFINE_VFP_S_IDX (26), - DEFINE_VFP_S_IDX (27), - DEFINE_VFP_S_IDX (28), - DEFINE_VFP_S_IDX (29), - DEFINE_VFP_S_IDX (30), - DEFINE_VFP_S_IDX (31), - DEFINE_VFP_D_IDX (0), - DEFINE_VFP_D_IDX (1), - DEFINE_VFP_D_IDX (2), - DEFINE_VFP_D_IDX (3), - DEFINE_VFP_D_IDX (4), - DEFINE_VFP_D_IDX (5), - DEFINE_VFP_D_IDX (6), - DEFINE_VFP_D_IDX (7), - DEFINE_VFP_D_IDX (8), - DEFINE_VFP_D_IDX (9), - DEFINE_VFP_D_IDX (10), - DEFINE_VFP_D_IDX (11), - DEFINE_VFP_D_IDX (12), - DEFINE_VFP_D_IDX (13), - DEFINE_VFP_D_IDX (14), - DEFINE_VFP_D_IDX (15), - DEFINE_VFP_D_IDX (16), - DEFINE_VFP_D_IDX (17), - DEFINE_VFP_D_IDX (18), - DEFINE_VFP_D_IDX (19), - DEFINE_VFP_D_IDX (20), - DEFINE_VFP_D_IDX (21), - DEFINE_VFP_D_IDX (22), - DEFINE_VFP_D_IDX (23), - DEFINE_VFP_D_IDX (24), - DEFINE_VFP_D_IDX (25), - DEFINE_VFP_D_IDX (26), - DEFINE_VFP_D_IDX (27), - DEFINE_VFP_D_IDX (28), - DEFINE_VFP_D_IDX (29), - DEFINE_VFP_D_IDX (30), - DEFINE_VFP_D_IDX (31), - { e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_fpscr, NULL, NULL } + { DEFINE_VFP_S_IDX ( 0), g_contained_q0, g_invalidate_q0 }, + { DEFINE_VFP_S_IDX ( 1), g_contained_q0, g_invalidate_q0 }, + { DEFINE_VFP_S_IDX ( 2), g_contained_q0, g_invalidate_q0 }, + { DEFINE_VFP_S_IDX ( 3), g_contained_q0, g_invalidate_q0 }, + { DEFINE_VFP_S_IDX ( 4), g_contained_q1, g_invalidate_q1 }, + { DEFINE_VFP_S_IDX ( 5), g_contained_q1, g_invalidate_q1 }, + { DEFINE_VFP_S_IDX ( 6), g_contained_q1, g_invalidate_q1 }, + { DEFINE_VFP_S_IDX ( 7), g_contained_q1, g_invalidate_q1 }, + { DEFINE_VFP_S_IDX ( 8), g_contained_q2, g_invalidate_q2 }, + { DEFINE_VFP_S_IDX ( 9), g_contained_q2, g_invalidate_q2 }, + { DEFINE_VFP_S_IDX (10), g_contained_q2, g_invalidate_q2 }, + { DEFINE_VFP_S_IDX (11), g_contained_q2, g_invalidate_q2 }, + { DEFINE_VFP_S_IDX (12), g_contained_q3, g_invalidate_q3 }, + { DEFINE_VFP_S_IDX (13), g_contained_q3, g_invalidate_q3 }, + { DEFINE_VFP_S_IDX (14), g_contained_q3, g_invalidate_q3 }, + { DEFINE_VFP_S_IDX (15), g_contained_q3, g_invalidate_q3 }, + { DEFINE_VFP_S_IDX (16), g_contained_q4, g_invalidate_q4 }, + { DEFINE_VFP_S_IDX (17), g_contained_q4, g_invalidate_q4 }, + { DEFINE_VFP_S_IDX (18), g_contained_q4, g_invalidate_q4 }, + { DEFINE_VFP_S_IDX (19), g_contained_q4, g_invalidate_q4 }, + { DEFINE_VFP_S_IDX (20), g_contained_q5, g_invalidate_q5 }, + { DEFINE_VFP_S_IDX (21), g_contained_q5, g_invalidate_q5 }, + { DEFINE_VFP_S_IDX (22), g_contained_q5, g_invalidate_q5 }, + { DEFINE_VFP_S_IDX (23), g_contained_q5, g_invalidate_q5 }, + { DEFINE_VFP_S_IDX (24), g_contained_q6, g_invalidate_q6 }, + { DEFINE_VFP_S_IDX (25), g_contained_q6, g_invalidate_q6 }, + { DEFINE_VFP_S_IDX (26), g_contained_q6, g_invalidate_q6 }, + { DEFINE_VFP_S_IDX (27), g_contained_q6, g_invalidate_q6 }, + { DEFINE_VFP_S_IDX (28), g_contained_q7, g_invalidate_q7 }, + { DEFINE_VFP_S_IDX (29), g_contained_q7, g_invalidate_q7 }, + { DEFINE_VFP_S_IDX (30), g_contained_q7, g_invalidate_q7 }, + { DEFINE_VFP_S_IDX (31), g_contained_q7, g_invalidate_q7 }, + + { DEFINE_VFP_D_IDX (0), g_contained_q0, g_invalidate_q0 }, + { DEFINE_VFP_D_IDX (1), g_contained_q0, g_invalidate_q0 }, + { DEFINE_VFP_D_IDX (2), g_contained_q1, g_invalidate_q1 }, + { DEFINE_VFP_D_IDX (3), g_contained_q1, g_invalidate_q1 }, + { DEFINE_VFP_D_IDX (4), g_contained_q2, g_invalidate_q2 }, + { DEFINE_VFP_D_IDX (5), g_contained_q2, g_invalidate_q2 }, + { DEFINE_VFP_D_IDX (6), g_contained_q3, g_invalidate_q3 }, + { DEFINE_VFP_D_IDX (7), g_contained_q3, g_invalidate_q3 }, + { DEFINE_VFP_D_IDX (8), g_contained_q4, g_invalidate_q4 }, + { DEFINE_VFP_D_IDX (9), g_contained_q4, g_invalidate_q4 }, + { DEFINE_VFP_D_IDX (10), g_contained_q5, g_invalidate_q5 }, + { DEFINE_VFP_D_IDX (11), g_contained_q5, g_invalidate_q5 }, + { DEFINE_VFP_D_IDX (12), g_contained_q6, g_invalidate_q6 }, + { DEFINE_VFP_D_IDX (13), g_contained_q6, g_invalidate_q6 }, + { DEFINE_VFP_D_IDX (14), g_contained_q7, g_invalidate_q7 }, + { DEFINE_VFP_D_IDX (15), g_contained_q7, g_invalidate_q7 }, + { DEFINE_VFP_D_IDX (16), g_contained_q8, g_invalidate_q8 }, + { DEFINE_VFP_D_IDX (17), g_contained_q8, g_invalidate_q8 }, + { DEFINE_VFP_D_IDX (18), g_contained_q9, g_invalidate_q9 }, + { DEFINE_VFP_D_IDX (19), g_contained_q9, g_invalidate_q9 }, + { DEFINE_VFP_D_IDX (20), g_contained_q10, g_invalidate_q10 }, + { DEFINE_VFP_D_IDX (21), g_contained_q10, g_invalidate_q10 }, + { DEFINE_VFP_D_IDX (22), g_contained_q11, g_invalidate_q11 }, + { DEFINE_VFP_D_IDX (23), g_contained_q11, g_invalidate_q11 }, + { DEFINE_VFP_D_IDX (24), g_contained_q12, g_invalidate_q12 }, + { DEFINE_VFP_D_IDX (25), g_contained_q12, g_invalidate_q12 }, + { DEFINE_VFP_D_IDX (26), g_contained_q13, g_invalidate_q13 }, + { DEFINE_VFP_D_IDX (27), g_contained_q13, g_invalidate_q13 }, + { DEFINE_VFP_D_IDX (28), g_contained_q14, g_invalidate_q14 }, + { DEFINE_VFP_D_IDX (29), g_contained_q14, g_invalidate_q14 }, + { DEFINE_VFP_D_IDX (30), g_contained_q15, g_invalidate_q15 }, + { DEFINE_VFP_D_IDX (31), g_contained_q15, g_invalidate_q15 }, + + { DEFINE_VFP_Q_IDX (0), NULL, g_invalidate_q0 }, + { DEFINE_VFP_Q_IDX (1), NULL, g_invalidate_q1 }, + { DEFINE_VFP_Q_IDX (2), NULL, g_invalidate_q2 }, + { DEFINE_VFP_Q_IDX (3), NULL, g_invalidate_q3 }, + { DEFINE_VFP_Q_IDX (4), NULL, g_invalidate_q4 }, + { DEFINE_VFP_Q_IDX (5), NULL, g_invalidate_q5 }, + { DEFINE_VFP_Q_IDX (6), NULL, g_invalidate_q6 }, + { DEFINE_VFP_Q_IDX (7), NULL, g_invalidate_q7 }, + { DEFINE_VFP_Q_IDX (8), NULL, g_invalidate_q8 }, + { DEFINE_VFP_Q_IDX (9), NULL, g_invalidate_q9 }, + { DEFINE_VFP_Q_IDX (10), NULL, g_invalidate_q10 }, + { DEFINE_VFP_Q_IDX (11), NULL, g_invalidate_q11 }, + { DEFINE_VFP_Q_IDX (12), NULL, g_invalidate_q12 }, + { DEFINE_VFP_Q_IDX (13), NULL, g_invalidate_q13 }, + { DEFINE_VFP_Q_IDX (14), NULL, g_invalidate_q14 }, + { DEFINE_VFP_Q_IDX (15), NULL, g_invalidate_q15 }, + + { e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL } }; // Exception registers @@ -1631,12 +1634,16 @@ DNBArchMachARM::GetRegisterValue(int set, int reg, DNBRegisterValue *value) break; case e_regSetVFP: - if (reg <= vfp_s31) + // "reg" is an index into the floating point register set at this point. + // We need to translate it up so entry 0 in the fp reg set is the same as vfp_s0 + // in the enumerated values for case statement below. + reg += vfp_s0; + if (reg >= vfp_s0 && reg <= vfp_s31) { - value->value.uint32 = m_state.context.vfp.__r[reg]; + value->value.uint32 = m_state.context.vfp.__r[reg - vfp_s0]; return true; } - else if (reg <= vfp_d31) + else if (reg >= vfp_d0 && reg <= vfp_d31) { uint32_t d_reg_idx = reg - vfp_d0; uint32_t s_reg_idx = d_reg_idx * 2; @@ -1644,6 +1651,13 @@ DNBArchMachARM::GetRegisterValue(int set, int reg, DNBRegisterValue *value) value->value.v_sint32[1] = m_state.context.vfp.__r[s_reg_idx + 1]; return true; } + else if (reg >= vfp_q0 && reg <= vfp_q15) + { + uint32_t s_reg_idx = (reg - vfp_q0) * 4; + memcpy (&value->value.v_uint8, (uint8_t *) &m_state.context.vfp.__r[s_reg_idx], 16); + return true; + } + else if (reg == vfp_fpscr) { value->value.uint32 = m_state.context.vfp.__fpscr; @@ -1718,12 +1732,17 @@ DNBArchMachARM::SetRegisterValue(int set, int reg, const DNBRegisterValue *value break; case e_regSetVFP: - if (reg <= vfp_s31) + // "reg" is an index into the floating point register set at this point. + // We need to translate it up so entry 0 in the fp reg set is the same as vfp_s0 + // in the enumerated values for case statement below. + reg += vfp_s0; + + if (reg >= vfp_s0 && reg <= vfp_s31) { - m_state.context.vfp.__r[reg] = value->value.uint32; + m_state.context.vfp.__r[reg - vfp_s0] = value->value.uint32; success = true; } - else if (reg <= vfp_d31) + else if (reg >= vfp_d0 && reg <= vfp_d31) { uint32_t d_reg_idx = reg - vfp_d0; uint32_t s_reg_idx = d_reg_idx * 2; @@ -1731,6 +1750,12 @@ DNBArchMachARM::SetRegisterValue(int set, int reg, const DNBRegisterValue *value m_state.context.vfp.__r[s_reg_idx + 1] = value->value.v_sint32[1]; success = true; } + else if (reg >= vfp_q0 && reg <= vfp_q15) + { + uint32_t s_reg_idx = (reg - vfp_q0) * 4; + memcpy ((uint8_t *) &m_state.context.vfp.__r[s_reg_idx], &value->value.v_uint8, 16); + return true; + } else if (reg == vfp_fpscr) { m_state.context.vfp.__fpscr = value->value.uint32; diff --git a/lldb/tools/debugserver/source/RNBRemote.cpp b/lldb/tools/debugserver/source/RNBRemote.cpp index f3612e8..2670051 100644 --- a/lldb/tools/debugserver/source/RNBRemote.cpp +++ b/lldb/tools/debugserver/source/RNBRemote.cpp @@ -878,65 +878,88 @@ g_gdb_register_map_arm[] = { 13, 4, "sp", {0}, NULL, 1}, { 14, 4, "lr", {0}, NULL, 1}, { 15, 4, "pc", {0}, NULL, 1}, - { 16, 12, "f0", {0}, k_zero_bytes, 0}, - { 17, 12, "f1", {0}, k_zero_bytes, 0}, - { 18, 12, "f2", {0}, k_zero_bytes, 0}, - { 19, 12, "f3", {0}, k_zero_bytes, 0}, - { 20, 12, "f4", {0}, k_zero_bytes, 0}, - { 21, 12, "f5", {0}, k_zero_bytes, 0}, - { 22, 12, "f6", {0}, k_zero_bytes, 0}, - { 23, 12, "f7", {0}, k_zero_bytes, 0}, - { 24, 4, "fps", {0}, k_zero_bytes, 0}, - { 25, 4,"cpsr", {0}, NULL, 1}, - { 26, 4, "s0", {0}, NULL, 0}, - { 27, 4, "s1", {0}, NULL, 0}, - { 28, 4, "s2", {0}, NULL, 0}, - { 29, 4, "s3", {0}, NULL, 0}, - { 30, 4, "s4", {0}, NULL, 0}, - { 31, 4, "s5", {0}, NULL, 0}, - { 32, 4, "s6", {0}, NULL, 0}, - { 33, 4, "s7", {0}, NULL, 0}, - { 34, 4, "s8", {0}, NULL, 0}, - { 35, 4, "s9", {0}, NULL, 0}, - { 36, 4, "s10", {0}, NULL, 0}, - { 37, 4, "s11", {0}, NULL, 0}, - { 38, 4, "s12", {0}, NULL, 0}, - { 39, 4, "s13", {0}, NULL, 0}, - { 40, 4, "s14", {0}, NULL, 0}, - { 41, 4, "s15", {0}, NULL, 0}, - { 42, 4, "s16", {0}, NULL, 0}, - { 43, 4, "s17", {0}, NULL, 0}, - { 44, 4, "s18", {0}, NULL, 0}, - { 45, 4, "s19", {0}, NULL, 0}, - { 46, 4, "s20", {0}, NULL, 0}, - { 47, 4, "s21", {0}, NULL, 0}, - { 48, 4, "s22", {0}, NULL, 0}, - { 49, 4, "s23", {0}, NULL, 0}, - { 50, 4, "s24", {0}, NULL, 0}, - { 51, 4, "s25", {0}, NULL, 0}, - { 52, 4, "s26", {0}, NULL, 0}, - { 53, 4, "s27", {0}, NULL, 0}, - { 54, 4, "s28", {0}, NULL, 0}, - { 55, 4, "s29", {0}, NULL, 0}, - { 56, 4, "s30", {0}, NULL, 0}, - { 57, 4, "s31", {0}, NULL, 0}, - { 58, 4, "fpscr", {0}, NULL, 0}, - { 59, 8, "d16", {0}, NULL, 0}, - { 60, 8, "d17", {0}, NULL, 0}, - { 61, 8, "d18", {0}, NULL, 0}, - { 62, 8, "d19", {0}, NULL, 0}, - { 63, 8, "d20", {0}, NULL, 0}, - { 64, 8, "d21", {0}, NULL, 0}, - { 65, 8, "d22", {0}, NULL, 0}, - { 66, 8, "d23", {0}, NULL, 0}, - { 67, 8, "d24", {0}, NULL, 0}, - { 68, 8, "d25", {0}, NULL, 0}, - { 69, 8, "d26", {0}, NULL, 0}, - { 70, 8, "d27", {0}, NULL, 0}, - { 71, 8, "d28", {0}, NULL, 0}, - { 72, 8, "d29", {0}, NULL, 0}, - { 73, 8, "d30", {0}, NULL, 0}, - { 74, 8, "d31", {0}, NULL, 0} + { 16, 4,"cpsr", {0}, NULL, 1}, // current program status register + { 17, 4, "s0", {0}, NULL, 0}, + { 18, 4, "s1", {0}, NULL, 0}, + { 19, 4, "s2", {0}, NULL, 0}, + { 20, 4, "s3", {0}, NULL, 0}, + { 21, 4, "s4", {0}, NULL, 0}, + { 22, 4, "s5", {0}, NULL, 0}, + { 23, 4, "s6", {0}, NULL, 0}, + { 24, 4, "s7", {0}, NULL, 0}, + { 25, 4, "s8", {0}, NULL, 0}, + { 26, 4, "s9", {0}, NULL, 0}, + { 27, 4, "s10", {0}, NULL, 0}, + { 28, 4, "s11", {0}, NULL, 0}, + { 29, 4, "s12", {0}, NULL, 0}, + { 30, 4, "s13", {0}, NULL, 0}, + { 31, 4, "s14", {0}, NULL, 0}, + { 32, 4, "s15", {0}, NULL, 0}, + { 33, 4, "s16", {0}, NULL, 0}, + { 34, 4, "s17", {0}, NULL, 0}, + { 35, 4, "s18", {0}, NULL, 0}, + { 36, 4, "s19", {0}, NULL, 0}, + { 37, 4, "s20", {0}, NULL, 0}, + { 38, 4, "s21", {0}, NULL, 0}, + { 39, 4, "s22", {0}, NULL, 0}, + { 40, 4, "s23", {0}, NULL, 0}, + { 41, 4, "s24", {0}, NULL, 0}, + { 42, 4, "s25", {0}, NULL, 0}, + { 43, 4, "s26", {0}, NULL, 0}, + { 44, 4, "s27", {0}, NULL, 0}, + { 45, 4, "s28", {0}, NULL, 0}, + { 46, 4, "s29", {0}, NULL, 0}, + { 47, 4, "s30", {0}, NULL, 0}, + { 48, 4, "s31", {0}, NULL, 0}, + { 49, 8, "d0", {0}, NULL, 0}, + { 50, 8, "d1", {0}, NULL, 0}, + { 51, 8, "d2", {0}, NULL, 0}, + { 52, 8, "d3", {0}, NULL, 0}, + { 53, 8, "d4", {0}, NULL, 0}, + { 54, 8, "d5", {0}, NULL, 0}, + { 55, 8, "d6", {0}, NULL, 0}, + { 56, 8, "d7", {0}, NULL, 0}, + { 57, 8, "d8", {0}, NULL, 0}, + { 58, 8, "d9", {0}, NULL, 0}, + { 59, 8, "d10", {0}, NULL, 0}, + { 60, 8, "d11", {0}, NULL, 0}, + { 61, 8, "d12", {0}, NULL, 0}, + { 62, 8, "d13", {0}, NULL, 0}, + { 63, 8, "d14", {0}, NULL, 0}, + { 64, 8, "d15", {0}, NULL, 0}, + { 65, 8, "d16", {0}, NULL, 0}, + { 66, 8, "d17", {0}, NULL, 0}, + { 67, 8, "d18", {0}, NULL, 0}, + { 68, 8, "d19", {0}, NULL, 0}, + { 69, 8, "d20", {0}, NULL, 0}, + { 70, 8, "d21", {0}, NULL, 0}, + { 71, 8, "d22", {0}, NULL, 0}, + { 72, 8, "d23", {0}, NULL, 0}, + { 73, 8, "d24", {0}, NULL, 0}, + { 74, 8, "d25", {0}, NULL, 0}, + { 75, 8, "d26", {0}, NULL, 0}, + { 76, 8, "d27", {0}, NULL, 0}, + { 77, 8, "d28", {0}, NULL, 0}, + { 78, 8, "d29", {0}, NULL, 0}, + { 79, 8, "d30", {0}, NULL, 0}, + { 80, 8, "d31", {0}, NULL, 0}, + { 81, 16, "q0", {0}, NULL, 0}, + { 82, 16, "q1", {0}, NULL, 0}, + { 83, 16, "q2", {0}, NULL, 0}, + { 84, 16, "q3", {0}, NULL, 0}, + { 85, 16, "q4", {0}, NULL, 0}, + { 86, 16, "q5", {0}, NULL, 0}, + { 87, 16, "q6", {0}, NULL, 0}, + { 88, 16, "q7", {0}, NULL, 0}, + { 89, 16, "q8", {0}, NULL, 0}, + { 90, 16, "q9", {0}, NULL, 0}, + { 91, 16, "q10", {0}, NULL, 0}, + { 92, 16, "q11", {0}, NULL, 0}, + { 93, 16, "q12", {0}, NULL, 0}, + { 94, 16, "q13", {0}, NULL, 0}, + { 95, 16, "q14", {0}, NULL, 0}, + { 96, 16, "q15", {0}, NULL, 0}, + { 97, 4, "fpscr", {0}, NULL, 0} }; register_map_entry_t