From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Date: Fri, 26 Aug 2016 10:30:38 +0000 (+0800)
Subject: armv8: fsl-layerscape: Update ddr erratum a008336
X-Git-Tag: v2016.11-rc1~40^2~32
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f;p=platform%2Fkernel%2Fu-boot.git

armv8: fsl-layerscape: Update ddr erratum a008336

DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..28928b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -58,11 +58,13 @@ static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-	out_le32(eddrtqcr1, 0x63b30002);
+	if (fsl_ddr_get_version(0) == 0x50200)
+		out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
 	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-	out_le32(eddrtqcr1, 0x63b30002);
+	if (fsl_ddr_get_version(0) == 0x50200)
+		out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #endif
 }