From: David S. Miller Date: Wed, 23 Apr 2008 07:49:33 +0000 (+0000) Subject: opcodes/ X-Git-Tag: sid-snapshot-20080501~83 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1a6b486f7396aef713425cd01fb9861e53fb6227;p=external%2Fbinutils.git opcodes/ * sparc-opc.c (asi_table): Add UltraSPARC and Niagara extended values. (prefetch_table): Add missing values. gas/ * config/tc-sparc.c (v9a_asr_table): Add missing 'stick' and 'stick_cmpr', and document ordering rules of table. (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and BFD_RELOC_SPARC_PC10. * doc/c-sparc.texi: New section on Sparc constants. Add documentation for %stick and %stick_cmpr. gas/testsuite/ * gas/sparc/pc2210.d: New file. * gas/sparc/pc2210.d: Likewise. * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 3547186..d2b627c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2008-04-23 David S. Miller + + * config/tc-sparc.c (v9a_asr_table): Add missing + 'stick' and 'stick_cmpr', and document ordering rules + of table. + (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and + BFD_RELOC_SPARC_PC10. + * doc/c-sparc.texi: New section on Sparc constants. + Add documentation for %stick and %stick_cmpr. + 2008-04-22 H.J. Lu * config/tc-i386.c (md_assemble): Don't check SSE instructions diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c index 8116c8e..1b657f5 100644 --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -768,13 +768,16 @@ struct priv_reg_entry hpriv_reg_table[] = {"", -1}, /* End marker. */ }; -/* v9a specific asrs. */ +/* v9a specific asrs. This table is ordered by initial + letter, in reverse. */ struct priv_reg_entry v9a_asr_table[] = { {"tick_cmpr", 23}, {"sys_tick_cmpr", 25}, {"sys_tick", 24}, + {"stick_cmpr", 25}, + {"stick", 24}, {"softint", 22}, {"set_softint", 20}, {"pic", 17}, @@ -3398,6 +3401,8 @@ tc_gen_reloc (section, fixp) case BFD_RELOC_32_PCREL_S2: case BFD_RELOC_SPARC13: case BFD_RELOC_SPARC22: + case BFD_RELOC_SPARC_PC22: + case BFD_RELOC_SPARC_PC10: case BFD_RELOC_SPARC_BASE13: case BFD_RELOC_SPARC_WDISP16: case BFD_RELOC_SPARC_WDISP19: diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi index cd0884c..3e172fc 100644 --- a/gas/doc/c-sparc.texi +++ b/gas/doc/c-sparc.texi @@ -121,6 +121,7 @@ for their UltraSPARC and Niagara line of processors. @menu * Sparc-Chars:: Special Characters * Sparc-Regs:: Register Names +* Sparc-Constants:: Constant Names * Sparc-Relocs:: Relocations @end menu @@ -185,10 +186,14 @@ processors: The tick compare register is referred to as @samp{%tick_cmpr}. @item -The system tick register is referred to as @samp{%sys_tick}. +The system tick register is referred to as @samp{%stick}. An alias, +@samp{%sys_tick}, exists but is deprecated and should not be used +by new software. @item -The system tick compare register is referred to as @samp{%sys_tick_cmpr}. +The system tick compare register is referred to as @samp{%stick_cmpr}. +An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should +not be used by new software. @item The software interrupt register is referred to as @samp{%softint}. @@ -334,7 +339,138 @@ to as @samp{%hver}. @item The hyperprivileged system tick compare register is referred -to as @samp{%hstick_cmpr}. +to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick} +register, the normal @samp{%stick} is used. +@end itemize + +@node Sparc-Constants +@subsection Constants +@cindex Sparc constants +@cindex constants, Sparc + +Several Sparc instructions take an immediate operand field for +which mnemonic names exist. Two such examples are @samp{membar} +and @samp{prefetch}. Another example are the set of V9 +memory access instruction that allow specification of an +address space identifier. + +The @samp{membar} instruction specifies a memory barrier that is +the defined by the operand which is a bitmask. The supported +mask mnemonics are: + +@itemize @bullet +@item +@samp{#Sync} requests that all operations (including nonmemory +reference operations) appearing prior to the @code{membar} must have +been performed and the effects of any exceptions become visible before +any instructions after the @code{membar} may be initiated. This +corresponds to @code{membar} cmask field bit 2. + +@item +@samp{#MemIssue} requests that all memory reference operations +appearing prior to the @code{membar} must have been performed before +any memory operation after the @code{membar} may be initiated. This +corresponds to @code{membar} cmask field bit 1. + +@item +@samp{#Lookaside} requests that a store appearing prior to the +@code{membar} must complete before any load following the +@code{membar} referencing the same address can be initiated. This +corresponds to @code{membar} cmask field bit 0. + +@item +@samp{#StoreStore} defines that the effects of all stores appearing +prior to the @code{membar} instruction must be visible to all +processors before the effect of any stores following the +@code{membar}. Equivalent to the deprecated @code{stbar} instruction. +This corresponds to @code{membar} mmask field bit 3. + +@item +@samp{#LoadStore} defines all loads appearing prior to the +@code{membar} instruction must have been performed before the effect +of any stores following the @code{membar} is visible to any other +processor. This corresponds to @code{membar} mmask field bit 2. + +@item +@samp{#StoreLoad} defines that the effects of all stores appearing +prior to the @code{membar} instruction must be visible to all +processors before loads following the @code{membar} may be performed. +This corresponds to @code{membar} mmask field bit 1. + +@item +@samp{#LoadLoad} defines that all loads appearing prior to the +@code{membar} instruction must have been performed before any loads +following the @code{membar} may be performed. This corresponds to +@code{membar} mmask field bit 0. + +@end itemize + +These values can be ored together, for example: + +@example +membar #Sync +membar #StoreLoad | #LoadLoad +membar #StoreLoad | #StoreStore +@end example + +The @code{prefetch} and @code{prefetcha} instructions take a prefetch +function code. The following prefetch function code constant +mnemonics are available: + +@itemize @bullet +@item +@samp{#n_reads} requests a prefetch for several reads, and corresponds +to a prefetch function code of 0. + +@samp{#one_read} requests a prefetch for one read, and corresponds +to a prefetch function code of 1. + +@samp{#n_writes} requests a prefetch for several writes (and possibly +reads), and corresponds to a prefetch function code of 2. + +@samp{#one_write} requests a prefetch for one write, and corresponds +to a prefetch function code of 3. + +@samp{#page} requests a prefetch page, and corresponds to a prefetch +function code of 4. + +@samp{#invalidate} requests a prefetch invalidate, and corresponds to +a prefetch function code of 16. + +@samp{#unified} requests a prefetch to the nearest unified cache, and +corresponds to a prefetch function code of 17. + +@samp{#n_reads_strong} requests a strong prefetch for several reads, +and corresponds to a prefetch function code of 20. + +@samp{#one_read_strong} requests a strong prefetch for one read, +and corresponds to a prefetch function code of 21. + +@samp{#n_writes_strong} requests a strong prefetch for several writes, +and corresponds to a prefetch function code of 22. + +@samp{#one_write_strong} requests a strong prefetch for one write, +and corresponds to a prefetch function code of 23. + +Onle one prefetch code may be specified. Here are some examples: + +@example +prefetch [%l0 + %l2], #one_read +prefetch [%g2 + 8], #n_writes +prefetcha [%g1] 0x8, #unified +prefetcha [%o0 + 0x10] %asi, #n_reads +@end example + +The actual behavior of a given prefetch function code is processor +specific. If a processor does not implement a given prefetch +function code, it will treat the prefetch instruction as a nop. + +For instructions that accept an immediate address space identifier, +@code{@value{AS}} provides many mnemonics corresponding to +V9 defined as well as UltraSPARC and Niagara extended values. +For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}. +See the V9 and processor specific manuals for details. + @end itemize @node Sparc-Relocs diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index d8cfbcf..a331751 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2008-04-23 David S. Miller + + * gas/sparc/pc2210.d: New file. + * gas/sparc/pc2210.d: Likewise. + * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test. + 2008-04-18 H.J. Lu * gas/i386/arch-10.d: Updated. diff --git a/gas/testsuite/gas/sparc/pc2210.d b/gas/testsuite/gas/sparc/pc2210.d new file mode 100644 index 0000000..974d3e5 --- /dev/null +++ b/gas/testsuite/gas/sparc/pc2210.d @@ -0,0 +1,13 @@ +#as: -Av7 +#objdump: -dr +#name: pc2210 + +.*: +file format .*sparc.* + +Disassembly of section .text: + +0+ <.text>: + 0: 13 00 00 00 sethi %hi\(0\), %o1 + 0: R_SPARC_PC22 .data + 4: 92 12 60 00 mov %o1, %o1 ! 0 <.text> + 4: R_SPARC_PC10 .data diff --git a/gas/testsuite/gas/sparc/pc2210.s b/gas/testsuite/gas/sparc/pc2210.s new file mode 100644 index 0000000..9190234 --- /dev/null +++ b/gas/testsuite/gas/sparc/pc2210.s @@ -0,0 +1,6 @@ + # Test R_SPARC_PC22 and R_SPARC_PC10 relocations + .data +sym: .word 0 + .text + sethi %pc22(sym), %o1 + or %o1, %pc10(sym), %o1 diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp index d3eec93..dfb6249 100644 --- a/gas/testsuite/gas/sparc/sparc.exp +++ b/gas/testsuite/gas/sparc/sparc.exp @@ -55,6 +55,7 @@ if [istarget sparc*-*-*] { run_dump_test "v9branch3" run_dump_test "v9branch4" run_dump_test "v9branch5" + run_dump_test "pc2210" run_list_test "pr4587" "" } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0ebdc2c..691b393 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2008-04-23 David S. Miller + + * sparc-opc.c (asi_table): Add UltraSPARC and Niagara + extended values. + (prefetch_table): Add missing values. + 2008-04-22 H.J. Lu * i386-gen.c (opcode_modifiers): Add NoAVX. diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index e344f9f..23a0459 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -1899,9 +1899,134 @@ static arg asi_table[] = { 0x89, "#ASI_SECONDARY_LITTLE" }, { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, - /* These are UltraSPARC extensions. */ - /* FIXME: There are dozens of them. Not sure we want them all. - Most are for kernel building but some are for vis type stuff. */ + /* These are UltraSPARC and Niagara extensions. */ + { 0x14, "#ASI_PHYS_USE_EC" }, + { 0x15, "#ASI_PHYS_BYPASS_EC_E" }, + { 0x16, "#ASI_BLK_AIUP_4V" }, + { 0x17, "#ASI_BLK_AIUS_4V" }, + { 0x1c, "#ASI_PHYS_USE_EC_L" }, + { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" }, + { 0x1e, "#ASI_BLK_AIUP_L_4V" }, + { 0x1f, "#ASI_BLK_AIUS_L_4V" }, + { 0x20, "#ASI_SCRATCHPAD" }, + { 0x21, "#ASI_MMU" }, + { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" }, + { 0x24, "#ASI_NUCLEUS_QUAD_LDD" }, + { 0x25, "#ASI_QUEUE" }, + { 0x26, "#ASI_QUAD_LDD_PHYS_4V" }, + { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" }, + { 0x30, "#ASI_PCACHE_DATA_STATUS" }, + { 0x31, "#ASI_PCACHE_DATA" }, + { 0x32, "#ASI_PCACHE_TAG" }, + { 0x33, "#ASI_PCACHE_SNOOP_TAG" }, + { 0x34, "#ASI_QUAD_LDD_PHYS" }, + { 0x38, "#ASI_WCACHE_VALID_BITS" }, + { 0x39, "#ASI_WCACHE_DATA" }, + { 0x3a, "#ASI_WCACHE_TAG" }, + { 0x3b, "#ASI_WCACHE_SNOOP_TAG" }, + { 0x3c, "#ASI_QUAD_LDD_PHYS_L" }, + { 0x40, "#ASI_SRAM_FAST_INIT" }, + { 0x41, "#ASI_CORE_AVAILABLE" }, + { 0x41, "#ASI_CORE_ENABLE_STAT" }, + { 0x41, "#ASI_CORE_ENABLE" }, + { 0x41, "#ASI_XIR_STEERING" }, + { 0x41, "#ASI_CORE_RUNNING_RW" }, + { 0x41, "#ASI_CORE_RUNNING_W1S" }, + { 0x41, "#ASI_CORE_RUNNING_W1C" }, + { 0x41, "#ASI_CORE_RUNNING_STAT" }, + { 0x41, "#ASI_CMT_ERROR_STEERING" }, + { 0x41, "#ASI_DCACHE_INVALIDATE" }, + { 0x41, "#ASI_DCACHE_UTAG" }, + { 0x41, "#ASI_DCACHE_SNOOP_TAG" }, + { 0x42, "#ASI_DCACHE_INVALIDATE" }, + { 0x43, "#ASI_DCACHE_UTAG" }, + { 0x44, "#ASI_DCACHE_SNOOP_TAG" }, + { 0x45, "#ASI_LSU_CONTROL_REG" }, + { 0x45, "#ASI_DCU_CONTROL_REG" }, + { 0x46, "#ASI_DCACHE_DATA" }, + { 0x47, "#ASI_DCACHE_TAG" }, + { 0x48, "#ASI_INTR_DISPATCH_STAT" }, + { 0x49, "#ASI_INTR_RECEIVE" }, + { 0x4a, "#ASI_UPA_CONFIG" }, + { 0x4a, "#ASI_JBUS_CONFIG" }, + { 0x4a, "#ASI_SAFARI_CONFIG" }, + { 0x4a, "#ASI_SAFARI_ADDRESS" }, + { 0x4b, "#ASI_ESTATE_ERROR_EN" }, + { 0x4c, "#ASI_AFSR" }, + { 0x4d, "#ASI_AFAR" }, + { 0x4e, "#ASI_EC_TAG_DATA" }, + { 0x50, "#ASI_IMMU" }, + { 0x51, "#ASI_IMMU_TSB_8KB_PTR" }, + { 0x52, "#ASI_IMMU_TSB_16KB_PTR" }, + { 0x54, "#ASI_ITLB_DATA_IN" }, + { 0x55, "#ASI_ITLB_DATA_ACCESS" }, + { 0x56, "#ASI_ITLB_TAG_READ" }, + { 0x57, "#ASI_IMMU_DEMAP" }, + { 0x58, "#ASI_DMMU" }, + { 0x59, "#ASI_DMMU_TSB_8KB_PTR" }, + { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" }, + { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" }, + { 0x5c, "#ASI_DTLB_DATA_IN" }, + { 0x5d, "#ASI_DTLB_DATA_ACCESS" }, + { 0x5e, "#ASI_DTLB_TAG_READ" }, + { 0x5f, "#ASI_DMMU_DEMAP" }, + { 0x60, "#ASI_IIU_INST_TRAP" }, + { 0x63, "#ASI_INTR_ID" }, + { 0x63, "#ASI_CORE_ID" }, + { 0x63, "#ASI_CESR_ID" }, + { 0x66, "#ASI_IC_INSTR" }, + { 0x67, "#ASI_IC_TAG" }, + { 0x68, "#ASI_IC_STAG" }, + { 0x6e, "#ASI_IC_PRE_DECODE" }, + { 0x6f, "#ASI_IC_NEXT_FIELD" }, + { 0x6f, "#ASI_BRPRED_ARRAY" }, + { 0x70, "#ASI_BLK_AIUP" }, + { 0x71, "#ASI_BLK_AIUS" }, + { 0x72, "#ASI_MCU_CTRL_REG" }, + { 0x74, "#ASI_EC_DATA" }, + { 0x75, "#ASI_EC_CTRL" }, + { 0x76, "#ASI_EC_W" }, + { 0x77, "#ASI_UDB_ERROR_W" }, + { 0x77, "#ASI_UDB_CONTROL_W" }, + { 0x77, "#ASI_INTR_W" }, + { 0x77, "#ASI_INTR_DATAN_W" }, + { 0x77, "#ASI_INTR_DISPATCH_W" }, + { 0x78, "#ASI_BLK_AIUPL" }, + { 0x79, "#ASI_BLK_AIUSL" }, + { 0x7e, "#ASI_EC_R" }, + { 0x7f, "#ASI_UDBH_ERROR_R" }, + { 0x7f, "#ASI_UDBL_ERROR_R" }, + { 0x7f, "#ASI_UDBH_CONTROL_R" }, + { 0x7f, "#ASI_UDBL_CONTROL_R" }, + { 0x7f, "#ASI_INTR_R" }, + { 0x7f, "#ASI_INTR_DATAN_R" }, + { 0xc0, "#ASI_PST8_P" }, + { 0xc1, "#ASI_PST8_S" }, + { 0xc2, "#ASI_PST16_P" }, + { 0xc3, "#ASI_PST16_S" }, + { 0xc4, "#ASI_PST32_P" }, + { 0xc5, "#ASI_PST32_S" }, + { 0xc8, "#ASI_PST8_PL" }, + { 0xc9, "#ASI_PST8_SL" }, + { 0xca, "#ASI_PST16_PL" }, + { 0xcb, "#ASI_PST16_SL" }, + { 0xcc, "#ASI_PST32_PL" }, + { 0xcd, "#ASI_PST32_SL" }, + { 0xd0, "#ASI_FL8_P" }, + { 0xd1, "#ASI_FL8_S" }, + { 0xd2, "#ASI_FL16_P" }, + { 0xd3, "#ASI_FL16_S" }, + { 0xd8, "#ASI_FL8_PL" }, + { 0xd9, "#ASI_FL8_SL" }, + { 0xda, "#ASI_FL16_PL" }, + { 0xdb, "#ASI_FL16_SL" }, + { 0xe0, "#ASI_BLK_COMMIT_P", }, + { 0xe1, "#ASI_BLK_COMMIT_S", }, + { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" }, + { 0xf0, "#ASI_BLK_P", }, + { 0xf1, "#ASI_BLK_S", }, + { 0xf8, "#ASI_BLK_PL", }, + { 0xf9, "#ASI_BLK_SL", }, { 0, 0 } }; @@ -1961,6 +2086,11 @@ static arg prefetch_table[] = { 3, "#one_write" }, { 4, "#page" }, { 16, "#invalidate" }, + { 17, "#unified", }, + { 20, "#n_reads_strong", }, + { 21, "#one_read_strong", }, + { 22, "#n_writes_strong", }, + { 23, "#one_write_strong", }, { 0, 0 } };