From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Thu, 13 Oct 2022 18:06:57 +0000 (-0700)
Subject: Merge patch series "Use composable cache instead of L2 cache"
X-Git-Tag: v6.6.17~6358^2~7
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1a5a2cbd21e58a824688ae2120a3e47b3cd0f876;p=platform%2Fkernel%2Flinux-rpi.git

Merge patch series "Use composable cache instead of L2 cache"

Zong Li <zong.li@sifive.com> says:

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name "composable cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

* b4-shazam-merge:
  riscv: Add cache information in AUX vector
  soc: sifive: ccache: define the macro for the register shifts
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: determine the cache level from dts
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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