From: ManuelJBrito Date: Thu, 9 Mar 2023 14:31:33 +0000 (+0000) Subject: [X86] Drop single use check for freeze(undef) in LowerAVXCONCAT_VECTORS X-Git-Tag: upstream/17.0.6~15367 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1a4d0eb866be909fe16da5ebffe4122aa0693d8c;p=platform%2Fupstream%2Fllvm.git [X86] Drop single use check for freeze(undef) in LowerAVXCONCAT_VECTORS Ignoring freeze(undef) if it has multiple uses in LowerAVXCONCAT_VECTORS causes the custom INSERT_SUBVECTOR for vector widening to be ignored. Differential Revision: https://reviews.llvm.org/D144903 --- diff --git a/clang/test/CodeGen/X86/avx-cast-builtins.c b/clang/test/CodeGen/X86/avx-cast-builtins.c new file mode 100644 index 0000000..8b941c4 --- /dev/null +++ b/clang/test/CodeGen/X86/avx-cast-builtins.c @@ -0,0 +1,101 @@ +// REQUIRES: x86-registered-target +// RUN: %clang_cc1 -O3 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx -target-feature +avx512f -target-feature +avx512fp16 -S -o - | FileCheck %s + + +#include + +__m256d test_mm256_castpd128_pd256(__m128d A) { + // CHECK-LABEL: test_mm256_castpd128_pd256 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm256_castpd128_pd256(A); +} + +__m256 test_mm256_castps128_ps256(__m128 A) { + // CHECK-LABEL: test_mm256_castps128_ps256 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm256_castps128_ps256(A); +} + +__m256i test_mm256_castsi128_si256(__m128i A) { + // CHECK-LABEL: test_mm256_castsi128_si256 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm256_castsi128_si256(A); +} + +__m256h test_mm256_castph128_ph256(__m128h A) { + // CHECK-LABEL: test_mm256_castph128_ph256 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm256_castph128_ph256(A); +} + +__m512h test_mm512_castph128_ph512(__m128h A) { + // CHECK-LABEL: test_mm512_castph128_ph512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castph128_ph512(A); +} + +__m512h test_mm512_castph256_ph512(__m256h A) { + // CHECK-LABEL: test_mm512_castph256_ph512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castph256_ph512(A); +} + +__m512d test_mm512_castpd256_pd512(__m256d A){ + // CHECK-LABEL: test_mm512_castpd256_pd512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castpd256_pd512(A); +} + +__m512 test_mm512_castps256_ps512(__m256 A){ + // CHECK-LABEL: test_mm512_castps256_ps512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castps256_ps512(A); +} + +__m512d test_mm512_castpd128_pd512(__m128d A){ + // CHECK-LABEL: test_mm512_castpd128_pd512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castpd128_pd512(A); +} + +__m512 test_mm512_castps128_ps512(__m128 A){ + // CHECK-LABEL: test_mm512_castps128_ps512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castps128_ps512(A); +} + +__m512i test_mm512_castsi128_si512(__m128i A){ + // CHECK-LABEL: test_mm512_castsi128_si512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castsi128_si512(A); +} + +__m512i test_mm512_castsi256_si512(__m256i A){ + // CHECK-LABEL: test_mm512_castsi256_si512 + // CHECK: # %bb.0: + // CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 + // CHECK-NEXT: ret{{[l|q]}} + return _mm512_castsi256_si512(A); +} diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a8c37db..864ef26 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -11656,7 +11656,7 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG, SDValue SubVec = Op.getOperand(i); if (SubVec.isUndef()) continue; - if (ISD::isFreezeUndef(SubVec.getNode()) && SubVec.hasOneUse()) + if (ISD::isFreezeUndef(SubVec.getNode())) ++NumFreezeUndef; else if (ISD::isBuildVectorAllZeros(SubVec.getNode())) ++NumZero; diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics.ll b/llvm/test/CodeGen/X86/avx512-intrinsics.ll index 591256d..5d545d8 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics.ll @@ -7495,10 +7495,7 @@ declare <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64>, <8 x i64>) nounwind re define <8 x double> @test_mm256_castpd128_pd256_freeze(<2 x double> %a0) nounwind { ; CHECK-LABEL: test_mm256_castpd128_pd256_freeze: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; CHECK-NEXT: ret{{[l|q]}} %a1 = freeze <2 x double> poison %res = shufflevector <2 x double> %a0, <2 x double> %a1, <8 x i32> @@ -7520,10 +7517,7 @@ define <8 x double> @test_mm256_castpd256_pd256_freeze(<4 x double> %a0) nounwin define <16 x float> @test_mm256_castps128_ps512_freeze(<4 x float> %a0) nounwind { ; CHECK-LABEL: test_mm256_castps128_ps512_freeze: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; CHECK-NEXT: ret{{[l|q]}} %a1 = freeze <4 x float> poison %res = shufflevector <4 x float> %a0, <4 x float> %a1, <16x i32> @@ -7545,10 +7539,7 @@ define <16 x float> @test_mm256_castps256_ps512_freeze(<8 x float> %a0) nounwind define <8 x i64> @test_mm512_castsi128_si512_freeze(<2 x i64> %a0) nounwind { ; CHECK-LABEL: test_mm512_castsi128_si512_freeze: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; CHECK-NEXT: ret{{[l|q]}} %a1 = freeze <2 x i64> poison %res = shufflevector <2 x i64> %a0, <2 x i64> %a1, <8 x i32> diff --git a/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll b/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll index 8ea5023..394270b 100644 --- a/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll @@ -1231,10 +1231,7 @@ define <16 x half> @test_mm256_castph128_ph256_freeze(<8 x half> %a0) nounwind { define <32 x half> @test_mm512_castph128_ph512_freeze(<8 x half> %a0) nounwind { ; CHECK-LABEL: test_mm512_castph128_ph512_freeze: ; CHECK: # %bb.0: -; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 -; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; CHECK-NEXT: retq %a1 = freeze <8 x half> poison %res = shufflevector <8 x half> %a0, <8 x half> %a1, <32 x i32>