From: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Date: Tue, 13 Jun 2023 10:39:30 +0000 (+0900)
Subject: drm/verisilicon: Add starfive_flush_dcache
X-Git-Tag: accepted/tizen/unified/riscv/20230725.071352~27
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1a185c6190438363ddf60644fcdf114ed705cdbe;p=platform%2Fkernel%2Flinux-starfive.git

drm/verisilicon: Add starfive_flush_dcache

There is a problem that the garbage cache value comes out when the
screen is displayed. Flush the cache by adding the flush feature.
The feature referred to v5.15 kernel.

Change-Id: I183eb0c1640c17b5ac27dcb1ce82555a5c651571
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---

diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c
index a512aaa..12c09da 100644
--- a/drivers/gpu/drm/verisilicon/vs_dc.c
+++ b/drivers/gpu/drm/verisilicon/vs_dc.c
@@ -22,6 +22,10 @@
 #include <drm/drm_vblank.h>
 #include <drm/vs_drm.h>
 
+#ifdef CONFIG_SIFIVE_FLUSH
+#include <soc/sifive/sifive_ccache.h>
+#endif
+
 #include "vs_crtc.h"
 #include "vs_dc_hw.h"
 #include "vs_dc.h"
@@ -517,6 +521,15 @@ static void update_fb(struct vs_plane *plane, u8 display_id,
 	update_format(drm_fb->format->format, drm_fb->modifier, fb);
 	update_swizzle(drm_fb->format->format, fb);
 	update_watermark(plane_state->watermark, fb);
+
+#ifdef CONFIG_SIFIVE_FLUSH
+	starfive_flush_dcache(fb->y_address, fb->height * fb->y_stride);
+	if (fb->u_address)
+		starfive_flush_dcache(fb->u_address, fb->height * fb->u_stride);
+	if (fb->v_address)
+		starfive_flush_dcache(fb->v_address, fb->height * fb->v_stride);
+#endif
+
 	plane_state->status.tile_mode = fb->tile_mode;
 }