From: Jan Beulich Date: Wed, 28 Sep 2005 15:34:53 +0000 (+0000) Subject: gas/testsuite/ X-Git-Tag: gdb-csl-arm-20051020-branchpoint~173 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=1a114b128470b4119aa3c32d8fd61ed581b4ede3;p=external%2Fbinutils.git gas/testsuite/ 2005-09-28 Jan Beulich * gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d, gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New. * gas/i386/i386.exp: Run new tests. ld/testsuite/ 2005-09-28 Jan Beulich * ld-x86-64/tlspic.dd: Adjust. opcodes/ 2005-09-28 Jan Beulich * i386-dis.c (stack_v_mode): Renamed from branch_v_mode. (indirEv): Use it. (stackEv): New. (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions. (dis386): Document and use new 'V' meta character. Use it for single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov. (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark data prefix as used whenever DFLAG was examined. Handle 'V'. (intel_operand_size): Use stack_v_mode. (OP_E): Use stack_v_mode, but handle only the special case of 64-bit mode without operand size override here; fall through to v_mode case otherwise. (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode and no operand size override is present. (OP_J): Use get32s for obtaining the displacement also when rex64 is present. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 5416d28..13be273 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2005-09-28 Jan Beulich + * gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d, + gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New. + * gas/i386/i386.exp: Run new tests. + +2005-09-28 Jan Beulich + * gas/i386/mixed-mode-reloc.s: Enable all insns. * gas/i386/mixed-mode-reloc32.d: Adjust. * gas/i386/mixed-mode-reloc64.d: Adjust. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 0e3f696..0c32a48 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -131,6 +131,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-opcode" run_dump_test "x86-64-pcrel" run_dump_test "x86-64-rip" + run_dump_test "x86-64-stack" + run_dump_test "x86-64-stack-intel" + run_dump_test "x86-64-stack-suffix" run_list_test "x86-64-inval" "-al" run_list_test "x86-64-segment" "-al" run_list_test "x86-64-inval-seg" "-al" diff --git a/gas/testsuite/gas/i386/x86-64-stack-intel.d b/gas/testsuite/gas/i386/x86-64-stack-intel.d new file mode 100644 index 0000000..0dfab4d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack-intel.d @@ -0,0 +1,40 @@ +#objdump: -dwMintel +#name: x86-64 stack-related opcodes (Intel mode) +#source: x86-64-stack.s + +.*: +file format elf64-x86-64 + +Disassembly of section .text: + +0+ <_start>: +[ ]*[0-9a-f]+:[ ]+50[ ]+push[ ]+rax +[ ]*[0-9a-f]+:[ ]+66 50[ ]+push[ ]+ax +[ ]*[0-9a-f]+:[ ]+66 48 50[ ]+push[ ]+rax +[ ]*[0-9a-f]+:[ ]+58[ ]+pop[ ]+rax +[ ]*[0-9a-f]+:[ ]+66 58[ ]+pop[ ]+ax +[ ]*[0-9a-f]+:[ ]+66 48 58[ ]+pop[ ]+rax +[ ]*[0-9a-f]+:[ ]+8f c0[ ]+pop[ ]+rax +[ ]*[0-9a-f]+:[ ]+66 8f c0[ ]+pop[ ]+ax +[ ]*[0-9a-f]+:[ ]+66 48 8f c0[ ]+pop[ ]+rax +[ ]*[0-9a-f]+:[ ]+8f 00[ ]+pop[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 8f 00[ ]+pop[ ]+WORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 48 8f 00[ ]+pop[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+ff d0[ ]+call[ ]+rax +[ ]*[0-9a-f]+:[ ]+66 ff d0[ ]+call[ ]+ax +[ ]*[0-9a-f]+:[ ]+66 48 ff d0[ ]+call[ ]+rax +[ ]*[0-9a-f]+:[ ]+ff 10[ ]+call[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 ff 10[ ]+call[ ]+WORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 48 ff 10[ ]+call[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+ff e0[ ]+jmp[ ]+rax +[ ]*[0-9a-f]+:[ ]+66 ff e0[ ]+jmp[ ]+ax +[ ]*[0-9a-f]+:[ ]+66 48 ff e0[ ]+jmp[ ]+rax +[ ]*[0-9a-f]+:[ ]+ff 20[ ]+jmp[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 ff 20[ ]+jmp[ ]+WORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 48 ff 20[ ]+jmp[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+ff f0[ ]+push[ ]+rax +[ ]*[0-9a-f]+:[ ]+66 ff f0[ ]+push[ ]+ax +[ ]*[0-9a-f]+:[ ]+66 48 ff f0[ ]+push[ ]+rax +[ ]*[0-9a-f]+:[ ]+ff 30[ ]+push[ ]+QWORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 ff 30[ ]+push[ ]+WORD PTR \[rax\] +[ ]*[0-9a-f]+:[ ]+66 48 ff 30[ ]+push[ ]+QWORD PTR \[rax\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-stack-suffix.d b/gas/testsuite/gas/i386/x86-64-stack-suffix.d new file mode 100644 index 0000000..c5d789d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack-suffix.d @@ -0,0 +1,40 @@ +#objdump: -dwMsuffix +#name: x86-64 stack-related opcodes (with suffixes) +#source: x86-64-stack.s + +.*: +file format elf64-x86-64 + +Disassembly of section .text: + +0+ <_start>: +[ ]*[0-9a-f]+:[ ]+50[ ]+pushq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 50[ ]+pushw[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 50[ ]+pushq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+58[ ]+popq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 58[ ]+popw[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 58[ ]+popq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+8f c0[ ]+popq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 8f c0[ ]+popw[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 8f c0[ ]+popq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+8f 00[ ]+popq[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 8f 00[ ]+popw[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 8f 00[ ]+popq[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+ff d0[ ]+callq[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+66 ff d0[ ]+callw[ ]+\*%ax +[ ]*[0-9a-f]+:[ ]+66 48 ff d0[ ]+callq[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+ff 10[ ]+callq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 ff 10[ ]+callw[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 ff 10[ ]+callq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+ff e0[ ]+jmpq[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+66 ff e0[ ]+jmpw[ ]+\*%ax +[ ]*[0-9a-f]+:[ ]+66 48 ff e0[ ]+jmpq[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+ff 20[ ]+jmpq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 ff 20[ ]+jmpw[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 ff 20[ ]+jmpq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+ff f0[ ]+pushq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 ff f0[ ]+pushw[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 ff f0[ ]+pushq[ ]+%rax +[ ]*[0-9a-f]+:[ ]+ff 30[ ]+pushq[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 ff 30[ ]+pushw[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 ff 30[ ]+pushq[ ]+\(%rax\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-stack.d b/gas/testsuite/gas/i386/x86-64-stack.d new file mode 100644 index 0000000..fa010a9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack.d @@ -0,0 +1,39 @@ +#objdump: -dw +#name: x86-64 stack-related opcodes + +.*: +file format elf64-x86-64 + +Disassembly of section .text: + +0+ <_start>: +[ ]*[0-9a-f]+:[ ]+50[ ]+pushq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 50[ ]+pushw?[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 50[ ]+pushq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+58[ ]+popq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 58[ ]+popw?[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 58[ ]+popq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+8f c0[ ]+popq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 8f c0[ ]+popw?[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 8f c0[ ]+popq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+8f 00[ ]+popq[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 8f 00[ ]+popw[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 8f 00[ ]+popq[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+ff d0[ ]+callq?[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+66 ff d0[ ]+callw?[ ]+\*%ax +[ ]*[0-9a-f]+:[ ]+66 48 ff d0[ ]+callq?[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+ff 10[ ]+callq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 ff 10[ ]+callw[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 ff 10[ ]+callq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+ff e0[ ]+jmpq?[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+66 ff e0[ ]+jmpw?[ ]+\*%ax +[ ]*[0-9a-f]+:[ ]+66 48 ff e0[ ]+jmpq?[ ]+\*%rax +[ ]*[0-9a-f]+:[ ]+ff 20[ ]+jmpq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 ff 20[ ]+jmpw[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 ff 20[ ]+jmpq[ ]+\*\(%rax\) +[ ]*[0-9a-f]+:[ ]+ff f0[ ]+pushq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+66 ff f0[ ]+pushw?[ ]+%ax +[ ]*[0-9a-f]+:[ ]+66 48 ff f0[ ]+pushq?[ ]+%rax +[ ]*[0-9a-f]+:[ ]+ff 30[ ]+pushq[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 ff 30[ ]+pushw[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+66 48 ff 30[ ]+pushq[ ]+\(%rax\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-stack.s b/gas/testsuite/gas/i386/x86-64-stack.s new file mode 100644 index 0000000..e0fc046 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack.s @@ -0,0 +1,23 @@ + .macro try bytes:vararg + .byte \bytes + .byte 0x66, \bytes + .byte 0x66, 0x48, \bytes + .endm + + .text + +_start: + try 0x50 + try 0x58 + + try 0x8f, 0xc0 + try 0x8f, 0x00 + + try 0xff, 0xd0 + try 0xff, 0x10 + + try 0xff, 0xe0 + try 0xff, 0x20 + + try 0xff, 0xf0 + try 0xff, 0x30 diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 5ef47de..2b4e144 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2005-09-28 Jan Beulich + + * ld-x86-64/tlspic.dd: Adjust. + 2005-09-01 Hans-Peter Nilsson * ld-cris: Skip tests unsuitable for testing target diff --git a/ld/testsuite/ld-x86-64/tlspic.dd b/ld/testsuite/ld-x86-64/tlspic.dd index 66ea9d6..28d8418 100644 --- a/ld/testsuite/ld-x86-64/tlspic.dd +++ b/ld/testsuite/ld-x86-64/tlspic.dd @@ -20,10 +20,9 @@ Disassembly of section .text: +1008: 66 48 8d 3d 80 03 10[ ]+lea 1049472\(%rip\),%rdi +# 101390 <.*> +100f: 00 * # -> R_X86_64_DTPMOD64 sg1 - +1010: 66[ ]+data16 - +1011: 66[ ]+data16 - +1012: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*> + +1010: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr + +1017: [0-9a-f ]+ +1018: 90[ ]+nop * +1019: 90[ ]+nop * +101a: 90[ ]+nop * @@ -41,10 +40,9 @@ Disassembly of section .text: +1030: 66 48 8d 3d 08 03 10[ ]+lea 1049352\(%rip\),%rdi +# 101340 <.*> +1037: 00 * # -> R_X86_64_DTPMOD64 [0 0x2000000000000000] - +1038: 66[ ]+data16 - +1039: 66[ ]+data16 - +103a: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*> + +1038: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr + +103f: [0-9a-f ]+ +1040: 90[ ]+nop * +1041: 90[ ]+nop * +1042: 90[ ]+nop * @@ -62,10 +60,9 @@ Disassembly of section .text: +1058: 66 48 8d 3d 58 03 10[ ]+lea 1049432\(%rip\),%rdi +# 1013b8 <.*> +105f: 00 * # -> R_X86_64_DTPMOD64 [0 0x4000000000000000] - +1060: 66[ ]+data16 - +1061: 66[ ]+data16 - +1062: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*> + +1060: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr + +1067: [0-9a-f ]+ +1068: 90[ ]+nop * +1069: 90[ ]+nop * +106a: 90[ ]+nop * @@ -83,10 +80,9 @@ Disassembly of section .text: +1080: 66 48 8d 3d e8 02 10[ ]+lea 1049320\(%rip\),%rdi +# 101370 <.*> +1087: 00 * # -> R_X86_64_DTPMOD64 [0 0x6000000000000000] - +1088: 66[ ]+data16 - +1089: 66[ ]+data16 - +108a: 48 e8 [0-9a-f ]+rex64 callq [0-9a-f]+ <.*> + +1088: 66 66 48 e8 [0-9a-f ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr + +108f: [0-9a-f ]+ +1090: 90[ ]+nop * +1091: 90[ ]+nop * +1092: 90[ ]+nop * diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9ce7380..39a479e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,23 @@ +2005-09-28 Jan Beulich + + * i386-dis.c (stack_v_mode): Renamed from branch_v_mode. + (indirEv): Use it. + (stackEv): New. + (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions. + (dis386): Document and use new 'V' meta character. Use it for + single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop + opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov. + (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark + data prefix as used whenever DFLAG was examined. Handle 'V'. + (intel_operand_size): Use stack_v_mode. + (OP_E): Use stack_v_mode, but handle only the special case of + 64-bit mode without operand size override here; fall through to + v_mode case otherwise. + (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode + and no operand size override is present. + (OP_J): Use get32s for obtaining the displacement also when rex64 + is present. + 2005-09-08 Paul Brook * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index e7fff65..a3b205a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -200,8 +200,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Eq OP_E, q_mode #define Edq OP_E, dq_mode #define Edqw OP_E, dqw_mode -#define indirEv OP_indirE, branch_v_mode +#define indirEv OP_indirE, stack_v_mode #define indirEp OP_indirE, f_mode +#define stackEv OP_E, stack_v_mode #define Em OP_E, m_mode #define Ew OP_E, w_mode #define Ma OP_E, v_mode @@ -280,10 +281,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Sw OP_SEG, w_mode #define Ap OP_DIR, 0 -#define Ob OP_OFF, b_mode -#define Ob64 OP_OFF64, b_mode -#define Ov OP_OFF, v_mode -#define Ov64 OP_OFF64, v_mode +#define Ob OP_OFF64, b_mode +#define Ov OP_OFF64, v_mode #define Xb OP_DSreg, eSI_reg #define Xv OP_DSreg, eSI_reg #define Yb OP_ESreg, eDI_reg @@ -329,7 +328,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */ #define f_mode 13 /* 4- or 6-byte pointer operand */ #define const_1_mode 14 -#define branch_v_mode 15 /* v_mode for branch. */ +#define stack_v_mode 15 /* v_mode for stack-related opcodes. */ #define es_reg 100 #define cs_reg 101 @@ -479,6 +478,7 @@ struct dis386 { 'S' => print 'w', 'l' or 'q' if suffix_always is true 'T' => print 'q' in 64bit mode and behave as 'P' otherwise 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise + 'V' => print 'q' in 64bit mode and behave as 'S' otherwise 'W' => print 'b' or 'w' ("w" or "de" in intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) 'Y' => 'q' if instruction has an REX 64bit overwrite prefix @@ -519,7 +519,7 @@ static const struct dis386 dis386[] = { { "adcB", AL, Ib, XX }, { "adcS", eAX, Iv, XX }, { "push{T|}", ss, XX, XX }, - { "popT|}", ss, XX, XX }, + { "pop{T|}", ss, XX, XX }, /* 18 */ { "sbbB", Eb, Gb, XX }, { "sbbS", Ev, Gv, XX }, @@ -584,23 +584,23 @@ static const struct dis386 dis386[] = { { "dec{S|}", RMeSI, XX, XX }, { "dec{S|}", RMeDI, XX, XX }, /* 50 */ - { "pushS", RMrAX, XX, XX }, - { "pushS", RMrCX, XX, XX }, - { "pushS", RMrDX, XX, XX }, - { "pushS", RMrBX, XX, XX }, - { "pushS", RMrSP, XX, XX }, - { "pushS", RMrBP, XX, XX }, - { "pushS", RMrSI, XX, XX }, - { "pushS", RMrDI, XX, XX }, + { "pushV", RMrAX, XX, XX }, + { "pushV", RMrCX, XX, XX }, + { "pushV", RMrDX, XX, XX }, + { "pushV", RMrBX, XX, XX }, + { "pushV", RMrSP, XX, XX }, + { "pushV", RMrBP, XX, XX }, + { "pushV", RMrSI, XX, XX }, + { "pushV", RMrDI, XX, XX }, /* 58 */ - { "popS", RMrAX, XX, XX }, - { "popS", RMrCX, XX, XX }, - { "popS", RMrDX, XX, XX }, - { "popS", RMrBX, XX, XX }, - { "popS", RMrSP, XX, XX }, - { "popS", RMrBP, XX, XX }, - { "popS", RMrSI, XX, XX }, - { "popS", RMrDI, XX, XX }, + { "popV", RMrAX, XX, XX }, + { "popV", RMrCX, XX, XX }, + { "popV", RMrDX, XX, XX }, + { "popV", RMrBX, XX, XX }, + { "popV", RMrSP, XX, XX }, + { "popV", RMrBP, XX, XX }, + { "popV", RMrSI, XX, XX }, + { "popV", RMrDI, XX, XX }, /* 60 */ { "pusha{P|}", XX, XX, XX }, { "popa{P|}", XX, XX, XX }, @@ -654,7 +654,7 @@ static const struct dis386 dis386[] = { { "movQ", Sv, Sw, XX }, { "leaS", Gv, M, XX }, { "movQ", Sw, Sv, XX }, - { "popU", Ev, XX, XX }, + { "popU", stackEv, XX, XX }, /* 90 */ { "nop", NOP_Fixup, 0, XX, XX }, { "xchgS", RMeCX, eAX, XX }, @@ -674,10 +674,10 @@ static const struct dis386 dis386[] = { { "sahf{|}", XX, XX, XX }, { "lahf{|}", XX, XX, XX }, /* a0 */ - { "movB", AL, Ob64, XX }, - { "movS", eAX, Ov64, XX }, - { "movB", Ob64, AL, XX }, - { "movS", Ov64, eAX, XX }, + { "movB", AL, Ob, XX }, + { "movS", eAX, Ov, XX }, + { "movB", Ob, AL, XX }, + { "movS", Ov, eAX, XX }, { "movs{b||b|}", Yb, Xb, XX }, { "movs{R||R|}", Yv, Xv, XX }, { "cmps{b||b|}", Xb, Yb, XX }, @@ -1361,7 +1361,7 @@ static const struct dis386 grps[][8] = { { "JcallT", indirEp, XX, XX }, { "jmpT", indirEv, XX, XX }, { "JjmpT", indirEp, XX, XX }, - { "pushU", Ev, XX, XX }, + { "pushU", stackEv, XX, XX }, { "(bad)", XX, XX, XX }, }, /* GRP6 */ @@ -2860,7 +2860,7 @@ putop (const char *template, int sizeflag) case 'T': if (intel_syntax) break; - if (mode_64bit) + if (mode_64bit && (sizeflag & DFLAG)) { *obufp++ = 'q'; break; @@ -2882,16 +2882,17 @@ putop (const char *template, int sizeflag) *obufp++ = 'l'; else *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); } + used_prefixes |= (prefixes & PREFIX_DATA); } break; case 'U': if (intel_syntax) break; - if (mode_64bit) + if (mode_64bit && (sizeflag & DFLAG)) { - *obufp++ = 'q'; + if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + *obufp++ = 'q'; break; } /* Fall through. */ @@ -2909,8 +2910,8 @@ putop (const char *template, int sizeflag) *obufp++ = intel_syntax ? 'd' : 'l'; else *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); } + used_prefixes |= (prefixes & PREFIX_DATA); } break; case 'R': @@ -2945,6 +2946,16 @@ putop (const char *template, int sizeflag) if (!(rex & REX_MODE64)) used_prefixes |= (prefixes & PREFIX_DATA); break; + case 'V': + if (intel_syntax) + break; + if (mode_64bit && (sizeflag & DFLAG)) + { + if (sizeflag & SUFFIX_ALWAYS) + *obufp++ = 'q'; + break; + } + /* Fall through. */ case 'S': if (intel_syntax) break; @@ -3134,7 +3145,7 @@ intel_operand_size (int bytemode, int sizeflag) case dqw_mode: oappend ("WORD PTR "); break; - case branch_v_mode: + case stack_v_mode: if (mode_64bit && (sizeflag & DFLAG)) { oappend ("QWORD PTR "); @@ -3223,18 +3234,15 @@ OP_E (int bytemode, int sizeflag) else oappend (names32[rm + add]); break; - case branch_v_mode: - if (mode_64bit) - oappend (names64[rm + add]); - else + case stack_v_mode: + if (mode_64bit && (sizeflag & DFLAG)) { - if ((sizeflag & DFLAG) || bytemode != branch_v_mode) - oappend (names32[rm + add]); - else - oappend (names16[rm + add]); + oappend (names64[rm + add]); used_prefixes |= (prefixes & PREFIX_DATA); + break; } - break; + bytemode = v_mode; + /* FALLTHRU */ case v_mode: case dq_mode: case dqw_mode: @@ -3630,7 +3638,7 @@ OP_REG (int code, int sizeflag) break; case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: - if (mode_64bit) + if (mode_64bit && (sizeflag & DFLAG)) { s = names64[code - rAX_reg + add]; break; @@ -3873,7 +3881,7 @@ OP_J (int bytemode, int sizeflag) disp -= 0x100; break; case v_mode: - if (sizeflag & DFLAG) + if ((sizeflag & DFLAG) || (rex & REX_MODE64)) disp = get32s (); else {