From: Guennadi Liakhovetski Date: Wed, 15 May 2013 05:50:51 +0000 (+0200) Subject: mmc: sh_mmcif: don't clear masked interrupts X-Git-Tag: v3.11-rc1~50^2~63 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=19f1ba51c79f133aec3ce558b8292e3b081363f3;p=profile%2Fivi%2Fkernel-x86-ivi.git mmc: sh_mmcif: don't clear masked interrupts Masking events on MMCIF means that an occurrence of the masked event won't raise an interrupt, but the event bit will still be set in the interrupt status register. If simultaneously a different event occurs which was enabled, both flags will be set. However, only the unmasked event bit should be cleared in the status register in such a case. Clearing also the masked bit can lead to lost interrupts, which indeed can be observed on the armadillo800eva r8a7740 board with an eMMC chip. The problem has been introduced by the recent "mmc: sh_mmcif: simplify IRQ processing" patch. Fix the problem by only clearing enabled interrupts. Signed-off-by: Guennadi Liakhovetski Tested-by: Nguyen Viet Dung Tested-by: Kuninori Morimoto Signed-off-by: Chris Ball --- diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 117a1f7..8ef5efa 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -1244,7 +1244,8 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) u32 state; state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); - sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); + sh_mmcif_writel(host->addr, MMCIF_CE_INT, + ~(state & sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK))); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); if (state & ~MASK_CLEAN)