From: thead_admin Date: Sun, 24 Dec 2023 02:32:32 +0000 (+0000) Subject: Linux_SDK_V1.4.2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=19cd3db1936d2c13159e4d2162b3eb66b1121c1c;p=platform%2Fkernel%2Flinux-thead.git Linux_SDK_V1.4.2 Signed-off-by: thead_admin (cherry picked from commit d4c68ef2c128089b56980b0a8b00771206144d77) Signed-off-by: Jaehoon Chung --- diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 168603c2c9da..bee73c7b824c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,7 +44,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK - select CPU_PM if CPU_IDLE + select CPU_PM if CPU_IDLE || HIBERNATION select COMPAT_BINFMT_ELF if BINFMT_ELF && COMPAT select EDAC_SUPPORT select DMA_DIRECT_REMAP @@ -549,6 +549,12 @@ source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE def_bool y +config ARCH_HIBERNATION_POSSIBLE + def_bool y + +config ARCH_HIBERNATION_HEADER + def_bool HIBERNATION + endmenu menu "CPU Power Management" diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile index 75a6eb36da0d..6b1efc03cbd5 100644 --- a/arch/riscv/boot/dts/thead/Makefile +++ b/arch/riscv/boot/dts/thead/Makefile @@ -4,48 +4,57 @@ ifeq ($(CONFIG_OF_OVERLAY),y) DTC_FLAGS += -@ endif -dtb-$(CONFIG_SOC_THEAD) += ice.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu.dtb light_mpw.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-npu-fce.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-gpu.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsp.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-audio.dtb light-a-val-audio-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-fm-emu-dsi0-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val.dtb light-a-val-sv.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-ddr2G.dtb light-a-val-ddr1G.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-npu-fce.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-iso7816.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-nand.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio.dtb light-a-val-audio-i2s-8ch.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-tdm.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-audio-spdif.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-dsi0.dtb light-a-val-dsi1.dtb light-a-val-hdmi.dtb light-a-val-dsi0-dsi1.dtb light-a-val-dsi0-hdmi.dtb light-a-val-dsi0-hdmi-audio.dtb light-a-val-dpi0.dtb light-a-val-dpi0-dpi1.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-wcn.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-gpio-keys.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-khv.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-sec.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-miniapp-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-product.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-product.dtb light-b-product-sec.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-product-ddr1G.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-product-miniapp-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-full.dtb -dtb-$(CONFIG_SOC_THEAD) += light-ant-ref.dtb -dtb-$(CONFIG_SOC_THEAD) += light-ant-discrete.dtb -dtb-$(CONFIG_SOC_THEAD) += light-beagle.dtb -dtb-$(CONFIG_SOC_THEAD) += light-lpi4a.dtb light-lpi4a-ddr2G.dtb light-lpi4a-16gb.dtb light-lpi4a-dsi0-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-cluster.dtb light-lpi4a-cluster-16gb.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-ref.dtb light-a-ref-dsi0.dtb light-a-ref-dsi0-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-ref.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light-ant-ref-crash.dtb light-ant-discrete-crash.dtb light-lpi4a-crash.dtb light-lpi4a-camera-tuning.dtb light-lpi4a-hdmi.dtb -dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb +dtb-$(CONFIG_SOC_THEAD_ICE) += ice.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_MPW) += th1520_mpw.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-npu-fce.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-gpu.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsp.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-audio.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_EMU) += th1520-fm-emu-dsi0-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val.dtb th1520-a-val-sec.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-crash.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-i2s-8ch.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-tdm.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-audio-spdif.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-a-val-dsi0-dsi1.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-sv.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-ddr2G.dtb th1520-a-val-ddr1G.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-npu-fce.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-iso7816.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-nand.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-dsi0.dtb th1520-a-val-dsi1.dtb th1520-a-val-hdmi.dtb th1520-a-val-dsi0-hdmi-audio.dtb th1520-a-val-dpi0.dtb th1520-a-val-dpi0-dpi1.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-wcn.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-gpio-keys.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-khv.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-miniapp-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_PRD) += th1520-a-product.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-val-full.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-a-ref.dtb th1520-a-ref-dsi0.dtb th1520-a-ref-dsi0-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-b-product.dtb th1520-b-product-sec.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-b-product-crash.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-ddr1G.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-product-miniapp-hdmi.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-ref.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-b-power.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_ANT) += th1520-ant-ref-crash.dtb th1520-ant-discrete-crash.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-ant-discrete.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-beagle.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product.dtb th1520-lpi4a-product-sec.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-product-crash.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-camera-tuning.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-hx8279.dtb +dtb-$(CONFIG_SOC_THEAD) += th1520-lpi4a-dsi0.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_DEV) += th1520-lpi4a-ddr2G.dtb +dtb-$(CONFIG_SOC_THEAD_TH1520_ANDROID) += th1520-a-val-android.dtb +dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu.dtb fire-emu-crash.dtb +dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb +dtb-$(CONFIG_SOC_THEAD_FIRE) += fire-emu-soc-base-sec.dtb -dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb - -dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb -dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base.dtb fire-emu-soc-c910x4.dtb fire-emu-gpu-dpu-dsi0.dtb fire-emu-vi-dsp-vo.dtb fire-emu-vi-vp-vo.dtb -dtb-$(CONFIG_SOC_THEAD) += fire-emu-soc-base-sec.dtb dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-laptop.dtb dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-console.dtb light-lpi4a-console-16g.dtb dtb-$(CONFIG_SOC_THEAD) += light-lpi4a-z14inch-m0.dtb light-lpi4a-z14inch-m0-16g.dtb diff --git a/arch/riscv/boot/dts/thead/fire-crash.dts b/arch/riscv/boot/dts/thead/fire-crash.dts deleted file mode 100644 index 17e501a10cf8..000000000000 --- a/arch/riscv/boot/dts/thead/fire-crash.dts +++ /dev/null @@ -1,847 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "fire.dtsi" -#include -#include -#include "light-vi-devices.dtsi" - -/ { - model = "T-HEAD fire fpga board"; - compatible = "thead,fire-emu", "thead,fire"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - status = "disabled"; - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - status = "disabled"; - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <1>; - compatible = "linux,bt-sco"; - status = "okay"; - }; - - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 26 0>; - WIFI,reset_n = <&gpio2_porta 28 0>; - status = "disabled"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "disabled"; - }; - - gpio_keys: gpio_keys{ - compatible = "gpio-keys"; - pinctrl-names = "default"; - status = "disabled"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <2>; - gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>; - }; - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <2>; - gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>; - }; - }; - - aon: light-aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic"; - status = "disabled"; - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "disabled"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - status = "disabled"; - }; - }; -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@0f800000 { - reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ - 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ - no-map; - }; - facelib_mem: memory@22000000 { - reg = <0x0 0x22000000 0x0 0x10000000>; - no-map; - }; - -}; - -&clk { - status = "disabled"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - status = "disabled"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "disabled"; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "disabled"; - touch1@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <12 0>; - irq-gpios = <&gpio1_porta 12 0>; - reset-gpios = <&gpio1_porta 11 0>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "okay"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - status = "disabled"; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <66000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi2"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - FM_GPIO3_3 0x1 0x208 /* pwm1 */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - pcal6408ahk_a: gpio@20 { - compatible = "nxp,pcal9554b"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&isp0 { - status = "disabled"; -}; - -&isp1 { - status = "disabled"; -}; - -&isp_ry0 { - status = "disabled"; -}; - -&dewarp { - status = "disabled"; -}; - -&dec400_isp0 { - status = "disabled"; -}; - -&dec400_isp1 { - status = "disabled"; -}; - -&dec400_isp2 { - status = "disabled"; -}; - -&bm_visys { - status = "disabled"; -}; - -&bm_csi0 { - status = "disabled"; -}; - -&bm_csi1 { - status = "disabled"; -}; - -&bm_csi2 { - status = "disabled"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "disabled"; -}; - -&xtensa_dsp { - status = "disabled"; -}; - -&xtensa_dsp0 { - status = "disabled"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1{ - status = "disabled"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - floodlight_en_pin = <&gpio1_porta 25 0>; - //projection_i2c_bus = /bits/ 8 <2>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - status = "disabled"; -}; - -&vvcam_sensor1 { - status = "disabled"; -}; - -&vvcam_sensor2 { - status = "disabled"; -}; - -&vvcam_sensor3 { - status = "disabled"; -}; - -&vvcam_sensor4 { - status = "disabled"; -}; - -&vvcam_sensor5 { - status = "disabled"; -}; - -&video0{ - status = "disabled"; -}; - - -&video1{ - status = "disabled"; -}; - -&video2{ - status = "disabled"; -}; - -&video3{ - status = "disabled"; -}; - -&video4{ - status = "disabled"; -}; - -&video5{ - status = "disabled"; -}; - -&video6{ - status = "disabled"; -}; - -&video7{ - status = "disabled"; -}; - - -&video8{ - status = "disabled"; -}; - -&video9{ - status = "disabled"; -}; - - -&video10{ - status = "disabled"; -}; - -&video11{ - status = "disabled"; -}; - -&video12{ - status = "disabled"; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "disabled"; -}; - -&vdec { - status = "disabled"; -}; - -&venc { - status = "disabled"; -}; - -&isp_venc_shake { - status = "disabled"; -}; - -&vidmem { - status = "disabled"; -}; - -&gpu { - status = "disabled"; -}; - -&dpu_enc0 { - status = "disabled"; -}; - -&dpu_enc1 { - status = "disabled"; -}; - -&dpu { - status = "disabled"; -}; - -&dsi0 { - status = "disabled"; -}; - -&dhost_0 { - status = "disabled"; -}; - -&disp1_out { - status = "disabled"; -}; - -&hdmi_tx { - status = "disabled"; -}; - -&lightsound { - status = "disabled"; -}; - -&light_i2s { - status = "disabled"; -}; - -&i2s0 { - status = "disabled"; -}; - -&i2s1 { - status = "disabled"; -}; - -&i2s3 { - status = "disabled"; -}; - -&khvhost { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/fire-emu-crash.dts b/arch/riscv/boot/dts/thead/fire-emu-crash.dts deleted file mode 100644 index 260d8a6b1978..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-crash.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "fire-crash.dts" - -&aon { - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic"; - status = "disabled"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/fire-emu-gpu-dpu-dsi0.dts b/arch/riscv/boot/dts/thead/fire-emu-gpu-dpu-dsi0.dts deleted file mode 100644 index 938e46fe097f..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-gpu-dpu-dsi0.dts +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "fire-emu.dts" - -&gpu { - status = "okay"; -}; - -&vosys_reg { - status = "okay"; -}; - -&display_subsystem { - status = "okay"; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; - - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "hlt,hpk070h275"; - reg = <0>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&aon { - status = "okay"; -}; - -&mbox_910t { - status = "okay"; -}; - -&mbox_910t_client1 { - status = "okay"; -}; - -&mbox_910t_client2 { - status = "okay"; -}; - -&dmac1 { - status = "okay"; -}; - -&lightsound { - status = "okay"; -}; - -&dmac2 { - status = "disabled"; -}; - diff --git a/arch/riscv/boot/dts/thead/fire-emu-soc-base-sec.dts b/arch/riscv/boot/dts/thead/fire-emu-soc-base-sec.dts deleted file mode 100644 index 21e96ca2aa8f..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-soc-base-sec.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -/* #include "fire-emu.dts" */ -#include "fire-emu-soc-base.dts" - -&light_iopmp { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/fire-emu-soc-base.dts b/arch/riscv/boot/dts/thead/fire-emu-soc-base.dts deleted file mode 100644 index df6eeebeec85..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-soc-base.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "fire-emu.dts" - -&sdhci0 { - status = "okay"; -}; - -&usb3_drd { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "okay"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - status = "okay"; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <66000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi2"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - diff --git a/arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts b/arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts deleted file mode 100644 index e7d225925f35..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-soc-c910x4.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -#include "fire-emu.dts" - -&c910_1 { - status = "okay"; -}; - -&c910_2 { - status = "okay"; -}; - -&c910_3 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/thead/fire-emu-vi-dsp-vo.dts b/arch/riscv/boot/dts/thead/fire-emu-vi-dsp-vo.dts deleted file mode 100644 index c5cee401c6d4..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-vi-dsp-vo.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "fire-emu.dts" - -&c910_1 { - status = "okay"; -}; - -&vi_pre { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; -}; - -&xtensa_dsp1 { - status = "okay"; -}; - -&vosys_reg { - status = "okay"; -}; - -&display_subsystem { - status = "okay"; -}; - -&dpu { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dpu_enc0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/thead/fire-emu-vi-vp-vo.dts b/arch/riscv/boot/dts/thead/fire-emu-vi-vp-vo.dts deleted file mode 100644 index b6e753740f97..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu-vi-vp-vo.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "fire-emu.dts" - -&c910_1 { - status = "okay"; -}; - -&vi_pre { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&g2d { - status = "okay"; -}; - -&vosys_reg { - status = "okay"; -}; - -&display_subsystem { - status = "okay"; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "hlt,hpk070h275"; - reg = <0>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&dpu { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - diff --git a/arch/riscv/boot/dts/thead/fire-emu.dts b/arch/riscv/boot/dts/thead/fire-emu.dts deleted file mode 100644 index f6dc93d752d0..000000000000 --- a/arch/riscv/boot/dts/thead/fire-emu.dts +++ /dev/null @@ -1,876 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "fire.dtsi" -#include -#include -#include "light-vi-devices.dtsi" - -/ { - model = "T-HEAD fire fpga board"; - compatible = "thead,fire-emu", "thead,fire"; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - lcd1_backlight: pwm-backlight@1 { - compatible = "pwm-backlight"; - pwms = <&pwm 1 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <1>; - compatible = "linux,bt-sco"; - status = "okay"; - }; - - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 26 0>; - WIFI,reset_n = <&gpio2_porta 28 0>; - status = "disabled"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "disabled"; - }; - - gpio_keys: gpio_keys{ - compatible = "gpio-keys"; - pinctrl-names = "default"; - status = "disabled"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <2>; - gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>; - }; - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <2>; - gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>; - }; - }; - - aon: light-aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic"; - status = "disabled"; - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "disabled"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - status = "disabled"; - }; - }; -}; - -&cmamem { - alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000] -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@0f800000 { - reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ - 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ - no-map; - }; - facelib_mem: memory@22000000 { - reg = <0x0 0x22000000 0x0 0x10000000>; - no-map; - }; - -}; - -&clk { - status = "disabled"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - status = "disabled"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "disabled"; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - status = "disabled"; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - status = "disabled"; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "disabled"; - touch1@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <12 0>; - irq-gpios = <&gpio1_porta 12 0>; - reset-gpios = <&gpio1_porta 11 0>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "okay"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - status = "disabled"; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&qspi0 { - status = "disabled"; -}; - -&qspi1 { - status = "disabled"; -}; -&gmac0 { - max-speed = <100>; - phy-mode = "mii"; - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x0>; - }; - - }; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - /*mmc-hs400-1_8v;*/ - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "disabled"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - FM_GPIO3_3 0x1 0x208 /* pwm1 */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - pcal6408ahk_a: gpio@20 { - compatible = "nxp,pcal9554b"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&isp0 { - status = "disabled"; -}; - -&isp1 { - status = "disabled"; -}; - -&isp_ry0 { - status = "disabled"; -}; - -&dewarp { - status = "disabled"; -}; - -&dec400_isp0 { - status = "disabled"; -}; - -&dec400_isp1 { - status = "disabled"; -}; - -&dec400_isp2 { - status = "disabled"; -}; - -&bm_visys { - status = "disabled"; -}; - -&bm_csi0 { - status = "disabled"; -}; - -&bm_csi1 { - status = "disabled"; -}; - -&bm_csi2 { - status = "disabled"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "disabled"; -}; - -&xtensa_dsp { - status = "disabled"; -}; - -&xtensa_dsp0 { - status = "disabled"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1{ - status = "disabled"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - floodlight_en_pin = <&gpio1_porta 25 0>; - //projection_i2c_bus = /bits/ 8 <2>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - status = "disabled"; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "disabled"; -}; - -&venc { - status = "disabled"; -}; - -&isp_venc_shake { - status = "disabled"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "disabled"; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - status = "disabled"; - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - status = "disabled"; - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - status = "disabled"; - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; - -&thermal_zones { - cpu-thermal-zone { - status = "disabled"; - }; -}; - -&dummy_clock_apb { - clock-frequency = <50000000>; -}; - -&uart0 { - clocks = <&dummy_clock_apb>; -}; -&uart1 { - clocks = <&dummy_clock_apb>; -}; -&uart2 { - clocks = <&dummy_clock_apb>; -}; -&uart3 { - clocks = <&dummy_clock_apb>; -}; -&uart4 { - clocks = <&dummy_clock_apb>; -}; -&uart5 { - clocks = <&dummy_clock_apb>; -}; - -&usb3_drd { - status = "disabled"; -}; - -&usb { - status = "disabled"; -}; - -&dspsys_reg { - status = "disabled"; -}; - -&audio_ioctrl { - status = "disabled"; -}; - -&audio_cpr { - status = "disabled"; -}; - -&timer0 { - clock-frequency = <50000000>; -}; - -&timer1 { - clock-frequency = <50000000>; -}; - -&timer2 { - clock-frequency = <50000000>; -}; - -&timer3 { - clock-frequency = <50000000>; -}; - -&g2d { - status = "disabled"; -}; - -&vosys_reg { - status = "disabled"; -}; - -&dmac2 { - status = "disabled"; -}; - -&sdhci1 { - status = "disabled"; -}; - -&pvt { - status = "disabled"; -}; - -&audio_i2c0 { - status = "disabled"; -}; - -&csia_reg { - status = "disabled"; -}; - -&visys_clk_gate { /* VI_SYSREG_R */ - status = "disabled"; -}; - -&vpsys_clk_gate { /* VP_SYSREG_R */ - status = "disabled"; -}; - -&vosys_clk_gate { /* VO_SYSREG_R */ - status = "disabled"; -}; - -&dspsys_clk_gate { - status = "disabled"; -}; - -&watchdog0 { - status = "disabled"; -}; - -&watchdog1 { - status = "disabled"; -}; - diff --git a/arch/riscv/boot/dts/thead/fire.dtsi b/arch/riscv/boot/dts/thead/fire.dtsi deleted file mode 100644 index c2ad7bd4051a..000000000000 --- a/arch/riscv/boot/dts/thead/fire.dtsi +++ /dev/null @@ -1,2091 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "thead,fire"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac0; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - audio_i2c0 = &audio_i2c0; - mmc0 = &emmc; - mmc1 = &sdhci0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &qspi0; - spi2 = &qspi1; - - flash_led0 = &vvcam_flash_led0; - vivcam0 = &vvcam_sensor0; - vivcam1 = &vvcam_sensor1; - vivcam2 = &vvcam_sensor2; - vivcam3 = &vvcam_sensor3; - vivcam4 = &vvcam_sensor4; - vivcam5 = &vvcam_sensor5; - vivcam6 = &vvcam_sensor6; - - viv_video0 = &video0; - viv_video1 = &video1; - viv_video2 = &video2; - viv_video3 = &video3; - viv_video4 = &video4; - viv_video5 = &video5; - viv_video6 = &video6; - viv_video7 = &video7; - viv_video8 = &video8; - viv_video9 = &video9; - viv_video10 = &video10; - viv_video11 = &video11; - viv_video12 = &video12; - viv_video13 = &video13; - viv_video14 = &video14; - viv_video15 = &video15; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0xffe00000>; - }; - - resmem: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - cmamem: linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x14000000>; // 320MB by default - alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] - linux,cma-default; - }; - }; - - thermal_zones: thermal-zones { - cpu-thermal-zone { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&pvt 0>; - trips { - cpu_config0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_config1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - cpu_cdev { - trip = <&cpu_config0>; - cooling-device = - <&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <3000000>; - c910_0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_1: cpu@1 { - device_type = "cpu"; - reg = <1>; - status = "disabled"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_2: cpu@2 { - device_type = "cpu"; - reg = <2>; - status = "disabled"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_3: cpu@3 { - device_type = "cpu"; - reg = <3>; - status = "disabled"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - - display_subsystem: display-subsystem { - compatible = "verisilicon,display-subsystem"; - ports = <&dpu_disp0>, <&dpu_disp1>; - status = "disabled"; - }; - - dpu-encoders { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dpu_enc0: dpu-encoder@0 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc0_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; - - dpu_enc1: dpu-encoder@1 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc1_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; - entry-reg = <0xff 0xff019050>; - entry-cnt = <4>; - control-reg = <0xff 0xff015004>; - control-val = <0x1c>; - csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>; - }; - - clint0: clint@ffdc000000 { - compatible = "riscv,clint0"; - interrupts-extended = < - &cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - >; - reg = <0xff 0xdc000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; - }; - - intc: interrupt-controller@ffd8000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff &cpu0_intc 9 - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - >; - reg = <0xff 0xd8000000 0x0 0x04000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <240>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_clock_apb: apb-clock@0 { - compatible = "fixed-clock"; - reg = <0>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_apb"; - #clock-cells = <0>; - }; - - dummy_clock_ref: ref-clock@1 { - compatible = "fixed-clock"; - reg = <1>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ref"; - #clock-cells = <0>; - }; - - dummy_clock_suspend: suspend-clock@2 { - compatible = "fixed-clock"; - reg = <2>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_suspend"; - #clock-cells = <0>; - }; - - dummy_clock_rtc: rtc-clock@3 { - compatible = "fixed-clock"; - reg = <3>; /* Not address, just for index */ - clock-frequency = <32768>; - clock-output-names = "dummy_clock_rtc"; - #clock-cells = <0>; - }; - - dummy_clock_ahb: ahb-clock@4 { - compatible = "fixed-clock"; - reg = <4>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_gpu: gpu-clock@6 { - compatible = "fixed-clock"; - reg = <6>; /* Not address, just for index */ - clock-frequency = <18000000>; - clock-output-names = "dummy_clock_gpu"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_ref: dphy-ref-clock@7 { - compatible = "fixed-clock"; - reg = <7>; /* Not address, just for index */ - clock-frequency = <40000000>; - clock-output-names = "dummy_clock_dphy_ref"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_cfg: dphy-cfg-clock@8 { - compatible = "fixed-clock"; - reg = <8>; /* Not address, just for index */ - clock-frequency = <40000000>; - clock-output-names = "dummy_clock_dphy_cfg"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel0: dpu-pixel-clock@9 { - compatible = "fixed-clock"; - reg = <9>; - clock-frequency = <25200000>; - clock-output-names = "dummy_clock_dpu_pixel0"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel1: dpu-pixel-clock@10 { - compatible = "fixed-clock"; - reg = <10>; - clock-frequency = <25200000>; - clock-output-names = "dummy_clock_dpu_pixel1"; - #clock-cells = <0>; - }; - - osc_32k: clock-osc-32k@11 { - compatible = "fixed-clock"; - reg = <11>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m@12 { - compatible = "fixed-clock"; - reg = <12>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - rc_24m: clock-rc-24m@13 { - compatible = "fixed-clock"; - reg = <13>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "rc_24m"; - }; - - dummy_clock_eip: eip-clock@14 { - compatible = "fixed-clock"; - reg = <14>; /* Not address, just for index */ - clock-frequency = <30000000>; - clock-output-names = "dummy_clock_eip"; - #clock-cells = <0>; - }; - - dummy_clock_spi: spi-clock@15 { - compatible = "fixed-clock"; - reg = <15>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_spi"; - #clock-cells = <0>; - }; - - dummy_clock_qspi: spi-clock@16 { - compatible = "fixed-clock"; - reg = <15>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_qspi"; - #clock-cells = <0>; - }; - - dummy_gmac_ahb: gmac-ahb-clock@16 { - compatible = "fixed-clock"; - reg = <16>; - clock-frequency = <50000000>; - clock-output-names = "dummy_gmac_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_gmac: gmac-clock@17 { - compatible = "fixed-clock"; - reg = <17>; - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_gmac"; - #clock-cells = <0>; - }; - - dummy_clock_sdhci: sdhci-clock@18 { - compatible = "fixed-clock"; - reg = <18>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_sdhci"; - #clock-cells = <0>; - }; - - dummy_clock_aonsys_clk: aonsys-clk-clock@19 { - compatible = "fixed-clock"; - reg = <19>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_aonsys_clk"; - #clock-cells = <0>; - }; - - dummy_clock_uart: uart-sclk-clock@20 { - compatible = "fixed-clock"; - reg = <20>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_uart"; - #clock-cells = <0>; - }; - - dummy_clock_visys: visys-dummy-clock@21 { - compatible = "fixed-clock"; - reg = <21>; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - dummy_clock_vipre: vipre-dummy-clock@22 { - compatible = "fixed-clock"; - reg = <22>; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - dummy_clock_vpsys: vpsys-dummy-clock@23 { - compatible = "fixed-clock"; - reg = <23>; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - }; - - iso7816: iso7816-card@fff7f30000 { - compatible = "thead,light-iso7816-card"; - reg = <0xff 0xf7f30000 0x0 0x4000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_iso7816>; - interrupts = <69>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - teesys_syscon: teesys-reg@ffff200000 { - compatible = "syscon"; - reg = <0xff 0xff200000 0x0 0x10000>; - }; - - visys_reg: visys-reg@ffe4040000 { - compatible = "thead,light-visys-reg", "syscon"; - reg = <0xff 0xe4040000 0x0 0x1000>; - status = "disabled"; - }; - - dspsys_reg: dspsys-reg@ffef040000 { - compatible = "thead,light-dspsys-reg", "syscon"; - reg = <0xff 0xef040000 0x0 0x1000>; - status = "okay"; - }; - - audio_ioctrl: audio_ioctrl@ffcb01d000 { - compatible = "thead,light-audio-ioctrl-reg", "syscon"; - reg = <0xff 0xcb01d000 0x0 0x1000>; - status = "okay"; - }; - - audio_cpr: audio_cpr@ffcb000000 { - compatible = "thead,light-audio-cpr-reg", "syscon"; - reg = <0xff 0xcb000000 0x0 0x1000>; - status = "okay"; - }; - - nvmem_controller: efuse@ffff210000 { - compatible = "thead,light-fm-efuse", "syscon"; - reg = <0xff 0xff210000 0x0 0x10000>; - thead,teesys = <&teesys_syscon>; - #address-cells = <1>; - #size-cells = <1>; - - gmac0_mac_address: mac-address@176 { - reg = <0xb0 6>; - }; - - }; - - misc_sysreg: misc_sysreg@ffec02c000 { - compatible = "thead,light-misc-sysreg", "syscon"; - reg = <0xff 0xec02c000 0x0 0x1000>; - status = "okay"; - }; - - usb3_drd: usb3_drd@ffec03f000 { - compatible = "thead,light-usb3-drd", "syscon"; - reg = <0xff 0xec03f000 0x0 0x1000>; - status = "okay"; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio0_porta: gpio0-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <56>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio1_porta: gpio1-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <57>; - }; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio2_porta: gpio2-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <58>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio3_porta: gpio3-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <59>; - }; - }; - - ao_gpio: gpio@fffff41000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff41000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - ao_gpio_porta: ao_gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <76>; - }; - }; - - ao_gpio4: gpio@fffff52000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff52000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - ao_gpio4_porta: ao_gpio4-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <55>; - }; - }; - - padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 { - compatible = "thead,light-fm-left-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - status = "okay"; - }; - - padctrl0_apsys: padctrl0-apsys@ffec007000 { - compatible = "thead,light-fm-right-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - status = "okay"; - }; - - pwm: pwm@ffec01c000 { - compatible = "thead,pwm-light"; - reg = <0xff 0xec01c000 0x0 0x4000>; - #pwm-cells = <2>; - clocks = <&dummy_clock_apb>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <16>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <17>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <18>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <19>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - padctrl_aosys: padctrl-aosys@fffff4a000 { - compatible = "thead,light-fm-aon-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - status = "disabled"; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <20>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <21>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <22>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <23>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - uart0: serial@ffe7014000 { /* Normal serial, for C910 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <36>; - clocks = <&dummy_clock_uart>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <37>; - clocks = <&dummy_clock_uart>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <38>; - clocks = <&dummy_clock_uart>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <39>; - clocks = <&dummy_clock_uart>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <40>; - clocks = <&dummy_clock_uart>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "support"; - status = "okay"; - }; - - uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <41>; - clocks = <&dummy_clock_uart>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - adc: adc@0xfffff51000 { - compatible = "thead,light-adc"; - reg = <0xff 0xfff51000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <61>; - clocks = <&dummy_clock_aonsys_clk>; - clock-names = "adc"; - /* ADC pin is proprietary,no need to config pinctrl */ - status = "disabled"; - }; - - spi0: spi@ffe700c000 { - compatible = "snps,dw-apb-ssi"; - reg = <0xff 0xe700c000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - interrupt-parent = <&intc>; - interrupts = <54>; - clocks = <&dummy_clock_spi>; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi0: spi@ffea000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xea000000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - interrupt-parent = <&intc>; - interrupts = <52>; - clocks = <&dummy_clock_qspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi1: spi@fff8000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xf8000000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1>; - interrupt-parent = <&intc>; - interrupts = <53>; - clocks = <&dummy_clock_spi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - g2d: gc620@ffecc80000 { - compatible = "thead,c910-gc620"; - reg = <0xff 0xecc80000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <101>; - interrupt-names = "irq_2d"; - clocks = <&dummy_clock_vpsys>, - <&dummy_clock_vpsys>, - <&dummy_clock_vpsys>; - clock-names = "pclk", "aclk", "cclk"; - status = "okay"; - }; - - dsi0: dw-mipi-dsi0@ffef500000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef500000 0x0 0x10000>; - status = "disabled"; - - dphy_0: dsi0-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi0>; - vosys-regmap = <&vosys_reg>; - clocks = <&dummy_clock_dphy_ref>, - <&dummy_clock_dphy_cfg>, - <&dummy_clock_dphy_ref>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dphy_cfg>; - clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; - #phy-cells = <0>; - }; - - dhost_0: dsi0-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi0>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&dummy_clock_dphy_cfg>, - <&dummy_clock_dpu_pixel0>; - clock-names = "pclk", "pixclk"; - phys = <&dphy_0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dsi1: dw-mipi-dsi1@ffef510000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef510000 0x0 0x10000>; - status = "disabled"; - - dphy_1: dsi1-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi1>; - vosys-regmap = <&vosys_reg>; - clocks = <&dummy_clock_dphy_ref>, - <&dummy_clock_dphy_cfg>, - <&dummy_clock_dphy_ref>, - <&dummy_clock_dpu_pixel1>, - <&dummy_clock_dphy_cfg>; - clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; - #phy-cells = <0>; - }; - - dhost_1: dsi1-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi1>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&dummy_clock_dphy_cfg>, - <&dummy_clock_dpu_pixel1>; - clock-names = "pclk", "pixclk"; - phys = <&dphy_1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vosys_reg: vosys@ffef528000 { - compatible = "thead,light-vo-subsys", "syscon"; - reg = <0xff 0xef528000 0x0 0x1000>; - status = "okay"; - }; - - hdmi_tx: dw-hdmi-tx@ffef540000 { - compatible = "thead,light-hdmi-tx"; - reg = <0xff 0xef540000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <111>; - clocks = <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>; - clock-names = "iahb", "isfr", "cec", "pixclk", "i2s"; - reg-io-width = <4>; - phy_version = <301>; - /* TODO: add phy property */ - status = "disabled"; - }; - - dpu: dc8200@ffef600000 { - compatible = "verisilicon,dc8200"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff 0xef600000 0x0 0x100>, - <0xff 0xef600800 0x0 0x2000>, - <0xff 0xef630010 0x0 0x60>; - interrupt-parent = <&intc>; - interrupts = <93>; - clocks = <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>, - <&dummy_clock_dpu_pixel0>; - clock-names = "core_clk", "pix_clk0", "pix_clk1", - "axi_clk", "cfg_clk", "pixclk0", - "pixclk1", "dpu0_pll_foutpostdiv", - "dpu1_pll_foutpostdiv"; - status = "disabled"; - - dpu_disp0: port@0 { - reg = <0>; - - disp0_out: endpoint { - remote-endpoint = <&enc0_in>; - }; - }; - - dpu_disp1: port@1 { - reg = <1>; - - disp1_out: endpoint { - remote-endpoint = <&enc1_in>; - }; - }; - }; - - watchdog0: watchdog@ffefc30000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc30000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <24>; - clocks = <&dummy_clock_apb>; - clock-names = "tclk"; - resets = <&rst LIGHT_RESET_WDT0>; - status = "okay"; - }; - - watchdog1: watchdog@ffefc31000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc31000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <25>; - clocks = <&dummy_clock_apb>; - clock-names = "tclk"; - resets = <&rst LIGHT_RESET_WDT1>; - status = "okay"; - }; - - rtc: rtc@fffff40000 { - compatible = "apm,xgene-rtc"; - reg = <0xff 0xfff40000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <74>; - clocks = <&dummy_clock_rtc>; - clock-names = "rtc"; - status = "okay"; - }; - - usb_1: usb@ffec03f000 { - compatible = "thead,dwc3"; - usb3-misc-regmap = <&misc_sysreg>; - usb3-drd-regmap = <&usb3_drd>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb: dwc3@ffe7040000 { - compatible = "snps,dwc3"; - reg = <0xff 0xe7040000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <68>; - clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>; - clock-names = "ref", "bus_early", "suspend"; - reg-shift = <2>; - reg-io-width = <4>; - maximum-speed = "super-speed"; - dr_mode = "host"; - dma-mask = <0xf 0xffffffff>; - snps,usb3_lpm_capable; - snps,usb_sofitpsync; - status = "disabled"; - }; - }; - - pmu: pmu { - interrupt-parent = <&cpu0_intc>; - interrupts = <17>; - compatible = "riscv,c910_pmu"; - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,light-fm-ree-clk"; - reg = <0xff 0xef010000 0x0 0x1000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; - clock-names = "osc_32k", "osc_24m", "rc_24m"; - status = "okay"; - }; - - rst: reset-controller@ffef014000 { - compatible = "thead,light-reset-src","syscon"; - reg = <0xff 0xef014000 0x0 0x1000>; - #reset-cells = <1>; - status = "okay"; - }; - - sys_reg: sys_reg@ffef010100 { - compatible = "thead,light_sys_reg"; - reg = <0xff 0xef010100 0x0 0x100>; - status = "okay"; - }; - - dmac0: dmac@ffefc00000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xefc00000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <27>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - dmac1: tee_dmac@ffff340000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xff340000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <150>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "disabled"; - }; - - dmac2: audio_dmac@0xFFC8000000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xc8000000 0x0 0x2000>; - interrupt-parent = <&intc>; - interrupts = <167>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <16>; - snps,block-size = <65536 65536 65536 65536 - 65536 65536 65536 65536 - 65536 65536 65536 65536 - 65536 65536 65536 65536>; - snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <3>; - snps,rd_osr_lmt = <3>; - snps,blen = <16 8 4 0 0 0 0>; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7070000 0x0 0x2000 - 0xff 0xec00301c 0x0 0x4 - 0xff 0xec003020 0x0 0x4 - 0xff 0xec003000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <66>; - interrupt-names = "macirq"; - clocks = <&dummy_clock_gmac>; - clock-names = "gmac_pll_clk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac0_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - emmc: sdhci@ffe7080000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <62>; - interrupt-names = "sdhciirq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - }; - - sdhci0: sd@ffe7090000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <64>; - interrupt-names = "sdhci0irq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - }; - - sdhci1: sd@ffe70a0000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <71>; - interrupt-names = "sdhci1irq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - }; - - hwspinlock: hwspinlock@ffefc10000 { - compatible = "light,hwspinlock"; - reg = <0xff 0xefc10000 0x0 0x10000>; - status = "disabled"; - }; - - gpu: gpu@ffef400000 { - compatible = "img,gpu"; - reg = <0xff 0xef400000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <102>; - interrupt-names = "gpuirq"; - vosys-regmap = <&vosys_reg>; - //power-domains = <&pd LIGHT_AON_GPU_PD>; - clocks = <&dummy_clock_gpu>, - <&dummy_clock_gpu>; - clock-names = "cclk", "aclk"; - gpu_clk_rate = <18000000>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - vdec: vdec@ffecc00000 { - compatible = "thead,light-vc8000d"; - reg = <0xff 0xecc00000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <131>; - //power-domains = <&pd LIGHT_AON_VDEC_PD>; - clocks = <&dummy_clock_vpsys>, - <&dummy_clock_vpsys>, - <&dummy_clock_vpsys>; - clock-names = "aclk", "cclk", "pclk"; - status = "disabled"; - }; - - venc: venc@ffecc10000 { - compatible = "thead,light-vc8000e"; - reg = <0xff 0xecc10000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <133>; - //power-domains = <&pd LIGHT_AON_VENC_PD>; - clocks = <&dummy_clock_vpsys>, - <&dummy_clock_vpsys>, - <&dummy_clock_vpsys>; - clock-names = "aclk", "cclk", "pclk"; - status = "disabled"; - }; - - isp_venc_shake: shake@ffe4078000 { - compatible = "thead,light-ivs"; - reg = <0xff 0xe4078000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <158>; - status = "disabled"; - }; - - vidmem: vidmem@ffecc08000 { - compatible = "thead,light-vidmem"; - reg = <0xff 0xecc08000 0x0 0x1000>; - status = "okay"; - }; - - light_i2s: light_i2s@ffe7034000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xe7034000 0x0 0x4000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_light_i2s0>; - light,mode = "i2s-master"; - light,sel = "ap_i2s"; - interrupt-parent = <&intc>; - interrupts = <70>; - dmas = <&dmac0 35>, <&dmac0 40>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&dummy_clock_apb>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s0: audio_i2s0@0xffcb014000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xcb014000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s0"; - interrupt-parent = <&intc>; - interrupts = <174>; - dmas = <&dmac2 9>, <&dmac2 16>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&dummy_clock_apb>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s1: audio_i2s1@0xffcb015000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xcb015000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s1"; - interrupt-parent = <&intc>; - interrupts = <175>; - dmas = <&dmac2 11>, <&dmac2 17>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&dummy_clock_apb>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s3: audio_i2s3@0xffcb017000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xcb017000 0x0 0x1000>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s3"; - interrupt-parent = <&intc>; - interrupts = <177>; - dmas = <&dmac2 14>, <&dmac2 16>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&dummy_clock_apb>; - clock-names = "pclk"; - status = "disabled"; - }; - - pvt: pvt@fffff4e000 { - compatible = "moortec,mr75203"; - reg = <0xff 0xfff4e000 0x0 0x80>, - <0xff 0xfff4e080 0x0 0x100>, - <0xff 0xfff4e180 0x0 0x680>, - <0xff 0xfff4e800 0x0 0x600>; - reg-names = "common", "ts", "pd", "vm"; - clocks = <&dummy_clock_aonsys_clk>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - i2c0: i2c@ffe7f20000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f20000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <44>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@ffe7f24000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f24000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <45>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@ffec00c000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec00c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <46>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@ffec014000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <47>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@ffe7f28000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f28000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <48>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - audio_i2c0: i2c@0xffcb01a000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xcb01a000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <182>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x82>; - ss_lcnt = /bits/ 16 <0x78>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - isp0: isp@ffe4100000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <117>,<118>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "aclk", "hclk", "isp0_pclk", "cclk"; - status = "disabled"; - }; - - isp1: isp@ffe4110000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <120>,<121>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk"; - status = "disabled"; - }; - - isp_ry0: isp_ry@ffe4120000 { - compatible = "thead,light-isp_ry"; - reg = <0xff 0xe4120000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <123>,<124>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "aclk", "hclk", "cclk"; - status = "disabled"; - }; - - dewarp: dewarp@ffe4130000 { - compatible = "thead,light-dewarp"; - reg = <0xff 0xe4130000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <98>,<99>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "aclk", "hclk", "vseclk", "dweclk"; - status = "disabled"; - }; - - dec400_isp0: dec400@ffe4060000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4060000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp1: dec400@ffe4068000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4068000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp2: dec400@ffe4070000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4070000 0x0 0x8000>; - status = "disabled"; - }; - - bm_visys: bm_visys@ffe4040000 { - compatible = "thead,light-bm-visys"; - reg = <0xff 0xe4040000 0x0 0x1000>; - status = "disabled"; - }; - - bm_csi0: csi@ffe4000000{ //CSI2 - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4000000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <128>; - dphyglueiftester = <0x180>; - sysreg_mipi_csi_ctrl = <0x140>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "pixclk", "cfg_clk"; - phy_name = "CSI_4LANE"; - status = "disabled"; - }; - - csia_reg: visys-reg@ffe4020000 { - compatible = "thead,light-visys-reg", "syscon"; - reg = < 0xff 0xe4020000 0x0 0x10000>; - status = "okay"; - }; - - bm_csi1: csi@ffe4010000{ //CSI2X2_B - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4010000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0 - dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed. - sysreg_mipi_csi_ctrl = <0x148>; - visys-regmap = <&visys_reg>; - csia-regmap = <&csia_reg>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "pixclk", "cfg_clk"; - phy_name = "CSI_B"; - status = "disabled"; - }; - - bm_csi2: csi@ffe4020000{ //CSI2X2_A - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4020000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <127>; - dphyglueiftester = <0x184>; - sysreg_mipi_csi_ctrl = <0x144>; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "pixclk", "cfg_clk"; - phy_name = "CSI_A"; - status = "disabled"; - }; - - bm_isp0: bm_isp@ffe4100000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - status = "disabled"; - }; - - bm_isp1: bm_isp@ffe4110000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - status = "disabled"; - }; - - //isp-ry - bm_isp2: bm_isp@ffe4120000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4120000 0x0 0x10000>; - status = "disabled"; - }; - - vi_pre: vi_pre@ffe4030000 { - compatible = "thead,vi_pre"; - reg = <0xff 0xe4030000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <134>; - clocks = <&dummy_clock_vipre>, - <&dummy_clock_vipre>, - <&dummy_clock_vipre>; - clock-names ="aclk", "pclk", "pixclk"; - status = "disabled"; - }; - - video0: cam_dev@100 { - compatible = "thead,video"; - status = "disabled"; - }; - - video1: cam_dev@200 { - compatible = "thead,video"; - status = "disabled"; - }; - - video2: cam_dev@300 { - compatible = "thead,video"; - status = "disabled"; - }; - - video3: cam_dev@400 { - compatible = "thead,video"; - status = "disabled"; - }; - - video4: cam_dev@500 { - compatible = "thead,video"; - status = "disabled"; - }; - - video5: cam_dev@600 { - compatible = "thead,video"; - status = "disabled"; - }; - - video6: cam_dev@700 { - compatible = "thead,video"; - status = "disabled"; - }; - - video7: cam_dev@800 { - compatible = "thead,video"; - status = "disabled"; - }; - - video8: cam_dev@900 { - compatible = "thead,video"; - status = "disabled"; - }; - - video9: cam_dev@a00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video10: cam_dev@b00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video11: cam_dev@c00 { - compatible = "thead,video"; - status = "disabled"; - }; - video12: cam_dev@d00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video13: cam_dev@e00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video14: cam_dev@f00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video15: cam_dev@f01 { - compatible = "thead,video"; - status = "disabled"; - }; - - vvcam_flash_led0: vvcam_flash_led@0 { - compatible = "thead,light-vvcam-flash_led"; - status = "disabled"; - }; - - vvcam_sensor0: vvcam_sensor@0 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor1: vvcam_sensor@1 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor2: vvcam_sensor@2 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor3: vvcam_sensor@3 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor4: vvcam_sensor@4 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor5: vvcam_sensor@5 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor6: vvcam_sensor@6 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - xtensa_dsp: dsp@01{ - compatible = "thead,dsp-hw-common"; - reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */ - status = "disabled"; - }; - - xtensa_dsp0: dsp@0 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef048000 0x0 0x008000>; /* DSP shared memory */ - dsp = <0>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <156>; - firmware-name = "xrp0.elf"; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "cclk"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - xtensa_dsp1: dsp@1 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef050000 0x0 0x008000>; /* DSP shared memory */ - dsp = <1>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <157>; - firmware-name = "xrp1.elf"; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "cclk"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - mrvbr: mrvbr@ffff018050 { - compatible = "mrvbr"; - reg = <0xff 0xff019050 0x0 0x1000>; - }; - - mrmr: mrmr@ffff014004 { - compatible = "mrmr"; - reg = <0xff 0xff015004 0x0 0x1000>; - }; - - bmu: ddr-pmu@ffff008000 { - compatible = "thead,light-ddr-pmu"; - reg = <0xff 0xff008000 0x0 0x800 - 0xff 0xff008800 0x0 0x800 - 0xff 0xff009000 0x0 0x800 - 0xff 0xff009800 0x0 0x800 - 0xff 0xff00a000 0x0 0x800>; - interrupt-parent = <&intc>; - interrupts = <87>; - status = "okay"; - }; - - mbox_910t: mbox@ffffc38000 { - compatible = "thead,light-mbox"; - reg = <0xff 0xffc38000 0x0 0x4000>, - <0xff 0xffc44000 0x0 0x1000>, - <0xff 0xffc4c000 0x0 0x1000>, - <0xff 0xffc54000 0x0 0x1000>; - reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&dummy_clock_apb>; - clock-names = "ipg"; - icu_cpu_id = <0>; - #mbox-cells = <2>; - status = "disabled"; - }; - - trng: rng@ffff300000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xff 0xff300000 0x0 0x7d>; - interrupt-parent = <&intc>; - interrupts = <149>; - clocks = <&dummy_clock_eip>; - status = "disabled"; - }; - - - eip_28: eip-28@ffff300000 { - compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28"; - reg = <0xff 0xff300000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <144>,<145>,<146>,<147>; - clocks = <&dummy_clock_eip>; - status = "disabled"; - }; - - khvhost: khvhost { - compatible = "thead,khv-host"; - interrupt-parent = <&intc>; - interrupts = <215>; /* TEE INT SRC_7 */ - }; - - visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */ - compatible = "thead,visys-gate-controller"; - visys-regmap = <&visys_reg>; - #clock-cells = <1>; - status = "okay"; - }; - - vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */ - compatible = "thead,vpsys-gate-controller"; - reg = <0xff 0xecc30000 0x0 0x1000>; - #clock-cells = <1>; - status = "okay"; - }; - - vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */ - compatible = "thead,vosys-gate-controller"; - reg = <0xff 0xef528000 0x0 0x1000>; - #clock-cells = <1>; - status = "okay"; - }; - - dspsys_clk_gate: dspsys-clk-gate { - compatible = "thead,dspsys-gate-controller"; - dspsys-regmap = <&dspsys_reg>; - #clock-cells = <1>; - status = "okay"; - }; - }; - -}; - diff --git a/arch/riscv/boot/dts/thead/ice.dts b/arch/riscv/boot/dts/thead/ice.dts deleted file mode 100644 index 9c6e6e2e5313..000000000000 --- a/arch/riscv/boot/dts/thead/ice.dts +++ /dev/null @@ -1,399 +0,0 @@ -/dts-v1/; -/ { - model = "T-HEAD c910 ice"; - compatible = "thead,c910_ice"; - #address-cells = <2>; - #size-cells = <2>; - - memory@0 { - device_type = "memory"; - /* - * Total memory size: 4GB (0x00000000 0x100000000) - * 0x00200000 - 0x0e0000000: 3407MB for Linux system - * 0xe0000000 - 0x100000000: 512MB for GPU - */ - reg = <0x0 0x200000 0x0 0xdfe00000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <3000000>; - cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.2Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@1 { - device_type = "cpu"; - reg = <1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.2Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0x3 0xf01ffffc>; - using-csr-reset; - csr-copy = < - 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc - 0x3b0 0x3b1 0x3b2 0x3b3 - 0x3b4 0x3b5 0x3b6 0x3b7 - 0x3a0 - >; - }; - - clint0: clint@3f4000000 { - compatible = "riscv,clint0"; - interrupts-extended = < - &cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - >; - reg = <0x3 0xf4000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; - }; - - intc: interrupt-controller@3f0000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff &cpu0_intc 9 - &cpu1_intc 0xffffffff &cpu1_intc 9 - >; - reg = <0x3 0xf0000000 0x0 0x04000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <80>; - }; - - dummy_apb: apb-clock { - compatible = "fixed-clock"; - clock-frequency = <62500000>; - clock-output-names = "dummy_apb"; - #clock-cells = <0>; - }; - - dummy_ahb: ahb-clock { - compatible = "fixed-clock"; - clock-frequency = <250000000>; - clock-output-names = "dummy_ahb"; - #clock-cells = <0>; - }; - - dummy_axi: axi-clock { - compatible = "fixed-clock"; - clock-frequency = <500000000>; - clock-output-names = "dummy_axi"; - #clock-cells = <0>; - }; - - dummy_gmac: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <1000000000>; - clock-output-names = "dummy_gmac"; - #clock-cells = <0>; - }; - - dummy_clk_sdio: dummy-clk-sdio { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - clock-output-names = "dummy_clk_sdio"; - #clock-cells = <0>; - }; - - usb: dwc3@3fff10000 { - compatible = "snps,dwc3"; - reg = <0x3 0xfff10000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <44>; - clocks = <&dummy_ahb>, <&dummy_ahb>, <&dummy_ahb>; - clock-names = "ref", "bus_early", "suspend"; - maximum-speed = "super-speed"; - dr_mode = "peripheral"; - snps,usb3_lpm_capable; - snps,dis_u3_susphy_quirk; - }; - - gpio0: gpio@3fff71000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3 0xfff71000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - /* GPIO0[0-31] */ - gpio0_porta: gpio0-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <27>; - }; - - /* GPIO0[32-63] */ - gpio0_portb: gpio0-controller@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <1>; - }; - }; - - gpio1: gpio@3fff72000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x3 0xfff72000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - /* GPIO1[0-31] */ - gpio1_porta: gpio1-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - - /* GPIO1[32-63] */ - gpio1_portb: gpio1-controller@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <1>; - }; - - /* GPIO1[64-95] */ - gpio1_portc: gpio1-controller@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <2>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led0 { /* GPIO0[11] - UART2_TXD */ - label = "led0"; - gpios = <&gpio0_porta 11 1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - /* autorepeat; */ - - key_0 { /* GPIO0[10] - UART2_RXD */ - gpios = <&gpio0_porta 10 1>; - linux,code = <59>; - label = "key_0"; - }; - }; - - i2c@3fff74000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c-ice"; - reg = <0x3 0xfff74000 0x0 0x1000>; - interrupts = <21>; - interrupt-parent = <&intc>; - clocks = <&dummy_apb>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; - - goodix_ts@14 { - #gpio-cells = <2>; - compatible = "goodix,gt917s"; - reg = <0x14>; - interrupt-parent = <&gpio0_porta>; - interrupts = <31 0>; - irq-gpios = <&gpio0_porta 31 0>; - reset-gpios = <&gpio0_porta 30 0>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - }; - }; - - serial@3fff73000 { - compatible = "snps,dw-apb-uart"; - reg = <0x3 0xfff73000 0x0 0x400>; - interrupt-parent = <&intc>; - interrupts = <23>; - clocks = <&dummy_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; - - pmu: pmu { - interrupt-parent = <&cpu0_intc>; - interrupts = <17>; - compatible = "riscv,c910_pmu"; - }; - - dmac0: dmac@3fffd0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x3 0xfffd0000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <65>; - clocks = <&dummy_axi>, <&dummy_ahb>; - clock-names = "core-clk", "cfgr-clk"; - - dma-channels = <8>; - snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>; - snps,priority = <0 1 2 3 4 5 6 7>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - - status = "disabled"; - }; - - sdhc0: sdhc0@3fffb0000 { - compatible = "snps,dw-mshc"; - reg = <0x3 0xfffb0000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <37>; - clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>; - clock-names = "ciu", "biu"; - num-slots = <1>; - card-detect-delay = <200>; - cap-mmc-highspeed; - cap-cmd23; - non-removable; - bus-width = <8>; - }; - - sdhc1: sdhc1@3fffa0000 { - compatible = "snps,dw-mshc"; - reg = <0x3 0xfffa0000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <38>; - clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>; - clock-names = "ciu", "biu"; - num-slots = <1>; - card-detect-delay = <200>; - cap-sd-highspeed; - bus-width = <4>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <3>; - snps,rd_osr_lmt = <3>; - snps,blen = <16 8 4 0 0 0 0>; - }; - - gmac: ethernet@3fffc0000 { - compatible = "thead,dwmac"; - reg = < 0x3 0xfffc0000 0x0 0x2000 - 0x3 0xfe83025c 0x0 0x4 - 0x3 0xfe83031c 0x0 0x4 - 0x3 0xfff770c0 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <40>; - interrupt-names = "macirq"; - clocks = <&dummy_ahb>, <&dummy_gmac>; - clock-names = "stmmaceth", "gmac_pll_clk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - - phy-mode = "rgmii-id"; - rx-clk-delay = <0x1f>; /* for RGMII */ - tx-clk-delay = <0x1f>; /* for RGMII */ - - phy-handle = <ð_phy_0>; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - eth_phy_0: ethernet-phy@0 { - reg = <0>; - }; - }; - }; - - gpu: gpu@3fff27000 { - compatible = "verisilicon,gc8000ul"; - reg = <0x3 0xfff27000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <63>; - contiguous-base = <0x0 0xe0000000>; - contiguous-size = <0x0 0x20000000>; - }; - - watchdog: watchdog@3fffe3000 { - compatible = "ice,ice-wdt"; - reg = <0x3 0xfffe3000 0x0 0x1000>; - interrupts = <20>; - }; - - dpu: dpu@3fff28000 { - compatible = "verisilicon,dc8000-fb"; - reg = <0x3 0xfff28000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <64>; - }; - }; - - chosen { - /* bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1"; */ - /* linux,initrd-start = <0x2000000>; */ - /* linux,initrd-end = <0x17000000>; */ - bootargs = "console=ttyS0,115200 rdinit=/sbin/init root=/dev/mmcblk0p4 rw rootfstype=ext4 blkdevparts=mmcblk0:2M(table),2M(dtb),60M(kernel),-(rootfs) clk_ignore_unused loglevel=7 rootwait crashkernel=256M-:128M c910_mmu_v1"; - stdout-path = "serial0@3fff73000:115200"; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-product-powergate.dts b/arch/riscv/boot/dts/thead/light-a-product-powergate.dts deleted file mode 100644 index 8458f4ad6b8c..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-product-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-product.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-product.dts b/arch/riscv/boot/dts/thead/light-a-product.dts deleted file mode 100644 index 38dde44bfc0f..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-product.dts +++ /dev/null @@ -1,1108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" - -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "SYS_STATUS"; - //gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - lcd1_backlight: pwm-backlight@1 { - compatible = "pwm-backlight"; - pwms = <&pwm 1 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <1>; - compatible = "linux,bt-sco"; - status = "okay"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_a 3 1>; - enable-active-high; - regulator-always-on; - }; - - reg_tp1_pwr_en: regulator-tp1-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_a 6 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 26 0>; - WIFI,reset_n = <&gpio2_porta 28 0>; - status = "disabled"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "disabled"; - }; - - aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&ao_gpio_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio0_porta 10 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 11 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vext_2v8_reg: soc_vext_2v8 { - compatible = "regulator-fixed"; - regulator-name = "soc_vext_2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 24 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 22 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio1_porta 25 1>; - enable-active-high; - regulator-always-on; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&gpio1_porta 21 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 22 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio1_porta 23 1>; - enable-active-high; - regulator-always-on; - }; - - aon_reg_ricoh: light-ricoh-reg { - compatible = "thead,light-ricoh-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ap_reg: soc_dvdd08_ap { - regulator-name = "soc_dvdd08_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_dvdd33_emmc { - regulator-name = "soc_dvdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_dvdd18_emmc { - regulator-name = "soc_dvdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; -}; - -&cmamem { - alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000] -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@0f800000 { - reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ - 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ - no-map; - }; - facelib_mem: memory@22000000 { - reg = <0x0 0x22000000 0x0 0x10000000>; - no-map; - }; -}; - -&adc { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - touch1@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <12 0>; - irq-gpios = <&gpio1_porta 12 0>; - reset-gpios = <&gpio1_porta 11 0>; - AVDD28-supply = <®_tp1_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <66000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi2"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "okay"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - FM_GPIO3_3 0x1 0x208 /* pwm1 */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - pcal6408ahk_a: gpio@20 { - compatible = "nxp,pcal9554b"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1{ - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - //flood_lignt_name = "aw36413"; - //projection_lignt_name = "aw36515"; - - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - projection_i2c_bus = /bits/ 8 <2>; - flash_led_touch_pin = <&gpio1_porta 29 0>; //flash led touch pin - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor1 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 50 20>; - i2c_addr = /bits/ 8 <0x31>; - sensor_pdn = <&gpio1_porta 14 0>; - sensor_rst = <&gpio1_porta 15 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&video0{ - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - }; - }; -}; - -&video1{ - status = "okay"; - channel0 { // VSE0 - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; -}; - -&video2{ - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_ODD"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DDR"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_EVEN"; - }; - }; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts b/arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts deleted file mode 100644 index c134431d4fc7..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-ref-dsi0-hdmi.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-ref-dsi0.dts" - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts b/arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts deleted file mode 100644 index 57bd3ae2b2f9..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-ref-dsi0.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-ref.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&lcd0_1v8>; - vspn5v7-supply = <&lcd0_5v7>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-ref.dts b/arch/riscv/boot/dts/thead/light-a-ref.dts deleted file mode 100644 index 4287c4a117f9..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-ref.dts +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ -#include "light-a-val.dts" diff --git a/arch/riscv/boot/dts/thead/light-a-val-android.dts b/arch/riscv/boot/dts/thead/light-a-val-android.dts deleted file mode 100644 index e4504f3e5e0f..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-android.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-dsi0.dts" - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; -&sdhci1 { - status = "okay"; -}; - -&wcn_bt { - status = "okay"; -}; - -&wcn_wifi { - status = "okay"; -}; - -&lightsound { - status = "okay"; - - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; - - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -/ { - firmware { - android { - compatible = "android,firmware"; - boot_devices = "soc/ffe7080000.sdhci"; - fstab { - compatible = "android,fstab"; - system { - compatible = "android,system"; - dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/system"; - type = "ext4"; - mnt_flags = "ro,barrier=1"; - fsmgr_flags = "wait"; - }; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/ffe7080000.sdhci/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1"; - fsmgr_flags = "wait"; - }; - }; - }; - }; -}; - diff --git a/arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts b/arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts deleted file mode 100644 index 0238975192fc..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-audio-hdmi.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-audio.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&dpu { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-audio-i2s-8ch.dts b/arch/riscv/boot/dts/thead/light-a-val-audio-i2s-8ch.dts deleted file mode 100644 index 215f57b2ca1f..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-audio-i2s-8ch.dts +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-audio.dts" - -/ { - model = "T-HEAD Light FM Audio VAL board"; - compatible = "thead,light-val-audio-i2s-8ch", "thead,light"; -}; - - -&lightsound { - status = "okay"; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - mclk-fs = <512>; - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; - - simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd3 3>; - }; - codec { - mclk-fs = <512>; - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; - - simple-audio-card,dai-link@3 { /* I2S - AUDIO SYS CODEC 7210_1*/ - reg = <3>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd0 0>; - }; - codec { - mclk-fs = <512>; - sound-dai = <&es7210_audio_codec_adc1>; - }; - }; - - simple-audio-card,dai-link@4 { /* I2S - AUDIO SYS CODEC 7210_1*/ - reg = <4>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd1 1>; - }; - codec { - mclk-fs = <512>; - sound-dai = <&es7210_audio_codec_adc1>; - }; - }; -}; - -&i2s_8ch_sd0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa4>, - <&pinctrl_audio_i2s_8ch_sd0>, - <&pinctrl_audiopa2>, - <&pinctrl_audiopa3>, - <&pinctrl_audiopa8>, - <&pinctrl_audio_i2s_8ch_bus>; -}; - -&i2s_8ch_sd1 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa0>, - <&pinctrl_audio_i2s_8ch_sd2>; -}; - -&i2s_8ch_sd3 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; - channels-max = <8>; -}; - -&es7210_audio_codec_adc1 { - status = "okay"; - channels-max = <8>; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-audio-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-audio-powergate.dts deleted file mode 100644 index 230d1b20d2de..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-audio-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-audio.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-audio-spdif.dts b/arch/riscv/boot/dts/thead/light-a-val-audio-spdif.dts deleted file mode 100644 index 91282bc91549..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-audio-spdif.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -&spdif0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_spdif0>; - status = "okay"; -}; - -&spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_spdif1>; - status = "okay"; -}; - -&lightsound { - status = "okay"; - simple-audio-card,dai-link@0 { /* SPDIF0 */ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&spdif0>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* SPDIF1 */ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&spdif1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; \ No newline at end of file diff --git a/arch/riscv/boot/dts/thead/light-a-val-audio-tdm.dts b/arch/riscv/boot/dts/thead/light-a-val-audio-tdm.dts deleted file mode 100644 index 39683e2097f4..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-audio-tdm.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -&tdm_slot1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_tdm>; - status = "okay"; -}; - -&tdm_slot2 { - status = "okay"; -}; - -&tdm_slot3 { - status = "okay"; -}; - -&tdm_slot4 { - status = "okay"; -}; - -&tdm_slot5 { - status = "okay"; -}; - -&tdm_slot6 { - status = "okay"; -}; - -&tdm_slot7 { - status = "okay"; -}; - -&tdm_slot8 { - status = "okay"; -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - es7210_adc2: es7210@42 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x42>; - work-mode = "ES7210_TDM_1LRCK_DSPB"; - channels-max = <8>; - sound-name-prefix = "ES7210_ADC2"; - MVDD-supply = <&soc_aud_adc_3v3_en_reg>; - AVDD-supply = <&soc_aud_adc_3v3_en_reg>; - DVDD-supply = <&soc_dvdd18_aon_reg>; - PVDD-supply = <&soc_dvdd18_aon_reg>; - }; - - es7210_adc3: es7210@43 { - #sound-dai-cells = <0>; - compatible = "MicArray_1"; - reg = <0x43>; - work-mode = "ES7210_TDM_1LRCK_DSPB"; - channels-max = <8>; - sound-name-prefix = "ES7210_ADC3"; - MVDD-supply = <&soc_aud_adc_3v3_en_reg>; - AVDD-supply = <&soc_aud_adc_3v3_en_reg>; - DVDD-supply = <&soc_dvdd18_aon_reg>; - PVDD-supply = <&soc_dvdd18_aon_reg>; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "AW87519 IN", "ES8156 ROUT", - "Speaker", "AW87519 VO"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* TDM - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot1>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@2 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot2>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@3 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot3>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@4 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot4>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@5 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot5>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@6 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot6>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@7 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot7>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; - - simple-audio-card,dai-link@8 { - reg = <1>; - format = "dsp_b"; - cpu { - sound-dai = <&tdm_slot8>; - }; - codec { - sound-dai = <&es7210_adc2>; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-audio.dts b/arch/riscv/boot/dts/thead/light-a-val-audio.dts deleted file mode 100644 index ede93c44b73d..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-audio.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -/ { - model = "T-HEAD Light FM Audio VAL board"; - compatible = "thead,light-val-audio", "thead,light"; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; -}; - - diff --git a/arch/riscv/boot/dts/thead/light-a-val-crash.dts b/arch/riscv/boot/dts/thead/light-a-val-crash.dts deleted file mode 100644 index 78a51f0061c3..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-crash.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-crash.dts" - -&aon { - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-ddr1G-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-ddr1G-powergate.dts deleted file mode 100644 index d3d867b0985a..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-ddr1G-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-ddr1G.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts b/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts deleted file mode 100644 index c9a20172b01a..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-ddr1G.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-a-val-ddr2G.dts" - -/ { - model = "T-HEAD Light VAL configuration for 1GB DDR board"; - compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x3fe00000>; - }; -}; - -&cmamem { - size = <0 0x8c00000>; // 140MB by default - alloc-ranges = <0 0x02000000 0 0x0cc00000>; // [0x0600_0000 ~ 0x0EC0_0000] -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-ddr2G-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-ddr2G-powergate.dts deleted file mode 100644 index 59c9b821f5b1..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-ddr2G-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-ddr2G.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts b/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts deleted file mode 100644 index ea5a732680d3..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-ddr2G.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -/ { - model = "T-HEAD Light VAL configuration for 2GB DDR board"; - compatible = "thead,light-val", "thead,light-val-ddr2G", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x7fe00000>; - }; -}; - -&cmamem { - alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] -}; - -&facelib_mem { - reg = <0x0 0x22000000 0 0x02000000>; - no-map; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1-powergate.dts deleted file mode 100644 index aaf0fffb35b8..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dpi0-dpi1.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1.dts b/arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1.dts deleted file mode 100644 index 2f0a2db370aa..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dpi0-dpi1.dts +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-dpi0.dts" - -/ { - dpi_panel1: dpi-panel@1 { - compatible = "light,dummy-panel"; - - port { - dpi1_in: endpoint { - remote-endpoint = <&enc1_out>; - }; - }; - }; -}; - -&dpu_enc1 { - compatible = "verisilicon,dpi-encoder"; - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc1_out: endpoint { - remote-endpoint = <&dpi1_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dpi0-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dpi0-powergate.dts deleted file mode 100644 index 9a68fb55181e..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dpi0-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dpi0.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dpi0.dts b/arch/riscv/boot/dts/thead/light-a-val-dpi0.dts deleted file mode 100644 index 93a4c60dd2b3..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dpi0.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; - - dpi_panel0: dpi-panel@0 { - compatible = "light,dummy-panel"; - - port { - dpi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - }; -}; - -&dpu_enc0 { - compatible = "verisilicon,dpi-encoder"; - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dpi0_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1-powergate.dts deleted file mode 100644 index 37335799c26e..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dsi0-dsi1.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1.dts deleted file mode 100644 index 4c18ad82ee26..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0-dsi1.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-dsi0.dts" - -&dpu_enc1 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc1_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; -}; - -&dsi1 { - status = "okay"; -}; - -&dhost_1 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi1_in: endpoint { - remote-endpoint = <&enc1_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi1_out: endpoint { - remote-endpoint = <&panel1_in>; - }; - }; - }; - - panel1@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - reset-gpio = <&gpio1_porta 9 1>; /* active low */ - vdd1v8-supply = <&lcd1_1v8>; - vspn5v7-supply = <&lcd1_5v7>; - - port { - panel1_in: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-audio.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-audio.dts deleted file mode 100644 index 6d54c69c9c80..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-audio.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-dsi0-hdmi.dts" - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-powergate.dts deleted file mode 100644 index 09303b53c850..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dsi0-hdmi.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi.dts deleted file mode 100644 index 622726103c9d..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0-hdmi.dts +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-dsi0.dts" - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0-powergate.dts deleted file mode 100644 index 5c5653e054bc..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dsi0.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi0.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi0.dts deleted file mode 100644 index b7ae591ea030..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi0.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&lcd0_1v8>; - vspn5v7-supply = <&lcd0_5v7>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi1-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi1-powergate.dts deleted file mode 100644 index 2ed9e637bcfb..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi1-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dsi1.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsi1.dts b/arch/riscv/boot/dts/thead/light-a-val-dsi1.dts deleted file mode 100644 index cd533d3f6df5..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsi1.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc1 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc1_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi1 { - status = "okay"; -}; - -&dhost_1 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi1_in: endpoint { - remote-endpoint = <&enc1_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi1_out: endpoint { - remote-endpoint = <&panel1_in>; - }; - }; - }; - - panel1@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd1_backlight>; - reset-gpio = <&gpio1_porta 9 1>; /* active low */ - vdd1v8-supply = <&lcd1_1v8>; - vspn5v7-supply = <&lcd1_5v7>; - - port { - panel1_in: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1-powergate.dts deleted file mode 100644 index fd2fbb65ee94..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-dsp0-dsp1.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1.dts b/arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1.dts deleted file mode 100644 index db9ea52412a9..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-dsp0-dsp1.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - - -&xtensa_dsp1 { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-full-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-full-powergate.dts deleted file mode 100644 index 18ede1367f64..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-full-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-full.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-full.dts b/arch/riscv/boot/dts/thead/light-a-val-full.dts deleted file mode 100644 index 149b1a2a92d3..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-full.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&lcd0_1v8>; - vspn5v7-supply = <&lcd0_5v7>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; -}; - -&qspi0 { - status = "okay"; -}; - - -&qspi1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; -}; - -&wcn_bt { - status = "okay"; -}; - -&wcn_wifi { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-gpio-keys.dts b/arch/riscv/boot/dts/thead/light-a-val-gpio-keys.dts deleted file mode 100644 index 2bea1a9c95d0..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-gpio-keys.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -/ { - model = "T-HEAD Light FM GPIO-KEYS VAL board"; - compatible = "thead,light-val-gpio-keys", "thead,light"; -}; - -&gpio_keys { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-hdmi-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-hdmi-powergate.dts deleted file mode 100644 index d821460a6ebf..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-hdmi-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-hdmi.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-hdmi.dts b/arch/riscv/boot/dts/thead/light-a-val-hdmi.dts deleted file mode 100644 index 23bf31b32fe9..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-hdmi.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&dpu { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - - simple-audio-card,dai-link@1 { /* I2S - HDMI */ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-iso7816-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-iso7816-powergate.dts deleted file mode 100644 index 130416d046a9..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-iso7816-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-iso7816.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-iso7816.dts b/arch/riscv/boot/dts/thead/light-a-val-iso7816.dts deleted file mode 100644 index b0ad7cb5ac0e..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-iso7816.dts +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -&iso7816 { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-khv-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-khv-powergate.dts deleted file mode 100644 index 0e980b692102..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-khv-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-khv.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-khv.dts b/arch/riscv/boot/dts/thead/light-a-val-khv.dts deleted file mode 100644 index 8d92ff7173a7..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-khv.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 512M for guest memory */ - guestmem: memory@50000000 { - reg = <0x0 0x50000000 0x0 0x20000000>; - }; -}; - -&khvhost { - memory-region = <&guestmem>; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts b/arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts deleted file mode 100644 index 1bf9d5e18b9f..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-miniapp-dsi0.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&lcd0_1v8>; - vspn5v7-supply = <&lcd0_5v7>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&padctrl_audiosys { - status = "okay"; - - light-audio-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audio_i2s_8ch: audio_i2s_8ch_grp { - thead,pins = < - FM_AUDIO_IO_PA0 0x2 0x008 - FM_AUDIO_IO_PA2 0x2 0x008 - FM_AUDIO_IO_PA3 0x2 0x008 - FM_AUDIO_IO_PA8 0x2 0x008 - >; - }; - }; -}; - -&lightsound { - status = "okay"; - - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; -}; - -&wcn_bt { - status = "okay"; -}; - -&wcn_wifi { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi-powergate.dts deleted file mode 100644 index beedbd4f6983..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-miniapp-hdmi.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts b/arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts deleted file mode 100644 index 107a9a1ed695..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-miniapp-hdmi.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&dpu { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s0 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec_adc0>; - }; - }; -}; - - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&es7210_audio_codec_adc0 { - status = "okay"; -}; - -&sdhci1 { - status = "okay"; -}; - -&wcn_bt { - status = "okay"; -}; - -&wcn_wifi { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-nand-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-nand-powergate.dts deleted file mode 100644 index 985d307fe0fc..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-nand-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-nand.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-nand.dts b/arch/riscv/boot/dts/thead/light-a-val-nand.dts deleted file mode 100644 index 9c4f1be58bb6..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-nand.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -&qspi0 { - status = "okay"; -}; - -&qspi1 { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-npu-fce-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-npu-fce-powergate.dts deleted file mode 100644 index 4b0fbb51dc50..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-npu-fce-powergate.dts +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-npu-fce.dts" -#include "light-powergate.dts" - -&npu { - power-domains = <&pd LIGHT_AON_NPU_PD>; -}; - diff --git a/arch/riscv/boot/dts/thead/light-a-val-npu-fce.dts b/arch/riscv/boot/dts/thead/light-a-val-npu-fce.dts deleted file mode 100644 index f4627fa091a6..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-npu-fce.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" - -/ { - model = "T-HEAD Light FM NPU&FCE on VAL board"; - compatible = "thead,light-val-npu-fce", "thead,light"; - -}; - -&facelib_mem { - reg = <0x0 0xd0000000 0 0x20000000>; - no-map; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/thead/light-a-val-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-powergate.dts deleted file mode 100644 index 26017d092218..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-sec-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-sec-powergate.dts deleted file mode 100644 index 0c436798ccc3..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-sec-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-sec.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-sec.dts b/arch/riscv/boot/dts/thead/light-a-val-sec.dts deleted file mode 100644 index 19cff7bdeee6..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-sec.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val-audio-hdmi.dts" - - -&light_iopmp { - status = "disabled"; -}; -&qspi1 { - status = "disabled"; -}; - -&eip_28 { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-sv-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-sv-powergate.dts deleted file mode 100644 index dea8da970c2c..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-sv-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-sv.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-sv.dts b/arch/riscv/boot/dts/thead/light-a-val-sv.dts deleted file mode 100644 index 9112faeb50b3..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-sv.dts +++ /dev/null @@ -1,1640 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -&c910_0 { - operating-points = < - /* kHz uV */ - 55000 600000 - 65000 600000 - 75000 600000 - 85000 600000 - 95000 600000 - 105000 600000 - 115000 600000 - 125000 600000 - 128000 600000 - 136000 600000 - 144000 600000 - 152000 600000 - 160000 600000 - 168000 600000 - 176000 600000 - 184000 600000 - 192000 600000 - 200000 600000 - 204000 600000 - 216000 600000 - 228000 600000 - 240000 600000 - 252000 600000 - 264000 600000 - 276000 600000 - 288000 600000 - 300000 600000 - 304000 700000 - 312000 700000 - 320000 700000 - 328000 700000 - 336000 700000 - 344000 700000 - 352000 700000 - 360000 700000 - 368000 700000 - 376000 700000 - 384000 700000 - 392000 700000 - 400000 700000 - 412000 700000 - 420000 700000 - 428000 700000 - 436000 700000 - 444000 700000 - 452000 700000 - 460000 700000 - 468000 700000 - 476000 700000 - 484000 700000 - 492000 700000 - 500000 700000 - 504000 700000 - 513600 700000 - 523200 700000 - 532800 700000 - 542400 700000 - 552000 700000 - 561600 700000 - 571200 700000 - 580800 700000 - 590400 700000 - 600000 700000 - 606000 700000 - 618000 700000 - 630000 700000 - 642000 700000 - 654000 700000 - 666000 700000 - 678000 700000 - 690000 700000 - 702000 700000 - 712000 700000 - 720000 700000 - 728000 700000 - 736000 700000 - 744000 700000 - 752000 700000 - 760000 700000 - 768000 700000 - 776000 700000 - 784000 700000 - 792000 700000 - 800000 700000 - 808000 800000 - 816000 800000 - 824000 800000 - 832000 800000 - 840000 800000 - 848000 800000 - 856000 800000 - 864000 800000 - 872000 800000 - 880000 800000 - 888000 800000 - 896000 800000 - 900000 800000 - 904000 800000 - 912000 800000 - 920000 800000 - 928000 800000 - 936000 800000 - 944000 800000 - 952000 800000 - 960000 800000 - 968000 800000 - 976000 800000 - 984000 800000 - 992000 800000 - 1000000 800000 - 1008000 800000 - 1020000 800000 - 1032000 800000 - 1044000 800000 - 1056000 800000 - 1068000 800000 - 1080000 800000 - 1092000 800000 - 1104000 800000 - 1116000 800000 - 1128000 800000 - 1140000 800000 - 1152000 800000 - 1164000 800000 - 1176000 800000 - 1188000 800000 - 1200000 800000 - 1212000 800000 - 1224000 800000 - 1236000 800000 - 1248000 800000 - 1260000 800000 - 1272000 800000 - 1284000 800000 - 1296000 800000 - 1308000 800000 - 1320000 800000 - 1332000 800000 - 1344000 800000 - 1356000 800000 - 1368000 800000 - 1380000 800000 - 1392000 800000 - 1404000 800000 - 1416000 800000 - 1428000 800000 - 1440000 800000 - 1452000 800000 - 1464000 800000 - 1476000 800000 - 1488000 800000 - 1500000 800000 - 1512000 1000000 - 1536000 1000000 - 1560000 1000000 - 1584000 1000000 - 1608000 1000000 - 1632000 1000000 - 1656000 1000000 - 1680000 1000000 - 1704000 1000000 - 1728000 1000000 - 1752000 1000000 - 1776000 1000000 - 1800000 1000000 - 1824000 1000000 - 1848000 1000000 - 1872000 1100000 - 1896000 1100000 - 1920000 1100000 - 1944000 1100000 - 1968000 1100000 - 1992000 1100000 - 2016000 1100000 - 2040000 1100000 - 2064000 1100000 - 2088000 1100000 - 2112000 1100000 - 2136000 1100000 - 2160000 1100000 - 2184000 1100000 - 2208000 1100000 - 2232000 1100000 - 2256000 1100000 - 2280000 1100000 - 2304000 1100000 - 2328000 1100000 - 2352000 1100000 - 2376000 1100000 - 2400000 1100000 - 2424000 1100000 - 2448000 1100000 - 2472000 1100000 - 2496000 1100000 - 2520000 1100000 - 2544000 1100000 - 2568000 1100000 - 2592000 1100000 - 2616000 1100000 - >; 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- dvfs_sv; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val-wcn-powergate.dts b/arch/riscv/boot/dts/thead/light-a-val-wcn-powergate.dts deleted file mode 100644 index 41fc6991e167..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-wcn-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-a-val-wcn.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-a-val-wcn.dts b/arch/riscv/boot/dts/thead/light-a-val-wcn.dts deleted file mode 100644 index 37619faff781..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val-wcn.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-a-val.dts" - -&sdhci1 { - status = "okay"; -}; - -&wcn_bt { - status = "okay"; -}; - -&wcn_wifi { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-a-val.dts b/arch/riscv/boot/dts/thead/light-a-val.dts deleted file mode 100644 index 65c3e46e66fa..000000000000 --- a/arch/riscv/boot/dts/thead/light-a-val.dts +++ /dev/null @@ -1,2691 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" - -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0"; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - lcd1_backlight: pwm-backlight@1 { - compatible = "pwm-backlight"; - pwms = <&pwm 1 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - audio-mbox-regmap = <&audio_mbox>; - status = "okay"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - light_rpmsg: light_rpmsg { - compatible = "light,rpmsg-bus", "simple-bus"; - memory-region = <&rpmsgmem>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - rpmsg: rpmsg{ - vdev-nums = <1>; - reg = <0x0 0x1E000000 0 0x10000>; - compatible = "light,light-rpmsg"; - status = "okay"; - }; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - sound-name-prefix = "DUMMY"; - status = "okay"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_a 3 1>; - enable-active-high; - regulator-always-on; - }; - - reg_tp1_pwr_en: regulator-tp1-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_a 6 1>; - enable-active-high; - regulator-always-on; - }; - - lcd0_1v8: regulator-lcd0-vdd18 { - compatible = "regulator-fixed"; - regulator-name = "lcd0_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pcal6408ahk_a 2 0>; - enable-active-high; - }; - - lcd0_5v7: regulator-lcd0-vspn57 { - compatible = "regulator-fixed"; - regulator-name = "lcd0_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&pcal6408ahk_a 4 0>; - enable-active-high; - }; - - lcd1_1v8: regulator-lcd1-vdd18 { - compatible = "regulator-fixed"; - regulator-name = "lcd1_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pcal6408ahk_a 5 0>; - enable-active-high; - }; - - lcd1_5v7: regulator-lcd1-vspn57 { - compatible = "regulator-fixed"; - regulator-name = "lcd1_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&pcal6408ahk_a 7 0>; - enable-active-high; - }; - - soc_aud_adc_3v3_en_reg: soc-aud-adc-3v3-en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_adc_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pcal6408ahk_b 1 1>; - enable-active-high; - }; - - soc_aud_dac_3v3_en_reg: soc-aud-dac-3v3-en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_dac_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pcal6408ahk_b 2 1>; - enable-active-high; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 26 0>; - WIFI,reset_n = <&gpio2_porta 28 0>; - status = "disabled"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "disabled"; - }; - - gpio_keys: gpio_keys{ - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - status = "disabled"; - key-volumedown { - label = "Volume Down Key"; - wakeup-source; - linux,code = ; - debounce-interval = <2>; - gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>; - }; - key-volumeup { - label = "Volume Up Key"; - wakeup-source; - linux,code = ; - debounce-interval = <2>; - gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>; - }; - }; - - aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - soc_vext_2v8_reg: soc_vext_2v8 { - regulator-name = "soc_vext_2v8"; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - }; - soc_avdd28_rgb_reg: soc_avdd28_rgb { - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3475000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1675000>; - regulator-boot-on; - regulator-always-on; - }; - soc_avdd25_ir_reg: soc_avdd25_ir { - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3475000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dovdd18_ir_reg: soc_dovdd18_ir { - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd12_ir_reg: soc_dvdd12_ir { - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1675000>; - regulator-boot-on; - regulator-always-on; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; -}; - -&cmamem { - alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000] -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@0f800000 { - reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ - 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ - no-map; - }; - facelib_mem: memory@22000000 { - reg = <0x0 0x22000000 0x0 0x10000000>; - no-map; - }; - audio_mem: memory@32000000 { - reg = <0x0 0x32000000 0x0 0x6400000>; - no-map; - }; - rpmsgmem: memory@1E000000 { - reg = <0x0 0x1E000000 0x0 0x10000>; - no-map; - }; -}; - -&adc { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa6>, - <&pinctrl_audiopa7>, - <&pinctrl_audio_i2c0>; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_dac_3v3_en_reg>; - DVDD-supply = <&soc_dvdd18_aon_reg>; - PVDD-supply = <&soc_dvdd18_aon_reg>; - mclk-sclk-ratio = <4>; - }; - - es7210_audio_codec_adc0: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - status = "disabled"; - work-mode = "ES7210_NORMAL_I2S"; - channels-max = <2>; - mclk-sclk-ratio = <4>; - sound-name-prefix = "ES7210_ADC0"; - MVDD-supply = <&soc_aud_adc_3v3_en_reg>; - AVDD-supply = <&soc_aud_adc_3v3_en_reg>; - DVDD-supply = <&soc_dvdd18_aon_reg>; - PVDD-supply = <&soc_dvdd18_aon_reg>; - }; - - es7210_audio_codec_adc1: es7210@41 { - #sound-dai-cells = <0>; - compatible = "MicArray_1"; - reg = <0x41>; - status = "disabled"; - work-mode = "ES7210_NORMAL_I2S"; - channels-max = <2>; - mclk-sclk-ratio = <4>; - sound-name-prefix = "ES7210_ADC1"; - MVDD-supply = <&soc_aud_adc_3v3_en_reg>; - AVDD-supply = <&soc_aud_adc_3v3_en_reg>; - DVDD-supply = <&soc_dvdd18_aon_reg>; - PVDD-supply = <&soc_dvdd18_aon_reg>; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - reset-gpio = <&pcal6408ahk_b 3 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&audio_i2c1 { - clock-frequency = <100000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa13>, - <&pinctrl_audiopa16>, - <&pinctrl_audio_i2c1>; - - pcal6408ahk_b: gpio@20 { - compatible = "nxp,pcal9554b"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - touch1@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <12 0>; - irq-gpios = <&gpio1_porta 12 0>; - reset-gpios = <&gpio1_porta 11 0>; - AVDD28-supply = <®_tp1_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - - spi_norflash@0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - status = "disable"; - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <5>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - rx-sample-dly = <5>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <66000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi2"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac1>; - status = "okay"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdio0>; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "disabled"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x234 - FM_UART0_RXD 0x0 0x234 - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_i2c2: i2c2grp { - thead,pins = < - FM_I2C2_SCL 0x0 0x204 - FM_I2C2_SDA 0x0 0x204 - >; - }; - - pinctrl_i2c3: i2c3grp { - thead,pins = < - FM_I2C3_SCL 0x0 0x204 - FM_I2C3_SDA 0x0 0x204 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_gmac1: gmac1grp { - thead,pins = < - FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */ - FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */ - FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */ - FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */ - FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */ - FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */ - FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */ - FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */ - FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */ - FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */ - FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */ - FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */ - >; - }; - - pinctrl_sdio0: sdio0grp { - thead,pins = < - FM_SDIO0_DETN 0x0 0x208 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - FM_GPIO3_3 0x1 0x208 /* pwm1 */ - >; - }; - - pinctrl_hdmi: hdmigrp { - thead,pins = < - FM_HDMI_SCL 0x0 0x208 - FM_HDMI_SDA 0x0 0x208 - FM_HDMI_CEC 0x0 0x208 - >; - }; - - pinctrl_gmac0: gmac0grp { - thead,pins = < - FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */ - FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */ - FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */ - FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */ - FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */ - FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */ - FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */ - FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */ - FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */ - FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */ - FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */ - FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */ - FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */ - FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */ - FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */ - FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - pinctrl_i2c0: i2c0grp { - thead,pins = < - FM_I2C0_SCL 0x0 0x204 - FM_I2C0_SDA 0x0 0x204 - >; - }; - - pinctrl_i2c1: i2c1grp { - thead,pins = < - FM_I2C1_SCL 0x0 0x204 - FM_I2C1_SDA 0x0 0x204 - >; - }; - - pinctrl_uart1: uart1grp { - thead,pins = < - FM_UART1_TXD 0x0 0x234 - FM_UART1_RXD 0x0 0x234 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x208 - FM_UART4_RXD 0x0 0x208 - FM_UART4_CTSN 0x0 0x208 - FM_UART4_RTSN 0x0 0x208 - >; - }; - - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x1 0x202 - FM_UART3_RXD 0x1 0x202 - FM_GPIO0_20 0x2 0x202 /* UART3_IR_OUT */ - FM_GPIO0_21 0x2 0x202 /* UART3_IR_IN */ - >; - }; - - pinctrl_i2c4: i2c4grp { - thead,pins = < - FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */ - FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */ - >; - }; - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa0: audiopa0 { - thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa1: audiopa1 { - thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa2: audiopa2 { - thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa3: audiopa3 { - thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa4: audiopa4 { - thead,pins = < FM_AUDIO_PA4 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa5: audiopa5 { - thead,pins = < FM_AUDIO_PA5 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa6: audiopa6 { - thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa7: audiopa7 { - thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa8: audiopa8 { - thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa9: audiopa9 { - thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa10: audiopa10 { - thead,pins = < FM_AUDIO_PA10 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa11: audiopa11 { - thead,pins = < FM_AUDIO_PA11 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa12: audiopa12 { - thead,pins = < FM_AUDIO_PA12 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa13: audiopa13 { - thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa14: audiopa14 { - thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa15: audiopa15 { - thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa16: audiopa16 { - thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa17: audiopa17 { - thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_CPU_JTG_TDI 0x3 0x238 - FM_CPU_JTG_TDO 0x3 0x238 - >; - }; - }; -}; - -&padctrl_audiosys { - - status = "okay"; - - light-audio-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audio_i2c0: audio_i2c0_grp { - thead,pins = < - FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004 - FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004 - >; - }; - pinctrl_audio_i2c1: audio_i2c1_grp { - thead,pins = < - FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_1 0x004 - FM_AUDIO_IO_PA16 LIGHT_PIN_FUNC_3 0x004 - >; - }; - pinctrl_audio_i2s0: audio_i2s0_grp { - thead,pins = < - FM_AUDIO_IO_PA9 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA10 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA11 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA12 LIGHT_PIN_FUNC_0 0x008 - >; - }; - pinctrl_audio_i2s1: audio_i2s1_grp { - thead,pins = < - FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 - >; - }; - pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp { - thead,pins = < - FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008 - FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008 - FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd0: audio_i2s_8ch_sd0_grp { - thead,pins = < - FM_AUDIO_IO_PA4 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd1: audio_i2s_8ch_sd1_grp { - thead,pins = < - FM_AUDIO_IO_PA5 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp { - thead,pins = < - FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp { - thead,pins = < - FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_tdm: audio_tdm_grp { - thead,pins = < - FM_AUDIO_IO_PA27 LIGHT_PIN_FUNC_1 0x007 - FM_AUDIO_IO_PA28 LIGHT_PIN_FUNC_1 0x007 - FM_AUDIO_IO_PA29 LIGHT_PIN_FUNC_1 0x000 - >; - }; - pinctrl_audio_spdif0: audio_spdif0_grp { - thead,pins = < - FM_AUDIO_IO_PA21 LIGHT_PIN_FUNC_1 0x000 - FM_AUDIO_IO_PA22 LIGHT_PIN_FUNC_1 0x007 - >; - }; - pinctrl_audio_spdif1: audio_spdif1_grp { - thead,pins = < - FM_AUDIO_IO_PA23 LIGHT_PIN_FUNC_1 0x007 - FM_AUDIO_IO_PA24 LIGHT_PIN_FUNC_1 0x000 - >; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; - - pcal6408ahk_a: gpio@20 { - compatible = "nxp,pcal9554b"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1{ - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - floodlight_en_pin = <&gpio1_porta 25 0>; - //projection_i2c_bus = /bits/ 8 <2>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_voltage_uV = <1800000 1200000 2800000>; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor1 { - sensor_name = "OV5693"; - i2c_bus = /bits/ 8 <3>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "disabled"; -}; - - -&vvcam_sensor1 { - sensor_name = "OV5693"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_voltage_uV = <1800000 1200000 2800000>; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x36>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor2 { - sensor_name = "GC5035"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor3 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - status = "okay"; -}; - -&vvcam_sensor4 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x31>; - sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&vvcam_sensor5 { - sensor_name = "OV12870"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_voltage_uV = <1800000 1200000 2800000>; - sensor_regulator_timing_us = <100 50 0>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_addr = /bits/ 8 <0x10>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor6 { - sensor_name = "GC02M1B"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_voltage_uV = <1800000 1675000 2800000>; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor7 { - sensor_name = "IMX334"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x1a>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&video0{ - status = "okay"; - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - - -&video1{ - status = "okay"; - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video2{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - sensor2 { - subdev_name = "vivcam"; - idx = <7>; //imx334 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_3840x2180_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <3840>; - max_height = <2180>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video6{ - status = "okay"; - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video7{ - status = "okay"; - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&video8{ - status = "okay"; - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video9{ - status = "okay"; - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - - -&video10{ - status = "okay"; - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - }; -}; - -&video11{ - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video12{ // TUNINGTOOL - status = "okay"; - channel0 { // CSI2 - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - }; -}; - -&video15{ - status = "okay"; - vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //<0>=vivcam0 :2310 - csi_idx = <0>; //<0>=CSI2 - flash_led_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <7>; //imx334 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_3840x2180_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_DDR"; - }; - }; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa9>, - <&pinctrl_audiopa10>, - <&pinctrl_audiopa11>, - <&pinctrl_audiopa12>, - <&pinctrl_audio_i2s0>; -}; - -&i2s_8ch_sd0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa4>, - <&pinctrl_audio_i2s_8ch_sd0>; -}; - -&i2s_8ch_sd1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa5>, - <&pinctrl_audio_i2s_8ch_sd1>; -}; - -&i2s_8ch_sd2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa0>, - <&pinctrl_audio_i2s_8ch_sd2>, - <&pinctrl_audiopa2>, - <&pinctrl_audiopa3>, - <&pinctrl_audiopa8>, - <&pinctrl_audio_i2s_8ch_bus>; -}; - -&i2s_8ch_sd3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa1>, - <&pinctrl_audio_i2s_8ch_sd3>; -}; - - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; - -&hdmi_tx { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; -}; diff --git a/arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts b/arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts deleted file mode 100644 index 1bf6121a78dd..000000000000 --- a/arch/riscv/boot/dts/thead/light-ant-discrete-crash.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-crash.dts" - -&aon { - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; - c910_2: cpu@2 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; - c910_3: cpu@3 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-ant-discrete.dts b/arch/riscv/boot/dts/thead/light-ant-discrete.dts deleted file mode 100644 index 79f012311eaa..000000000000 --- a/arch/riscv/boot/dts/thead/light-ant-discrete.dts +++ /dev/null @@ -1,2213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x7fe00000>; - }; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - status = "okay"; - sound-name-prefix = "DUMMY"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 12 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 22 0>; - status = "okay"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio1_porta 19 0x1>; - }; - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio2_porta 25 0x1>; - }; - }; - - aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_aud_3v3_en_reg: soc_aud_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&ao_gpio_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_aud_1v8_en_reg: soc_aud_1v8_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_1v8_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&ao_gpio_porta 8 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vdd_3v3_en_reg: soc_vdd_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0_porta 30 1>; - enable-active-high; - regulator-always-on; - }; - - soc_lcd0_bias_en_reg: soc_lcd0_bias_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&gpio1_porta 10 1>; - enable-active-high; - }; - - soc_vdd18_lcd0_en_reg: soc_lcd0_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 9 1>; - enable-active-high; - }; - - soc_vdd5v_se_en_reg: soc_vdd5v_se_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd5v_se_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_wcn33_en_reg: soc_wcn33_en { - compatible = "regulator-fixed"; - regulator-name = "soc_wcn33_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 29 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vbus_en_reg: soc_vbus_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vbus_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 28 1>; - enable-active-high; - regulator-always-on; - }; - - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 15 1>; - enable-active-high; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 14 1>; - enable-active-high; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&gpio0_porta 28 1>; - enable-active-high; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 29 1>; - enable-active-high; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; - -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1c000000 { - reg = <0x0 0x1c000000 0 0x2000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; -}; - -&adc { - vref-supply = <®_vref_1v8>; - #io-channel-cells = <1>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; - -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - sound-name-prefix = "ES7210"; - status = "disabled"; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - reset-gpio = <&ao_gpio4_porta 9 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; - - spidev@0 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; - -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "disabled"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_CLK_OUT_2 0x3 0x208 - >; - }; - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - - }; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1 { - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <0>; - floodlight_en_pin = <&gpio1_porta 26 0>; - projection_i2c_bus = /bits/ 8 <1>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - io-channels = <&adc 2>; - io-channel-names = "projection_adc"; - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor1 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x31>; - sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&vvcam_sensor2 { - sensor_name = "GC5035"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor3 { - sensor_name = "GC02M1B"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&video0{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - - -&video1{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video2{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video6{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; // vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx= <0>; - path_type = "SENSOR_1080X1280_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx= <0>; - path_type = "SENSOR_1080X1280_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - -}; - -&video7{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&video8{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video9{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx= <0>; - path_type = "SENSOR_1080X1280_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - - -&video10{ // TUNINGTOOL - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx= <1>; - path_type = "SENSOR_1920X1080_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - }; -}; - -&video11{ - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx= <0>; - path_type = "SENSOR_1080X1280_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video12{ // TUNINGTOOL - channel0 { // CSI2 - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - }; -}; - - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>; - vspn5v7-supply = <&soc_lcd0_bias_en_reg>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; - c910_2: cpu@2 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; - c910_3: cpu@3 { - operating-points = < - /* kHz uV */ - 300000 720000 - 800000 720000 - 1500000 820000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 770000 - 800000 820000 - 1500000 820000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-ant-ref-crash.dts b/arch/riscv/boot/dts/thead/light-ant-ref-crash.dts deleted file mode 100644 index 8987da77b1ba..000000000000 --- a/arch/riscv/boot/dts/thead/light-ant-ref-crash.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-crash.dts" - -&aon { - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-ant-ref-sec.dts b/arch/riscv/boot/dts/thead/light-ant-ref-sec.dts deleted file mode 100644 index 0cbed3d721f9..000000000000 --- a/arch/riscv/boot/dts/thead/light-ant-ref-sec.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-ant-ref.dts" - - - -&light_iopmp { - status = "disabled"; -}; - -&qspi1 { - status = "disabled"; -}; - - diff --git a/arch/riscv/boot/dts/thead/light-ant-ref.dts b/arch/riscv/boot/dts/thead/light-ant-ref.dts deleted file mode 100644 index 49321fbe55ba..000000000000 --- a/arch/riscv/boot/dts/thead/light-ant-ref.dts +++ /dev/null @@ -1,2407 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x7fe00000>; - }; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - status = "okay"; - sound-name-prefix = "DUMMY"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 12 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 22 0>; - status = "okay"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 29 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume_up - &pinctrl_volume_down>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio1_porta 19 0x1>; - }; - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio2_porta 25 0x1>; - }; - }; - - aon: aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_aud_3v3_en_reg: soc_aud_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&ao_gpio_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_aud_1v8_en_reg: soc_aud_1v8_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_1v8_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&ao_gpio_porta 8 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vdd_3v3_en_reg: soc_vdd_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0_porta 30 1>; - enable-active-high; - regulator-always-on; - }; - - soc_lcd0_bias_en_reg: soc_lcd0_bias_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&gpio1_porta 10 1>; - enable-active-high; - }; - - soc_vdd18_lcd0_en_reg: soc_lcd0_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 9 1>; - enable-active-high; - }; - - soc_vdd5v_se_en_reg: soc_vdd5v_se_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd5v_se_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_wcn33_en_reg: soc_wcn33_en { - compatible = "regulator-fixed"; - regulator-name = "soc_wcn33_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 29 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vbus_en_reg: soc_vbus_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vbus_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 28 1>; - enable-active-high; - regulator-always-on; - }; - - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 15 1>; - enable-active-high; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 14 1>; - enable-active-high; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&gpio0_porta 28 1>; - enable-active-high; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 29 1>; - enable-active-high; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; - -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1c000000 { - reg = <0x0 0x1c000000 0 0x2000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; - -}; - -&adc { - vref-supply = <®_vref_1v8>; - #io-channel-cells = <1>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; - -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - sound-name-prefix = "ES7210"; - status = "disabled"; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - reset-gpio = <&ao_gpio4_porta 9 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; - - spidev@0 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; - -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "disabled"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - >; - }; - - pinctrl_volume_up: volume_up_grp { - thead,pins = < - FM_GPIO2_25 0x0 0x238 - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - pinctrl_volume_down: volume_down_grp { - thead,pins = < - FM_CLK_OUT_2 0x3 0x238 - >; - }; - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - - }; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1 { - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - floodlight_en_pin = <&gpio1_porta 26 0>; - projection_i2c_bus = /bits/ 8 <1>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - io-channels = <&adc 2>; - io-channel-names = "projection_adc"; - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor1 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x31>; - sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&vvcam_sensor2 { - sensor_name = "GC5035"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_voltage_uV = <1800000 1200000 2800000>; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor3 { - sensor_name = "GC02M1B"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_voltage_uV = <1800000 1800000 2800000>; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&video0{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - - -&video1{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video2{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video6{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; // vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - -}; - -&video7{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&video8{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_DSP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video9{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - - -&video10{ // TUNINGTOOL - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - }; -}; - -&video11{ - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video12{ // TUNINGTOOL - channel0 { // CSI2 - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - skip_init = <1>; - }; - dma { - path_type = "VIPRE_CSI1_ISP0"; - }; - }; - -}; - -&video13{ - status = "okay"; - //vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_MCM_WR0"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video14{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_MCM_WR0"; - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video15{ - status = "okay"; - //vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //<0>=vivcam0 :2310 - csi_idx = <1>; //<1>=CSI2_B - flash_led_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_DDR"; - }; - }; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>; - vspn5v7-supply = <&soc_lcd0_bias_en_reg>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - max_width = /bits/ 16 <1280>; - max_height = /bits/ 16 <720>; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-audio-hdmi.dts b/arch/riscv/boot/dts/thead/light-b-audio-hdmi.dts deleted file mode 100644 index bacc501154e1..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-audio-hdmi.dts +++ /dev/null @@ -1,2525 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x7fe00000>; - }; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - audio-mbox-regmap = <&audio_mbox>; - status = "okay"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - light_rpmsg: light_rpmsg { - compatible = "light,rpmsg-bus", "simple-bus"; - memory-region = <&rpmsgmem>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - rpmsg: rpmsg{ - vdev-nums = <1>; - reg = <0x0 0x1E000000 0 0x10000>; - compatible = "light,light-rpmsg"; - status = "okay"; - }; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - status = "okay"; - sound-name-prefix = "DUMMY"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 12 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 24 0>; - status = "okay"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 25 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - wakeup-source; - linux,code = ; - debounce-interval = <1>; - gpios = <&ao_gpio_porta 11 0x1>; - }; - key-volumeup { - label = "Volume Up Key"; - wakeup-source; - linux,code = ; - debounce-interval = <1>; - gpios = <&ao_gpio_porta 10 0x1>; - }; - }; - - aon: aon@0 { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_aud_3v3_en_reg: soc_aud_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_3v3_en>; - gpio = <&ao_gpio_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_aud_1v8_en_reg: soc_aud_1v8_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_1v8_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_1v8_en>; - gpio = <&ao_gpio_porta 8 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vdd_3v3_en_reg: soc_vdd_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0_porta 30 1>; - enable-active-high; - regulator-always-on; - }; - - soc_lcd0_bias_en_reg: soc_lcd0_bias_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&gpio1_porta 10 1>; - enable-active-high; - }; - - soc_vdd5v_se_en_reg: soc_vdd5v_se_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd5v_se_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_wcn33_en_reg: soc_wcn33_en { - compatible = "regulator-fixed"; - regulator-name = "soc_wcn33_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 29 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vbus_en_reg: soc_vbus_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vbus_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 28 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2_porta 31 1>; - enable-active-high; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio3_porta 0 1>; - enable-active-high; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio2_porta 30 1>; - enable-active-high; - }; - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 15 1>; - enable-active-high; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 14 1>; - enable-active-high; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&gpio0_porta 28 1>; - enable-active-high; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio0_porta 27 1>; - enable-active-high; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 29 1>; - enable-active-high; - }; - - aon_reg_ricoh: light-ricoh-reg { - compatible = "thead,light-ricoh-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ap_reg: soc_dvdd08_ap { - regulator-name = "soc_dvdd08_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_lcd0_en_reg: soc_lcd0_en { - regulator-name = "soc_lcd0_en"; - }; - soc_vext_1v8_reg: soc_vext_1v8 { - regulator-name = "soc_vext_1v8"; - regulator-boot-on; - regulator-always-on; - }; - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; - -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; - - audio_mem: memory@32000000 { - reg = <0x0 0x32000000 0x0 0x6400000>; - no-map; - }; - rpmsgmem: memory@1E000000 { - reg = <0x0 0x1E000000 0x0 0x10000>; - no-map; - }; - -}; - -&adc { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; - -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa6>, - <&pinctrl_audiopa7>, - <&pinctrl_audio_i2c0>; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - mclk-sclk-ratio = <4>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - work-mode = "ES7210_NORMAL_I2S"; - channels-max = <2>; - mclk-sclk-ratio = <4>; - sound-name-prefix = "ES7210_ADC0"; - MVDD-supply = <&soc_aud_3v3_en_reg>; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - pingctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_pa_rst0>; - reset-gpio = <&ao_gpio4_porta 9 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; - - spidev@0 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "disabled"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa0: audiopa0 { - thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa1: audiopa1 { - thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa2: audiopa2 { - thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa3: audiopa3 { - thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa6: audiopa6 { - thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa7: audiopa7 { - thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa8: audiopa8 { - thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audio_pa_rst0: audio_pa_rst0 { - thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >; - }; - pinctrl_audiopa13: audiopa13 { - thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa14: audiopa14 { - thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa15: audiopa15 { - thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa17: audiopa17 { - thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audio_3v3_en: audio_3v3_en { - thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >; - }; - pinctrl_audio_1v8_en: audio_1v8_en { - thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_AOGPIO_11 0x0 0x238 - FM_AOGPIO_10 0x3 0x238 - >; - }; - }; -}; - -&padctrl_audiosys { - - status = "okay"; - - light-audio-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audio_i2c0: audio_i2c0_grp { - thead,pins = < - FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004 - FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004 - >; - }; - pinctrl_audio_i2s1: audio_i2s1_grp { - thead,pins = < - FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 - >; - }; - pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp { - thead,pins = < - FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008 - FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008 - FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp { - thead,pins = < - FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp { - thead,pins = < - FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008 - >; - }; - }; -}; - - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1 { - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - floodlight_en_pin = <&gpio1_porta 25 0>; - //projection_i2c_bus = /bits/ 8 <2>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -/* -&vvcam_sensor0 { - sensor_name = "IMX334"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x1a>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; -*/ - -&vvcam_sensor1 { - sensor_name = "OV5693"; - i2c_bus = /bits/ 8 <3>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "disabled"; -}; - -&vvcam_sensor2 { - sensor_name = "GC5035"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor3 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - status = "okay"; -}; - -&vvcam_sensor4 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x31>; - sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&vvcam_sensor5 { - sensor_name = "OV12870"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <100 50 0>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_addr = /bits/ 8 <0x10>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor6 { - sensor_name = "GC02M1B"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&video0{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - - -&video1{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video2{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video6{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - -}; - -&video7{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&video8{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video9{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - - -&video10{ // TUNINGTOOL - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - }; -}; - -&video11{ - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video12{ // TUNINGTOOL - channel0 { // CSI2 - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - }; -}; - -&video14{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_MCM_WR0"; - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video15{ - status = "okay"; - //vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //<0>=vivcam0 :2310 - csi_idx = <0>; //<0>=CSI2 - flash_led_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_DDR"; - }; - }; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa13>, - <&pinctrl_audiopa14>, - <&pinctrl_audiopa15>, - <&pinctrl_audiopa17>, - <&pinctrl_audio_i2s1>; -}; - -&i2s_8ch_sd2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa0>, - <&pinctrl_audio_i2s_8ch_sd2>, - <&pinctrl_audiopa2>, - <&pinctrl_audiopa3>, - <&pinctrl_audiopa8>, - <&pinctrl_audio_i2s_8ch_bus>; -}; - -&i2s_8ch_sd3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa1>, - <&pinctrl_audio_i2s_8ch_sd3>; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-power.dts b/arch/riscv/boot/dts/thead/light-b-power.dts deleted file mode 100644 index eeaea596b3fd..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-power.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-b-product.dts" - -&aon { - /delete-node/light-ricoh-reg; - - soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd18_lcd0_bk_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 9 1>; - enable-active-high; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; -#if 0 - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - }; -#endif - - }; -}; - - -&panel0 { - - vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-crash.dts b/arch/riscv/boot/dts/thead/light-b-product-crash.dts deleted file mode 100644 index 401a76a7bd8d..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-crash.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-crash.dts" - -&aon { - aon_reg_ricoh: light-ricoh-reg { - compatible = "thead,light-ricoh-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-ddr1G-powergate.dts b/arch/riscv/boot/dts/thead/light-b-product-ddr1G-powergate.dts deleted file mode 100644 index 7bee2c7f43ba..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-ddr1G-powergate.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-b-product-ddr1G.dts" -#include "light-powergate.dts" - -&soc_vdd18_lcd0_en_reg { - /delete-property/regulator-always-on; -}; -&soc_lcd0_bias_en_reg { - /delete-property/regulator-always-on; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts b/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts deleted file mode 100644 index e4b91e7d9e3c..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-ddr1G.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-b-product.dts" - -/ { - model = "T-HEAD Light-B VAL configuration for 1GB DDR board"; - compatible = "thead,light-val", "thead,light-val-ddr1G", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x3fe00000>; - }; -}; - -&cmamem { - size = <0 0x8c00000>; // 140MB by default - alloc-ranges = <0 0x02000000 0 0x0cc000000>; // [0x0600_0000 ~ 0x0EC0_0000] -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-miniapp-hdmi.dts b/arch/riscv/boot/dts/thead/light-b-product-miniapp-hdmi.dts deleted file mode 100644 index 0c056ad2f9d5..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-miniapp-hdmi.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-b-product.dts" - -&dpu_enc0 { - status = "disabled"; -}; - -&dsi0 { - status = "disabled"; -}; - -&dhost_0 { - status = "disabled"; -}; - -&wcn_bt { - status = "okay"; -}; - -&wcn_wifi { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-powergate.dts b/arch/riscv/boot/dts/thead/light-b-product-powergate.dts deleted file mode 100644 index b205d16b9124..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-powergate.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-b-product.dts" -#include "light-powergate.dts" - - -&soc_vdd18_lcd0_en_reg { - /delete-property/regulator-always-on; -}; - -&soc_lcd0_bias_en_reg { - /delete-property/regulator-always-on; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product-sec-powergate.dts b/arch/riscv/boot/dts/thead/light-b-product-sec-powergate.dts deleted file mode 100644 index c26127637a16..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-sec-powergate.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-b-product-sec.dts" -#include "light-powergate.dts" - diff --git a/arch/riscv/boot/dts/thead/light-b-product-sec.dts b/arch/riscv/boot/dts/thead/light-b-product-sec.dts deleted file mode 100644 index d4862ca6a9cd..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product-sec.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-b-audio-hdmi.dts" - - - -&light_iopmp { - status = "disabled"; -}; - -&qspi1 { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-product.dts b/arch/riscv/boot/dts/thead/light-b-product.dts deleted file mode 100644 index 2c74164e9f83..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-product.dts +++ /dev/null @@ -1,2726 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x7fe00000>; - }; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - audio-mbox-regmap = <&audio_mbox>; - status = "okay"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - light_rpmsg: light_rpmsg { - compatible = "light,rpmsg-bus", "simple-bus"; - memory-region = <&rpmsgmem>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - rpmsg: rpmsg{ - vdev-nums = <1>; - reg = <0x0 0x1E000000 0 0x10000>; - compatible = "light,light-rpmsg"; - status = "okay"; - }; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - status = "okay"; - sound-name-prefix = "DUMMY"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 12 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi>; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 24 0>; - status = "okay"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt>; - BT,power_gpio = <&gpio2_porta 25 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - wakeup-source; - linux,code = ; - debounce-interval = <1>; - gpios = <&ao_gpio_porta 11 0x1>; - }; - key-volumeup { - label = "Volume Up Key"; - wakeup-source; - linux,code = ; - debounce-interval = <1>; - gpios = <&ao_gpio_porta 10 0x1>; - }; - }; - - aon: aon@0 { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_aud_3v3_en_reg: soc_aud_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_3v3_en>; - gpio = <&ao_gpio_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_aud_1v8_en_reg: soc_aud_1v8_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_1v8_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_1v8_en>; - gpio = <&ao_gpio_porta 8 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vdd_3v3_en_reg: soc_vdd_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0_porta 30 1>; - enable-active-high; - regulator-always-on; - }; - - soc_lcd0_bias_en_reg: soc_lcd0_bias_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_bias_en"; - regulator-min-microvolt = <5700000>; - regulator-max-microvolt = <5700000>; - gpio = <&gpio1_porta 10 1>; - enable-active-high; - }; - - soc_vdd5v_se_en_reg: soc_vdd5v_se_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd5v_se_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_wcn33_en_reg: soc_wcn33_en { - compatible = "regulator-fixed"; - regulator-name = "soc_wcn33_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 29 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vbus_en_reg: soc_vbus_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vbus_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 28 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio2_porta 31 1>; - enable-active-high; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio3_porta 0 1>; - enable-active-high; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio2_porta 30 1>; - enable-active-high; - }; - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 15 1>; - enable-active-high; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 13 1>; - enable-active-high; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 14 1>; - enable-active-high; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&gpio0_porta 28 1>; - enable-active-high; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio0_porta 27 1>; - enable-active-high; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 29 1>; - enable-active-high; - }; - - aon_reg_ricoh: light-ricoh-reg { - compatible = "thead,light-ricoh-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ap_reg: soc_dvdd08_ap { - regulator-name = "soc_dvdd08_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_lcd0_en_reg: soc_lcd0_en { - regulator-name = "soc_lcd0_en"; - }; - soc_vext_1v8_reg: soc_vext_1v8 { - regulator-name = "soc_vext_1v8"; - regulator-boot-on; - regulator-always-on; - }; - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; - -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; - audio_mem: memory@32000000 { - reg = <0x0 0x32000000 0x0 0x6400000>; - no-map; - }; - rpmsgmem: memory@1E000000 { - reg = <0x0 0x1E000000 0x0 0x10000>; - no-map; - }; - -}; - -&adc { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; - -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa6>, - <&pinctrl_audiopa7>, - <&pinctrl_audio_i2c0>; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - mclk-sclk-ratio = <4>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - work-mode = "ES7210_NORMAL_I2S"; - channels-max = <2>; - mclk-sclk-ratio = <4>; - sound-name-prefix = "ES7210_ADC0"; - MVDD-supply = <&soc_aud_3v3_en_reg>; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - pingctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_pa_rst0>; - reset-gpio = <&ao_gpio4_porta 9 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; - - spidev@0 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "disabled"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdio0>; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x234 - FM_UART0_RXD 0x0 0x234 - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_i2c2: i2c2grp { - thead,pins = < - FM_I2C2_SCL 0x0 0x204 - FM_I2C2_SDA 0x0 0x204 - >; - }; - - pinctrl_i2c3: i2c3grp { - thead,pins = < - FM_I2C3_SCL 0x0 0x204 - FM_I2C3_SDA 0x0 0x204 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_wifi: wifi_grp { - thead,pins = < - FM_GPIO2_22 0x0 0x202 - FM_GPIO2_24 0x0 0x202 - >; - }; - - pinctrl_bt: bt_grp { - thead,pins = < - FM_GPIO2_23 0x0 0x202 - FM_GPIO2_25 0x0 0x202 - >; - }; - - pinctrl_sdio0: sdio0grp { - thead,pins = < - FM_SDIO0_DETN 0x0 0x208 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x20f /* pwm0 */ - >; - }; - - pinctrl_hdmi: hdmigrp { - thead,pins = < - FM_HDMI_SCL 0x0 0x208 - FM_HDMI_SDA 0x0 0x208 - FM_HDMI_CEC 0x0 0x208 - >; - }; - - pinctrl_gmac0: gmac0grp { - thead,pins = < - FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */ - FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */ - FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */ - FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */ - FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */ - FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */ - FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */ - FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */ - FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */ - FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */ - FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */ - FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */ - FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */ - FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */ - FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */ - FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - pinctrl_i2c0: i2c0grp { - thead,pins = < - FM_I2C0_SCL 0x0 0x204 - FM_I2C0_SDA 0x0 0x204 - >; - }; - - pinctrl_i2c1: i2c1grp { - thead,pins = < - FM_I2C1_SCL 0x0 0x204 - FM_I2C1_SDA 0x0 0x204 - >; - }; - - pinctrl_uart1: uart1grp { - thead,pins = < - FM_UART1_TXD 0x0 0x234 - FM_UART1_RXD 0x0 0x234 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x208 - FM_UART4_RXD 0x0 0x208 - FM_UART4_CTSN 0x0 0x208 - FM_UART4_RTSN 0x0 0x208 - >; - }; - - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x1 0x202 - FM_UART3_RXD 0x1 0x202 - >; - }; - - pinctrl_i2c4: i2c4grp { - thead,pins = < - FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */ - FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */ - >; - }; - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa0: audiopa0 { - thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa1: audiopa1 { - thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa2: audiopa2 { - thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa3: audiopa3 { - thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa6: audiopa6 { - thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa7: audiopa7 { - thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa8: audiopa8 { - thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audio_pa_rst0: audio_pa_rst0 { - thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >; - }; - pinctrl_audiopa13: audiopa13 { - thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa14: audiopa14 { - thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa15: audiopa15 { - thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa17: audiopa17 { - thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audio_3v3_en: audio_3v3_en { - thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >; - }; - pinctrl_audio_1v8_en: audio_1v8_en { - thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_AOGPIO_11 0x0 0x238 - FM_AOGPIO_10 0x3 0x238 - >; - }; - }; -}; - -&padctrl_audiosys { - - status = "okay"; - - light-audio-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audio_i2c0: audio_i2c0_grp { - thead,pins = < - FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004 - FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004 - >; - }; - pinctrl_audio_i2s1: audio_i2s1_grp { - thead,pins = < - FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 - >; - }; - pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp { - thead,pins = < - FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008 - FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008 - FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp { - thead,pins = < - FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008 - >; - }; - pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp { - thead,pins = < - FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008 - >; - }; - }; -}; - - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1 { - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_flash_led0{ - flash_led_name = "aw36413_aw36515"; - floodlight_i2c_bus = /bits/ 8 <2>; - floodlight_en_pin = <&gpio1_porta 25 0>; - //projection_i2c_bus = /bits/ 8 <2>; - flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor1 { - sensor_name = "OV5693"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_voltage_uV = <1800000 1200000 2800000>; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x36>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor2 { - sensor_name = "GC5035"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <100 50 0>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor3 { - sensor_name = "SC2310"; - sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&gpio1_porta 29 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; - DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; - AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; - i2c_bus = /bits/ 8 <4>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x30>; - status = "okay"; -}; - -&vvcam_sensor4 { - sensor_name = "SC132GS"; - sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x31>; - sensor_rst = <&gpio1_porta 24 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&vvcam_sensor5 { - sensor_name = "OV12870"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <100 50 0>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_addr = /bits/ 8 <0x10>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor6 { - sensor_name = "GC02M1B"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <1>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x37>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&vvcam_sensor7 { - sensor_name = "IMX334"; - sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; - sensor_regulator_timing_us = <70 50 20>; - sensor_rst = <&gpio1_porta 16 0>; - sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x1a>; - i2c_bus = /bits/ 8 <3>; - status = "okay"; -}; - -&video0{ - status = "okay"; - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - - -&video1{ - status = "okay"; - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video2{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video6{ - status = "okay"; - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - -}; - -&video7{ - status = "okay"; - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&video8{ - status = "okay"; - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video9{ - status = "okay"; - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - - -&video10{ // TUNINGTOOL - status = "okay"; - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : sc2310 - csi_idx = <1>; //<1>=CSI2X2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - }; -}; - -&video11{ - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video12{ // TUNINGTOOL - status = "okay"; - channel0 { // CSI2 - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - }; -}; - -&video14{ - status = "okay"; - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_MCM_WR0"; - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video15{ - status = "okay"; - //vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //<0>=vivcam0 :2310 - csi_idx = <0>; //<0>=CSI2 - flash_led_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_DDR"; - }; - }; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; - - panel0: panel0@0 { - compatible = "txd,dy800qwxpab"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&gpio1_porta 5 1>; /* active low */ - vdd1v8-supply = <&soc_vdd18_lcd0_en_reg>; - vspn5v7-supply = <&soc_lcd0_bias_en_reg>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,widgets = "Speaker", "Speaker"; - simple-audio-card,routing = - "Speaker", "AW87519 VO", - "AW87519 IN", "ES8156 ROUT"; - simple-audio-card,aux-devs = <&audio_aw87519_pa>; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa13>, - <&pinctrl_audiopa14>, - <&pinctrl_audiopa15>, - <&pinctrl_audiopa17>, - <&pinctrl_audio_i2s1>; -}; - -&i2s_8ch_sd2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa0>, - <&pinctrl_audio_i2s_8ch_sd2>, - <&pinctrl_audiopa2>, - <&pinctrl_audiopa3>, - <&pinctrl_audiopa8>, - <&pinctrl_audio_i2s_8ch_bus>; -}; - -&i2s_8ch_sd3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa1>, - <&pinctrl_audio_i2s_8ch_sd3>; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-b-ref.dts b/arch/riscv/boot/dts/thead/light-b-ref.dts deleted file mode 100644 index eeaea596b3fd..000000000000 --- a/arch/riscv/boot/dts/thead/light-b-ref.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-b-product.dts" - -&aon { - /delete-node/light-ricoh-reg; - - soc_vdd18_lcd0_bk_en_reg: soc_vdd18_lcd0_bk_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd18_lcd0_bk_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1_porta 9 1>; - enable-active-high; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; -#if 0 - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - }; -#endif - - }; -}; - - -&panel0 { - - vdd1v8-supply = <&soc_vdd18_lcd0_bk_en_reg>; -}; diff --git a/arch/riscv/boot/dts/thead/light-beagle-ref.dts b/arch/riscv/boot/dts/thead/light-beagle-ref.dts deleted file mode 100644 index c51a610a6a3b..000000000000 --- a/arch/riscv/boot/dts/thead/light-beagle-ref.dts +++ /dev/null @@ -1,2150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/ - * Copyright (C) 2022 Deepak Khatri - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - model = "BeagleBoard.org BeagleV-Ahead"; - compatible = "beagle,light", "thead,light-val", "thead,light"; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_default>; - - led-0 { - label = "beaglebone:green:usr0"; - gpios = <&ao_gpio4_porta 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - //function = LED_FUNCTION_HEARTBEAT; - }; - - led-1 { - label = "beaglebone:green:usr1"; - gpios = <&ao_gpio4_porta 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - //function = LED_FUNCTION_DISK_ACTIVITY; - }; - - led-2 { - label = "beaglebone:green:usr2"; - gpios = <&ao_gpio4_porta 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu"; - //function = LED_FUNCTION_CPU; - }; - - led-3 { - label = "beaglebone:green:usr3"; - gpios = <&ao_gpio4_porta 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - //function = LED_FUNCTION_DISK_ACTIVITY; - }; - - led-4 { - label = "beaglebone:green:usr4"; - gpios = <&ao_gpio4_porta 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "netdev"; - //function = LED_FUNCTION_WLAN; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <1>; - compatible = "linux,bt-sco"; - status = "okay"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - aon: aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_aud_3v3_en_reg: soc_aud_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&ao_gpio_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_aud_1v8_en_reg: soc_aud_1v8_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_1v8_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&ao_gpio_porta 8 1>; - enable-active-high; - regulator-always-on; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; - -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1c000000 { - reg = <0x0 0x1c000000 0 0x2000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; - -}; - -&adc { - vref-supply = <®_vref_1v8>; - #io-channel-cells = <1>; - status = "okay"; -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - sound-name-prefix = "ES7210"; - MVDD-supply = <&soc_aud_3v3_en_reg>; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - reset-gpio = <&ao_gpio4_porta 9 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - channel@1 { - compatible = "rohm,dh2228fv"; - //symlink = "bone/spi/0.1"; - #address-cells = <0x1>; - #size-cells = <0x0>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "disabled"; - - channel@0 { - compatible = "rohm,dh2228fv"; - //symlink = "bone/spi/1.1"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; - -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "disabled"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light_padctrl0: light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - >; - }; - - pinctrl_bt: btgrp { - thead,pins = < - FM_SDIO1_WPRTN 0x3 0x72 - FM_SDIO1_DETN 0x3 0x72 - FM_GPIO2_30 0x0 0x72 - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light_padctrl1: light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - }; -}; - -/* - PIN , 0x0, 0x1, 0x2, 0x3, 0x4, 0x5 - AUDIO_PA8, AUDIO_PA8, NULL, NULL, GPIO4_8, NULL, NULL - AUDIO_PA9, AUDIO_PA9, NULL, NULL, GPIO4_9, NULL, NULL - AUDIO_PA10, AUDIO_PA10, NULL, NULL, GPIO4_10, NULL, NULL - AUDIO_PA11, AUDIO_PA11, NULL, NULL, GPIO4_11, NULL, NULL - AUDIO_PA12, AUDIO_PA12, NULL, NULL, GPIO4_12, NULL, NULL -*/ - -#define FM_AUDIO_PA8_AUDIO_PA8 0x00 -#define FM_AUDIO_PA8_GPIO 0x03 - -&padctrl_aosys { - light_padctrl: light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - - led_pins_default: leds0_grp { - thead,pins = < - FM_AUDIO_PA8 0x3 0x72 - FM_AUDIO_PA9 0x3 0x72 - FM_AUDIO_PA10 0x3 0x72 - FM_AUDIO_PA11 0x3 0x72 - FM_AUDIO_PA12 0x3 0x72 - >; - }; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1 { - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&video0{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - - -&video1{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video2{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //vivcam0 sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - }; - dma { - path_type = "VIPRE_CSI1_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video6{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; // vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - -}; - -&video7{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&video8{ - vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <3>; - path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_DSP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video9{ - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //vivcam1 sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dsp{ - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - - -&video10{ // TUNINGTOOL - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <2>; //<2>=vivcam2 : gc5035 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <1>; - path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; //<3>=vivcam3 : gc02m1b - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - }; -}; - -&video11{ - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video12{ // TUNINGTOOL - channel0 { // CSI2 - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER"; - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <6>; //gc02m1b - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <0>; - path_type = "SENSOR_1600x1200_RAW10_LINER"; - skip_init = <1>; - }; - }; - dma { - path_type = "VIPRE_CSI1_ISP0"; - }; -}; - -&video13{ - status = "okay"; - //vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //sc2310 - csi_idx = <1>; //<1>=CSI2_B - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_MCM_WR0"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video14{ - vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <1>; //sc132gs - csi_idx = <2>; //<2>=CSI2X2_A - flash_led_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_MCM_WR0"; - output { - max_width = <1080>; - max_height = <1280>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video15{ - status = "okay"; - //vi_mem_pool_region = <0>; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; //<0>=vivcam0 :2310 - csi_idx = <1>; //<1>=CSI2_B - flash_led_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_DDR"; - }; - }; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s_8ch_sd2 2>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI */ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec 2>; - }; - }; -}; - -&light_i2s { - status = "disabled"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&i2s_8ch_sd2 { - status = "okay"; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-beagle.dts b/arch/riscv/boot/dts/thead/light-beagle.dts deleted file mode 100644 index cd8c5e74c8ce..000000000000 --- a/arch/riscv/boot/dts/thead/light-beagle.dts +++ /dev/null @@ -1,728 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-beagle-ref.dts" - -/ { - bcmdhd_wlan { - compatible = "android,bcmdhd_wlan"; - - gpio_wl_reg_on = <&gpio2_porta 31 1>; - gpio_wl_host_wake = <&gpio2_porta 25 1>; - }; -}; - -&pwm { - status = "disabled"; -}; - -&qspi0 { - status = "disabled"; -}; - -&qspi1 { - status = "disabled"; -}; - -&vvcam_sensor4 { // beagle board J5 CSI0 connector - sensor_name = "IMX219"; - sensor_pdn = <&gpio2_porta 23 0>; //powerdown pin / shutdown pin - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - i2c_addr = /bits/ 8 <0x10>; - i2c_bus = /bits/ 8 <1>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor5 { // beagle board J4 CSI1 connector - sensor_name = "IMX219"; - sensor_pdn = <&gpio2_porta 24 0>; //powerdown pin / shutdown pin - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - i2c_addr = /bits/ 8 <0x10>; - i2c_bus = /bits/ 8 <3>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - status = "okay"; -}; - -/* -sensor imx219 mounted on beagle board J4 CSI1 (=light CSI2X2_A+CSI2X2_B / CSI2X2_A only) -video0: sensor-vipre-isp0 -video1: sensor-vipre-isp0-dw -video7: sensor-vipre-isp0-dsp1-ry-dw -video10: tuningtool - -sensor imx219 mounted on beagle board J5 CSI0 (=light CSI2) -video2: sensor-vipre-isp1 -video3: sensor-vipre-isp1-dw -video4: sensor-vipre-isp1-dsp0-ry -video5: sensor-vipre-isp1-dsp0-ry-dw -video12: tuningtool -*/ - -&video0{ - vi_mem_pool_region = <0xFFFFFFFF>; // vi_mem: framebuffer, region[2] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <5>; // imx219 - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <5>; // imx219 - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <5>; // imx219 - csi_idx = <2>; //<2>=CSI2X2_A - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video2 { - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <16>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -&video4{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video5{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor0 { - subdev_name = "vivcam"; - idx = <4>; // imx219 - csi_idx = <0>; //<0>=CSI2 - mode_idx = <0>; - path_type = "SENSOR_1080P_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - output { - max_width = <1920>; - max_height = <1088>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - -#include "light-beagle-bone-buses.dtsi" diff --git a/arch/riscv/boot/dts/thead/light-crash.dts b/arch/riscv/boot/dts/thead/light-crash.dts deleted file mode 100644 index d94f63911983..000000000000 --- a/arch/riscv/boot/dts/thead/light-crash.dts +++ /dev/null @@ -1,882 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - model = "T-HEAD Light val board"; - compatible = "thead,light-val", "thead,light"; - - chosen { - bootargs = "console=ttyS0,115200 earlycon"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - status = "disabled"; - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - status = "disabled"; - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - sound-name-prefix = "DUMMY"; - status = "okay"; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 12 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&gpio2_porta 29 0>; - WIFI,reset_n = <&gpio2_porta 24 0>; - status = "okay"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default", "rts_gpio"; - BT,power_gpio = <&gpio2_porta 25 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&ao_gpio_porta 11 0x1>; - }; - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&ao_gpio_porta 10 0x1>; - }; - }; - - aon: light-aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1a000000 { - reg = <0x0 0x1a000000 0 0x4000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ - 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; -}; - -&adc { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - touch@5d { - #gpio-cells = <2>; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio1_porta>; - interrupts = <8 0>; - irq-gpios = <&gpio1_porta 8 0>; - reset-gpios = <&gpio1_porta 7 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1280>; - }; - -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - status = "disabled"; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - sound-name-prefix = "ES7210"; - status = "disabled"; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - reset-gpio = <&ao_gpio4_porta 9 0x1>; - sound-name-prefix = "AW87519"; - status = "okay"; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - status = "okay"; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - status = "disabled"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clocks = <&dummy_clock_uart_sclk>; - clock-names = "baudclk"; - clock-frequency = <100000000>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "disabled"; - - spidev@0 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "okay"; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <198000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - rxclk-sample-delay = <80>; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x208 /* pwm0 */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - FM_QSPI1_D2_WP 0x0 0x23a - FM_QSPI1_D3_HOLD 0x0 0x23a - >; - }; - - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_AOGPIO_11 0x0 0x208 - FM_AOGPIO_10 0x3 0x208 - >; - }; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; -}; - -&isp0 { - status = "disabled"; -}; - -&isp1 { - status = "disabled"; -}; - -&isp_ry0 { - status = "disabled"; -}; - -&dewarp { - status = "disabled"; -}; - -&dec400_isp0 { - status = "disabled"; -}; - -&dec400_isp1 { - status = "disabled"; -}; - -&dec400_isp2 { - status = "disabled"; -}; - -&bm_visys { - status = "disabled"; -}; - -&bm_csi0 { - status = "disabled"; -}; - -&bm_csi1 { - status = "disabled"; -}; - -&bm_csi2 { - status = "disabled"; -}; - -&vi_pre { - status = "disabled"; -}; - -&xtensa_dsp { - status = "disabled"; -}; - -&xtensa_dsp0 { - status = "disabled"; -}; - -&xtensa_dsp1 { - status = "disabled"; -}; - -&vvcam_flash_led0{ - status = "disabled"; -}; - - -&vvcam_sensor0 { - status = "disabled"; -}; - -&vvcam_sensor1 { - status = "disabled"; -}; - -&vvcam_sensor2 { - status = "disabled"; -}; - -&vvcam_sensor3 { - status = "disabled"; -}; - -&vvcam_sensor4 { - status = "disabled"; -}; - -&vvcam_sensor5 { - status = "disabled"; -}; - -&video0{ - status = "disabled"; -}; - - -&video1{ - status = "disabled"; -}; - -&video2{ - status = "disabled"; -}; - -&video3{ - status = "disabled"; -}; - -&video4{ - status = "disabled"; -}; - -&video5{ - status = "disabled"; -}; - -&video6{ - status = "disabled"; -}; - -&video7{ - status = "disabled"; -}; - - -&video8{ - status = "disabled"; -}; - -&video9{ - status = "disabled"; -}; - - -&video10{ - status = "disabled"; -}; - -&video11{ - status = "disabled"; -}; - -&video12{ - status = "disabled"; -}; - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "disabled"; -}; - -&vdec { - status = "disabled"; -}; - -&venc { - status = "disabled"; -}; - -&isp_venc_shake { - status = "disabled"; -}; - -&vidmem { - status = "disabled"; -}; - -&gpu { - status = "disabled"; -}; - -&npu { - status = "disabled"; -}; - -&fce { - status = "disabled"; -}; - -&dpu_enc0 { - status = "disabled"; -}; - -&dpu_enc1 { - status = "disabled"; -}; - -&dpu { - status = "disabled"; -}; - -&dsi0 { - status = "disabled"; -}; - -&dhost_0 { - status = "disabled"; -}; - -&disp1_out { - status = "disabled"; -}; - -&hdmi_tx { - status = "disabled"; -}; - -&lightsound { - status = "disabled"; -}; - -&khvhost { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/light-emu.dtsi b/arch/riscv/boot/dts/thead/light-emu.dtsi deleted file mode 100644 index a9090ba2ff0b..000000000000 --- a/arch/riscv/boot/dts/thead/light-emu.dtsi +++ /dev/null @@ -1,1536 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "thead,light"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - mmc0 = &emmc; - mmc1 = &sdhci0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &qspi0; - vivcam0 = &vvcam_sensor0; - vivcam1 = &vvcam_sensor1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - }; - - resmem: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x14000000>; - alloc-ranges = <0 0x20000000 0 0x40000000>; - linux,cma-default; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <3000000>; - cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1850000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1850000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@1 { - device_type = "cpu"; - reg = <1>; - status = "disabled"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1850000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1850000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@2 { - device_type = "cpu"; - reg = <2>; - status = "disabled"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1850000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1850000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@3 { - device_type = "cpu"; - reg = <3>; - status = "disabled"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1850000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1850000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - - display-subsystem { - compatible = "verisilicon,display-subsystem"; - ports = <&dpu_disp0>, <&dpu_disp1>; - status = "disabled"; - }; - - dpu-encoders { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dpu_enc0: dpu-encoder@0 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc0_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; - - dpu_enc1: dpu-encoder@1 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc1_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; - entry-reg = <0xff 0xff019050>; - entry-cnt = <4>; - control-reg = <0xff 0xff015004>; - control-val = <0x1c>; - csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>; - }; - - clint0: clint@ffdc000000 { - compatible = "riscv,clint0"; - interrupts-extended = < - &cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - >; - reg = <0xff 0xdc000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; - }; - - intc: interrupt-controller@ffd8000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff &cpu0_intc 9 - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - >; - reg = <0xff 0xd8000000 0x0 0x04000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <240>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_clock_apb: apb-clock@0 { - compatible = "fixed-clock"; - reg = <0>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_apb"; - #clock-cells = <0>; - }; - - dummy_clock_ref: ref-clock@1 { - compatible = "fixed-clock"; - reg = <1>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ref"; - #clock-cells = <0>; - }; - - dummy_clock_suspend: suspend-clock@2 { - compatible = "fixed-clock"; - reg = <2>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_suspend"; - #clock-cells = <0>; - }; - - dummy_clock_rtc: rtc-clock@3 { - compatible = "fixed-clock"; - reg = <3>; /* Not address, just for index */ - clock-frequency = <32768>; - clock-output-names = "dummy_clock_rtc"; - #clock-cells = <0>; - }; - - dummy_clock_ahb: ahb-clock@4 { - compatible = "fixed-clock"; - reg = <4>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_npu: npu-clock@5 { - compatible = "fixed-clock"; - reg = <5>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_npu"; - #clock-cells = <0>; - }; - - dummy_clock_gpu: gpu-clock@6 { - compatible = "fixed-clock"; - reg = <6>; /* Not address, just for index */ - clock-frequency = <18000000>; - clock-output-names = "dummy_clock_gpu"; - #clock-cells = <0>; - }; - dummy_clock_dphy_ref: dphy-ref-clock@7 { - compatible = "fixed-clock"; - reg = <7>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_dphy_ref"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_cfg: dphy-cfg-clock@8 { - compatible = "fixed-clock"; - reg = <8>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_dphy_cfg"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel: dpu-pixel-clock@9 { - compatible = "fixed-clock"; - reg = <9>; - clock-frequency = <25200000>; - clock-output-names = "dummy_clock_dpu_pixel"; - #clock-cells = <0>; - }; - - osc_32k: clock-osc-32k@6 { - compatible = "fixed-clock"; - reg = <9>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m@7 { - compatible = "fixed-clock"; - reg = <10>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - rc_24m: clock-rc-24m@8 { - compatible = "fixed-clock"; - reg = <11>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "rc_24m"; - }; - - dummy_clock_eip: eip-clock@12 { - compatible = "fixed-clock"; - reg = <12>; /* Not address, just for index */ - clock-frequency = <30000000>; - clock-output-names = "dummy_clock_eip"; - #clock-cells = <0>; - }; - }; - - iso7816: iso7816-card@fff7f30000 { - compatible = "thead,light-iso7816-card"; - reg = <0xff 0xf7f30000 0x0 0x4000>; - interrupts = <69>; - interrupt-parent = <&intc>; - }; - - teesys_syscon: teesys-reg@ffff200000 { - compatible = "syscon"; - reg = <0xff 0xff200000 0x0 0x10000>; - }; - - nvmem_controller: efuse@ffff210000 { - compatible = "thead,light-fm-efuse", "syscon"; - reg = <0xff 0xff210000 0x0 0x10000>; - thead,teesys = <&teesys_syscon>; - #address-cells = <1>; - #size-cells = <1>; - - gmac0_mac_address: mac-address@176 { - reg = <0xb0 6>; - }; - - gmac1_mac_address: mac-address@184 { - reg = <0xb8 6>; - }; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio0_porta: gpio0-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <56>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio1_porta: gpio1-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <57>; - }; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio2_porta: gpio2-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <58>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio3_porta: gpio3-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <59>; - }; - }; - - padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 { - compatible = "thead,light-fm-left-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - status = "okay"; - }; - - padctrl0_apsys: padctrl0-apsys@ffec007000 { - compatible = "thead,light-fm-right-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - status = "okay"; - }; - - pwm: pwm@ffec01c000 { - compatible = "thead,pwm-light"; - reg = <0xff 0xec01c000 0x0 0x4000>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <16>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <17>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <18>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <19>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - padctrl_aosys: padctrl-aosys@fffff4a000 { - compatible = "thead,light-fm-aon-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - status = "okay"; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <20>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <21>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <22>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <50000000>; - interrupts = <23>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - uart0: serial@ffe7014000 { /* Normal serial, for C910 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <36>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <37>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <38>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <39>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <40>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - dmas = <&dmac0 8>; - dma-names = "tx"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "support"; - status = "okay"; - }; - - uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <41>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - spi0: spi@ffe700c000 { - compatible = "snps,dw-apb-ssi"; - reg = <0xff 0xe700c000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <54>; - clocks = <&dummy_clock_apb>; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi0: spi@ffea000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xea000000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <52>; - clocks = <&dummy_clock_apb>; - #address-cells = <1>; - #size-cells = <0>; - }; - - g2d: gc620@ffecc80000 { - compatible = "thead,c910-gc620"; - reg = <0xff 0xecc80000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <101>; - interrupt-names = "irq_2d"; - status = "okay"; - }; - - dsi0: dw-mipi-dsi@ffef500000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef500000 0x0 0x10000>; - status = "disabled"; - - dphy_0: dsi0-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi0>; - clocks = <&dummy_clock_dphy_ref>, - <&dummy_clock_dphy_cfg>, - <&dummy_clock_apb>; - clock-names = "refclk", "cfgclk", "pclk"; - #phy-cells = <0>; - }; - - dhost_0: dsi0-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi0>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>; - clock-names = "ref", "pclk"; - phys = <&dphy_0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dsi1: dw-mipi-dsi@ffef510000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef510000 0x0 0x10000>; - status = "disabled"; - - dphy_1: dsi1-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi1>; - clocks = <&dummy_clock_dphy_ref>, - <&dummy_clock_dphy_cfg>, - <&dummy_clock_apb>; - clock-names = "refclk", "cfgclk", "pclk"; - #phy-cells = <0>; - }; - - dhost_1: dsi1-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi1>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>; - clock-names = "ref", "pclk"; - phys = <&dphy_1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - hdmi_tx: dw-hdmi-tx@ffef540000 { - compatible = "thead,light-hdmi-tx"; - reg = <0xff 0xef540000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <111>; - clocks = <&dummy_clock_apb>, <&dummy_clock_dphy_ref>; - clock-names = "iahb", "isfr"; - reg-io-width = <4>; - phy_version = <301>; - /* TODO: add phy property */ - status = "disabled"; - }; - - dpu: dc8200@ffef600000 { - compatible = "verisilicon,dc8200"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff 0xef600000 0x0 0x100>, - <0xff 0xef600800 0x0 0x2000>, - <0xff 0xef630010 0x0 0x60>; - interrupt-parent = <&intc>; - interrupts = <93>; - clocks = <&dummy_clock_apb>, <&dummy_clock_dpu_pixel>, <&dummy_clock_ahb>; - clock-names = "core_clk", "pix_clk", "axi_clk"; - status = "disabled"; - - dpu_disp0: port@0 { - reg = <0>; - - disp0_out: endpoint { - remote-endpoint = <&enc0_in>; - }; - }; - - dpu_disp1: port@1 { - reg = <1>; - - disp1_out: endpoint { - remote-endpoint = <&enc1_in>; - }; - }; - }; - - watchdog0: watchdog@ffefc30000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc30000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <24>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - status = "okay"; - }; - - watchdog1: watchdog@ffefc31000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc31000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <25>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - status = "okay"; - }; - - rtc: rtc@fffff40000 { - compatible = "apm,xgene-rtc"; - reg = <0xff 0xfff40000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <74>; - clocks = <&dummy_clock_rtc>; - clock-names = "rtc"; - status = "okay"; - }; - - usb: dwc3@ffe7040000 { - compatible = "snps,dwc3"; - reg = <0xff 0xe7040000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <68>; - clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>; - clock-names = "ref", "bus_early", "suspend"; - reg-shift = <2>; - reg-io-width = <4>; - maximum-speed = "super-speed"; - dr_mode = "peripheral"; - dma-mask = <0xf 0xffffffff>; - snps,usb3_lpm_capable; - snps,dis_u3_susphy_quirk; - }; - - pmu: pmu@0 { - compatible = "riscv,c910_pmu"; - reg = <0 0 0 0>; /* Not address, just for index */ - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,light-fm-ree-clk"; - reg = <0xff 0xef010000 0x0 0x1000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; - clock-names = "osc_32k", "osc_24m", "rc_24m"; - status = "okay"; - }; - - sys_reg: sys_reg@ffef018014 { - compatible = "thead,light_sys_reg"; - reg = <0xff 0xef018014 0x0 0x100>; - status = "okay"; - }; - - dmac0: dmac@ffefc00000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xefc00000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <27>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - dmac1: tee_dmac@ffff340000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xff340000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <150>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <3>; - snps,rd_osr_lmt = <3>; - snps,blen = <16 8 4 0 0 0 0>; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7070000 0x0 0x2000 - 0xff 0xec00301c 0x0 0x4 - 0xff 0xec003020 0x0 0x4 - 0xff 0xec003000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <66>; - interrupt-names = "macirq"; - clocks = <&dummy_clock_apb>; - clock-names = "stmmaceth"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac0_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - gmac1: ethernet@ffe7060000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7060000 0x0 0x2000 - 0xff 0xec00401c 0x0 0x4 - 0xff 0xec004020 0x0 0x4 - 0xff 0xec004000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <67>; - interrupt-names = "macirq"; - clocks = <&dummy_clock_apb>; - clock-names = "stmmaceth"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac1_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - emmc: sdhci@ffe7080000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <62>; - interrupt-names = "sdhciirq"; - clocks = <&dummy_clock_ahb>; - clock-names = "core"; - }; - - sdhci0: sd@ffe7090000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <64>; - interrupt-names = "sdhci0irq"; - clocks = <&dummy_clock_ahb>; - clock-names = "core"; - }; - - hwspinlock: hwspinlock@ffefc10000 { - compatible = "light,hwspinlock"; - reg = <0xff 0xefc10000 0x0 0x10000>; - }; - - npu: vha@fffc800000 { - compatible = "img,ax3386-nna"; - reg = <0xff 0xfc800000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <113>; - interrupt-names = "npuirq"; - clocks = <&dummy_clock_npu>; - clock-names = "dummy_clock_npu"; - vha_clk_rate = <24000000>; - ldo_vha-supply = <&npu>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - gpu: gpu@ffef400000 { - compatible = "img,gpu"; - reg = <0xff 0xef400000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <102>; - interrupt-names = "gpuirq"; - clocks = <&dummy_clock_gpu>; - clock-names = "dummy_clock_gpu"; - gpu_clk_rate = <18000000>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - fce: fce@fffcc50000 { - compatible = "thead,light-fce"; - reg = <0xff 0xfcc50000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <100>; - interrupt-names = "fceirq"; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - vdec: vdec@ffecc00000 { - compatible = "thead,light-vc8000d"; - reg = <0xff 0xecc00000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <131>; - status = "disabled"; - }; - - venc: venc@ffecc10000 { - compatible = "thead,light-vc8000e"; - reg = <0xff 0xecc10000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <133>; - status = "disabled"; - }; - - isp_venc_shake: shake@ffe4078000 { - compatible = "thead,light-ivs"; - reg = <0xff 0xe4078000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <158>; - status = "disabled"; - }; - - vidmem: vidmem@ffecc08000 { - compatible = "thead,light-vidmem"; - reg = <0xff 0xecc08000 0x0 0x1000>; - status = "disabled"; - }; - - light_i2s: light_i2s@ffe7034000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xe7034000 0x0 0x4000>; - light,mode = "i2s-master"; - interrupt-parent = <&intc>; - interrupts = <70>; - dmas = <&dmac0 35>, <&dmac0 39>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&dummy_clock_apb>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2c0: i2c@ffe7f20000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f20000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <44>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@ffec00c000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec00c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <46>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - isp0: isp@ffe4100000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <117>,<118>; - status = "disabled"; - }; - - isp1: isp@ffe4110000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <120>,<121>; - status = "disabled"; - - }; - - isp_ry0: isp_ry@ffe4120000 { - compatible = "thead,light-isp_ry"; - reg = <0xff 0xe4120000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <123>,<124>; - status = "disabled"; - }; - - dewarp: dewarp@ffe4130000 { - compatible = "thead,light-dewarp"; - reg = <0xff 0xe4130000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <98>,<99>; - status = "disabled"; - }; - - dec400_isp0: dec400@ffe4060000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4060000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp1: dec400@ffe4068000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4068000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp2: dec400@ffe4070000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4070000 0x0 0x8000>; - status = "disabled"; - }; - - bm_visys: bm_visys@ffe4040000 { - compatible = "thead,light-bm-visys"; - reg = <0xff 0xe4040000 0x0 0x1000>; - status = "disabled"; - }; - - bm_csi0: csi@ffe4000000{ - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4000000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <128>; - dphyglueiftester = <0x180>; - status = "disabled"; - }; - - bm_csi1: csi@ffe4020000{ - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4020000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <127>; - dphyglueiftester = <0x184>; - status = "disabled"; - }; - - bm_isp0: bm_isp@ffe4100000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - status = "disabled"; - }; - - bm_isp1: bm_isp@ffe4110000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - status = "disabled"; - }; - - //isp-ry - bm_isp2: bm_isp@ffe4120000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4120000 0x0 0x10000>; - status = "disabled"; - }; - - vi_pre: vi_pre@ffe4030000 { - compatible = "thead,vi_pre"; - reg = <0xff 0xe4030000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <134>; - status = "disabled"; - }; - - video: cam_dev@100 { - compatible = "thead,video"; - status = "disabled"; - }; - - vvcam_sensor0: vvcam_sensor@0 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor1: vvcam_sensor@1 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - xtensa_dsp: dsp@01{ - compatible = "thead,dsp-hw-common"; - reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */ - status = "disabled"; - }; - - xtensa_dsp0: dsp@0 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef048000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */ - 0x00 0x90000000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x90001000 0x0 0x00fff000>; /* DSP shared memory */ - dsp = <0>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <156>; - firmware-name = "xrp0.elf"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - xtensa_dsp1: dsp@1 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef050000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */ - 0x00 0xa0000000 0x0 0x00001000 /* DSP communication area */ - 0x0 0xa0001000 0x0 0x00fff000>; /* DSP shared memory */ - dsp = <1>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <157>; - firmware-name = "xrp1.elf"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - pmp: pmp@ffdc020000 { - compatible = "pmp"; - reg = <0xff 0xdc020000 0x0 0x1000>; - }; - - mrvbr: mrvbr@ffff018050 { - compatible = "mrvbr"; - reg = <0xff 0xff019050 0x0 0x1000>; - }; - - mrmr: mrmr@ffff014004 { - compatible = "mrmr"; - reg = <0xff 0xff015004 0x0 0x1000>; - }; - - bmu: ddr-pmu@ffff008000 { - compatible = "thead,light-ddr-pmu"; - reg = <0xff 0xff008000 0x0 0x800 - 0xff 0xff008800 0x0 0x800 - 0xff 0xff009000 0x0 0x800 - 0xff 0xff009800 0x0 0x800 - 0xff 0xff00a000 0x0 0x800>; - interrupt-parent = <&intc>; - interrupts = <87>; - status = "okay"; - }; - - mbox_910t: mbox@ffffc38000 { - compatible = "thead,light-mbox"; - reg = <0xff 0xffc38000 0x0 0x4000>, - <0xff 0xffc44000 0x0 0x1000>, - <0xff 0xffc4c000 0x0 0x1000>, - <0xff 0xffc54000 0x0 0x1000>; - reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&dummy_clock_apb>; - clock-names = "ipg"; - icu_cpu_id = <0>; - #mbox-cells = <2>; - }; - - trng: rng@ffff300000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xff 0xff300000 0x0 0x7d>; - interrupt-parent = <&intc>; - interrupts = <149>; - clocks = <&dummy_clock_eip>; - status = "disabled"; - }; - - - eip-28@ffff300000 { - compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28"; - reg = <0xff 0xff300000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <144>,<145>,<146>,<147>; - clocks = <&dummy_clock_eip>; - }; - }; - - aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; -}; - diff --git a/arch/riscv/boot/dts/thead/light-evb.dtsi b/arch/riscv/boot/dts/thead/light-evb.dtsi deleted file mode 100644 index ee82e3df57e3..000000000000 --- a/arch/riscv/boot/dts/thead/light-evb.dtsi +++ /dev/null @@ -1,1938 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "thead,light"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - mmc0 = &emmc; - mmc1 = &sdhci0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &qspi0; - spi2 = &qspi1; - vivcam0 = &vvcam_sensor0; - vivcam1 = &vvcam_sensor1; - vivcam2= &vvcam_sensor2; - vivcam3= &vvcam_sensor3; - vivcam4= &vvcam_sensor4; - vivcam5= &vvcam_sensor5; - vivcam6= &vvcam_sensor6; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x1 0x00000000>; - }; - - resmem: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x14000000>; - alloc-ranges = <0 0x20000000 0 0x40000000>; - linux,cma-default; - }; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <3000000>; - c910_0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_1: cpu@1 { - device_type = "cpu"; - reg = <1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_2: cpu@2 { - device_type = "cpu"; - reg = <2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_3: cpu@3 { - device_type = "cpu"; - reg = <3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - - display-subsystem { - compatible = "verisilicon,display-subsystem"; - ports = <&dpu_disp0>, <&dpu_disp1>; - status = "disabled"; - }; - - dpu-encoders { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dpu_enc0: dpu-encoder@0 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc0_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; - - dpu_enc1: dpu-encoder@1 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc1_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; - entry-reg = <0xff 0xff019050>; - entry-cnt = <4>; - control-reg = <0xff 0xff015004>; - control-val = <0x1c>; - csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>; - }; - - clint0: clint@ffdc000000 { - compatible = "riscv,clint0"; - interrupts-extended = < - &cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - >; - reg = <0xff 0xdc000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; - }; - - intc: interrupt-controller@ffd8000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff &cpu0_intc 9 - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - >; - reg = <0xff 0xd8000000 0x0 0x04000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <240>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_clock_apb: apb-clock@0 { - compatible = "fixed-clock"; - reg = <0>; /* Not address, just for index */ - clock-frequency = <62500000>; - clock-output-names = "dummy_clock_apb"; - #clock-cells = <0>; - }; - - dummy_clock_ref: ref-clock@1 { - compatible = "fixed-clock"; - reg = <1>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ref"; - #clock-cells = <0>; - }; - - dummy_clock_suspend: suspend-clock@2 { - compatible = "fixed-clock"; - reg = <2>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_suspend"; - #clock-cells = <0>; - }; - - dummy_clock_rtc: rtc-clock@3 { - compatible = "fixed-clock"; - reg = <3>; /* Not address, just for index */ - clock-frequency = <32768>; - clock-output-names = "dummy_clock_rtc"; - #clock-cells = <0>; - }; - - dummy_clock_ahb: ahb-clock@4 { - compatible = "fixed-clock"; - reg = <4>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_npu: npu-clock@5 { - compatible = "fixed-clock"; - reg = <5>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_npu"; - #clock-cells = <0>; - }; - - dummy_clock_gpu: gpu-clock@6 { - compatible = "fixed-clock"; - reg = <6>; /* Not address, just for index */ - clock-frequency = <18000000>; - clock-output-names = "dummy_clock_gpu"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_ref: dphy-ref-clock@7 { - compatible = "fixed-clock"; - reg = <7>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_dphy_ref"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_cfg: dphy-cfg-clock@8 { - compatible = "fixed-clock"; - reg = <8>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_dphy_cfg"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel0: dpu-pixel-clock@9 { - compatible = "fixed-clock"; - reg = <9>; - clock-frequency = <72000000>; - clock-output-names = "dummy_clock_dpu_pixel0"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel1: dpu-pixel-clock@10 { - compatible = "fixed-clock"; - reg = <10>; - clock-frequency = <74250000>; - clock-output-names = "dummy_clock_dpu_pixel1"; - #clock-cells = <0>; - }; - - osc_32k: clock-osc-32k@11 { - compatible = "fixed-clock"; - reg = <11>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m@12 { - compatible = "fixed-clock"; - reg = <12>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - rc_24m: clock-rc-24m@13 { - compatible = "fixed-clock"; - reg = <13>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "rc_24m"; - }; - - dummy_clock_eip: eip-clock@14 { - compatible = "fixed-clock"; - reg = <14>; /* Not address, just for index */ - clock-frequency = <400000000>; - clock-output-names = "dummy_clock_eip"; - #clock-cells = <0>; - }; - - dummy_clock_spi: spi-clock@15 { - compatible = "fixed-clock"; - reg = <15>; /* Not address, just for index */ - clock-frequency = <396000000>; - clock-output-names = "dummy_clock_spi"; - #clock-cells = <0>; - }; - - dummy_clock_qspi: spi-clock@16 { - compatible = "fixed-clock"; - reg = <15>; /* Not address, just for index */ - clock-frequency = <792000000>; - clock-output-names = "dummy_clock_qspi"; - #clock-cells = <0>; - }; - - dummy_gmac_ahb: gmac-ahb-clock@16 { - compatible = "fixed-clock"; - reg = <16>; - clock-frequency = <250000000>; - clock-output-names = "dummy_gmac_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_gmac: gmac-clock@17 { - compatible = "fixed-clock"; - reg = <17>; - clock-frequency = <500000000>; - clock-output-names = "dummy_clock_gmac"; - #clock-cells = <0>; - }; - - dummy_clock_sdhci: sdhci-clock@18 { - compatible = "fixed-clock"; - reg = <18>; /* Not address, just for index */ - clock-frequency = <198000000>; - clock-output-names = "dummy_clock_sdhci"; - #clock-cells = <0>; - }; - - dummy_clock_aonsys_clk: aonsys-clk-clock@19 { - compatible = "fixed-clock"; - reg = <19>; /* Not address, just for index */ - clock-frequency = <73728000>; - clock-output-names = "dummy_clock_aonsys_clk"; - #clock-cells = <0>; - }; - - dummy_clock_uart_sclk: uart-sclk-clock@20 { - compatible = "fixed-clock"; - reg = <20>; /* Not address, just for index */ - clock-frequency = <100000000>; - clock-output-names = "dummy_clock_uart_sclk"; - #clock-cells = <0>; - }; - }; - - iso7816: iso7816-card@fff7f30000 { - compatible = "thead,light-iso7816-card"; - reg = <0xff 0xf7f30000 0x0 0x4000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_iso7816>; - interrupts = <69>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - teesys_syscon: teesys-reg@ffff200000 { - compatible = "syscon"; - reg = <0xff 0xff200000 0x0 0x10000>; - }; - - nvmem_controller: efuse@ffff210000 { - compatible = "thead,light-fm-efuse", "syscon"; - reg = <0xff 0xff210000 0x0 0x10000>; - thead,teesys = <&teesys_syscon>; - #address-cells = <1>; - #size-cells = <1>; - - gmac0_mac_address: mac-address@176 { - reg = <0xb0 6>; - }; - - gmac1_mac_address: mac-address@184 { - reg = <0xb8 6>; - }; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio0_porta: gpio0-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <56>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio1_porta: gpio1-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <57>; - }; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio2_porta: gpio2-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <58>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - gpio3_porta: gpio3-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <59>; - }; - }; - - ao_gpio4: gpio@fffff52000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff52000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - ao_gpio4_porta: ao_gpio4-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <55>; - }; - }; - - ao_gpio: gpio@fffff41000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff41000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - ao_gpio_porta: ao_gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <76>; - }; - }; - - padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 { - compatible = "thead,light-fm-left-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - status = "okay"; - }; - - padctrl0_apsys: padctrl0-apsys@ffec007000 { - compatible = "thead,light-fm-right-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - status = "okay"; - }; - - pwm: pwm@ffec01c000 { - compatible = "thead,pwm-light"; - reg = <0xff 0xec01c000 0x0 0x4000>; - #pwm-cells = <2>; - clocks = <&clk CLKGEN_PWM_PCLK>, - <&clk CLKGEN_PWM_CCLK>; - clock-names = "pclk", "cclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <16>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <17>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <18>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <19>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - padctrl_aosys: padctrl-aosys@fffff4a000 { - compatible = "thead,light-fm-aon-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - status = "okay"; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <20>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <21>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <22>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <23>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - uart0: serial@ffe7014000 { /* Normal serial, for C910 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <36>; - clocks = <&clk CLKGEN_UART0_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <37>; - clocks = <&clk CLKGEN_UART1_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <38>; - clocks = <&clk CLKGEN_UART2_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <39>; - clocks = <&clk CLKGEN_UART3_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <40>; - clocks = <&clk CLKGEN_UART4_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "support"; - status = "okay"; - }; - - uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <41>; - clocks = <&clk CLKGEN_UART5_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - adc: adc@ffec020000 { - compatible = "thead,light-adc"; - reg = <0xff 0xfff51000 0x0 0x2000>; - interrupt-parent = <&intc>; - interrupts = <61>; - clocks = <&dummy_clock_aonsys_clk>; - clock-names = "adc"; - /* ADC pin is proprietary,no need to config pinctrl */ - status = "disabled"; - }; - - spi0: spi@ffe700c000 { - compatible = "snps,dw-apb-ssi"; - reg = <0xff 0xe700c000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - interrupt-parent = <&intc>; - interrupts = <54>; - clocks = <&dummy_clock_spi>; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi0: spi@ffea000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xea000000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - interrupt-parent = <&intc>; - interrupts = <52>; - clocks = <&dummy_clock_qspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi1: spi@fff8000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xf8000000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1>; - interrupt-parent = <&intc>; - interrupts = <53>; - clocks = <&dummy_clock_spi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - g2d: gc620@ffecc80000 { - compatible = "thead,c910-gc620"; - reg = <0xff 0xecc80000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <101>; - interrupt-names = "irq_2d"; - status = "okay"; - }; - - dsi0: dw-mipi-dsi@ffef500000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef500000 0x0 0x10000>; - status = "disabled"; - - dphy_0: dsi0-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi0>; - vosys-regmap = <&vosys_reg>; - clocks = <&dummy_clock_dphy_ref>, - <&dummy_clock_dphy_cfg>, - <&dummy_clock_apb>; - clock-names = "refclk", "cfgclk", "pclk"; - #phy-cells = <0>; - }; - - dhost_0: dsi0-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi0>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>; - clock-names = "ref", "pclk"; - phys = <&dphy_0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dsi1: dw-mipi-dsi@ffef510000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef510000 0x0 0x10000>; - status = "disabled"; - - dphy_1: dsi1-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi1>; - vosys-regmap = <&vosys_reg>; - clocks = <&dummy_clock_dphy_ref>, - <&dummy_clock_dphy_cfg>, - <&dummy_clock_apb>; - clock-names = "refclk", "cfgclk", "pclk"; - #phy-cells = <0>; - }; - - dhost_1: dsi1-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi1>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&dummy_clock_dphy_ref>, <&dummy_clock_apb>; - clock-names = "ref", "pclk"; - phys = <&dphy_1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vosys_reg: vosys@ffef528000 { - compatible = "thead,light-vo-subsys", "syscon"; - reg = <0xff 0xef528000 0x0 0x1000>; - status = "okay"; - }; - - hdmi_tx: dw-hdmi-tx@ffef540000 { - compatible = "thead,light-hdmi-tx"; - reg = <0xff 0xef540000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <111>; - clocks = <&dummy_clock_apb>, <&dummy_clock_dphy_ref>; - clock-names = "iahb", "isfr"; - reg-io-width = <4>; - phy_version = <301>; - /* TODO: add phy property */ - status = "disabled"; - }; - - dpu: dc8200@ffef600000 { - compatible = "verisilicon,dc8200"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff 0xef600000 0x0 0x100>, - <0xff 0xef600800 0x0 0x2000>, - <0xff 0xef630010 0x0 0x60>; - interrupt-parent = <&intc>; - interrupts = <93>; - clocks = <&dummy_clock_apb>, - <&clk DPU0_PLL_DIV_CLK>, - <&clk DPU1_PLL_DIV_CLK>, - <&dummy_clock_ahb>; - clock-names = "core_clk", "pix_clk0", "pix_clk1", "axi_clk"; - status = "disabled"; - - dpu_disp0: port@0 { - reg = <0>; - - disp0_out: endpoint { - remote-endpoint = <&enc0_in>; - }; - }; - - dpu_disp1: port@1 { - reg = <1>; - - disp1_out: endpoint { - remote-endpoint = <&enc1_in>; - }; - }; - }; - - watchdog0: watchdog@ffefc30000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc30000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <24>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - status = "okay"; - }; - - watchdog1: watchdog@ffefc31000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc31000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <25>; - clocks = <&dummy_clock_apb>; - clock-names = "baudclk"; - status = "okay"; - }; - - rtc: rtc@fffff40000 { - compatible = "apm,xgene-rtc"; - reg = <0xff 0xfff40000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <74>; - clocks = <&dummy_clock_rtc>; - clock-names = "rtc"; - status = "okay"; - }; - - usb: dwc3@ffe7040000 { - compatible = "snps,dwc3"; - reg = <0xff 0xe7040000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <68>; - clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>; - clock-names = "ref", "bus_early", "suspend"; - reg-shift = <2>; - reg-io-width = <4>; - maximum-speed = "super-speed"; - dr_mode = "host"; - dma-mask = <0xf 0xffffffff>; - snps,usb3_lpm_capable; - snps,dis_u3_susphy_quirk; - status = "okay"; - }; - - pmu: pmu@0 { - compatible = "riscv,c910_pmu"; - reg = <0 0 0 0>; /* Not address, just for index */ - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,light-fm-ree-clk"; - reg = <0xff 0xef010000 0x0 0x1000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; - clock-names = "osc_32k", "osc_24m", "rc_24m"; - status = "okay"; - }; - - sys_reg: sys_reg@ffef010100 { - compatible = "thead,light_sys_reg"; - reg = <0xff 0xef010100 0x0 0x100>; - status = "okay"; - }; - - dmac0: dmac@ffefc00000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xefc00000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <27>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - dmac1: tee_dmac@ffff340000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xff340000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <150>; - clocks = <&dummy_clock_apb>, <&dummy_clock_apb>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <3>; - snps,rd_osr_lmt = <3>; - snps,blen = <16 8 4 0 0 0 0>; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7070000 0x0 0x2000 - 0xff 0xec00301c 0x0 0x4 - 0xff 0xec003020 0x0 0x4 - 0xff 0xec003000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <66>; - interrupt-names = "macirq"; - clocks = <&clk CLKGEN_GMAC0_HCLK>, <&clk CLKGEN_GMAC0_CCLK>; - clock-names = "stmmaceth", "gmac_pll_clk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac0_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - gmac1: ethernet@ffe7060000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7060000 0x0 0x2000 - 0xff 0xec00401c 0x0 0x4 - 0xff 0xec004020 0x0 0x4 - 0xff 0xec004000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <67>; - interrupt-names = "macirq"; - clocks = <&clk CLKGEN_GMAC1_HCLK>, <&clk CLKGEN_GMAC1_CCLK>; - clock-names = "stmmaceth", "gmac_pll_clk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac1_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - emmc: sdhci@ffe7080000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <62>; - interrupt-names = "sdhciirq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - }; - - sdhci0: sd@ffe7090000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <64>; - interrupt-names = "sdhci0irq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - }; - - sdhci1: sd@ffe70a0000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <71>; - interrupt-names = "sdhci1irq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - }; - - hwspinlock: hwspinlock@ffefc10000 { - compatible = "light,hwspinlock"; - reg = <0xff 0xefc10000 0x0 0x10000>; - status = "disabled"; - }; - - npu: vha@fffc800000 { - compatible = "img,ax3386-nna"; - reg = <0xff 0xfc800000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <113>; - interrupt-names = "npuirq"; - clocks = <&dummy_clock_npu>; - clock-names = "dummy_clock_npu"; - vha_clk_rate = <24000000>; - ldo_vha-supply = <&npu>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - gpu: gpu@ffef400000 { - compatible = "img,gpu"; - reg = <0xff 0xef400000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <102>; - interrupt-names = "gpuirq"; - clocks = <&dummy_clock_gpu>; - clock-names = "dummy_clock_gpu"; - gpu_clk_rate = <18000000>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - fce: fce@fffcc50000 { - compatible = "thead,light-fce"; - reg = <0xff 0xfcc50000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <100>; - interrupt-names = "fceirq"; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - vdec: vdec@ffecc00000 { - compatible = "thead,light-vc8000d"; - reg = <0xff 0xecc00000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <131>; - status = "disabled"; - }; - - venc: venc@ffecc10000 { - compatible = "thead,light-vc8000e"; - reg = <0xff 0xecc10000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <133>; - status = "disabled"; - }; - - isp_venc_shake: shake@ffe4078000 { - compatible = "thead,light-ivs"; - reg = <0xff 0xe4078000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <158>; - status = "disabled"; - }; - - vidmem: vidmem@ffecc08000 { - compatible = "thead,light-vidmem"; - reg = <0xff 0xecc08000 0x0 0x1000>; - status = "disabled"; - }; - - light_i2s: light_i2s@ffe7034000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xe7034000 0x0 0x4000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_light_i2s0>; - light,mode = "i2s-master"; - interrupt-parent = <&intc>; - interrupts = <70>; - dmas = <&dmac0 35>, <&dmac0 39>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&dummy_clock_apb>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2c0: i2c@ffe7f20000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f20000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <44>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x2>; - hs_lcnt = /bits/ 16 <0x7>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@ffe7f24000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f24000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <45>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x2>; - hs_lcnt = /bits/ 16 <0x6>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@ffec00c000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec00c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <46>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x2>; - hs_lcnt = /bits/ 16 <0x7>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@ffec014000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <47>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x2>; - hs_lcnt = /bits/ 16 <0x7>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@ffe7f28000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f28000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <48>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x2>; - hs_lcnt = /bits/ 16 <0x7>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - isp0: isp@ffe4100000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <117>,<118>; - status = "disabled"; - }; - - isp1: isp@ffe4110000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <120>,<121>; - status = "disabled"; - - }; - - isp_ry0: isp_ry@ffe4120000 { - compatible = "thead,light-isp_ry"; - reg = <0xff 0xe4120000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <123>,<124>; - status = "disabled"; - }; - - dewarp: dewarp@ffe4130000 { - compatible = "thead,light-dewarp"; - reg = <0xff 0xe4130000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <98>,<99>; - status = "disabled"; - }; - - dec400_isp0: dec400@ffe4060000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4060000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp1: dec400@ffe4068000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4068000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp2: dec400@ffe4070000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4070000 0x0 0x8000>; - status = "disabled"; - }; - - bm_visys: bm_visys@ffe4040000 { - compatible = "thead,light-bm-visys"; - reg = <0xff 0xe4040000 0x0 0x1000>; - status = "disabled"; - }; - - bm_csi0: csi@ffe4000000{ //CSI2 - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4000000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <128>; - dphyglueiftester = <0x180>; - sysreg_mipi_csi_ctrl = <0x140>; - status = "disabled"; - }; - - bm_csi1: csi@ffe4010000{ //CSI2X2_B - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4010000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0 - dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed. - sysreg_mipi_csi_ctrl = <0x148>; - status = "disabled"; - }; - - bm_csi2: csi@ffe4020000{ //CSI2X2_A - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4020000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <127>; - dphyglueiftester = <0x184>; - sysreg_mipi_csi_ctrl = <0x144>; - status = "disabled"; - }; - - - bm_isp0: bm_isp@ffe4100000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - status = "disabled"; - }; - - bm_isp1: bm_isp@ffe4110000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - status = "disabled"; - }; - - //isp-ry - bm_isp2: bm_isp@ffe4120000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4120000 0x0 0x10000>; - status = "disabled"; - }; - - vi_pre: vi_pre@ffe4030000 { - compatible = "thead,vi_pre"; - reg = <0xff 0xe4030000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <134>; - status = "disabled"; - }; - - video0: cam_dev@100 { - compatible = "thead,video"; - status = "disabled"; - }; - - video1: cam_dev@200 { - compatible = "thead,video"; - status = "disabled"; - }; - - video2: cam_dev@300 { - compatible = "thead,video"; - status = "disabled"; - }; - - vvcam_sensor0: vvcam_sensor@0 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor1: vvcam_sensor@1 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor2: vvcam_sensor@2 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor3: vvcam_sensor@3 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor4: vvcam_sensor@4 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor5: vvcam_sensor@5 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor6: vvcam_sensor@6 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - xtensa_dsp: dsp@01{ - compatible = "thead,dsp-hw-common"; - reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */ - status = "disabled"; - }; - - xtensa_dsp0: dsp@0 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef048000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */ - 0x00 0x90000000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x90001000 0x0 0x00fff000>; /* DSP shared memory */ - dsp = <0>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <156>; - firmware-name = "xrp0.elf"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - xtensa_dsp1: dsp@1 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef050000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */ - 0x00 0xa0000000 0x0 0x00001000 /* DSP communication area */ - 0x0 0xa0001000 0x0 0x00fff000>; /* DSP shared memory */ - dsp = <1>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <157>; - firmware-name = "xrp1.elf"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x70000000 0x00 0x70000000 0x40000000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - pmp: pmp@ffdc020000 { - compatible = "pmp"; - reg = <0xff 0xdc020000 0x0 0x1000>; - }; - - mrvbr: mrvbr@ffff018050 { - compatible = "mrvbr"; - reg = <0xff 0xff019050 0x0 0x1000>; - }; - - mrmr: mrmr@ffff014004 { - compatible = "mrmr"; - reg = <0xff 0xff015004 0x0 0x1000>; - }; - - bmu: ddr-pmu@ffff008000 { - compatible = "thead,light-ddr-pmu"; - reg = <0xff 0xff008000 0x0 0x800 - 0xff 0xff008800 0x0 0x800 - 0xff 0xff009000 0x0 0x800 - 0xff 0xff009800 0x0 0x800 - 0xff 0xff00a000 0x0 0x800>; - interrupt-parent = <&intc>; - interrupts = <87>; - status = "okay"; - }; - - mbox_910t: mbox@ffffc38000 { - compatible = "thead,light-mbox"; - reg = <0xff 0xffc38000 0x0 0x4000>, - <0xff 0xffc44000 0x0 0x1000>, - <0xff 0xffc4c000 0x0 0x1000>, - <0xff 0xffc54000 0x0 0x1000>; - reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&dummy_clock_apb>; - clock-names = "ipg"; - icu_cpu_id = <0>; - #mbox-cells = <2>; - }; - - trng: rng@ffff300000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xff 0xff300000 0x0 0x7d>; - interrupt-parent = <&intc>; - interrupts = <149>; - clocks = <&dummy_clock_eip>; - status = "disabled"; - }; - - - eip_28: eip-28@ffff300000 { - compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28"; - reg = <0xff 0xff300000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <144>,<145>,<146>,<147>; - clocks = <&dummy_clock_eip>; - status = "disabled"; - }; - }; - - aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio0_porta 10 1>; - enable-active-high; - regulator-always-on; - }; - soc_vext_2v8_reg: soc_vext_2v8 { - compatible = "regulator-fixed"; - regulator-name = "soc_vext_2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio0_porta 11 1>; - enable-active-high; - regulator-always-on; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&ao_gpio_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 24 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 22 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 23 1>; - enable-active-high; - regulator-always-on; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio1_porta 7 1>; - enable-active-high; - regulator-always-on; - }; - - aon_reg_ricoh: light-ricoh-reg { - compatible = "thead,light-ricoh-pmic"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ap_reg: soc_dvdd08_ap { - regulator-name = "soc_dvdd08_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; -}; - diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-audio.dts b/arch/riscv/boot/dts/thead/light-fm-emu-audio.dts deleted file mode 100644 index 22e97282787b..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-audio.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-fm-emu.dts" - -/ { - model = "T-HEAD Light FM EMP Audio FPGA board"; - compatible = "thead,light-fm-emu-audio", "thead,light"; -}; - -&lightsound { - status = "okay"; -}; - -&light_i2s { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-dsi0-hdmi.dts b/arch/riscv/boot/dts/thead/light-fm-emu-dsi0-hdmi.dts deleted file mode 100644 index ac31f618d2a4..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-dsi0-hdmi.dts +++ /dev/null @@ -1,16 +0,0 @@ -#include "light-fm-emu-dsi0.dts" - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-dsi0.dts b/arch/riscv/boot/dts/thead/light-fm-emu-dsi0.dts deleted file mode 100644 index 777a3127b9d5..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-dsi0.dts +++ /dev/null @@ -1,64 +0,0 @@ -#include "light-fm-emu.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&dpu_enc0 { - status = "okay"; - - ports { - /* output */ - port@1 { - reg = <1>; - - enc0_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; -}; - -&dpu { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - panel@0 { - compatible = "hlt,hpk070h275"; - reg = <0>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-dsp.dts b/arch/riscv/boot/dts/thead/light-fm-emu-dsp.dts deleted file mode 100644 index 72f9e3a4d54b..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-dsp.dts +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-fm-emu.dts" - -/ { - model = "T-HEAD Light FM EMU DSP FPGA board"; - compatible = "thead,light-fm-emu-dsp", "thead,light"; - - chosen { - linux,initrd-end = <0x0 0x1B000000>; - }; -}; - -&resmem { - dsp_mem: memory@70000000 { - reg = <0x0 0x70000000 0 0x40000000>; - no-map; - }; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; -}; - -&xtensa_dsp1 { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-gpu.dts b/arch/riscv/boot/dts/thead/light-fm-emu-gpu.dts deleted file mode 100644 index fc2e80c778b0..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-gpu.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-fm-emu.dts" - -/ { - model = "T-HEAD Light FM EMU GPU FPGA board"; - compatible = "thead,light-fm-emu-gpu", "thead,light"; - - chosen { - linux,initrd-end = <0x0 0x18000000>; - }; -}; - -&gpu { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-hdmi.dts b/arch/riscv/boot/dts/thead/light-fm-emu-hdmi.dts deleted file mode 100644 index 46d0606a2796..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-hdmi.dts +++ /dev/null @@ -1,26 +0,0 @@ -#include "light-fm-emu.dts" - -/ { - display-subsystem { - status = "okay"; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&dpu { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-fm-emu-npu-fce.dts b/arch/riscv/boot/dts/thead/light-fm-emu-npu-fce.dts deleted file mode 100644 index f6f9b8322992..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu-npu-fce.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include "light-fm-emu.dts" - -/ { - model = "T-HEAD Light FM EMU NPU&FCE FPGA board"; - compatible = "thead,light-fm-emu-npu-fce", "thead,light"; - - chosen { - linux,initrd-end = <0x0 0x1B000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - facelib_mem: memory@e0000000 { - reg = <0x1 0xe0000000 0 0x20000000>; - no-map; - }; - }; -}; - -&npu { - vha_clk_rate = <13000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/thead/light-fm-emu.dts b/arch/riscv/boot/dts/thead/light-fm-emu.dts deleted file mode 100644 index 9bb7ba0f5e44..000000000000 --- a/arch/riscv/boot/dts/thead/light-fm-emu.dts +++ /dev/null @@ -1,511 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-emu.dtsi" - -/ { - model = "T-HEAD Light FM EMU FPGA board"; - compatible = "thead,light-fm-emu", "thead,light"; - - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon sram=0xffe0000000,0x180000"; - linux,initrd-start = <0x0 0x2000000>; - linux,initrd-end = <0x0 0x4600000>; - stdout-path = "serial0:115200n8"; - }; - - keys { - compatible = "gpio-keys"; - - key0 { - label = "key0"; - gpios = <&gpio1_porta 7 1>; /* GPIO_ACTIVE_LOW: 1 */ - linux,code = <59>; /* KEY_F1: 59 */ - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "led0"; - gpios = <&gpio1_porta 8 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dsp: IOPMP_DSP { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - status = "disabled"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - simple-audio-card,dai-link@0 { /* I2S - CODEC */ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 0>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; - - simple-audio-card,dai-link@1 { /* I2S - HDMI */ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <1>; - compatible = "linux,bt-sco"; - status = "okay"; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&spi0 { - num-cs = <2>; - cs-gpios = <&gpio2_porta 15 0>, // GPIO_ACTIVE_HIGH: 0 - <&gpio2_porta 23 0>; // GPIO_ACTIVE_LOW: 1 - status = "okay"; - - spi_norflash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <8000000>; - w25q,fast-read; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - spi-max-frequency = <12500000>; - }; -}; - -&uart0 { - clock-frequency = <50000000>; -}; - -&qspi0 { - num-cs = <2>; - cs-gpios = <&gpio2_porta 3 0>, // GPIO_ACTIVE_HIGH: 0 - <&gpio2_porta 26 0>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; - - spidev@1 { - compatible = "spidev"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - spi-max-frequency = <6250000>; - }; -}; - -&gmac0 { - max-speed = <100>; - phy-mode = "mii"; - phy-handle = <&phy_88E1111_0>; - status = "okay"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x0 0x0>; - }; - }; -}; - -&gmac1 { - max-speed = <100>; - phy-mode = "mii"; - phy-handle = <&phy_88E1111_1>; - status = "disabled"; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_1: ethernet-phy@0 { - reg = <0x0 0x0>; - }; - }; -}; - -&emmc { - max-frequency = <50000000>; - non-removable; - no-sdio; - no-sd; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <50000000>; - no-1-8-v; - bus-width = <4>; - status = "okay"; -}; - -&padctrl0_apsys { - light-fm-evb { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x72 - FM_UART0_RXD 0x0 0x72 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x0 0x72 - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_CSN0 0x0 0x72 - >; - }; - }; -}; - -&padctrl1_apsys { - light-fm-evb { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x0 0x72 - FM_UART3_RXD 0x0 0x72 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x72 - FM_UART4_RXD 0x0 0x72 - FM_UART4_CTSN 0x0 0x72 - FM_UART4_RTSN 0x0 0x72 - >; - }; - }; -}; - -&padctrl_aosys { - light-fm-evb { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - - }; -}; - -&i2c2 { - status = "okay"; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&vi_pre { - status = "okay"; -}; - -&vvcam_sensor0 { - sensor_name = "OV5693"; - status = "okay"; -}; - -&video{ - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; - csi_idx = <0>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - /* - csi0 { - subdev_name = "bm_csi"; - idx = <0>; - }; - */ - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_PATH_MEM_DW_SC_MEM"; - }; - }; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-camera-tuning.dts b/arch/riscv/boot/dts/thead/light-lpi4a-camera-tuning.dts deleted file mode 100644 index 317295b7b935..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-camera-tuning.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-lpi4a.dts" - - - -&video10{ // TUNINGTOOL - status = "okay"; - channel0 { - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; // 0=640 480 1=2592x1944 - path_type = "SENSOR_2592x1944_LINER"; - }; - dma { - path_type = "VIPRE_CSI0_ISP0"; - }; - }; -}; - -&video15{ - status = "okay"; - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - channel0 { - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0>; - csi_idx = <0>; - mode_idx = <0>; - path_type = "SENSOR_VGA_RAW12_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_DDR"; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-crash.dts b/arch/riscv/boot/dts/thead/light-lpi4a-crash.dts deleted file mode 100644 index 117fe33d2820..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-crash.dts +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2023 Alibaba Group Holding Limited. - */ - -#include "light-crash.dts" - -&aon { - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts b/arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts deleted file mode 100644 index 8b75b5ee0a3b..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-ddr2G.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Alibaba Group Holding Limited. - */ - -#include "light-lpi4a.dts" - -/ { - model = "T-HEAD Light Lichee Pi 4A configuration for 2GB DDR board"; - compatible = "thead,light-val", "thead,light-lpi4a-ddr2G", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0x7fe00000>; - }; -}; - -&cmamem { - alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-hdmi.dts b/arch/riscv/boot/dts/thead/light-lpi4a-hdmi.dts deleted file mode 100644 index 4ef7487d57ef..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-hdmi.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-lpi4a.dts" - -&lightsound { - status = "okay"; - simple-audio-card,dai-link@0 { /* I2S - HDMI*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; -}; - -&dpu_enc0 { - status = "disabled"; -}; - -&dsi0 { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-hx8279.dts b/arch/riscv/boot/dts/thead/light-lpi4a-hx8279.dts deleted file mode 100644 index d940542f72ec..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-hx8279.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022-2023 Alibaba Group Holding Limited. - */ - -#include "light-lpi4a-ref.dts" - -/ { - model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board"; - compatible = "thead,light-val", "thead,light-lpi4a", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x1 0xffe00000>; - }; -}; - -&cmamem { - size = <0 0x20000000>; // 512MB on lpi4a (SOM) - alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000] -}; - -&i2c3 { - touch@14 { - #gpio-cells = <2>; - compatible = "goodix,gt9271"; - reg = <0x14>; - interrupt-parent = <&ao_gpio_porta>; - interrupts = <3 0>; - irq-gpios = <&ao_gpio_porta 3 0>; - reset-gpios = <&pcal6408ahk_d 0 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <1200>; - touchscreen-size-y = <1920>; - tp-size = <9271>; - status = "okay"; - }; -}; - -&dsi0 { - status = "okay"; -}; - - -&dhost_0 { - panel0@0 { - compatible = "himax,hx8279"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */ - hsvcc-supply = <&soc_vdd18_lcd0_en_reg>; - vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-ref.dts b/arch/riscv/boot/dts/thead/light-lpi4a-ref.dts deleted file mode 100644 index 58aa809b6d81..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-ref.dts +++ /dev/null @@ -1,1813 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light.dtsi" -#include -#include -#include "light-vi-devices.dtsi" -/ { - chosen { - bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - status = "disabled"; - led0 { - label = "SYS_STATUS"; - gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ - default-state = "off"; - }; - }; - - display-subsystem { - status = "okay"; - }; - - lcd0_backlight: pwm-backlight@0 { - compatible = "pwm-backlight"; - pwms = <&pwm 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - }; - - light_iopmp: iopmp { - compatible = "thead,light-iopmp"; - - /* config#1: multiple valid regions */ - iopmp_emmc: IOPMP_EMMC { - regions = <0x000000 0x100000>, - <0x100000 0x200000>; - attr = <0xFFFFFFFF>; - dummy_slave= <0x800000>; - }; - - /* config#2: iopmp bypass */ - iopmp_sdio0: IOPMP_SDIO0 { - bypass_en; - }; - - /* config#3: iopmp default region set */ - iopmp_sdio1: IOPMP_SDIO1 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_usb0: IOPMP_USB0 { - attr = <0xFFFFFFFF>; - is_default_region; - }; - - iopmp_ao: IOPMP_AO { - is_default_region; - }; - - iopmp_aud: IOPMP_AUD { - is_default_region; - }; - - iopmp_chip_dbg: IOPMP_CHIP_DBG { - is_default_region; - }; - - iopmp_eip120i: IOPMP_EIP120I { - is_default_region; - }; - - iopmp_eip120ii: IOPMP_EIP120II { - is_default_region; - }; - - iopmp_eip120iii: IOPMP_EIP120III { - is_default_region; - }; - - iopmp_isp0: IOPMP_ISP0 { - is_default_region; - }; - - iopmp_isp1: IOPMP_ISP1 { - is_default_region; - }; - - iopmp_dw200: IOPMP_DW200 { - is_default_region; - }; - - iopmp_vipre: IOPMP_VIPRE { - is_default_region; - }; - - iopmp_venc: IOPMP_VENC { - is_default_region; - }; - - iopmp_vdec: IOPMP_VDEC { - is_default_region; - }; - - iopmp_g2d: IOPMP_G2D { - is_default_region; - }; - - iopmp_fce: IOPMP_FCE { - is_default_region; - }; - - iopmp_npu: IOPMP_NPU { - is_default_region; - }; - - iopmp0_dpu: IOPMP0_DPU { - bypass_en; - }; - - iopmp1_dpu: IOPMP1_DPU { - bypass_en; - }; - - iopmp_gpu: IOPMP_GPU { - is_default_region; - }; - - iopmp_gmac1: IOPMP_GMAC1 { - is_default_region; - }; - - iopmp_gmac2: IOPMP_GMAC2 { - is_default_region; - }; - - iopmp_dmac: IOPMP_DMAC { - is_default_region; - }; - - iopmp_tee_dmac: IOPMP_TEE_DMAC { - is_default_region; - }; - - iopmp_dsp0: IOPMP_DSP0 { - is_default_region; - }; - - iopmp_dsp1: IOPMP_DSP1 { - is_default_region; - }; - - iopmp_audio0: IOPMP_AUDIO0 { - is_default_region; - }; - - iopmp_audio1: IOPMP_AUDIO1 { - is_default_region; - }; - }; - - mbox_910t_client1: mbox_910t_client1 { - compatible = "thead,light-mbox-client"; - mbox-names = "902"; - mboxes = <&mbox_910t 1 0>; - status = "disabled"; - }; - - - mbox_910t_client2: mbox_910t_client2 { - compatible = "thead,light-mbox-client"; - mbox-names = "906"; - mboxes = <&mbox_910t 2 0>; - audio-mbox-regmap = <&audio_mbox>; - status = "okay"; - }; - - lightsound: lightsound@1 { - compatible = "simple-audio-card"; - simple-audio-card,name = "Light-Sound-Card"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - light_rpmsg: light_rpmsg { - compatible = "light,rpmsg-bus", "simple-bus"; - memory-region = <&rpmsgmem>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - rpmsg: rpmsg{ - vdev-nums = <1>; - reg = <0x0 0x1E000000 0 0x10000>; - compatible = "light,light-rpmsg"; - status = "okay"; - }; - }; - - dummy_codec: dummy_codec { - #sound-dai-cells = <0>; - compatible = "thead,light-dummy-pcm"; - status = "okay"; - sound-name-prefix = "DUMMY"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm 1 10000000 0>; - cooling-levels = <0 64 192 255>; - }; - - reg_vref_1v8: regulator-adc-verf { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - status = "okay"; - }; - - reg_tp_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "regulator-pwr-en"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_d 4 1>; - enable-active-high; - regulator-always-on; - }; - - reg_usb_hub_vdd1v2: regulator-hub-vdd12-en { - compatible = "regulator-fixed"; - regulator-name = "regulator-hub-vdd12-en"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pcal6408ahk_d 2 1>; - enable-active-high; - regulator-always-on; - }; - - reg_usb_hub_vcc5v: regulator-hub-vcc5v-en { - compatible = "regulator-fixed"; - regulator-name = "regulator-hub-vcc5v-en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pcal6408ahk_d 3 1>; - enable-active-high; - regulator-always-on; - }; - - wcn_wifi: wireless-wlan { - compatible = "wlan-platdata"; - clock-names = "clk_wifi"; - ref-clock-frequency = <24000000>; - keep_wifi_power_on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_wake>; - wifi_chip_type = "rtl8723ds"; - WIFI,poweren_gpio = <&pcal6408ahk_c 4 0>; - status = "okay"; - }; - - wcn_bt: wireless-bluetooth { - compatible = "bluetooth-platdata"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_wake>; - BT,power_gpio = <&pcal6408ahk_c 5 0>; - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pinctrl_volume>; - pinctrl-names = "default"; - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio1_porta 19 0x1>; - }; - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - debounce-interval = <1>; - gpios = <&gpio2_porta 25 0x1>; - }; - }; - - aon: aon { - compatible = "thead,light-aon"; - mbox-names = "aon"; - mboxes = <&mbox_910t 1 0>; - status = "okay"; - - pd: light-aon-pd { - compatible = "thead,light-aon-pd"; - #power-domain-cells = <1>; - }; - - soc_aud_3v3_en_reg: soc_aud_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - }; - - soc_aud_1v8_en_reg: soc_aud_1v8_en { - compatible = "regulator-fixed"; - regulator-name = "soc_aud_1v8_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - }; - - soc_vdd_3v3_en_reg: soc_vdd_3v3_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd_3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio0_porta 30 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vdd33_lcd0_en_reg: soc_lcd0_vdd33_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_vdd33_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pcal6408ahk_d 5 1>; - enable-active-high; - }; - - soc_vdd18_lcd0_en_reg: soc_lcd0_vdd18_en { - compatible = "regulator-fixed"; - regulator-name = "soc_lcd0_vdd18_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pcal6408ahk_d 6 1>; - enable-active-high; - }; - - soc_vdd5v_se_en_reg: soc_vdd5v_se_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vdd5v_se_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2_porta 14 1>; - enable-active-high; - regulator-always-on; - }; - - soc_wcn33_en_reg: soc_wcn33_en { - compatible = "regulator-fixed"; - regulator-name = "soc_wcn33_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2_porta 29 1>; - enable-active-high; - regulator-always-on; - }; - - soc_vbus_en_reg: soc_vbus_en { - compatible = "regulator-fixed"; - regulator-name = "soc_vbus_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1_porta 22 1>; - enable-active-high; - regulator-always-on; - }; - - - soc_avdd28_rgb_reg: soc_avdd28_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd28_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_b 1 1>; - regulator-always-on; - enable-active-high; - }; - - soc_dovdd18_rgb_reg: soc_dovdd18_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_b 2 1>; - regulator-always-on; - enable-active-high; - }; - - soc_dvdd12_rgb_reg: soc_dvdd12_rgb { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_rgb"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pcal6408ahk_b 0 1>; - regulator-always-on; - enable-active-high; - }; - - soc_avdd25_ir_reg: soc_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&pcal6408ahk_b 5 1>; - enable-active-high; - }; - - soc_dovdd18_ir_reg: soc_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pcal6408ahk_b 3 1>; - enable-active-high; - }; - - soc_dvdd12_ir_reg: soc_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pcal6408ahk_b 4 1>; - enable-active-high; - }; - - soc_cam2_avdd25_ir_reg: soc_cam2_avdd25_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_cam2_avdd25_ir"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - gpio = <&pcal6408ahk_b 7 1>; - enable-active-high; - }; - - soc_cam2_dovdd18_ir_reg: soc_cam2_dovdd18_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_cam2_dovdd18_ir"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pcal6408ahk_b 6 1>; - enable-active-high; - }; - - soc_cam2_dvdd12_ir_reg: soc_cam2_dvdd12_ir { - compatible = "regulator-fixed"; - regulator-name = "soc_cam2_dvdd12_ir"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pcal6408ahk_c 0 1>; - enable-active-high; - }; - - aon_reg_dialog: light-dialog-reg { - compatible = "thead,light-dialog-pmic-ant"; - status = "okay"; - - dvdd_cpu_reg: appcpu_dvdd { - regulator-name = "appcpu_dvdd"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - dvddm_cpu_reg: appcpu_dvddm { - regulator-name = "appcpu_dvddm"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_aon_reg: soc_dvdd18_aon { - regulator-name = "soc_dvdd18_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd33_usb3_reg: soc_avdd33_usb3 { - regulator-name = "soc_avdd33_usb3"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_aon_reg: soc_dvdd08_aon { - regulator-name = "soc_dvdd08_aon"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd08_ddr_reg: soc_dvdd08_ddr { - regulator-name = "soc_dvdd08_ddr"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { - regulator-name = "soc_vdd_ddr_1v8"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { - regulator-name = "soc_vdd_ddr_1v1"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { - regulator-name = "soc_vdd_ddr_0v6"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dvdd18_ap_reg: soc_dvdd18_ap { - regulator-name = "soc_dvdd18_ap"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { - regulator-name = "soc_avdd08_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { - regulator-name = "soc_avdd18_mipi_hdmi"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd33_emmc_reg: soc_vdd33_emmc { - regulator-name = "soc_vdd33_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_vdd18_emmc_reg: soc_vdd18_emmc { - regulator-name = "soc_vdd18_emmc"; - regulator-boot-on; - regulator-always-on; - }; - - soc_dovdd18_scan_reg: soc_dovdd18_scan { - regulator-name = "soc_dovdd18_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - soc_dvdd12_scan_reg: soc_dvdd12_scan { - regulator-name = "soc_dvdd12_scan"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - soc_avdd28_scan_en_reg: soc_avdd28_scan_en { - regulator-name = "soc_avdd28_scan_en"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - }; - - }; - - c910_cpufreq { - compatible = "thead,light-mpw-cpufreq"; - status = "okay"; - }; - - test: light-aon-test { - compatible = "thead,light-aon-test"; - }; - }; - - thermal-zones { - cpu-thermal-zone { - trips { - fan_config0: fan-trip0 { - temperature = <40000>; - hysteresis = <5000>; - type = "active"; - }; - - fan_config1: fan-trip1 { - temperature = <50000>; - hysteresis = <5000>; - type = "active"; - }; - - fan_config2: fan-trip2 { - temperature = <60000>; - hysteresis = <5000>; - type = "active"; - }; - }; - - cooling-maps { - fan-on { - trip = <&fan_config0>; - cooling-device = - <&fan 1 1>; - }; - fan-faster { - trip = <&fan_config1>; - cooling-device = - <&fan 2 2>; - }; - fan-full { - trip = <&fan_config2>; - cooling-device = - <&fan 3 3>; - }; - }; - }; - }; - -}; - -&resmem { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tee_mem: memory@1c000000 { - reg = <0x0 0x1c000000 0 0x2000000>; - no-map; - }; - - dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ - reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ - 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ - 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ - 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ - no-map; - }; - dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ - reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ - 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ - 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ - 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ - no-map; - }; - vi_mem: framebuffer@10000000 { - reg = <0x0 0x10000000 0x0 0x6700000>; /* vi_mem_pool_region[0] 44 MB (default) */ - //0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ - //0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ - no-map; - }; - facelib_mem: memory@17000000 { - reg = <0x0 0x17000000 0 0x02000000>; - no-map; - }; - audio_mem: memory@32000000 { - reg = <0x0 0x32000000 0x0 0x6400000>; - no-map; - }; - rpmsgmem: memory@1E000000 { - reg = <0x0 0x1E000000 0x0 0x10000>; - no-map; - }; - -}; - -&adc { - vref-supply = <®_vref_1v8>; - #io-channel-cells = <1>; - status = "okay"; -}; - -&audio_i2c0 { - clock-frequency = <100000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa29>, - <&pinctrl_audiopa30>, - <&pinctrl_audio_i2c0>; - - es8156_audio_codec: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - sound-name-prefix = "ES8156"; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - es7210_audio_codec: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - sound-name-prefix = "ES7210"; - MVDD-supply = <&soc_aud_3v3_en_reg>; - AVDD-supply = <&soc_aud_3v3_en_reg>; - DVDD-supply = <&soc_aud_1v8_en_reg>; - PVDD-supply = <&soc_aud_1v8_en_reg>; - }; - - audio_aw87519_pa: amp@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - sound-name-prefix = "AW87519"; - status = "disabled"; - }; - - audio_aw87519_pa1@5b { - compatible = "awinic,aw87519_pa"; - reg = <0x5b>; - status = "disabled"; - }; - -}; - -&audio_i2c1 { - clock-frequency = <100000>; - status = "okay"; - pinctrl-0 = <&pinctrl_audiopa6>, - <&pinctrl_audiopa7>, - <&pinctrl_audio_i2c1>; - - es8156_audio_codec_1: es8156@8 { - #sound-dai-cells = <0>; - compatible = "everest,es8156"; - reg = <0x08>; - status = "disabled"; - }; - - es7210_audio_codec_1: es7210@40 { - #sound-dai-cells = <0>; - compatible = "MicArray_0"; - reg = <0x40>; - status = "disabled"; - }; - - audio_aw87519_pa2@58 { - compatible = "awinic,aw87519_pa"; - reg = <0x58>; - status = "disabled"; - }; - - audio_aw87519_pa3@5b { - compatible = "awinic,aw87519_pa"; - reg = <0x5b>; - status = "disabled"; - }; -}; - -&spi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 - rx-sample-delay-ns = <10>; - - spi_norflash@0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64jwm", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - w25q,fast-read; - }; - - spidev@1 { - status = "disable"; - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x1>; - spi-max-frequency = <50000000>; - }; -}; - -&uart0 { - clock-frequency = <100000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -&qspi0 { - num-cs = <1>; - cs-gpios = <&gpio2_porta 3 0>; - rx-sample-dly = <4>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - }; -}; - -&qspi1 { - compatible = "snps,dw-apb-ssi"; - num-cs = <1>; - cs-gpios = <&gpio0_porta 1 0>; - status = "okay"; - - spidev@0 { - compatible = "spidev"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <50000000>; - }; - -}; - -&gmac0 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111_0: ethernet-phy@0 { - reg = <0x1>; - }; - - phy_88E1111_1: ethernet-phy@1 { - reg = <0x2>; - }; - }; -}; - -&gmac1 { - phy-mode = "rgmii-id"; - rx-clk-delay = <0x00>; /* for RGMII */ - tx-clk-delay = <0x00>; /* for RGMII */ - phy-handle = <&phy_88E1111_1>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac1>; -}; - -&emmc { - max-frequency = <198000000>; - non-removable; - mmc-hs400-1_8v; - io_fixed_1v8; - is_emmc; - no-sdio; - no-sd; - pull_up; - bus-width = <8>; - status = "okay"; -}; - -&sdhci0 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - wprtn_ignore; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdio0>; -}; - -&sdhci1 { - max-frequency = <100000000>; - bus-width = <4>; - pull_up; - no-sd; - no-mmc; - non-removable; - io_fixed_1v8; - post-power-on-delay-ms = <50>; - wprtn_ignore; - cap-sd-highspeed; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&padctrl0_apsys { /* right-pinctrl */ - light-evb-padctrl0 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_uart0: uart0grp { - thead,pins = < - FM_UART0_TXD 0x0 0x202 - FM_UART0_RXD 0x0 0x202 - >; - }; - - pinctrl_i2c2: i2c2grp { - thead,pins = < - FM_I2C2_SCL 0x0 0x204 - FM_I2C2_SDA 0x0 0x204 - >; - }; - - pinctrl_i2c3: i2c3grp { - thead,pins = < - FM_I2C3_SCL 0x0 0x204 - FM_I2C3_SDA 0x0 0x204 - >; - }; - - pinctrl_spi0: spi0grp { - thead,pins = < - FM_SPI_CSN 0x3 0x20a - FM_SPI_SCLK 0x0 0x20a - FM_SPI_MISO 0x0 0x23a - FM_SPI_MOSI 0x0 0x23a - >; - }; - - pinctrl_qspi0: qspi0grp { - thead,pins = < - FM_QSPI0_SCLK 0x0 0x20f - FM_QSPI0_CSN0 0x3 0x20f - FM_QSPI0_CSN1 0x0 0x20f - FM_QSPI0_D0_MOSI 0x0 0x23f - FM_QSPI0_D1_MISO 0x0 0x23f - FM_QSPI0_D2_WP 0x0 0x23f - FM_QSPI0_D3_HOLD 0x0 0x23f - >; - }; - - pinctrl_light_i2s0: i2s0grp { - thead,pins = < - FM_QSPI0_SCLK 0x2 0x208 - FM_QSPI0_CSN0 0x2 0x238 - FM_QSPI0_CSN1 0x2 0x208 - FM_QSPI0_D0_MOSI 0x2 0x238 - FM_QSPI0_D1_MISO 0x2 0x238 - FM_QSPI0_D2_WP 0x2 0x238 - FM_QSPI0_D3_HOLD 0x2 0x238 - >; - }; - - pinctrl_gmac1: gmac1grp { - thead,pins = < - FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */ - FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */ - FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */ - FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */ - FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */ - FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */ - FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */ - FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */ - FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */ - FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */ - FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */ - FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */ - >; - }; - - pinctrl_sdio0: sdio0grp { - thead,pins = < - FM_SDIO0_DETN 0x0 0x202 - >; - }; - - pinctrl_pwm: pwmgrp { - thead,pins = < - FM_GPIO3_2 0x1 0x20f /* pwm0 */ - FM_GPIO3_3 0x1 0x20f /* pwm1 */ - >; - }; - - pinctrl_hdmi: hdmigrp { - thead,pins = < - FM_HDMI_SCL 0x0 0x202 - FM_HDMI_SDA 0x0 0x202 - FM_HDMI_CEC 0x0 0x202 - >; - }; - - pinctrl_gmac0: gmac0grp { - thead,pins = < - FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */ - FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */ - FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */ - FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */ - FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */ - FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */ - FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */ - FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */ - FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */ - FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */ - FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */ - FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */ - FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */ - FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */ - FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */ - FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */ - >; - }; - }; -}; - -&padctrl1_apsys { /* left-pinctrl */ - light-evb-padctrl1 { - /* - * Pin Configuration Node: - * Format: - */ - pinctrl_qspi1: qspi1grp { - thead,pins = < - FM_QSPI1_SCLK 0x0 0x20a - FM_QSPI1_CSN0 0x3 0x20a - FM_QSPI1_D0_MOSI 0x0 0x23a - FM_QSPI1_D1_MISO 0x0 0x23a - >; - }; - - pinctrl_i2c0: i2c0grp { - thead,pins = < - FM_I2C0_SCL 0x0 0x204 - FM_I2C0_SDA 0x0 0x204 - >; - }; - - pinctrl_i2c1: i2c1grp { - thead,pins = < - FM_I2C1_SCL 0x0 0x204 - FM_I2C1_SDA 0x0 0x204 - >; - }; - - pinctrl_uart1: uart1grp { - thead,pins = < - FM_UART1_TXD 0x0 0x202 - FM_UART1_RXD 0x0 0x202 - >; - }; - - pinctrl_uart4: uart4grp { - thead,pins = < - FM_UART4_TXD 0x0 0x202 - FM_UART4_RXD 0x0 0x202 - FM_UART4_CTSN 0x0 0x202 - FM_UART4_RTSN 0x0 0x202 - >; - }; - - pinctrl_uart3: uart3grp { - thead,pins = < - FM_UART3_TXD 0x1 0x202 - FM_UART3_RXD 0x1 0x202 - >; - }; - - pinctrl_wifi_wake: wifi_grp { - thead,pins = < - FM_GPIO0_27 0x0 0x202 - >; - }; - - pinctrl_bt_wake: bt_grp { - thead,pins = < - FM_GPIO0_28 0x0 0x202 - >; - }; - - pinctrl_iso7816: iso7816grp { - thead,pins = < - FM_QSPI1_SCLK 0x1 0x208 - FM_QSPI1_D0_MOSI 0x1 0x238 - FM_QSPI1_D1_MISO 0x1 0x238 - FM_QSPI1_D2_WP 0x1 0x238 - FM_QSPI1_D3_HOLD 0x1 0x238 - >; - }; - - pinctrl_volume: volume_grp { - thead,pins = < - FM_CLK_OUT_2 0x3 0x208 - >; - }; - }; -}; - -&padctrl_aosys { - light-aon-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audiopa1: audiopa1_grp { - thead,pins = < - FM_AUDIO_PA1 0x3 0x72 - >; - }; - - pinctrl_audiopa2: audiopa2_grp { - thead,pins = < - FM_AUDIO_PA2 0x0 0x72 - >; - }; - pinctrl_audiopa6: audiopa6 { - thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa7: audiopa7 { - thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa14: audiopa14 { - thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa15: audiopa15 { - thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa16: audiopa16 { - thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa17: audiopa17 { - thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa18: audiopa18 { - thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_1 0x000 >; - }; - pinctrl_audiopa19: audiopa19 { - thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_1 0x000 >; - }; - pinctrl_audiopa21: audiopa21 { - thead,pins = < FM_AOGPIO_10 LIGHT_PIN_FUNC_1 0x000 >; - }; - pinctrl_audiopa22: audiopa22 { - thead,pins = < FM_AOGPIO_11 LIGHT_PIN_FUNC_1 0x000 >; - }; - pinctrl_audiopa29: audiopa29 { - thead,pins = < FM_AUDIO_PA29 LIGHT_PIN_FUNC_0 0x000 >; - }; - pinctrl_audiopa30: audiopa30 { - thead,pins = < FM_AUDIO_PA30 LIGHT_PIN_FUNC_0 0x000 >; - }; - - }; -}; - -&padctrl_audiosys { - - status = "okay"; - - light-audio-padctrl { - /* - * Pin Configuration Node: - * Format: - */ - - pinctrl_audio_i2c0: audio_i2c0_grp { - thead,pins = < - FM_AUDIO_IO_PA29 LIGHT_PIN_FUNC_2 0x004 - FM_AUDIO_IO_PA30 LIGHT_PIN_FUNC_2 0x004 - >; - }; - pinctrl_audio_i2c1: audio_i2c1_grp { - thead,pins = < - FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_2 0x004 - FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_2 0x004 - >; - }; - pinctrl_audio_i2s1: audio_i2s1_grp { - thead,pins = < - FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA16 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 - >; - }; - pinctrl_audio_i2s2: audio_i2s2_grp { - thead,pins = < - FM_AUDIO_IO_PA18 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA19 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA21 LIGHT_PIN_FUNC_0 0x008 - FM_AUDIO_IO_PA22 LIGHT_PIN_FUNC_0 0x008 - >; - }; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - - pcal6408ahk_b: gpio@20 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - - pcal6408ahk_c: gpio@20 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - - pcal6408ahk_d: gpio@20 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&isp_ry0 { - status = "okay"; -}; - -&dewarp { - status = "okay"; -}; - -&dec400_isp0 { - status = "okay"; -}; - -&dec400_isp1 { - status = "okay"; -}; - -&dec400_isp2 { - status = "okay"; -}; - -&bm_visys { - status = "okay"; -}; - -&bm_csi0 { - status = "okay"; -}; - -&bm_csi1 { - status = "okay"; -}; - -&bm_csi2 { - status = "okay"; -}; - -&vi_pre { - //vi_pre_irq_en = <1>; - status = "okay"; -}; - -&xtensa_dsp { - status = "okay"; -}; - -&xtensa_dsp0 { - status = "okay"; - memory-region = <&dsp0_mem>; -}; - -&xtensa_dsp1 { - status = "okay"; - memory-region = <&dsp1_mem>; -}; - -&vvcam_sensor0 { - sensor_name = "OV12870"; - sensor_regulators = "soc_dovdd18_rgb", "soc_dvdd12_rgb", "soc_avdd28_rgb"; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin - sensor_rst = <&pcal6408ahk_c 1 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x10>; - i2c_bus = /bits/ 8 <0>; - status = "okay"; -}; - -&vvcam_sensor1 {//cam1 csia - sensor_name = "SC132GS"; - sensor_regulators = "soc_dovdd18_ir", "soc_dvdd12_ir", "soc_avdd25_ir"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x30>; - sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin - sensor_rst = <&pcal6408ahk_c 2 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <1>; - status = "okay"; -}; - -&vvcam_sensor2 {//cam2 csib - sensor_name = "SC132GS"; - sensor_regulators = "soc_cam2_dovdd18_ir", "soc_cam2_dvdd12_ir", "soc_cam2_avdd25_ir"; - sensor_regulator_timing_us = <70 1000 2000>; - i2c_addr = /bits/ 8 <0x30>; - sensor_pdn = <&gpio2_porta 13 0>; //powerdown pin / shutdown pin - sensor_rst = <&pcal6408ahk_c 3 0>; - sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_IR-supply = <&soc_cam2_dovdd18_ir_reg>; - DVDD12_IR-supply = <&soc_cam2_dvdd12_ir_reg>; - AVDD25_IR-supply = <&soc_cam2_avdd25_ir_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_bus = /bits/ 8 <2>; - status = "okay"; -}; - -&vvcam_sensor3 {//cam3 csi0 modified - sensor_name = "OV5693"; - sensor_regulators = "soc_dovdd18_rgb", "soc_dvdd12_rgb", "soc_avdd28_rgb"; - sensor_regulator_voltage_uV = <1800000 1200000 2800000>; - sensor_regulator_timing_us = <70 50 20>; - sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin - sensor_rst = <&pcal6408ahk_c 1 0>; - sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready - DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; - DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; - AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; - i2c_reg_width = /bits/ 8 <2>; - i2c_data_width = /bits/ 8 <1>; - i2c_addr = /bits/ 8 <0x36>; - i2c_bus = /bits/ 8 <0>; - status = "okay"; -}; - -&video2 { - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <2600>; - max_height = <2000>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel1 { - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - output { - max_width = <2600>; - max_height = <2000>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; - channel2 { - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - output { - max_width = <2600>; - max_height = <2000>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - }; -}; - -&video3{ - vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] - status = "okay"; - channel0 { - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <2600>; - max_height = <2000>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - dw_dst_depth = <2>; - }; - }; - channel1 { - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <2600>; - max_height = <2000>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - dw_dst_depth = <2>; - }; - }; - channel2 { - sensor1 { - subdev_name = "vivcam"; - idx = <3>; - csi_idx = <0>; - mode_idx = <1>; - path_type = "SENSOR_2592x1944_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - output { - max_width = <2600>; - max_height = <2000>; - bit_per_pixel = <12>; - frame_count = <3>; - }; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - dw_dst_depth = <2>; - }; - }; -}; - - -&trng { - status = "disabled"; -}; - -&eip_28 { - status = "okay"; -}; - -&vdec { - status = "okay"; -}; - -&venc { - status = "okay"; -}; - -&isp_venc_shake { - status = "okay"; -}; - -&vidmem { - status = "okay"; - memory-region = <&vi_mem>; -}; - -&gpu { - status = "okay"; -}; - -&npu { - vha_clk_rate = <1000000000>; - status = "okay"; -}; - -&fce { - memory-region = <&facelib_mem>; - status = "okay"; -}; - -&dpu_enc1 { - ports { - /delete-node/ port@0; - }; -}; - -&dpu { - status = "okay"; -}; - -&dhost_0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dsi0_in: endpoint { - remote-endpoint = <&enc0_out>; - }; - }; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; -}; - -&disp1_out { - remote-endpoint = <&hdmi_tx_in>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; - - port@0 { - /* input */ - hdmi_tx_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; -}; - -&lightsound { - status = "okay"; - simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es8156_audio_codec>; - }; - }; - simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ - reg = <1>; - format = "i2s"; - cpu { - sound-dai = <&i2s1 0>; - }; - codec { - sound-dai = <&es7210_audio_codec>; - }; - }; - simple-audio-card,dai-link@2 { /* I2S - HDMI*/ - reg = <2>; - format = "i2s"; - cpu { - sound-dai = <&light_i2s 1>; - }; - codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&light_i2s { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa14>, - <&pinctrl_audiopa15>, - <&pinctrl_audiopa16>, - <&pinctrl_audiopa17>, - <&pinctrl_audio_i2s1>; - light,mclk_keepon = <1>; -}; - -&i2s2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopa18>, - <&pinctrl_audiopa19>, - <&pinctrl_audiopa21>, - <&pinctrl_audiopa22>, - <&pinctrl_audio_i2s2>; -}; - -&usb_1 { - hubswitch-gpio = <&ao_gpio_porta 4 0>; - vbus-supply = <&soc_vbus_en_reg>; - hub1v2-supply = <®_usb_hub_vdd1v2>; - hub5v-supply = <®_usb_hub_vcc5v>; -}; - -&cpus { - c910_0: cpu@0 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_1: cpu@1 { - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_2: cpu@2 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; - c910_3: cpu@3 { - - operating-points = < - /* kHz uV */ - 300000 650000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 800000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-lpi4a-sec.dts b/arch/riscv/boot/dts/thead/light-lpi4a-sec.dts deleted file mode 100644 index 5a5aa7911350..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a-sec.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -/dts-v1/; - -#include "light-lpi4a-hdmi.dts" - - -&light_iopmp { - status = "disabled"; -}; - -&qspi1 { - status = "disabled"; -}; - diff --git a/arch/riscv/boot/dts/thead/light-lpi4a.dts b/arch/riscv/boot/dts/thead/light-lpi4a.dts deleted file mode 100644 index 9883f90651f0..000000000000 --- a/arch/riscv/boot/dts/thead/light-lpi4a.dts +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022-2023 Alibaba Group Holding Limited. - */ - -#include "light-lpi4a-ref.dts" - -/ { - model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board"; - compatible = "thead,light-val", "thead,light-lpi4a", "thead,light"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x1 0xffe00000>; - }; -}; - -&cmamem { - size = <0 0x20000000>; // 512MB on lpi4a (SOM) - alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000] -}; - -&i2c3 { - touch@14 { - #gpio-cells = <2>; - compatible = "goodix,gt9271"; - reg = <0x14>; - interrupt-parent = <&ao_gpio_porta>; - interrupts = <3 0>; - irq-gpios = <&ao_gpio_porta 3 0>; - reset-gpios = <&pcal6408ahk_d 0 0>; - AVDD28-supply = <®_tp_pwr_en>; - touchscreen-size-x = <800>; - touchscreen-size-y = <1200>; - tp-size = <9271>; - status = "okay"; - }; -}; - -&dsi0 { - status = "okay"; -}; - -&dhost_0 { - panel0@0 { - compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3"; - reg = <0>; - backlight = <&lcd0_backlight>; - reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */ - hsvcc-supply = <&soc_vdd18_lcd0_en_reg>; - vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>; - - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; diff --git a/arch/riscv/boot/dts/thead/light-powergate.dts b/arch/riscv/boot/dts/thead/light-powergate.dts deleted file mode 100644 index ca412d3c7f7a..000000000000 --- a/arch/riscv/boot/dts/thead/light-powergate.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -&npu { - power-domains = <&pd LIGHT_AON_NPU_PD>; -}; - -&gpu { - power-domains = <&pd LIGHT_AON_GPU_PD>; -}; - -&vdec { - power-domains = <&pd LIGHT_AON_VDEC_PD>; -}; - -&venc { - power-domains = <&pd LIGHT_AON_VENC_PD>; -}; - -&xtensa_dsp0 { - power-domains = <&pd LIGHT_AON_DSP0_PD>; - clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>, <&dspsys_clk_gate CLKGEN_DSP0_CCLK>; - clock-names = "pclk", "cclk"; -}; - -&xtensa_dsp1 { - power-domains = <&pd LIGHT_AON_DSP1_PD>; - clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>, <&dspsys_clk_gate CLKGEN_DSP1_CCLK>; - clock-names = "pclk", "cclk"; -}; - -&isp0 { - clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>; - clock-names = "aclk", "hclk", "isp0_pclk", "cclk"; -}; - -&isp1 { - clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>; - clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk"; -}; - -&isp_ry0 { - clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>; - clock-names = "aclk", "hclk", "cclk"; -}; - -&dewarp { - clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>, - <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>; - clock-names = "aclk", "hclk", "vseclk", "dweclk"; -}; - -&bm_csi0 { //CSI2 - clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; - clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2"; -}; - -&bm_csi1 { //CSI2X2_B - clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; - clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2"; -}; - -&bm_csi2 { //CSI2X2_A - clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; - clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2"; -}; - -&vi_pre { - clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>; - clock-names ="aclk", "pclk", "pixclk"; -}; - diff --git a/arch/riscv/boot/dts/thead/light-vi-devices.dtsi b/arch/riscv/boot/dts/thead/light-vi-devices.dtsi deleted file mode 100644 index f3f7c00bf8a5..000000000000 --- a/arch/riscv/boot/dts/thead/light-vi-devices.dtsi +++ /dev/null @@ -1,948 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021-2022 Alibaba Group Holding Limited. - */ - -&video0{ - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP"; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_SP2_BP"; - }; - }; -}; - -&video1{ - status = "disabled"; - channel0 { // VSE0 - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - }; - }; - channel1 { // VSE1 - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - }; - }; - channel2 { // VSE2 - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - }; - }; -}; - -&video2 { - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor2 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP"; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_SP2_BP"; - }; - }; -}; - -&video3 { - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - }; - }; -}; - -&video4 { - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP"; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_SP2_BP"; - }; - }; -}; - -&video5 { - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP1"; - }; - isp { - subdev_name = "isp"; - idx = <1>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - }; - }; -}; - - -&video6 { - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DSP"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_ODD"; - }; - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DSP"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_EVEN"; - }; - }; -}; - - -&video7{ - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE0"; - }; - - }; - channel1 { - channel_id = <1>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE1"; - }; - }; - channel2 { - channel_id = <2>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_PP"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_ISP_RY"; - }; - ry { - subdev_name = "ry"; - idx = <0>; - path_type = "ISP_RY_MI_PATH_MP"; - }; - dw { - subdev_name = "dw"; - idx = <0>; - path_type = "DW_DWE_VSE2"; - }; - }; -}; - - -&video8{ - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_DSP"; - }; - dsp { - subdev_name = "dsp"; - idx = <0>; - path_type = "DSP_PATH_VIPRE_DDR"; - }; - }; -}; - - -&video9 { //IR debug - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_DSP"; - }; - dsp { - subdev_name = "dsp"; - idx = <1>; - path_type = "DSP_PATH_VIPRE_DDR"; - }; - }; -}; - - -&video10{ // TUNING TOOL - status = "disabled"; - channel0 { // CSI2X2_B - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - skip_init = <1>; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI1_ISP0"; - }; - }; -}; - - -&video11{ - status = "disabled"; - channel0 { - channel_id = <0>; - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI2_ISP0"; - }; - isp { - subdev_name = "isp"; - idx = <0>; - path_type = "ISP_MI_PATH_MP"; - }; - }; -}; - - -&video12{ // TUNING TOOL - status = "disabled"; - channel0 { // CSI2 - status = "okay"; - sensor0 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - skip_init = <1>; - }; - sensor1 { - subdev_name = "vivcam"; - idx = <0xff>; // invalid - csi_idx = <0xff>; - path_type = "SENSOR_VGA_RAW10_LINER"; - skip_init = <1>; - }; - dma { - subdev_name = "vipre"; - idx = <0>; - path_type = "VIPRE_CSI0_ISP0"; - }; - }; -}; - - diff --git a/arch/riscv/boot/dts/thead/light.dtsi b/arch/riscv/boot/dts/thead/light.dtsi deleted file mode 100644 index 292168ae0355..000000000000 --- a/arch/riscv/boot/dts/thead/light.dtsi +++ /dev/null @@ -1,2644 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "thead,light"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - audio_i2c0 = &audio_i2c0; - audio_i2c1 = &audio_i2c1; - mmc0 = &emmc; - mmc1 = &sdhci0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &qspi0; - spi2 = &qspi1; - - flash_led0 = &vvcam_flash_led0; - vivcam0 = &vvcam_sensor0; - vivcam1 = &vvcam_sensor1; - vivcam2 = &vvcam_sensor2; - vivcam3 = &vvcam_sensor3; - vivcam4 = &vvcam_sensor4; - vivcam5 = &vvcam_sensor5; - vivcam6 = &vvcam_sensor6; - vivcam7 = &vvcam_sensor7; - - viv_video0 = &video0; - viv_video1 = &video1; - viv_video2 = &video2; - viv_video3 = &video3; - viv_video4 = &video4; - viv_video5 = &video5; - viv_video6 = &video6; - viv_video7 = &video7; - viv_video8 = &video8; - viv_video9 = &video9; - viv_video10 = &video10; - viv_video11 = &video11; - viv_video12 = &video12; - viv_video13 = &video13; - viv_video14 = &video14; - viv_video15 = &video15; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x200000 0x0 0xffe00000>; - }; - - resmem: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - cmamem: linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x14000000>; // 320MB by default - alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] - linux,cma-default; - }; - }; - - aon_iram: aon-iram@ffffef8000 { - compatible = "syscon"; - reg = <0xff 0xffef8000 0x0 0x10000>; - }; - - thermal-zones { - cpu-thermal-zone { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&pvt 0>; - trips { - cpu_config0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_config1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - cpu_cdev { - trip = <&cpu_config0>; - cooling-device = - <&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <3000000>; - c910_0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - c910_1: cpu@1 { - device_type = "cpu"; - reg = <1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_2: cpu@2 { - device_type = "cpu"; - reg = <2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - c910_3: cpu@3 { - device_type = "cpu"; - reg = <3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.848Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "1MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - #cooling-cells = <2>; - - operating-points = < - /* kHz uV */ - 300000 600000 - 800000 700000 - 1500000 800000 - 1848000 1000000 - >; - light,dvddm-operating-points = < - /* kHz uV */ - 300000 750000 - 800000 800000 - 1500000 800000 - 1848000 1000000 - >; - clock-latency = <61036>; - clocks = <&clk C910_CCLK>, - <&clk C910_CCLK_I0>, - <&clk CPU_PLL1_FOUTPOSTDIV>, - <&clk CPU_PLL0_FOUTPOSTDIV>; - clock-names = "c910_cclk", "c910_cclk_i0", - "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; - dvdd-supply = <&dvdd_cpu_reg>; - dvddm-supply = <&dvddm_cpu_reg>; - - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - idle_states: idle-states { - CPU_RET_0_0: cpu-retentive-0-0 { - compatible = "riscv,idle-state"; - riscv,sbi-suspend-param = <0x10000000>; - entry-latency-us = <20>; - exit-latency-us = <40>; - min-residency-us = <80>; - }; - - CPU_NONRET_0_0: cpu-nonretentive-0-0 { - compatible = "riscv,idle-state"; - riscv,sbi-suspend-param = <0x90000000>; - entry-latency-us = <250>; - exit-latency-us = <500>; - min-residency-us = <950>; - }; - - CLUSTER_RET_0: cluster-retentive-0 { - compatible = "riscv,idle-state"; - riscv,sbi-suspend-param = <0x11000000>; - local-timer-stop; - entry-latency-us = <50>; - exit-latency-us = <100>; - min-residency-us = <250>; - wakeup-latency-us = <130>; - }; - - CLUSTER_NONRET_0: cluster-nonretentive-0 { - compatible = "riscv,idle-state"; - riscv,sbi-suspend-param = <0x91000000>; - local-timer-stop; - entry-latency-us = <600>; - exit-latency-us = <1100>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - }; - }; - - display-subsystem { - compatible = "verisilicon,display-subsystem"; - ports = <&dpu_disp0>, <&dpu_disp1>; - status = "disabled"; - }; - - dpu-encoders { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dpu_enc0: dpu-encoder@0 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc0_in: endpoint { - remote-endpoint = <&disp0_out>; - }; - }; - }; - }; - - dpu_enc1: dpu-encoder@1 { - /* default encoder is DSI */ - compatible = "verisilicon,dsi-encoder"; - reg = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* input */ - port@0 { - reg = <0>; - - enc1_in: endpoint { - remote-endpoint = <&disp1_out>; - }; - }; - }; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; - entry-reg = <0xff 0xff019050>; - entry-cnt = <4>; - control-reg = <0xff 0xff015004>; - control-val = <0x1c>; - csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>; - }; - - clint0: clint@ffdc000000 { - compatible = "riscv,clint0"; - interrupts-extended = < - &cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - >; - reg = <0xff 0xdc000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; - }; - - intc: interrupt-controller@ffd8000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff &cpu0_intc 9 - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - >; - reg = <0xff 0xd8000000 0x0 0x04000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <240>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_clock_apb: apb-clock@0 { - compatible = "fixed-clock"; - reg = <0>; /* Not address, just for index */ - clock-frequency = <62500000>; - clock-output-names = "dummy_clock_apb"; - #clock-cells = <0>; - }; - - dummy_clock_ref: ref-clock@1 { - compatible = "fixed-clock"; - reg = <1>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ref"; - #clock-cells = <0>; - }; - - dummy_clock_suspend: suspend-clock@2 { - compatible = "fixed-clock"; - reg = <2>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_suspend"; - #clock-cells = <0>; - }; - - dummy_clock_rtc: rtc-clock@3 { - compatible = "fixed-clock"; - reg = <3>; /* Not address, just for index */ - clock-frequency = <32768>; - clock-output-names = "dummy_clock_rtc"; - #clock-cells = <0>; - }; - - dummy_clock_ahb: ahb-clock@4 { - compatible = "fixed-clock"; - reg = <4>; /* Not address, just for index */ - clock-frequency = <50000000>; - clock-output-names = "dummy_clock_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_gpu: gpu-clock@6 { - compatible = "fixed-clock"; - reg = <6>; /* Not address, just for index */ - clock-frequency = <18000000>; - clock-output-names = "dummy_clock_gpu"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_ref: dphy-ref-clock@7 { - compatible = "fixed-clock"; - reg = <7>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_dphy_ref"; - #clock-cells = <0>; - }; - - dummy_clock_dphy_cfg: dphy-cfg-clock@8 { - compatible = "fixed-clock"; - reg = <8>; /* Not address, just for index */ - clock-frequency = <24000000>; - clock-output-names = "dummy_clock_dphy_cfg"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel0: dpu-pixel-clock@9 { - compatible = "fixed-clock"; - reg = <9>; - clock-frequency = <72000000>; - clock-output-names = "dummy_clock_dpu_pixel0"; - #clock-cells = <0>; - }; - - dummy_clock_dpu_pixel1: dpu-pixel-clock@10 { - compatible = "fixed-clock"; - reg = <10>; - clock-frequency = <74250000>; - clock-output-names = "dummy_clock_dpu_pixel1"; - #clock-cells = <0>; - }; - - osc_32k: clock-osc-32k@11 { - compatible = "fixed-clock"; - reg = <11>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m@12 { - compatible = "fixed-clock"; - reg = <12>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - rc_24m: clock-rc-24m@13 { - compatible = "fixed-clock"; - reg = <13>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "rc_24m"; - }; - - dummy_clock_eip: eip-clock@14 { - compatible = "fixed-clock"; - reg = <14>; /* Not address, just for index */ - clock-frequency = <400000000>; - clock-output-names = "dummy_clock_eip"; - #clock-cells = <0>; - }; - - dummy_clock_spi: spi-clock@15 { - compatible = "fixed-clock"; - reg = <15>; /* Not address, just for index */ - clock-frequency = <396000000>; - clock-output-names = "dummy_clock_spi"; - #clock-cells = <0>; - }; - - dummy_clock_qspi: spi-clock@16 { - compatible = "fixed-clock"; - reg = <15>; /* Not address, just for index */ - clock-frequency = <792000000>; - clock-output-names = "dummy_clock_qspi"; - #clock-cells = <0>; - }; - - dummy_gmac_ahb: gmac-ahb-clock@16 { - compatible = "fixed-clock"; - reg = <16>; - clock-frequency = <250000000>; - clock-output-names = "dummy_gmac_ahb"; - #clock-cells = <0>; - }; - - dummy_clock_gmac: gmac-clock@17 { - compatible = "fixed-clock"; - reg = <17>; - clock-frequency = <500000000>; - clock-output-names = "dummy_clock_gmac"; - #clock-cells = <0>; - }; - - dummy_clock_sdhci: sdhci-clock@18 { - compatible = "fixed-clock"; - reg = <18>; /* Not address, just for index */ - clock-frequency = <198000000>; - clock-output-names = "dummy_clock_sdhci"; - #clock-cells = <0>; - }; - - dummy_clock_aonsys_clk: aonsys-clk-clock@19 { - compatible = "fixed-clock"; - reg = <19>; /* Not address, just for index */ - clock-frequency = <73728000>; - clock-output-names = "dummy_clock_aonsys_clk"; - #clock-cells = <0>; - }; - - dummy_clock_uart_sclk: uart-sclk-clock@20 { - compatible = "fixed-clock"; - reg = <20>; /* Not address, just for index */ - clock-frequency = <100000000>; - clock-output-names = "dummy_clock_uart_sclk"; - #clock-cells = <0>; - }; - - dummy_clock_visys: visys-dummy-clock@21 { - compatible = "fixed-clock"; - reg = <21>; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - }; - - iso7816: iso7816-card@fff7f30000 { - compatible = "thead,light-iso7816-card"; - reg = <0xff 0xf7f30000 0x0 0x4000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_iso7816>; - interrupts = <69>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - teesys_syscon: teesys-reg@ffff200000 { - compatible = "syscon"; - reg = <0xff 0xff200000 0x0 0x10000>; - }; - - visys_reg: visys-reg@ffe4040000 { - compatible = "thead,light-visys-reg", "syscon"; - reg = <0xff 0xe4040000 0x0 0x1000>; - status = "disabled"; - }; - - dspsys_reg: dspsys-reg@ffef040000 { - compatible = "thead,light-dspsys-reg", "syscon"; - reg = <0xff 0xef040000 0x0 0x1000>; - status = "okay"; - }; - - miscsys_reg: miscsys-reg@ffec02c000 { - compatible = "thead,light-miscsys-reg", "syscon"; - reg = <0xff 0xec02c000 0x0 0x1000>; - status = "okay"; - }; - - tee_miscsys_reg: tee_miscsys-reg@fffc02d000 { - compatible = "thead,light-miscsys-reg", "syscon"; - reg = <0xff 0xfc02d000 0x0 0x1000>; - status = "okay"; - }; - - audio_ioctrl: audio_ioctrl@ffcb01d000 { - compatible = "thead,light-audio-ioctrl-reg", "syscon"; - reg = <0xff 0xcb01d000 0x0 0x1000>; - status = "okay"; - }; - - audio_cpr: audio_cpr@ffcb000000 { - compatible = "thead,light-audio-cpr-reg", "syscon"; - reg = <0xff 0xcb000000 0x0 0x1000>; - status = "okay"; - }; - - audio_mbox: audio_mbox@0xffefc48000 { - compatible = "thead,light-audio-mbox-reg", "syscon"; - reg = <0xff 0xefc48000 0x0 0x1000>; - status = "okay"; - }; - - nvmem_controller: efuse@ffff210000 { - compatible = "thead,light-fm-efuse", "syscon"; - reg = <0xff 0xff210000 0x0 0x10000>; - thead,teesys = <&teesys_syscon>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>; - clock-names = "pclk"; - - gmac0_mac_address: mac-address@176 { - reg = <0xb0 6>; - }; - - gmac1_mac_address: mac-address@184 { - reg = <0xb8 6>; - }; - }; - - misc_sysreg: misc_sysreg@ffec02c000 { - compatible = "thead,light-misc-sysreg", "syscon"; - reg = <0xff 0xec02c000 0x0 0x1000>; - status = "okay"; - }; - - usb3_drd: usb3_drd@ffec03f000 { - compatible = "thead,light-usb3-drd", "syscon"; - reg = <0xff 0xec03f000 0x0 0x1000>; - status = "okay"; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLKGEN_GPIO0_PCLK>, - <&clk CLKGEN_GPIO0_DBCLK>; - clock-names = "bus", "db"; - gpio0_porta: gpio0-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <56>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLKGEN_GPIO1_PCLK>, - <&clk CLKGEN_GPIO1_DBCLK>; - clock-names = "bus", "db"; - gpio1_porta: gpio1-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <57>; - }; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLKGEN_GPIO2_PCLK>, - <&clk CLKGEN_GPIO2_DBCLK>; - clock-names = "bus", "db"; - gpio2_porta: gpio2-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <58>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk CLKGEN_GPIO3_PCLK>, - <&clk CLKGEN_GPIO3_DBCLK>; - clock-names = "bus", "db"; - gpio3_porta: gpio3-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <59>; - }; - }; - - ao_gpio: gpio@fffff41000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff41000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - ao_gpio_porta: ao_gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <76>; - }; - }; - - ao_gpio4: gpio@fffff52000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff52000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - ao_gpio4_porta: ao_gpio4-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - nr-gpios-snps = <32>; - reg = <0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <55>; - }; - }; - - padctrl1_apsys: padctrl1-apsys@ffe7f3c000 { - compatible = "thead,light-fm-left-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>; - clock-names = "pclk"; - status = "okay"; - }; - - padctrl0_apsys: padctrl0-apsys@ffec007000 { - compatible = "thead,light-fm-right-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>; - clock-names = "pclk"; - status = "okay"; - }; - - pwm: pwm@ffec01c000 { - compatible = "thead,pwm-light"; - reg = <0xff 0xec01c000 0x0 0x4000>; - #pwm-cells = <2>; - clocks = <&clk CLKGEN_PWM_PCLK>, - <&clk CLKGEN_PWM_CCLK>; - clock-names = "pclk", "cclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <16>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <17>; - interrupt-parent = <&intc>; - status = "okay"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <18>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <19>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - padctrl_aosys: padctrl-aosys@fffff4a000 { - compatible = "thead,light-fm-aon-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - status = "okay"; - }; - - padctrl_audiosys: padctrl-audiosys@ffcb01d000 { - compatible = "thead,light-fm-audio-pinctrl"; - reg = <0xff 0xcb01d000 0x0 0x1000>; - status = "disabled"; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <20>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <21>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <22>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&dummy_clock_apb>; - clock-names = "timer"; - clock-frequency = <62500000>; - interrupts = <23>; - interrupt-parent = <&intc>; - status = "disabled"; - }; - - uart0: serial@ffe7014000 { /* Normal serial, for C910 log */ - compatible = "snps,dw-apb-uart", "light,uart0"; - reg = <0xff 0xe7014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <36>; - clocks = <&clk CLKGEN_UART0_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <37>; - clocks = <&clk CLKGEN_UART1_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "okay"; - }; - - uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <38>; - clocks = <&clk CLKGEN_UART2_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <39>; - clocks = <&clk CLKGEN_UART3_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <40>; - clocks = <&clk CLKGEN_UART4_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "support"; - status = "okay"; - }; - - uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */ - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <41>; - clocks = <&clk CLKGEN_UART5_SCLK>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - hw-flow-control = "unsupport"; - status = "disabled"; - }; - - adc: adc@0xfffff51000 { - compatible = "thead,light-adc"; - reg = <0xff 0xfff51000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <61>; - clocks = <&dummy_clock_aonsys_clk>; - clock-names = "adc"; - /* ADC pin is proprietary,no need to config pinctrl */ - status = "disabled"; - }; - - spi0: spi@ffe700c000 { - compatible = "snps,dw-apb-ssi"; - reg = <0xff 0xe700c000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - interrupt-parent = <&intc>; - interrupts = <54>; - clocks = <&clk CLKGEN_SPI_SSI_CLK>, - <&clk CLKGEN_SPI_PCLK>; - clock-names = "sclk", "pclk"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi0: spi@ffea000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xea000000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - interrupt-parent = <&intc>; - interrupts = <52>; - clocks = <&clk CLKGEN_QSPI0_SSI_CLK>, - <&clk CLKGEN_QSPI0_PCLK>; - clock-names = "sclk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - - qspi1: spi@fff8000000 { - compatible = "snps,dw-apb-ssi-quad"; - reg = <0xff 0xf8000000 0x0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi1>; - interrupt-parent = <&intc>; - interrupts = <53>; - clocks = <&clk CLKGEN_QSPI1_SSI_CLK>, - <&clk CLKGEN_QSPI1_PCLK>; - clock-names = "sclk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - -/* g2d: gc620@ffecc80000 { - compatible = "thead,c910-gc620"; - reg = <0xff 0xecc80000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <101>; - interrupt-names = "irq_2d"; - clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>, - <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>, - <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>; - clock-names = "pclk", "aclk", "cclk"; - status = "okay"; - };*/ - - g2d: gpu@13040000 { - compatible = "vivante,gc"; - reg = <0xff 0xecc80000 0x0 0x40000>; - - clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>, - <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>, - <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>; - clock-names = "bus", "core", "shader"; - - interrupt-parent = <&intc>; - interrupts = <101>; - }; - - dsi0: dw-mipi-dsi0@ffef500000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef500000 0x0 0x10000>; - status = "disabled"; - - dphy_0: dsi0-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi0>; - vosys-regmap = <&vosys_reg>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>, - <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>, - <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>, - <&clk OSC_24M>, - <&clk OSC_24M>; - clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; - #phy-cells = <0>; - }; - - dhost_0: dsi0-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi0>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>, - <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>; - clock-names = "pclk", "pixclk"; - phys = <&dphy_0>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dsi1: dw-mipi-dsi1@ffef510000 { - compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; - reg = <0xff 0xef510000 0x0 0x10000>; - status = "disabled"; - - dphy_1: dsi1-dphy { - compatible = "thead,light-mipi-dphy"; - regmap = <&dsi1>; - vosys-regmap = <&vosys_reg>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>, - <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>, - <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>, - <&clk OSC_24M>, - <&clk OSC_24M>; - clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; - #phy-cells = <0>; - }; - - dhost_1: dsi1-host { - compatible = "verisilicon,dw-mipi-dsi"; - regmap = <&dsi1>; - interrupt-parent = <&intc>; - interrupts = <129>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>, - <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>; - clock-names = "pclk", "pixclk"; - phys = <&dphy_1>; - phy-names = "dphy"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vosys_reg: vosys@ffef528000 { - compatible = "thead,light-vo-subsys", "syscon"; - reg = <0xff 0xef528000 0x0 0x1000>; - status = "okay"; - }; - - hdmi_tx: dw-hdmi-tx@ffef540000 { - compatible = "thead,light-hdmi-tx"; - reg = <0xff 0xef540000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <111>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>, - <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>, - <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>, - <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>; - clock-names = "iahb", "isfr", "cec", "pixclk"; - reg-io-width = <4>; - phy_version = <301>; - /* TODO: add phy property */ - status = "disabled"; - }; - - dpu: dc8200@ffef600000 { - compatible = "verisilicon,dc8200"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff 0xef600000 0x0 0x100>, - <0xff 0xef600800 0x0 0x2000>, - <0xff 0xef630010 0x0 0x60>; - interrupt-parent = <&intc>; - interrupts = <93>; - vosys-regmap = <&vosys_reg>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>, - <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>, - <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>, - <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>, - <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>, - <&clk DPU0_PLL_DIV_CLK>, - <&clk DPU1_PLL_DIV_CLK>, - <&clk DPU0_PLL_FOUTPOSTDIV>, - <&clk DPU1_PLL_FOUTPOSTDIV>; - clock-names = "core_clk", "pix_clk0", "pix_clk1", - "axi_clk", "cfg_clk", "pixclk0", - "pixclk1", "dpu0_pll_foutpostdiv", - "dpu1_pll_foutpostdiv"; - status = "disabled"; - - dpu_disp0: port@0 { - reg = <0>; - - disp0_out: endpoint { - remote-endpoint = <&enc0_in>; - }; - }; - - dpu_disp1: port@1 { - reg = <1>; - - disp1_out: endpoint { - remote-endpoint = <&enc1_in>; - }; - }; - }; - - watchdog0: watchdog@ffefc30000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc30000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <24>; - clocks = <&clk CLKGEN_WDT0_PCLK>; - clock-names = "tclk"; - resets = <&rst LIGHT_RESET_WDT0>; - status = "okay"; - }; - - watchdog1: watchdog@ffefc31000 { - compatible = "snps,dw-wdt"; - reg = <0xff 0xefc31000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <25>; - clocks = <&clk CLKGEN_WDT1_PCLK>; - clock-names = "tclk"; - resets = <&rst LIGHT_RESET_WDT1>; - status = "okay"; - }; - - rtc: rtc@fffff40000 { - compatible = "apm,xgene-rtc"; - reg = <0xff 0xfff40000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <74>; - clocks = <&dummy_clock_rtc>; - clock-names = "rtc"; - wakeup-source; - status = "okay"; - }; - - usb_1: usb@ffec03f000 { - compatible = "thead,dwc3"; - usb3-misc-regmap = <&misc_sysreg>; - usb3-drd-regmap = <&usb3_drd>; - clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK>; - clock-names = "drd", "ctrl", "phy", "suspend"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb: dwc3@ffe7040000 { - compatible = "snps,dwc3"; - reg = <0xff 0xe7040000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <68>; - reg-shift = <2>; - reg-io-width = <4>; - maximum-speed = "super-speed"; - dr_mode = "host"; - dma-mask = <0xf 0xffffffff>; - snps,usb3_lpm_capable; - snps,usb_sofitpsync; - status = "okay"; - }; - }; - - pmu: pmu { - interrupt-parent = <&cpu0_intc>; - interrupts = <17>; - compatible = "riscv,c910_pmu"; - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,light-fm-ree-clk"; - reg = <0xff 0xef010000 0x0 0x1000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; - clock-names = "osc_32k", "osc_24m", "rc_24m"; - status = "okay"; - }; - - rst: reset-controller@ffef014000 { - compatible = "thead,light-reset-src","syscon"; - reg = <0xff 0xef014000 0x0 0x1000>; - #reset-cells = <1>; - status = "okay"; - }; - - vpsys_rst: vpsys-reset-controller@ffecc30000 { - compatible = "thead,light-vpsys-reset-src","syscon"; - reg = <0xff 0xecc30000 0x0 0x1000>; - #reset-cells = <1>; - status = "okay"; - }; - - sys_reg: sys_reg@ffef010100 { - compatible = "thead,light_sys_reg"; - reg = <0xff 0xef010100 0x0 0x100>; - status = "okay"; - }; - - dmac0: dmac@ffefc00000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xefc00000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <27>; - clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - dmac1: tee_dmac@ffff340000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xff340000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <150>; - clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <4>; - snps,block-size = <65536 65536 65536 65536>; - snps,priority = <0 1 2 3>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "disabled"; - }; - - dmac2: audio_dmac@0xFFC8000000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xc8000000 0x0 0x2000>; - interrupt-parent = <&intc>; - interrupts = <167>; - clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>; - clock-names = "core-clk", "cfgr-clk"; - #dma-cells = <1>; - dma-channels = <16>; - snps,block-size = <65536 65536 65536 65536 - 65536 65536 65536 65536 - 65536 65536 65536 65536 - 65536 65536 65536 65536>; - snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; // <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - snps,dma-masters = <1>; - snps,data-width = <4>; - snps,axi-max-burst-len = <16>; - status = "okay"; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <3>; - snps,rd_osr_lmt = <3>; - snps,blen = <16 8 4 0 0 0 0>; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7070000 0x0 0x2000 - 0xff 0xec00301c 0x0 0x4 - 0xff 0xec003020 0x0 0x4 - 0xff 0xec003000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <66>; - interrupt-names = "macirq"; - clocks = <&clk CLKGEN_GMAC0_CCLK>, - <&clk CLKGEN_GMAC0_PCLK>, - <&clk CLKGEN_GMAC_AXI_ACLK>, - <&clk CLKGEN_GMAC_AXI_PCLK>; - clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac0_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - gmac1: ethernet@ffe7060000 { - compatible = "thead,light-dwmac"; - reg = <0xff 0xe7060000 0x0 0x2000 - 0xff 0xec00401c 0x0 0x4 - 0xff 0xec004020 0x0 0x4 - 0xff 0xec004000 0x0 0x1c>; - reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; - interrupt-parent = <&intc>; - interrupts = <67>; - interrupt-names = "macirq"; - clocks = <&clk CLKGEN_GMAC1_CCLK>, - <&clk CLKGEN_GMAC1_PCLK>, - <&clk CLKGEN_GMAC_AXI_ACLK>, - <&clk CLKGEN_GMAC_AXI_PCLK>; - clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - nvmem-cells = <&gmac1_mac_address>; - nvmem-cell-names = "mac-address"; - }; - - emmc: sdhci@ffe7080000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <62>; - interrupt-names = "sdhciirq"; - clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>; - clock-names = "core", "bus"; - }; - - sdhci0: sd@ffe7090000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <64>; - interrupt-names = "sdhci0irq"; - clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>; - clock-names = "core", "bus"; - }; - - sdhci1: sd@ffe70a0000 { - compatible = "snps,dwcmshc-sdhci"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <71>; - interrupt-names = "sdhci1irq"; - clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>; - clock-names = "core", "bus"; - }; - - hwspinlock: hwspinlock@ffefc10000 { - compatible = "light,hwspinlock"; - reg = <0xff 0xefc10000 0x0 0x10000>; - status = "disabled"; - }; - - npu: vha@fffc800000 { - compatible = "img,ax3386-nna"; - reg = <0xff 0xfc800000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <113>; - interrupt-names = "npuirq"; - power-domains = <&pd LIGHT_AON_NPU_PD>; - clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>, - <&clk CLKGEN_TOP_AXI4S_ACLK>; - clock-names = "pclk", "aclk"; - vha_clk_rate = <1000000000>; - ldo_vha-supply = <&npu>; - dma-mask = <0xff 0xffffffff>; - resets = <&rst LIGHT_RESET_NPU>; - status = "disabled"; - }; - - gpu: gpu@ffef400000 { - compatible = "img,gpu"; - reg = <0xff 0xef400000 0x0 0x100000>; - interrupt-parent = <&intc>; - interrupts = <102>; - interrupt-names = "gpuirq"; - vosys-regmap = <&vosys_reg>; - power-domains = <&pd LIGHT_AON_GPU_PD>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>, - <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>; - clock-names = "cclk", "aclk"; - gpu_clk_rate = <18000000>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - fce: fce@fffcc50000 { - compatible = "thead,light-fce"; - reg = <0xff 0xfcc50000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <100>; - interrupt-names = "fceirq"; - clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>, - <&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>; - clock-names = "aclk", "pclk"; - resets = <&vpsys_rst LIGHT_RESET_FCE>; - dma-mask = <0xf 0xffffffff>; - status = "disabled"; - }; - - vdec: vdec@ffecc00000 { - compatible = "thead,light-vc8000d"; - reg = <0xff 0xecc00000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <131>; - power-domains = <&pd LIGHT_AON_VDEC_PD>; - clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>, - <&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>, - <&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>; - clock-names = "aclk", "cclk", "pclk"; - status = "disabled"; - }; - - venc: venc@ffecc10000 { - compatible = "thead,light-vc8000e"; - reg = <0xff 0xecc10000 0x0 0x8000>; - interrupt-parent = <&intc>; - interrupts = <133>; - power-domains = <&pd LIGHT_AON_VENC_PD>; - clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>, - <&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>, - <&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>; - clock-names = "aclk", "cclk", "pclk"; - status = "disabled"; - }; - - isp_venc_shake: shake@ffe4078000 { - compatible = "thead,light-ivs"; - reg = <0xff 0xe4078000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <158>; - status = "disabled"; - }; - - vidmem: vidmem@ffecc08000 { - compatible = "thead,light-vidmem"; - reg = <0xff 0xecc08000 0x0 0x1000>; - status = "disabled"; - }; - - light_i2s: light_i2s@ffe7034000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xe7034000 0x0 0x4000>; - light,mode = "i2s-master"; - light,sel = "ap_i2s"; - interrupt-parent = <&intc>; - interrupts = <70>; - dmas = <&dmac0 35>, <&dmac0 40>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s0: audio_i2s0@0xffcb014000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xcb014000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s0"; - interrupt-parent = <&intc>; - interrupts = <174>; - dmas = <&dmac2 9>, <&dmac2 8>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S0>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s1: audio_i2s1@0xffcb015000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xcb015000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s1"; - interrupt-parent = <&intc>; - interrupts = <175>; - dmas = <&dmac2 11>, <&dmac2 10>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S1>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s2: audio_i2s2@0xffcb016000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s"; - reg = <0xff 0xcb016000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s2"; - interrupt-parent = <&intc>; - interrupts = <176>; - dmas = <&dmac2 13>, <&dmac2 12>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S2>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s_8ch_sd0: audio_i2s_8ch_sd0@0xffcb017000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s-8ch"; - reg = <0xff 0xcb017000 0x0 0x1000>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s_8ch_sd0"; - interrupt-parent = <&intc>; - interrupts = <177>; - dmas = <&dmac2 36>, <&dmac2 14>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s_8ch_sd1: audio_i2s_8ch_sd1@0xffcb017000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s-8ch"; - reg = <0xff 0xcb017000 0x0 0x1000>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s_8ch_sd1"; - interrupt-parent = <&intc>; - interrupts = <177>; - dmas = <&dmac2 37>, <&dmac2 15>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s_8ch_sd2: audio_i2s_8ch_sd2@0xffcb017000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s-8ch"; - reg = <0xff 0xcb017000 0x0 0x1000>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s_8ch_sd2"; - interrupt-parent = <&intc>; - interrupts = <177>; - dmas = <&dmac2 38>, <&dmac2 16>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; - clock-names = "pclk"; - status = "disabled"; - }; - - i2s_8ch_sd3: audio_i2s_8ch_sd3@0xffcb017000 { - #sound-dai-cells = <1>; - compatible = "light,light-i2s-8ch"; - reg = <0xff 0xcb017000 0x0 0x1000>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,sel = "i2s_8ch_sd3"; - interrupt-parent = <&intc>; - interrupts = <177>; - dmas = <&dmac2 39>, <&dmac2 17>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot1: audio_tdm_slot1@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <1>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 28>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot2: audio_tdm_slot2@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <2>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 29>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot3: audio_tdm_slot3@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <3>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 30>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot4: audio_tdm_slot4@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <4>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 31>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot5: audio_tdm_slot5@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <5>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 32>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot6: audio_tdm_slot6@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <6>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 33>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot7: audio_tdm_slot7@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <7>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 34>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - tdm_slot8: audio_tdm_slot8@0xffcb012000 { - #sound-dai-cells = <0>; - compatible = "light,light-tdm"; - reg = <0xff 0xcb012000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - light,mode = "i2s-master"; - light,tdm_slots = <8>; - light,tdm_slot_num = <8>; - interrupt-parent = <&intc>; - interrupts = <178>; - dmas = <&dmac2 35>; - dma-names = "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; - clock-names = "pclk"; - status = "disabled"; - }; - - spdif0: audio_spdif0@0xffcb018000 { - #sound-dai-cells = <0>; - compatible = "light,light-spdif"; - reg = <0xff 0xcb018000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - interrupt-parent = <&intc>; - interrupts = <179>; - dmas = <&dmac2 25>, <&dmac2 24>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF0>; - clock-names = "pclk"; - id = <0>; - status = "disabled"; - }; - - spdif1: audio_spdif1@0xffcb019000 { - #sound-dai-cells = <0>; - compatible = "light,light-spdif"; - reg = <0xff 0xcb019000 0x0 0x1000>; - audio-pin-regmap = <&audio_ioctrl>; - audio-cpr-regmap = <&audio_cpr>; - pinctrl-names = "default"; - interrupt-parent = <&intc>; - interrupts = <180>; - dmas = <&dmac2 27>, <&dmac2 26>; - dma-names = "tx", "rx"; - light,dma_maxburst = <4>; - #dma-cells = <1>; - clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF1>; - clock-names = "pclk"; - id = <1>; - status = "disabled"; - }; - - pvt: pvt@fffff4e000 { - compatible = "moortec,mr75203"; - reg = <0xff 0xfff4e000 0x0 0x80>, - <0xff 0xfff4e080 0x0 0x100>, - <0xff 0xfff4e180 0x0 0x680>, - <0xff 0xfff4e800 0x0 0x600>; - reg-names = "common", "ts", "pd", "vm"; - clocks = <&dummy_clock_aonsys_clk>; - #thermal-sensor-cells = <1>; - status = "okay"; - }; - - i2c0: i2c@ffe7f20000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f20000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <44>; - clocks = <&clk CLKGEN_I2C0_PCLK>; - clock-names = "pclk"; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@ffe7f24000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f24000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <45>; - clocks = <&clk CLKGEN_I2C1_PCLK>; - clock-names = "pclk"; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@ffec00c000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec00c000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <46>; - clocks = <&clk CLKGEN_I2C2_PCLK>; - clock-names = "pclk"; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac0 16>, <&dmac0 17>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@ffec014000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xec014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <47>; - clocks = <&clk CLKGEN_I2C3_PCLK>; - clock-names = "pclk"; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac0 18>, <&dmac0 19>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@ffe7f28000{ - compatible = "snps,designware-i2c"; - reg = <0xff 0xe7f28000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <48>; - clocks = <&clk CLKGEN_I2C4_PCLK>; - clock-names = "pclk"; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac0 20>, <&dmac0 21>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x104>; - ss_lcnt = /bits/ 16 <0xec>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x9>; - hs_lcnt = /bits/ 16 <0x11>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - audio_i2c0: i2c@0xffcb01a000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xcb01a000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <182>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac2 21>, <&dmac2 20>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x82>; - ss_lcnt = /bits/ 16 <0x78>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; - #address-cells = <1>; - #size-cells = <0>; - }; - - audio_i2c1: i2c@0xffcb01b000 { - compatible = "snps,designware-i2c"; - reg = <0xff 0xcb01b000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <183>; - clocks = <&dummy_clock_apb>; - clock-frequency = <100000>; - i2c_mode = "dma"; - dmas = <&dmac2 23>, <&dmac2 22>; - dma-names = "tx", "rx"; - #dma-cells = <1>; - ss_hcnt = /bits/ 16 <0x82>; - ss_lcnt = /bits/ 16 <0x78>; - fs_hcnt = /bits/ 16 <0x37>; - fs_lcnt = /bits/ 16 <0x42>; - fp_hcnt = /bits/ 16 <0x14>; - fp_lcnt = /bits/ 16 <0x1a>; - hs_hcnt = /bits/ 16 <0x5>; - hs_lcnt = /bits/ 16 <0x15>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - isp0: isp@ffe4100000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <117>,<118>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>; - clock-names = "aclk", "hclk", "isp0_pclk", "cclk"; - status = "disabled"; - }; - - isp1: isp@ffe4110000 { - compatible = "thead,light-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <120>,<121>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>; - clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk"; - status = "disabled"; - }; - - isp_ry0: isp_ry@ffe4120000 { - compatible = "thead,light-isp_ry"; - reg = <0xff 0xe4120000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <123>,<124>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>; - clock-names = "aclk", "hclk", "cclk"; - status = "disabled"; - }; - - dewarp: dewarp@ffe4130000 { - compatible = "thead,light-dewarp"; - reg = <0xff 0xe4130000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <98>,<99>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>, - <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>, - <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>; - clock-names = "aclk", "hclk", "vseclk", "dweclk"; - status = "disabled"; - }; - - dec400_isp0: dec400@ffe4060000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4060000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp1: dec400@ffe4068000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4068000 0x0 0x8000>; - status = "disabled"; - }; - - dec400_isp2: dec400@ffe4070000 { - compatible = "thead,dec400"; - reg = <0xff 0xe4070000 0x0 0x8000>; - status = "disabled"; - }; - - bm_visys: bm_visys@ffe4040000 { - compatible = "thead,light-bm-visys"; - reg = <0xff 0xe4040000 0x0 0x1000>; - status = "disabled"; - }; - - bm_csi0: csi@ffe4000000{ //CSI2 - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4000000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <128>; - dphyglueiftester = <0x180>; - sysreg_mipi_csi_ctrl = <0x140>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>; - clock-names = "pclk", "pixclk", "cfg_clk"; - phy_name = "CSI_4LANE"; - status = "disabled"; - }; - - csia_reg: visys-reg@ffe4020000 { - compatible = "thead,light-visys-reg", "syscon"; - reg = < 0xff 0xe4020000 0x0 0x10000>; - status = "okay"; - }; - - bm_csi1: csi@ffe4010000{ //CSI2X2_B - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4010000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0 - dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed. - sysreg_mipi_csi_ctrl = <0x148>; - visys-regmap = <&visys_reg>; - csia-regmap = <&csia_reg>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>; - clock-names = "pclk", "pixclk", "cfg_clk"; - phy_name = "CSI_B"; - status = "disabled"; - }; - - bm_csi2: csi@ffe4020000{ //CSI2X2_A - compatible = "thead,light-bm-csi"; - reg = < 0xff 0xe4020000 0x0 0x10000>; - interrupt-parent = <&intc>; - interrupts = <127>; - dphyglueiftester = <0x184>; - sysreg_mipi_csi_ctrl = <0x144>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>, - <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; - clock-names = "pclk", "pixclk", "cfg_clk"; - phy_name = "CSI_A"; - status = "disabled"; - }; - - bm_isp0: bm_isp@ffe4100000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4100000 0x0 0x10000>; - status = "disabled"; - }; - - bm_isp1: bm_isp@ffe4110000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4110000 0x0 0x10000>; - status = "disabled"; - }; - - //isp-ry - bm_isp2: bm_isp@ffe4120000 { - compatible = "thead,light-bm-isp"; - reg = <0xff 0xe4120000 0x0 0x10000>; - status = "disabled"; - }; - - vi_pre: vi_pre@ffe4030000 { - compatible = "thead,vi_pre"; - reg = <0xff 0xe4030000 0x0 0x1000>; - interrupt-parent = <&intc>; - interrupts = <134>; - clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>, - <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>, - <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>; - clock-names ="aclk", "pclk", "pixclk"; - status = "disabled"; - }; - - video0: cam_dev@100 { - compatible = "thead,video"; - status = "disabled"; - }; - - video1: cam_dev@200 { - compatible = "thead,video"; - status = "disabled"; - }; - - video2: cam_dev@300 { - compatible = "thead,video"; - status = "disabled"; - }; - - video3: cam_dev@400 { - compatible = "thead,video"; - status = "disabled"; - }; - - video4: cam_dev@500 { - compatible = "thead,video"; - status = "disabled"; - }; - - video5: cam_dev@600 { - compatible = "thead,video"; - status = "disabled"; - }; - - video6: cam_dev@700 { - compatible = "thead,video"; - status = "disabled"; - }; - - video7: cam_dev@800 { - compatible = "thead,video"; - status = "disabled"; - }; - - video8: cam_dev@900 { - compatible = "thead,video"; - status = "disabled"; - }; - - video9: cam_dev@a00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video10: cam_dev@b00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video11: cam_dev@c00 { - compatible = "thead,video"; - status = "disabled"; - }; - video12: cam_dev@d00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video13: cam_dev@e00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video14: cam_dev@f00 { - compatible = "thead,video"; - status = "disabled"; - }; - - video15: cam_dev@f01 { - compatible = "thead,video"; - status = "disabled"; - }; - - vvcam_flash_led0: vvcam_flash_led@0 { - compatible = "thead,light-vvcam-flash_led"; - status = "disabled"; - }; - - vvcam_sensor0: vvcam_sensor@0 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor1: vvcam_sensor@1 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor2: vvcam_sensor@2 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor3: vvcam_sensor@3 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor4: vvcam_sensor@4 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor5: vvcam_sensor@5 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor6: vvcam_sensor@6 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - vvcam_sensor7: vvcam_sensor@7 { - compatible = "thead,light-vvcam-sensor"; - status = "disabled"; - }; - - xtensa_dsp: dsp@01{ - compatible = "thead,dsp-hw-common"; - reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */ - status = "disabled"; - }; - - xtensa_dsp0: dsp@0 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef048000 0x0 0x008000>; /* DSP shared memory */ - dsp = <0>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <156>; - firmware-name = "xrp0.elf"; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "cclk"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe0180000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - xtensa_dsp1: dsp@1 { - compatible = "cdns,xrp-hw-simple"; - reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */ - 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */ - 0xff 0xef050000 0x0 0x008000>; /* DSP shared memory */ - dsp = <1>; - dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ - dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ - device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ - device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ - device-irq-mode = <1>; /*level trigger*/ - host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ - host-irq-mode = <1>; /*level trigger */ - host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ - interrupt-parent = <&intc>; - interrupts = <157>; - firmware-name = "xrp1.elf"; - clocks = <&dummy_clock_visys>, - <&dummy_clock_visys>; - clock-names = "pclk", "cclk"; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - dsp@0 { - ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 - 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 - 0x00 0xfa000000 0xff 0xe0000000 0x00180000 - 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 - 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ - }; - }; - - pmp: pmp@ffdc020000 { - compatible = "pmp"; - reg = <0xff 0xdc020000 0x0 0x1000>; - }; - - mrvbr: mrvbr@ffff018050 { - compatible = "mrvbr"; - reg = <0xff 0xff019050 0x0 0x1000>; - }; - - mrmr: mrmr@ffff014004 { - compatible = "mrmr"; - reg = <0xff 0xff015004 0x0 0x1000>; - }; - - bmu: ddr-pmu@ffff008000 { - compatible = "thead,light-ddr-pmu"; - reg = <0xff 0xff008000 0x0 0x800 - 0xff 0xff008800 0x0 0x800 - 0xff 0xff009000 0x0 0x800 - 0xff 0xff009800 0x0 0x800 - 0xff 0xff00a000 0x0 0x800>; - interrupt-parent = <&intc>; - interrupts = <87>; - status = "okay"; - }; - - mbox_910t: mbox@ffffc38000 { - compatible = "thead,light-mbox"; - reg = <0xff 0xffc38000 0x0 0x4000>, - <0xff 0xffc44000 0x0 0x1000>, - <0xff 0xffc4c000 0x0 0x1000>, - <0xff 0xffc54000 0x0 0x1000>; - reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; - interrupt-parent = <&intc>; - interrupts = <28>; - clocks = <&dummy_clock_apb>; - clock-names = "ipg"; - icu_cpu_id = <0>; - #mbox-cells = <2>; - }; - - trng: rng@ffff300000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xff 0xff300000 0x0 0x7d>; - interrupt-parent = <&intc>; - interrupts = <149>; - clocks = <&dummy_clock_eip>; - status = "disabled"; - }; - - - eip_28: eip-28@ffff300000 { - compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28"; - reg = <0xff 0xff300000 0x0 0x40000>; - interrupt-parent = <&intc>; - interrupts = <144>,<145>,<146>,<147>; - clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SI_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SII_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SIII_CLK>, - <&miscsys_clk_gate CLKGEN_MISCSYS_EIP150B_HCLK>; - clock-names = "120si_clk","120sii_clk","120siii_clk","hclk"; - status = "disabled"; - }; - - khvhost: khvhost { - compatible = "thead,khv-host"; - interrupt-parent = <&intc>; - interrupts = <215>; /* TEE INT SRC_7 */ - }; - - light_event: light-event { - compatible = "thead,light-event"; - aon-iram-regmap = <&aon_iram>; - status = "okay"; - }; - - aon_suspend_ctrl: aon_suspend_ctrl { - compatible = "thead,light-aon-suspend-ctrl"; - status = "okay"; - }; - - visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */ - compatible = "thead,visys-gate-controller"; - visys-regmap = <&visys_reg>; - #clock-cells = <1>; - status = "okay"; - }; - - vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */ - compatible = "thead,vpsys-gate-controller"; - reg = <0xff 0xecc30000 0x0 0x1000>; - #clock-cells = <1>; - status = "okay"; - }; - - vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */ - compatible = "thead,vosys-gate-controller"; - reg = <0xff 0xef528000 0x0 0x1000>; - #clock-cells = <1>; - status = "okay"; - }; - - dspsys_clk_gate: dspsys-clk-gate { - compatible = "thead,dspsys-gate-controller"; - dspsys-regmap = <&dspsys_reg>; - #clock-cells = <1>; - status = "okay"; - }; - - audiosys_clk_gate: audiosys-clk-gate { - compatible = "thead,audiosys-gate-controller"; - audiosys-regmap = <&audio_cpr>; - #clock-cells = <1>; - status = "okay"; - }; - - miscsys_clk_gate: miscsys-clk-gate { - compatible = "thead,miscsys-gate-controller"; - miscsys-regmap = <&miscsys_reg>; - tee-miscsys-regmap = <&tee_miscsys_reg>; - #clock-cells = <1>; - status = "okay"; - }; - - }; - -}; - diff --git a/arch/riscv/boot/dts/thead/light_mpw.dts b/arch/riscv/boot/dts/thead/light_mpw.dts deleted file mode 100644 index 9ded4be25d13..000000000000 --- a/arch/riscv/boot/dts/thead/light_mpw.dts +++ /dev/null @@ -1,259 +0,0 @@ -/dts-v1/; -/ { - model = "T-HEAD c910 light mpw"; - compatible = "thead,c910_light_mpw"; - #address-cells = <2>; - #size-cells = <2>; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00200000 0x0 0xf0000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <0x2dc6c0>; - cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@1 { - device_type = "cpu"; - reg = <1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@2 { - device_type = "cpu"; - reg = <2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu@3 { - device_type = "cpu"; - reg = <3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcvsu"; - mmu-type = "riscv,sv39"; - cpu-freq = "1.5Ghz"; - cpu-icache = "64KB"; - cpu-dcache = "64KB"; - cpu-l2cache = "2MB"; - cpu-tlb = "1024 4-ways"; - cpu-cacheline = "64Bytes"; - cpu-vector = "0.7.1"; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - reset: reset-sample { - compatible = "thead,reset-sample"; - plic-delegate = <0xff 0xd81ffffc>; - using-csr-reset; - csr-copy = < - 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc - 0x3b0 0x3b1 0x3b2 0x3b3 - 0x3b4 0x3b5 0x3b6 0x3b7 - 0x3a0 - >; - }; - - clint0: clint@ffdc000000 { - compatible = "riscv,clint0"; - interrupts-extended = < - &cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - >; - reg = <0xff 0xdc000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; - }; - - intc: interrupt-controller@ffd8000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff &cpu0_intc 9 - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - >; - reg = <0xff 0xd8000000 0x0 0x08000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <80>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_apb: apb-clock { - compatible = "fixed-clock"; - clock-frequency = <62500000>; - clock-output-names = "dummy_apb"; - #clock-cells = <0>; - }; - - dummy_clock_sdhci: sdhci-clock { - compatible = "fixed-clock"; - reg = <4>; /* Not address, just for index */ - clock-frequency = <198000000>; - clock-output-names = "dummy_clock_sdhci"; - #clock-cells = <0>; - }; - - dummy_clock_gmac: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <1000000000>; - clock-output-names = "dummy_clock_gmac"; - #clock-cells = <0>; - }; - }; - - serial@ffe7014000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x4000>; - interrupt-parent = <&intc>; - interrupts = <36>; - clocks = <&dummy_apb>; - clock-names = "baudclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <3>; - snps,rd_osr_lmt = <3>; - snps,blen = <16 8 4 0 0 0 0>; - }; - - gmac: ethernet@ffe7070000 { - compatible = "snps,dwmac"; - reg = <0xff 0xe7070000 0x0 0x2000>; - interrupt-parent = <&intc>; - interrupts = <66>; - interrupt-names = "macirq"; - clocks = <&dummy_clock_gmac>; - clock-names = "stmmaceth"; - snps,pbl = <32>; - snps,fixed-burst; - snps,axi-config = <&stmmac_axi_setup>; - - phy-mode = "rgmii-txid"; - phy-handle = <&phy_88E1111>; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy_88E1111: ethernet-phy@0 { - reg = <0x1>; - }; - }; - }; - - emmc: sdhci@ffe7080000 { - compatible = "snps,dwcmshc-sdhci-light-mpw"; - reg = <0xff 0xe7080000 0x0 0x10000 - 0xff 0xEF014060 0x0 0x4>; - interrupt-parent = <&intc>; - interrupts = <62>; - interrupt-names = "sdhciirq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - max-frequency = <198000000>; - non-removable; - is_emmc; - no-sdio; - no-sd; - no-1-8-v; - bus-width = <8>; - status = "okay"; - }; - - sdcard: sd@ffe7090000 { - compatible = "snps,dwcmshc-sdhci-light-mpw"; - reg = <0xff 0xe7090000 0x0 0x10000 - 0xff 0xEF014064 0x0 0x4>; - interrupt-parent = <&intc>; - interrupts = <64>; - interrupt-names = "sdhci0irq"; - clocks = <&dummy_clock_sdhci>; - clock-names = "core"; - max-frequency = <198000000>; - bus-width = <4>; - status = "okay"; - }; - - pmu: pmu { - interrupt-parent = <&cpu0_intc>; - interrupts = <17>; - compatible = "riscv,c910_pmu"; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 root=PARTUUID=80a5a8e9-c744-491a-93c1-4f4194fd690b rootfstype=ext4 rdinit=/sbin/init rootwait rw earlyprintk clk_ignore_unused loglevel=7 eth=00:a0:a0:a0:a0:a1"; - stdout-path = "/soc/serial@ffe7014000:115200"; - }; -}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-audio-i2s-8ch.dts b/arch/riscv/boot/dts/thead/th1520-a-val-audio-i2s-8ch.dts new file mode 100644 index 000000000000..483ec2f9f489 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-audio-i2s-8ch.dts @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "th1520-a-val-audio.dts" + +/ { + model = "T-HEAD Light FM Audio VAL board"; + compatible = "thead,light-val-audio-i2s-8ch", "thead,light"; +}; + + +&lightsound { + status = "okay"; + + simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_sd2>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&es7210_audio_codec_adc0>; + }; + }; + + simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 7210*/ + reg = <2>; + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_sd3>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&es7210_audio_codec_adc0>; + }; + }; + + simple-audio-card,dai-link@3 { /* I2S - AUDIO SYS CODEC 7210_1*/ + reg = <3>; + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_sd0>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&es7210_audio_codec_adc1>; + }; + }; + + simple-audio-card,dai-link@4 { /* I2S - AUDIO SYS CODEC 7210_1*/ + reg = <4>; + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_sd1>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&es7210_audio_codec_adc1>; + }; + }; +}; + +&i2s_8ch_sd0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa4>, + <&pinctrl_audio_i2s_8ch_sd0>, + <&pinctrl_audiopa2>, + <&pinctrl_audiopa3>, + <&pinctrl_audiopa8>, + <&pinctrl_audio_i2s_8ch_bus>; +}; + +&i2s_8ch_sd1 { + status = "okay"; +}; + +&i2s_8ch_sd2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa0>, + <&pinctrl_audio_i2s_8ch_sd2>; +}; + +&i2s_8ch_sd3 { + status = "okay"; +}; + +&es7210_audio_codec_adc0 { + status = "okay"; + channels-max = <8>; +}; + +&es7210_audio_codec_adc1 { + status = "okay"; + channels-max = <8>; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-audio-spdif.dts b/arch/riscv/boot/dts/thead/th1520-a-val-audio-spdif.dts new file mode 100644 index 000000000000..a83d3f89494e --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-audio-spdif.dts @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "th1520-a-val.dtsi" + +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_spdif0>; + status = "okay"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_spdif1>; + status = "okay"; +}; + +&lightsound { + status = "okay"; + simple-audio-card,dai-link@0 { /* SPDIF0 */ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&spdif0>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + simple-audio-card,dai-link@1 { /* SPDIF1 */ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&spdif1>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-audio-tdm.dts b/arch/riscv/boot/dts/thead/th1520-a-val-audio-tdm.dts new file mode 100644 index 000000000000..084bb01fdfeb --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-audio-tdm.dts @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "th1520-a-val.dtsi" + +&tdm_slot1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_tdm>; + status = "okay"; +}; + +&tdm_slot2 { + status = "okay"; +}; + +&tdm_slot3 { + status = "okay"; +}; + +&tdm_slot4 { + status = "okay"; +}; + +&tdm_slot5 { + status = "okay"; +}; + +&tdm_slot6 { + status = "okay"; +}; + +&tdm_slot7 { + status = "okay"; +}; + +&tdm_slot8 { + status = "okay"; +}; + +&audio_i2c0 { + clock-frequency = <100000>; + status = "okay"; + + es7210_adc2: es7210@42 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x42>; + work-mode = "ES7210_TDM_1LRCK_DSPB"; + channels-max = <8>; + sound-name-prefix = "ES7210_ADC2"; + MVDD-supply = <&soc_aud_adc_3v3_en_reg>; + AVDD-supply = <&soc_aud_adc_3v3_en_reg>; + DVDD-supply = <&soc_dvdd18_aon_reg>; + PVDD-supply = <&soc_dvdd18_aon_reg>; + }; + + es7210_adc3: es7210@43 { + #sound-dai-cells = <0>; + compatible = "MicArray_1"; + reg = <0x43>; + work-mode = "ES7210_TDM_1LRCK_DSPB"; + channels-max = <8>; + sound-name-prefix = "ES7210_ADC3"; + MVDD-supply = <&soc_aud_adc_3v3_en_reg>; + AVDD-supply = <&soc_aud_adc_3v3_en_reg>; + DVDD-supply = <&soc_dvdd18_aon_reg>; + PVDD-supply = <&soc_dvdd18_aon_reg>; + }; +}; + +&lightsound { + status = "okay"; + simple-audio-card,widgets = "Speaker", "Speaker"; + simple-audio-card,routing = + "AW87519 IN", "ES8156 ROUT", + "Speaker", "AW87519 VO"; + simple-audio-card,aux-devs = <&audio_aw87519_pa>; + simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ + reg = <0>; + format = "i2s"; + cpu { + sound-dai = <&i2s0 0>; + }; + codec { + sound-dai = <&es8156_audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { /* TDM - AUDIO SYS CODEC 7210*/ + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot1>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@2 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot2>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@3 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot3>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@4 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot4>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@5 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot5>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@6 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot6>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@7 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot7>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; + + simple-audio-card,dai-link@8 { + reg = <1>; + format = "dsp_b"; + cpu { + sound-dai = <&tdm_slot8>; + }; + codec { + sound-dai = <&es7210_adc2>; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-audio.dts b/arch/riscv/boot/dts/thead/th1520-a-val-audio.dts new file mode 100644 index 000000000000..1d119ec61a87 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-audio.dts @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "th1520-a-val.dtsi" + +/ { + model = "T-HEAD Light FM Audio VAL board"; + compatible = "thead,light-val-audio", "thead,light"; +}; + +&lightsound { + status = "okay"; + simple-audio-card,widgets = "Speaker", "Speaker"; + simple-audio-card,routing = + "Speaker", "AW87519 VO", + "AW87519 IN", "ES8156 ROUT"; + simple-audio-card,aux-devs = <&audio_aw87519_pa>; + simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ + reg = <0>; + format = "i2s"; + cpu { + sound-dai = <&i2s0 0>; + }; + codec { + sound-dai = <&es8156_audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_sd2 2>; + }; + codec { + sound-dai = <&es7210_audio_codec_adc0>; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s_8ch_sd2 { + status = "okay"; +}; + +&es7210_audio_codec_adc0 { + status = "okay"; +}; + + diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-crash.dts b/arch/riscv/boot/dts/thead/th1520-a-val-crash.dts new file mode 100644 index 000000000000..1232f1284a8f --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-crash.dts @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "th1520-crash.dtsi" + +&aon { + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-dsi0-dsi1.dts b/arch/riscv/boot/dts/thead/th1520-a-val-dsi0-dsi1.dts new file mode 100644 index 000000000000..25dcef39cc13 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-dsi0-dsi1.dts @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-a-val-dsi0.dts" + +&dpu_enc1 { + status = "okay"; + + ports { + /* output */ + port@1 { + reg = <1>; + + enc1_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; +}; + +&dsi1 { + status = "okay"; +}; + +&dhost_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi1_in: endpoint { + remote-endpoint = <&enc1_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi1_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; + + panel1@0 { + compatible = "txd,dy800qwxpab"; + reg = <0>; + reset-gpio = <&gpio1_porta 9 1>; /* active low */ + vdd1v8-supply = <&lcd1_1v8>; + vspn5v7-supply = <&lcd1_5v7>; + + port { + panel1_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-dsi0-hdmi.dts b/arch/riscv/boot/dts/thead/th1520-a-val-dsi0-hdmi.dts new file mode 100644 index 000000000000..f449ae43ec58 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-dsi0-hdmi.dts @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-a-val-dsi0.dts" + +&dpu_enc1 { + ports { + /delete-node/ port@0; + }; +}; + +&disp1_out { + remote-endpoint = <&hdmi_tx_in>; +}; + +&hdmi_tx { + status = "okay"; + + port@0 { + /* input */ + hdmi_tx_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-dsi0.dts b/arch/riscv/boot/dts/thead/th1520-a-val-dsi0.dts new file mode 100644 index 000000000000..7fdeb2a22d7b --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-dsi0.dts @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-a-val.dtsi" + +/ { + display-subsystem { + status = "okay"; + }; +}; + +&dpu_enc0 { + status = "okay"; + + ports { + /* output */ + port@1 { + reg = <1>; + + enc0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; +}; + +&dpu { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dhost_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_in: endpoint { + remote-endpoint = <&enc0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; + + panel0@0 { + compatible = "txd,dy800qwxpab"; + reg = <0>; + backlight = <&lcd0_backlight>; + reset-gpio = <&gpio1_porta 5 1>; /* active low */ + vdd1v8-supply = <&lcd0_1v8>; + vspn5v7-supply = <&lcd0_5v7>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val-sec.dts b/arch/riscv/boot/dts/thead/th1520-a-val-sec.dts new file mode 100644 index 000000000000..35213b1a2d80 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val-sec.dts @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-a-val.dts" + + +&light_iopmp { + status = "disabled"; +}; + +&eip_28 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val.dts b/arch/riscv/boot/dts/thead/th1520-a-val.dts new file mode 100644 index 000000000000..bc68497bf7a7 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val.dts @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-a-val-audio.dts" + +/ { + display-subsystem { + status = "okay"; + }; +}; + +&dpu_enc1 { + ports { + /delete-node/ port@0; + }; +}; + +&disp1_out { + remote-endpoint = <&hdmi_tx_in>; +}; + +&dpu { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + port@0 { + /* input */ + hdmi_tx_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; +}; + +&lightsound { + status = "okay"; + + simple-audio-card,dai-link@2 { /* I2S - HDMI */ + reg = <2>; + format = "i2s"; + cpu { + sound-dai = <&light_i2s 1>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; +}; + +&light_i2s { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-a-val.dtsi b/arch/riscv/boot/dts/thead/th1520-a-val.dtsi new file mode 100644 index 000000000000..db9c83093334 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-a-val.dtsi @@ -0,0 +1,2703 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021-2022 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520.dtsi" +#include +#include +#include "th1520-vi-devices.dtsi" + +/ { + model = "T-HEAD Light val board"; + compatible = "thead,light-val", "thead,light"; + + chosen { + bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; + stdout-path = "serial0"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "SYS_STATUS"; + gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ + default-state = "off"; + }; + }; + + lcd0_backlight: pwm-backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + lcd1_backlight: pwm-backlight@1 { + compatible = "pwm-backlight"; + pwms = <&pwm 1 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + light_iopmp: iopmp { + compatible = "thead,light-iopmp"; + + /* config#1: multiple valid regions */ + iopmp_emmc: IOPMP_EMMC { + regions = <0x000000 0x100000>, + <0x100000 0x200000>; + attr = <0xFFFFFFFF>; + dummy_slave= <0x800000>; + }; + + /* config#2: iopmp bypass */ + iopmp_sdio0: IOPMP_SDIO0 { + bypass_en; + }; + + /* config#3: iopmp default region set */ + iopmp_sdio1: IOPMP_SDIO1 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_usb0: IOPMP_USB0 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_ao: IOPMP_AO { + is_default_region; + }; + + iopmp_aud: IOPMP_AUD { + is_default_region; + }; + + iopmp_chip_dbg: IOPMP_CHIP_DBG { + is_default_region; + }; + + iopmp_eip120i: IOPMP_EIP120I { + is_default_region; + }; + + iopmp_eip120ii: IOPMP_EIP120II { + is_default_region; + }; + + iopmp_eip120iii: IOPMP_EIP120III { + is_default_region; + }; + + iopmp_isp0: IOPMP_ISP0 { + is_default_region; + }; + + iopmp_isp1: IOPMP_ISP1 { + is_default_region; + }; + + iopmp_dw200: IOPMP_DW200 { + is_default_region; + }; + + iopmp_vipre: IOPMP_VIPRE { + is_default_region; + }; + + iopmp_venc: IOPMP_VENC { + is_default_region; + }; + + iopmp_vdec: IOPMP_VDEC { + is_default_region; + }; + + iopmp_g2d: IOPMP_G2D { + is_default_region; + }; + + iopmp_fce: IOPMP_FCE { + is_default_region; + }; + + iopmp_npu: IOPMP_NPU { + is_default_region; + }; + + iopmp0_dpu: IOPMP0_DPU { + bypass_en; + }; + + iopmp1_dpu: IOPMP1_DPU { + bypass_en; + }; + + iopmp_gpu: IOPMP_GPU { + is_default_region; + }; + + iopmp_gmac1: IOPMP_GMAC1 { + is_default_region; + }; + + iopmp_gmac2: IOPMP_GMAC2 { + is_default_region; + }; + + iopmp_dmac: IOPMP_DMAC { + is_default_region; + }; + + iopmp_tee_dmac: IOPMP_TEE_DMAC { + is_default_region; + }; + + iopmp_dsp0: IOPMP_DSP0 { + is_default_region; + }; + + iopmp_dsp1: IOPMP_DSP1 { + is_default_region; + }; + + iopmp_audio0: IOPMP_AUDIO0 { + is_default_region; + }; + + iopmp_audio1: IOPMP_AUDIO1 { + is_default_region; + }; + }; + + mbox_910t_client1: mbox_910t_client1 { + compatible = "thead,light-mbox-client"; + mbox-names = "902"; + mboxes = <&mbox_910t 1 0>; + status = "disabled"; + }; + + + mbox_910t_client2: mbox_910t_client2 { + compatible = "thead,light-mbox-client"; + mbox-names = "906"; + mboxes = <&mbox_910t 2 0>; + audio-mbox-regmap = <&audio_mbox>; + status = "okay"; + }; + + lightsound: lightsound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Light-Sound-Card"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + light_rpmsg: light_rpmsg { + compatible = "light,rpmsg-bus", "simple-bus"; + memory-region = <&rpmsgmem>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + rpmsg: rpmsg{ + vdev-nums = <1>; + reg = <0x0 0x1E000000 0 0x10000>; + compatible = "light,light-rpmsg"; + status = "okay"; + }; + }; + + dummy_codec: dummy_codec { + #sound-dai-cells = <0>; + compatible = "thead,light-dummy-pcm"; + sound-name-prefix = "DUMMY"; + status = "okay"; + }; + + reg_vref_1v8: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + reg_tp_pwr_en: regulator-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "PWR_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_a 3 1>; + enable-active-high; + regulator-always-on; + }; + + reg_tp1_pwr_en: regulator-tp1-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "PWR_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_a 6 1>; + enable-active-high; + regulator-always-on; + }; + + lcd0_1v8: regulator-lcd0-vdd18 { + compatible = "regulator-fixed"; + regulator-name = "lcd0_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_a 2 0>; + enable-active-high; + }; + + lcd0_5v7: regulator-lcd0-vspn57 { + compatible = "regulator-fixed"; + regulator-name = "lcd0_bias_en"; + regulator-min-microvolt = <5700000>; + regulator-max-microvolt = <5700000>; + gpio = <&pcal6408ahk_a 4 0>; + enable-active-high; + }; + + lcd1_1v8: regulator-lcd1-vdd18 { + compatible = "regulator-fixed"; + regulator-name = "lcd1_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_a 5 0>; + enable-active-high; + }; + + lcd1_5v7: regulator-lcd1-vspn57 { + compatible = "regulator-fixed"; + regulator-name = "lcd1_bias_en"; + regulator-min-microvolt = <5700000>; + regulator-max-microvolt = <5700000>; + gpio = <&pcal6408ahk_a 7 0>; + enable-active-high; + }; + + soc_aud_adc_3v3_en_reg: soc-aud-adc-3v3-en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_adc_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6408ahk_b 1 1>; + enable-active-high; + }; + + soc_aud_dac_3v3_en_reg: soc-aud-dac-3v3-en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_dac_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6408ahk_b 2 1>; + enable-active-high; + }; + + wcn_wifi: wireless-wlan { + compatible = "wlan-platdata"; + clock-names = "clk_wifi"; + ref-clock-frequency = <24000000>; + keep_wifi_power_on; + pinctrl-names = "default"; + wifi_chip_type = "rtl8723ds"; + WIFI,poweren_gpio = <&gpio2_porta 26 0>; + WIFI,reset_n = <&gpio2_porta 28 0>; + status = "disabled"; + }; + + wcn_bt: wireless-bluetooth { + compatible = "bluetooth-platdata"; + pinctrl-names = "default", "rts_gpio"; + BT,power_gpio = <&gpio2_porta 29 0>; + status = "disabled"; + }; + + gpio_keys: gpio_keys{ + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_volume>; + pinctrl-names = "default"; + status = "disabled"; + key-volumedown { + label = "Volume Down Key"; + wakeup-source; + linux,code = ; + debounce-interval = <2>; + gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>; + }; + key-volumeup { + label = "Volume Up Key"; + wakeup-source; + linux,code = ; + debounce-interval = <2>; + gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>; + }; + }; + + aon { + compatible = "thead,light-aon"; + mbox-names = "aon"; + mboxes = <&mbox_910t 1 0>; + status = "okay"; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd33_emmc_reg: soc_vdd33_emmc { + regulator-name = "soc_vdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_emmc_reg: soc_vdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + soc_vext_2v8_reg: soc_vext_2v8 { + regulator-name = "soc_vext_2v8"; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + }; + soc_avdd28_rgb_reg: soc_avdd28_rgb { + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + }; + soc_avdd25_ir_reg: soc_avdd25_ir { + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3475000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dovdd18_ir_reg: soc_dovdd18_ir { + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd12_ir_reg: soc_dvdd12_ir { + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + regulator-boot-on; + regulator-always-on; + }; + + }; + + c910_cpufreq { + compatible = "thead,light-mpw-cpufreq"; + status = "okay"; + }; + + test: light-aon-test { + compatible = "thead,light-aon-test"; + }; + }; +}; + +&cmamem { + alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000] +}; + +&resmem { + #address-cells = <2>; + #size-cells = <2>; + ranges; + //Note: with "no-map" reserv mem not saved in hibernation + tee_mem: memory@1a000000 { + reg = <0x0 0x1a000000 0 0x4000000>; + no-map; + }; + dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ + reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ + 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ + 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ + 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ + //no-map; + }; + dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ + reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ + 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ + 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ + 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ + //no-map; + }; + vi_mem: framebuffer@0f800000 { + reg = <0x0 0x0F800000 0x0 0x05400000 /* vi_mem_pool_region[0] 84 MB (default) */ + 0x0 0x14C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x16900000 0x0 0x03200000>; /* vi_mem_pool_region[2] 50 MB */ + no-map; + }; + facelib_mem: memory@22000000 { + reg = <0x0 0x22000000 0x0 0x10000000>; + //no-map; + }; + audio_mem: memory@32000000 { + reg = <0x0 0x32000000 0x0 0x6400000>; + //no-map; + }; + rpmsgmem: memory@1E000000 { + reg = <0x0 0x1E000000 0x0 0x10000>; + //no-map; + }; +}; + +&adc { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + touch@5d { + #gpio-cells = <2>; + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio1_porta>; + interrupts = <8 0>; + irq-gpios = <&gpio1_porta 8 0>; + reset-gpios = <&gpio1_porta 7 0>; + AVDD28-supply = <®_tp_pwr_en>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + }; +}; + +&audio_i2c0 { + clock-frequency = <100000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa6>, + <&pinctrl_audiopa7>, + <&pinctrl_audio_i2c0>; + + es8156_audio_codec: es8156@8 { + #sound-dai-cells = <0>; + compatible = "everest,es8156"; + reg = <0x08>; + sound-name-prefix = "ES8156"; + AVDD-supply = <&soc_aud_dac_3v3_en_reg>; + DVDD-supply = <&soc_dvdd18_aon_reg>; + PVDD-supply = <&soc_dvdd18_aon_reg>; + mclk-sclk-ratio = <4>; + }; + + es7210_audio_codec_adc0: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + status = "disabled"; + work-mode = "ES7210_NORMAL_I2S"; + channels-max = <2>; + mclk-sclk-ratio = <4>; + sound-name-prefix = "ES7210_ADC0"; + MVDD-supply = <&soc_aud_adc_3v3_en_reg>; + AVDD-supply = <&soc_aud_adc_3v3_en_reg>; + DVDD-supply = <&soc_dvdd18_aon_reg>; + PVDD-supply = <&soc_dvdd18_aon_reg>; + }; + + es7210_audio_codec_adc1: es7210@41 { + #sound-dai-cells = <0>; + compatible = "MicArray_1"; + reg = <0x41>; + status = "disabled"; + work-mode = "ES7210_NORMAL_I2S"; + channels-max = <2>; + mclk-sclk-ratio = <4>; + sound-name-prefix = "ES7210_ADC1"; + MVDD-supply = <&soc_aud_adc_3v3_en_reg>; + AVDD-supply = <&soc_aud_adc_3v3_en_reg>; + DVDD-supply = <&soc_dvdd18_aon_reg>; + PVDD-supply = <&soc_dvdd18_aon_reg>; + }; + + audio_aw87519_pa: amp@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + reset-gpio = <&pcal6408ahk_b 3 0x1>; + sound-name-prefix = "AW87519"; + status = "okay"; + }; +}; + +&audio_i2c1 { + clock-frequency = <100000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa13>, + <&pinctrl_audiopa16>, + <&pinctrl_audio_i2c1>; + + pcal6408ahk_b: gpio@20 { + compatible = "nxp,pcal9554b"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + touch1@5d { + #gpio-cells = <2>; + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio1_porta>; + interrupts = <12 0>; + irq-gpios = <&gpio1_porta 12 0>; + reset-gpios = <&gpio1_porta 11 0>; + AVDD28-supply = <®_tp1_pwr_en>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + }; +}; + +&spi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 + rx-sample-delay-ns = <10>; + + spi_norflash@0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + w25q,fast-read; + }; + + spidev@1 { + status = "disable"; + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x1>; + spi-max-frequency = <50000000>; + }; + + tpm_tis@0 { + status = "disable"; + compatible = "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&uart0 { + clock-frequency = <100000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&qspi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 3 0>; + rx-sample-dly = <5>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&qspi1 { + num-cs = <1>; + cs-gpios = <&gpio0_porta 1 0>; + rx-sample-dly = <5>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi2"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0>; + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_88E1111_0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy_88E1111_1: ethernet-phy@1 { + reg = <0x2>; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac1>; + status = "okay"; +}; + +&emmc { + max-frequency = <198000000>; + non-removable; + mmc-hs400-1_8v; + io_fixed_1v8; + is_emmc; + no-sdio; + no-sd; + pull_up; + bus-width = <8>; + status = "okay"; +}; + +&sdhci0 { + max-frequency = <198000000>; + bus-width = <4>; + pull_up; + wprtn_ignore; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdio0>; + status = "okay"; +}; + +&sdhci1 { + max-frequency = <100000000>; + bus-width = <4>; + pull_up; + no-sd; + no-mmc; + non-removable; + io_fixed_1v8; + rxclk-sample-delay = <80>; + post-power-on-delay-ms = <50>; + wprtn_ignore; + cap-sd-highspeed; + wakeup-source; + status = "disabled"; +}; + +&padctrl0_apsys { /* right-pinctrl */ + light-evb-padctrl0 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart0: uart0grp { + thead,pins = < + FM_UART0_TXD 0x0 0x234 + FM_UART0_RXD 0x0 0x234 + >; + }; + + pinctrl_qspi0: qspi0grp { + thead,pins = < + FM_QSPI0_SCLK 0x0 0x20f + FM_QSPI0_CSN0 0x3 0x20f + FM_QSPI0_CSN1 0x0 0x20f + FM_QSPI0_D0_MOSI 0x0 0x23f + FM_QSPI0_D1_MISO 0x0 0x23f + FM_QSPI0_D2_WP 0x0 0x23f + FM_QSPI0_D3_HOLD 0x0 0x23f + >; + }; + + pinctrl_light_i2s0: i2s0grp { + thead,pins = < + FM_QSPI0_SCLK 0x2 0x208 + FM_QSPI0_CSN0 0x2 0x238 + FM_QSPI0_CSN1 0x2 0x208 + FM_QSPI0_D0_MOSI 0x2 0x238 + FM_QSPI0_D1_MISO 0x2 0x238 + FM_QSPI0_D2_WP 0x2 0x238 + FM_QSPI0_D3_HOLD 0x2 0x238 + >; + }; + + pinctrl_i2c2: i2c2grp { + thead,pins = < + FM_I2C2_SCL 0x0 0x204 + FM_I2C2_SDA 0x0 0x204 + >; + }; + + pinctrl_i2c3: i2c3grp { + thead,pins = < + FM_I2C3_SCL 0x0 0x204 + FM_I2C3_SDA 0x0 0x204 + >; + }; + + pinctrl_spi0: spi0grp { + thead,pins = < + FM_SPI_CSN 0x3 0x20a + FM_SPI_SCLK 0x0 0x20a + FM_SPI_MISO 0x0 0x23a + FM_SPI_MOSI 0x0 0x23a + >; + }; + + pinctrl_gmac1: gmac1grp { + thead,pins = < + FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */ + FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */ + FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */ + FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */ + FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */ + FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */ + FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */ + FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */ + FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */ + FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */ + FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */ + FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */ + >; + }; + + pinctrl_sdio0: sdio0grp { + thead,pins = < + FM_SDIO0_DETN 0x0 0x208 + >; + }; + + pinctrl_pwm: pwmgrp { + thead,pins = < + FM_GPIO3_2 0x1 0x208 /* pwm0 */ + FM_GPIO3_3 0x1 0x208 /* pwm1 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + thead,pins = < + FM_HDMI_SCL 0x0 0x208 + FM_HDMI_SDA 0x0 0x208 + FM_HDMI_CEC 0x0 0x208 + >; + }; + + pinctrl_gmac0: gmac0grp { + thead,pins = < + FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */ + FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */ + FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */ + FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */ + FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */ + FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */ + FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */ + FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */ + FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */ + FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */ + FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */ + FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */ + FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */ + FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */ + FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */ + FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */ + >; + }; + }; +}; + +&padctrl1_apsys { /* left-pinctrl */ + light-evb-padctrl1 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_qspi1: qspi1grp { + thead,pins = < + FM_QSPI1_SCLK 0x0 0x20a + FM_QSPI1_CSN0 0x3 0x20a + FM_QSPI1_D0_MOSI 0x0 0x23a + FM_QSPI1_D1_MISO 0x0 0x23a + FM_QSPI1_D2_WP 0x0 0x23a + FM_QSPI1_D3_HOLD 0x0 0x23a + >; + }; + + pinctrl_iso7816: iso7816grp { + thead,pins = < + FM_QSPI1_SCLK 0x1 0x208 + FM_QSPI1_D0_MOSI 0x1 0x238 + FM_QSPI1_D1_MISO 0x1 0x238 + FM_QSPI1_D2_WP 0x1 0x238 + FM_QSPI1_D3_HOLD 0x1 0x238 + >; + }; + + pinctrl_i2c0: i2c0grp { + thead,pins = < + FM_I2C0_SCL 0x0 0x204 + FM_I2C0_SDA 0x0 0x204 + >; + }; + + pinctrl_i2c1: i2c1grp { + thead,pins = < + FM_I2C1_SCL 0x0 0x204 + FM_I2C1_SDA 0x0 0x204 + >; + }; + + pinctrl_uart1: uart1grp { + thead,pins = < + FM_UART1_TXD 0x0 0x234 + FM_UART1_RXD 0x0 0x234 + >; + }; + + pinctrl_uart4: uart4grp { + thead,pins = < + FM_UART4_TXD 0x0 0x208 + FM_UART4_RXD 0x0 0x208 + FM_UART4_CTSN 0x0 0x208 + FM_UART4_RTSN 0x0 0x208 + >; + }; + + pinctrl_uart3: uart3grp { + thead,pins = < + FM_UART3_TXD 0x1 0x202 + FM_UART3_RXD 0x1 0x202 + FM_GPIO0_20 0x2 0x202 /* UART3_IR_OUT */ + FM_GPIO0_21 0x2 0x202 /* UART3_IR_IN */ + >; + }; + + pinctrl_i2c4: i2c4grp { + thead,pins = < + FM_GPIO0_18 0x1 0x204 /* I2C4_SCL */ + FM_GPIO0_19 0x1 0x204 /* I2C4_SDA */ + >; + }; + }; +}; + +&padctrl_aosys { + light-aon-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audiopa0: audiopa0 { + thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa1: audiopa1 { + thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa2: audiopa2 { + thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa3: audiopa3 { + thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa4: audiopa4 { + thead,pins = < FM_AUDIO_PA4 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa5: audiopa5 { + thead,pins = < FM_AUDIO_PA5 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa6: audiopa6 { + thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa7: audiopa7 { + thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa8: audiopa8 { + thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa9: audiopa9 { + thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa10: audiopa10 { + thead,pins = < FM_AUDIO_PA10 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa11: audiopa11 { + thead,pins = < FM_AUDIO_PA11 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa12: audiopa12 { + thead,pins = < FM_AUDIO_PA12 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa13: audiopa13 { + thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa14: audiopa14 { + thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa15: audiopa15 { + thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa16: audiopa16 { + thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa17: audiopa17 { + thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; + }; + + pinctrl_volume: volume_grp { + thead,pins = < + FM_CPU_JTG_TDI 0x3 0x238 + FM_CPU_JTG_TDO 0x3 0x238 + >; + }; + }; +}; + +&padctrl_audiosys { + + status = "okay"; + + light-audio-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audio_i2c0: audio_i2c0_grp { + thead,pins = < + FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004 + FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004 + >; + }; + pinctrl_audio_i2c1: audio_i2c1_grp { + thead,pins = < + FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_1 0x004 + FM_AUDIO_IO_PA16 LIGHT_PIN_FUNC_3 0x004 + >; + }; + pinctrl_audio_i2s0: audio_i2s0_grp { + thead,pins = < + FM_AUDIO_IO_PA9 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA10 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA11 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA12 LIGHT_PIN_FUNC_0 0x008 + >; + }; + pinctrl_audio_i2s1: audio_i2s1_grp { + thead,pins = < + FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 + >; + }; + pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp { + thead,pins = < + FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008 + FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008 + FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_i2s_8ch_sd0: audio_i2s_8ch_sd0_grp { + thead,pins = < + FM_AUDIO_IO_PA4 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_i2s_8ch_sd1: audio_i2s_8ch_sd1_grp { + thead,pins = < + FM_AUDIO_IO_PA5 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp { + thead,pins = < + FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp { + thead,pins = < + FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_tdm: audio_tdm_grp { + thead,pins = < + FM_AUDIO_IO_PA27 LIGHT_PIN_FUNC_1 0x007 + FM_AUDIO_IO_PA28 LIGHT_PIN_FUNC_1 0x007 + FM_AUDIO_IO_PA29 LIGHT_PIN_FUNC_1 0x000 + >; + }; + pinctrl_audio_spdif0: audio_spdif0_grp { + thead,pins = < + FM_AUDIO_IO_PA21 LIGHT_PIN_FUNC_1 0x000 + FM_AUDIO_IO_PA22 LIGHT_PIN_FUNC_1 0x007 + >; + }; + pinctrl_audio_spdif1: audio_spdif1_grp { + thead,pins = < + FM_AUDIO_IO_PA23 LIGHT_PIN_FUNC_1 0x007 + FM_AUDIO_IO_PA24 LIGHT_PIN_FUNC_1 0x000 + >; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + pcal6408ahk_a: gpio@20 { + compatible = "nxp,pcal9554b"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + +&isp_ry0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&dec400_isp0 { + status = "okay"; +}; + +&dec400_isp1 { + status = "okay"; +}; + +&dec400_isp2 { + status = "okay"; +}; + +&bm_visys { + status = "okay"; +}; + +&bm_csi0 { + status = "okay"; +}; + +&bm_csi1 { + status = "okay"; +}; + +&bm_csi2 { + status = "okay"; +}; + +&vi_pre { + //vi_pre_irq_en = <1>; + status = "okay"; +}; + +&xtensa_dsp { + status = "okay"; +}; + +&xtensa_dsp0 { + status = "okay"; + memory-region = <&dsp0_mem>; +}; + +&xtensa_dsp1{ + status = "okay"; + memory-region = <&dsp1_mem>; +}; + +&vvcam_flash_led0{ + flash_led_name = "aw36413_aw36515"; + floodlight_i2c_bus = /bits/ 8 <2>; + floodlight_en_pin = <&gpio1_porta 25 0>; + //projection_i2c_bus = /bits/ 8 <2>; + flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin + status = "okay"; +}; + +&vvcam_sensor0 { + sensor_name = "SC2310"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_voltage_uV = <1800000 1200000 2800000>; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x30>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&vvcam_sensor1 { + sensor_name = "OV5693"; + i2c_bus = /bits/ 8 <3>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + status = "disabled"; +}; + + +&vvcam_sensor1 { + sensor_name = "OV5693"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_voltage_uV = <1800000 1200000 2800000>; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x36>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&vvcam_sensor2 { + sensor_name = "GC5035"; + sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; + sensor_regulator_timing_us = <100 50 0>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; + DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; + AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <4>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + status = "okay"; +}; + +&vvcam_sensor3 { + sensor_name = "SC2310"; + sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; + sensor_regulator_timing_us = <70 50 20>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; + DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; + AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; + i2c_bus = /bits/ 8 <4>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x30>; + status = "okay"; +}; + +&vvcam_sensor4 { + sensor_name = "SC132GS"; + sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; + sensor_regulator_timing_us = <70 1000 2000>; + i2c_addr = /bits/ 8 <0x31>; + sensor_rst = <&gpio1_porta 24 0>; + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; + DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; + AVDD25_IR-supply = <&soc_avdd25_ir_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_bus = /bits/ 8 <2>; + status = "okay"; +}; + +&vvcam_sensor5 { + sensor_name = "OV12870"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_voltage_uV = <1800000 1200000 2800000>; + sensor_regulator_timing_us = <100 50 0>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_addr = /bits/ 8 <0x10>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&vvcam_sensor6 { + sensor_name = "GC02M1B"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_voltage_uV = <1800000 1675000 2800000>; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&vvcam_sensor7 { + sensor_name = "IMX334"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x1a>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&video0{ + status = "okay"; + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + + +&video1{ + status = "okay"; + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video2{ + status = "okay"; + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + sensor2 { + subdev_name = "vivcam"; + idx = <7>; //imx334 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_3840x2180_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <3840>; + max_height = <2180>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video3{ + status = "okay"; + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video4{ + status = "okay"; + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video5{ + status = "okay"; + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video6{ + status = "okay"; + vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video7{ + status = "okay"; + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + + +&video8{ + status = "okay"; + vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_VIPRE_DDR"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video9{ + status = "okay"; + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + + +&video10{ + status = "okay"; + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; + }; + }; +}; + +&video11{ + status = "okay"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video12{ // TUNINGTOOL + status = "okay"; + channel0 { // CSI2 + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + skip_init = <1>; + }; + }; +}; + +&video15{ + status = "okay"; + vi_mem_pool_region = <0>; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //<0>=vivcam0 :2310 + csi_idx = <0>; //<0>=CSI2 + flash_led_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <7>; //imx334 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_3840x2180_RAW12_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_DDR"; + }; + }; +}; + +&trng { + status = "disabled"; +}; + +&eip_28 { + status = "okay"; +}; + +&vdec { + status = "okay"; +}; + +&venc { + status = "okay"; +}; + +&isp_venc_shake { + status = "okay"; +}; + +&vidmem { + status = "okay"; + memory-region = <&vi_mem>; +}; + +&gpu { + status = "okay"; +}; + +&npu { + vha_clk_rate = <1000000000>; + status = "okay"; +}; + +&fce { + memory-region = <&facelib_mem>; + status = "okay"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa9>, + <&pinctrl_audiopa10>, + <&pinctrl_audiopa11>, + <&pinctrl_audiopa12>, + <&pinctrl_audio_i2s0>; +}; + +&i2s_8ch_sd0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa4>, + <&pinctrl_audio_i2s_8ch_sd0>; +}; + +&i2s_8ch_sd1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa5>, + <&pinctrl_audio_i2s_8ch_sd1>; +}; + +&i2s_8ch_sd2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa0>, + <&pinctrl_audio_i2s_8ch_sd2>, + <&pinctrl_audiopa2>, + <&pinctrl_audiopa3>, + <&pinctrl_audiopa8>, + <&pinctrl_audio_i2s_8ch_bus>; +}; + +&i2s_8ch_sd3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa1>, + <&pinctrl_audio_i2s_8ch_sd3>; +}; + + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 650000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-b-product-crash.dts b/arch/riscv/boot/dts/thead/th1520-b-product-crash.dts new file mode 100644 index 000000000000..87cce35b29fa --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-b-product-crash.dts @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include "th1520-crash.dtsi" + +&aon { + aon_reg_ricoh: light-ricoh-reg { + compatible = "thead,light-ricoh-pmic"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-b-product-sec.dts b/arch/riscv/boot/dts/thead/th1520-b-product-sec.dts new file mode 100644 index 000000000000..2d4ca45d22d0 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-b-product-sec.dts @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-b-product.dts" + + + +&light_iopmp { + status = "disabled"; +}; + +&eip_28 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-b-product.dts b/arch/riscv/boot/dts/thead/th1520-b-product.dts new file mode 100644 index 000000000000..bd0140bf1bdf --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-b-product.dts @@ -0,0 +1,2525 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520.dtsi" +#include +#include +#include "th1520-vi-devices.dtsi" +/ { + model = "T-HEAD Light val board"; + compatible = "thead,light-val", "thead,light"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x200000 0x0 0x7fe00000>; + }; + + chosen { + bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + status = "disabled"; + led0 { + label = "SYS_STATUS"; + gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ + default-state = "off"; + }; + }; + + display-subsystem { + status = "okay"; + }; + + lcd0_backlight: pwm-backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + light_iopmp: iopmp { + compatible = "thead,light-iopmp"; + + /* config#1: multiple valid regions */ + iopmp_emmc: IOPMP_EMMC { + regions = <0x000000 0x100000>, + <0x100000 0x200000>; + attr = <0xFFFFFFFF>; + dummy_slave= <0x800000>; + }; + + /* config#2: iopmp bypass */ + iopmp_sdio0: IOPMP_SDIO0 { + bypass_en; + }; + + /* config#3: iopmp default region set */ + iopmp_sdio1: IOPMP_SDIO1 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_usb0: IOPMP_USB0 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_ao: IOPMP_AO { + is_default_region; + }; + + iopmp_aud: IOPMP_AUD { + is_default_region; + }; + + iopmp_chip_dbg: IOPMP_CHIP_DBG { + is_default_region; + }; + + iopmp_eip120i: IOPMP_EIP120I { + is_default_region; + }; + + iopmp_eip120ii: IOPMP_EIP120II { + is_default_region; + }; + + iopmp_eip120iii: IOPMP_EIP120III { + is_default_region; + }; + + iopmp_isp0: IOPMP_ISP0 { + is_default_region; + }; + + iopmp_isp1: IOPMP_ISP1 { + is_default_region; + }; + + iopmp_dw200: IOPMP_DW200 { + is_default_region; + }; + + iopmp_vipre: IOPMP_VIPRE { + is_default_region; + }; + + iopmp_venc: IOPMP_VENC { + is_default_region; + }; + + iopmp_vdec: IOPMP_VDEC { + is_default_region; + }; + + iopmp_g2d: IOPMP_G2D { + is_default_region; + }; + + iopmp_fce: IOPMP_FCE { + is_default_region; + }; + + iopmp_npu: IOPMP_NPU { + is_default_region; + }; + + iopmp0_dpu: IOPMP0_DPU { + bypass_en; + }; + + iopmp1_dpu: IOPMP1_DPU { + bypass_en; + }; + + iopmp_gpu: IOPMP_GPU { + is_default_region; + }; + + iopmp_gmac1: IOPMP_GMAC1 { + is_default_region; + }; + + iopmp_gmac2: IOPMP_GMAC2 { + is_default_region; + }; + + iopmp_dmac: IOPMP_DMAC { + is_default_region; + }; + + iopmp_tee_dmac: IOPMP_TEE_DMAC { + is_default_region; + }; + + iopmp_dsp0: IOPMP_DSP0 { + is_default_region; + }; + + iopmp_dsp1: IOPMP_DSP1 { + is_default_region; + }; + + iopmp_audio0: IOPMP_AUDIO0 { + is_default_region; + }; + + iopmp_audio1: IOPMP_AUDIO1 { + is_default_region; + }; + }; + + mbox_910t_client1: mbox_910t_client1 { + compatible = "thead,light-mbox-client"; + mbox-names = "902"; + mboxes = <&mbox_910t 1 0>; + status = "disabled"; + }; + + + mbox_910t_client2: mbox_910t_client2 { + compatible = "thead,light-mbox-client"; + mbox-names = "906"; + mboxes = <&mbox_910t 2 0>; + audio-mbox-regmap = <&audio_mbox>; + status = "okay"; + }; + + lightsound: lightsound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Light-Sound-Card"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + light_rpmsg: light_rpmsg { + compatible = "light,rpmsg-bus", "simple-bus"; + memory-region = <&rpmsgmem>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + rpmsg: rpmsg{ + vdev-nums = <1>; + reg = <0x0 0x1E000000 0 0x10000>; + compatible = "light,light-rpmsg"; + status = "okay"; + }; + }; + + dummy_codec: dummy_codec { + #sound-dai-cells = <0>; + compatible = "thead,light-dummy-pcm"; + status = "okay"; + sound-name-prefix = "DUMMY"; + }; + + reg_vref_1v8: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + reg_tp_pwr_en: regulator-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "PWR_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1_porta 12 1>; + enable-active-high; + regulator-always-on; + }; + + wcn_wifi: wireless-wlan { + compatible = "wlan-platdata"; + clock-names = "clk_wifi"; + ref-clock-frequency = <24000000>; + keep_wifi_power_on; + pinctrl-names = "default"; + wifi_chip_type = "rtl8723ds"; + WIFI,poweren_gpio = <&gpio2_porta 29 0>; + WIFI,reset_n = <&gpio2_porta 24 0>; + status = "okay"; + }; + + wcn_bt: wireless-bluetooth { + compatible = "bluetooth-platdata"; + pinctrl-names = "default", "rts_gpio"; + BT,power_gpio = <&gpio2_porta 25 0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_volume>; + pinctrl-names = "default"; + key-volumedown { + label = "Volume Down Key"; + wakeup-source; + linux,code = ; + debounce-interval = <1>; + gpios = <&ao_gpio_porta 11 0x1>; + }; + key-volumeup { + label = "Volume Up Key"; + wakeup-source; + linux,code = ; + debounce-interval = <1>; + gpios = <&ao_gpio_porta 10 0x1>; + }; + }; + + aon: aon@0 { + compatible = "thead,light-aon"; + mbox-names = "aon"; + mboxes = <&mbox_910t 1 0>; + status = "okay"; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + soc_aud_3v3_en_reg: soc_aud_3v3_en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_3v3_en>; + gpio = <&ao_gpio_porta 7 1>; + enable-active-high; + regulator-always-on; + }; + + soc_aud_1v8_en_reg: soc_aud_1v8_en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_1v8_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_1v8_en>; + gpio = <&ao_gpio_porta 8 1>; + enable-active-high; + regulator-always-on; + }; + + soc_vdd_3v3_en_reg: soc_vdd_3v3_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0_porta 30 1>; + enable-active-high; + regulator-always-on; + }; + + soc_lcd0_bias_en_reg: soc_lcd0_bias_en { + compatible = "regulator-fixed"; + regulator-name = "soc_lcd0_bias_en"; + regulator-min-microvolt = <5700000>; + regulator-max-microvolt = <5700000>; + gpio = <&gpio1_porta 10 1>; + enable-active-high; + }; + + soc_vdd5v_se_en_reg: soc_vdd5v_se_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd5v_se_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2_porta 14 1>; + enable-active-high; + regulator-always-on; + }; + + soc_wcn33_en_reg: soc_wcn33_en { + compatible = "regulator-fixed"; + regulator-name = "soc_wcn33_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2_porta 29 1>; + enable-active-high; + regulator-always-on; + }; + + soc_vbus_en_reg: soc_vbus_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vbus_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2_porta 28 1>; + enable-active-high; + regulator-always-on; + }; + + soc_dovdd18_scan_reg: soc_dovdd18_scan { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2_porta 31 1>; + enable-active-high; + }; + + soc_dvdd12_scan_reg: soc_dvdd12_scan { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio3_porta 0 1>; + enable-active-high; + }; + + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio2_porta 30 1>; + enable-active-high; + }; + + soc_avdd28_rgb_reg: soc_avdd28_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1_porta 15 1>; + enable-active-high; + }; + + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1_porta 13 1>; + enable-active-high; + }; + + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1_porta 14 1>; + enable-active-high; + }; + + soc_avdd25_ir_reg: soc_avdd25_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + gpio = <&gpio0_porta 28 1>; + enable-active-high; + }; + + soc_dovdd18_ir_reg: soc_dovdd18_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio0_porta 27 1>; + enable-active-high; + }; + + soc_dvdd12_ir_reg: soc_dvdd12_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio0_porta 29 1>; + enable-active-high; + }; + + aon_reg_ricoh: light-ricoh-reg { + compatible = "thead,light-ricoh-pmic"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd33_emmc_reg: soc_vdd33_emmc { + regulator-name = "soc_vdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_emmc_reg: soc_vdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_lcd0_en_reg: soc_lcd0_en { + regulator-name = "soc_lcd0_en"; + }; + soc_vext_1v8_reg: soc_vext_1v8 { + regulator-name = "soc_vext_1v8"; + regulator-boot-on; + regulator-always-on; + }; + }; + + c910_cpufreq { + compatible = "thead,light-mpw-cpufreq"; + status = "okay"; + }; + + test: light-aon-test { + compatible = "thead,light-aon-test"; + }; + }; + +}; + +&resmem { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tee_mem: memory@1a000000 { + reg = <0x0 0x1a000000 0 0x4000000>; + no-map; + }; + + dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ + reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ + 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ + 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ + 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ + //no-map; + }; + dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ + reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ + 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ + 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ + 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ + //no-map; + }; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ + 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + no-map; + }; + + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; + //no-map; + }; + + audio_mem: memory@32000000 { + reg = <0x0 0x32000000 0x0 0x6400000>; + //no-map; + }; + rpmsgmem: memory@1E000000 { + reg = <0x0 0x1E000000 0x0 0x10000>; + //no-map; + }; + +}; + +&adc { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + touch@5d { + #gpio-cells = <2>; + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio1_porta>; + interrupts = <8 0>; + irq-gpios = <&gpio1_porta 8 0>; + reset-gpios = <&gpio1_porta 7 0>; + AVDD28-supply = <®_tp_pwr_en>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + }; + +}; + +&audio_i2c0 { + clock-frequency = <100000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa6>, + <&pinctrl_audiopa7>, + <&pinctrl_audio_i2c0>; + + es8156_audio_codec: es8156@8 { + #sound-dai-cells = <0>; + compatible = "everest,es8156"; + reg = <0x08>; + sound-name-prefix = "ES8156"; + AVDD-supply = <&soc_aud_3v3_en_reg>; + DVDD-supply = <&soc_aud_1v8_en_reg>; + PVDD-supply = <&soc_aud_1v8_en_reg>; + mclk-sclk-ratio = <4>; + }; + + es7210_audio_codec: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + work-mode = "ES7210_NORMAL_I2S"; + channels-max = <2>; + mclk-sclk-ratio = <4>; + sound-name-prefix = "ES7210_ADC0"; + MVDD-supply = <&soc_aud_3v3_en_reg>; + AVDD-supply = <&soc_aud_3v3_en_reg>; + DVDD-supply = <&soc_aud_1v8_en_reg>; + PVDD-supply = <&soc_aud_1v8_en_reg>; + }; + + audio_aw87519_pa: amp@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + pingctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_pa_rst0>; + reset-gpio = <&ao_gpio4_porta 9 0x1>; + sound-name-prefix = "AW87519"; + status = "okay"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&spi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 + rx-sample-delay-ns = <10>; + status = "disabled"; + + spi_norflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + w25q,fast-read; + }; + + spidev@1 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x1>; + spi-max-frequency = <50000000>; + }; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&qspi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 3 0>; + rx-sample-dly = <4>; + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&qspi1 { + compatible = "snps,dw-apb-ssi"; + num-cs = <1>; + cs-gpios = <&gpio0_porta 1 0>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0>; + spi-max-frequency = <50000000>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_0>; + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_88E1111_0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy_88E1111_1: ethernet-phy@1 { + reg = <0x2>; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_1>; + status = "disabled"; +}; + +&emmc { + max-frequency = <198000000>; + non-removable; + mmc-hs400-1_8v; + io_fixed_1v8; + is_emmc; + no-sdio; + no-sd; + pull_up; + bus-width = <8>; + status = "okay"; +}; + +&sdhci0 { + max-frequency = <198000000>; + bus-width = <4>; + pull_up; + wprtn_ignore; + status = "okay"; +}; + +&sdhci1 { + max-frequency = <100000000>; + bus-width = <4>; + pull_up; + no-sd; + no-mmc; + non-removable; + io_fixed_1v8; + rxclk-sample-delay = <80>; + post-power-on-delay-ms = <50>; + wprtn_ignore; + cap-sd-highspeed; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&padctrl0_apsys { /* right-pinctrl */ + light-evb-padctrl0 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart0: uart0grp { + thead,pins = < + FM_UART0_TXD 0x0 0x72 + FM_UART0_RXD 0x0 0x72 + >; + }; + + pinctrl_spi0: spi0grp { + thead,pins = < + FM_SPI_CSN 0x3 0x20a + FM_SPI_SCLK 0x0 0x20a + FM_SPI_MISO 0x0 0x23a + FM_SPI_MOSI 0x0 0x23a + >; + }; + + pinctrl_qspi0: qspi0grp { + thead,pins = < + FM_QSPI0_SCLK 0x0 0x20f + FM_QSPI0_CSN0 0x3 0x20f + FM_QSPI0_CSN1 0x0 0x20f + FM_QSPI0_D0_MOSI 0x0 0x23f + FM_QSPI0_D1_MISO 0x0 0x23f + FM_QSPI0_D2_WP 0x0 0x23f + FM_QSPI0_D3_HOLD 0x0 0x23f + >; + }; + + pinctrl_light_i2s0: i2s0grp { + thead,pins = < + FM_QSPI0_SCLK 0x2 0x208 + FM_QSPI0_CSN0 0x2 0x238 + FM_QSPI0_CSN1 0x2 0x208 + FM_QSPI0_D0_MOSI 0x2 0x238 + FM_QSPI0_D1_MISO 0x2 0x238 + FM_QSPI0_D2_WP 0x2 0x238 + FM_QSPI0_D3_HOLD 0x2 0x238 + >; + }; + + pinctrl_pwm: pwmgrp { + thead,pins = < + FM_GPIO3_2 0x1 0x208 /* pwm0 */ + >; + }; + }; +}; + +&padctrl1_apsys { /* left-pinctrl */ + light-evb-padctrl1 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart3: uart3grp { + thead,pins = < + FM_UART3_TXD 0x0 0x72 + FM_UART3_RXD 0x0 0x72 + >; + }; + + pinctrl_uart4: uart4grp { + thead,pins = < + FM_UART4_TXD 0x0 0x72 + FM_UART4_RXD 0x0 0x72 + FM_UART4_CTSN 0x0 0x72 + FM_UART4_RTSN 0x0 0x72 + >; + }; + + pinctrl_qspi1: qspi1grp { + thead,pins = < + FM_QSPI1_SCLK 0x0 0x20a + FM_QSPI1_CSN0 0x3 0x20a + FM_QSPI1_D0_MOSI 0x0 0x23a + FM_QSPI1_D1_MISO 0x0 0x23a + FM_QSPI1_D2_WP 0x0 0x23a + FM_QSPI1_D3_HOLD 0x0 0x23a + >; + }; + + + pinctrl_iso7816: iso7816grp { + thead,pins = < + FM_QSPI1_SCLK 0x1 0x208 + FM_QSPI1_D0_MOSI 0x1 0x238 + FM_QSPI1_D1_MISO 0x1 0x238 + FM_QSPI1_D2_WP 0x1 0x238 + FM_QSPI1_D3_HOLD 0x1 0x238 + >; + }; + + }; +}; + +&padctrl_aosys { + light-aon-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audiopa0: audiopa0 { + thead,pins = < FM_AUDIO_PA0 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa1: audiopa1 { + thead,pins = < FM_AUDIO_PA1 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa2: audiopa2 { + thead,pins = < FM_AUDIO_PA2 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa3: audiopa3 { + thead,pins = < FM_AUDIO_PA3 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa6: audiopa6 { + thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa7: audiopa7 { + thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa8: audiopa8 { + thead,pins = < FM_AUDIO_PA8 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audio_pa_rst0: audio_pa_rst0 { + thead,pins = < FM_AUDIO_PA9 LIGHT_PIN_FUNC_3 0x000 >; + }; + pinctrl_audiopa13: audiopa13 { + thead,pins = < FM_AUDIO_PA13 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa14: audiopa14 { + thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa15: audiopa15 { + thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa17: audiopa17 { + thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audio_3v3_en: audio_3v3_en { + thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_3 0x008 >; + }; + pinctrl_audio_1v8_en: audio_1v8_en { + thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_3 0x008 >; + }; + + pinctrl_volume: volume_grp { + thead,pins = < + FM_AOGPIO_11 0x0 0x238 + FM_AOGPIO_10 0x3 0x238 + >; + }; + }; +}; + +&padctrl_audiosys { + + status = "okay"; + + light-audio-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audio_i2c0: audio_i2c0_grp { + thead,pins = < + FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_0 0x004 + FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_0 0x004 + >; + }; + pinctrl_audio_i2s1: audio_i2s1_grp { + thead,pins = < + FM_AUDIO_IO_PA13 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 + >; + }; + pinctrl_audio_i2s_8ch_bus: audio_i2s_8ch_bus_grp { + thead,pins = < + FM_AUDIO_IO_PA2 LIGHT_PIN_FUNC_3 0x008 + FM_AUDIO_IO_PA3 LIGHT_PIN_FUNC_3 0x008 + FM_AUDIO_IO_PA8 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_i2s_8ch_sd2: audio_i2s_8ch_sd2_grp { + thead,pins = < + FM_AUDIO_IO_PA0 LIGHT_PIN_FUNC_3 0x008 + >; + }; + pinctrl_audio_i2s_8ch_sd3: audio_i2s_8ch_sd3_grp { + thead,pins = < + FM_AUDIO_IO_PA1 LIGHT_PIN_FUNC_3 0x008 + >; + }; + }; +}; + + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; +}; + +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + +&isp_ry0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&dec400_isp0 { + status = "okay"; +}; + +&dec400_isp1 { + status = "okay"; +}; + +&dec400_isp2 { + status = "okay"; +}; + +&bm_visys { + status = "okay"; +}; + +&bm_csi0 { + status = "okay"; +}; + +&bm_csi1 { + status = "okay"; +}; + +&bm_csi2 { + status = "okay"; +}; + +&vi_pre { + vi_pre_irq_en = <1>; + status = "okay"; +}; + +&xtensa_dsp { + status = "okay"; +}; + +&xtensa_dsp0 { + status = "okay"; + memory-region = <&dsp0_mem>; +}; + +&xtensa_dsp1 { + status = "okay"; + memory-region = <&dsp1_mem>; +}; + +&vvcam_flash_led0{ + flash_led_name = "aw36413_aw36515"; + floodlight_i2c_bus = /bits/ 8 <2>; + floodlight_en_pin = <&gpio1_porta 25 0>; + //projection_i2c_bus = /bits/ 8 <2>; + flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin + status = "okay"; +}; + +&vvcam_sensor0 { + sensor_name = "SC2310"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x30>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +/* +&vvcam_sensor0 { + sensor_name = "IMX334"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x1a>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; +*/ + +&vvcam_sensor1 { + sensor_name = "OV5693"; + i2c_bus = /bits/ 8 <3>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + status = "disabled"; +}; + +&vvcam_sensor2 { + sensor_name = "GC5035"; + sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; + sensor_regulator_timing_us = <100 50 0>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; + DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; + AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <4>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + status = "okay"; +}; + +&vvcam_sensor3 { + sensor_name = "SC2310"; + sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN"; + sensor_regulator_timing_us = <70 50 20>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&gpio1_porta 29 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>; + DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>; + AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>; + i2c_bus = /bits/ 8 <4>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x30>; + status = "okay"; +}; + +&vvcam_sensor4 { + sensor_name = "SC132GS"; + sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR"; + sensor_regulator_timing_us = <70 1000 2000>; + i2c_addr = /bits/ 8 <0x31>; + sensor_rst = <&gpio1_porta 24 0>; + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; + DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; + AVDD25_IR-supply = <&soc_avdd25_ir_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_bus = /bits/ 8 <2>; + status = "okay"; +}; + +&vvcam_sensor5 { + sensor_name = "OV12870"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <100 50 0>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_addr = /bits/ 8 <0x10>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&vvcam_sensor6 { + sensor_name = "GC02M1B"; + sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB"; + sensor_regulator_timing_us = <70 50 20>; + sensor_rst = <&gpio1_porta 16 0>; + sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <1>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x37>; + i2c_bus = /bits/ 8 <3>; + status = "okay"; +}; + +&video0{ + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + + +&video1{ + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video2{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video3{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video4{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP2_BP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video5{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + +&video6{ + vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; + +}; + +&video7{ + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1080P_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + + +&video8{ + vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1] + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <3>; + path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_VIPRE_DDR"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video9{ + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dsp{ + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + + +&video10{ // TUNINGTOOL + channel0 { + sensor0 { + subdev_name = "vivcam"; + idx = <2>; //<2>=vivcam2 : gc5035 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER// + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; //<3>=vivcam3 : sc2310 + csi_idx = <1>; //<1>=CSI2X2_B + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; + }; + }; +}; + +&video11{ + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <1920>; + max_height = <1088>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video12{ // TUNINGTOOL + channel0 { // CSI2 + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //sc2310 + csi_idx = <0>; //<0>=CSI2 + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <6>; //gc02m1b + csi_idx = <0>; //<0>=CSI2 + mode_idx = <0>; + path_type = "SENSOR_1600x1200_RAW10_LINER"; + skip_init = <1>; + }; + }; +}; + +&video14{ + vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0] + status = "okay"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <4>; //sc132gs + csi_idx = <2>; //<2>=CSI2X2_A + flash_led_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_MCM_WR0"; + output { + max_width = <1080>; + max_height = <1280>; + bit_per_pixel = <16>; + frame_count = <3>; + }; + }; + }; +}; + +&video15{ + status = "okay"; + //vi_mem_pool_region = <0>; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0>; //<0>=vivcam0 :2310 + csi_idx = <0>; //<0>=CSI2 + flash_led_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_DDR"; + }; + }; +}; + +&trng { + status = "disabled"; +}; + +&eip_28 { + status = "okay"; +}; + +&vdec { + status = "okay"; +}; + +&venc { + status = "okay"; +}; + +&isp_venc_shake { + status = "okay"; +}; + +&vidmem { + status = "okay"; + memory-region = <&vi_mem>; +}; + +&gpu { + status = "okay"; +}; + +&npu { + vha_clk_rate = <1000000000>; + status = "okay"; +}; + +&fce { + memory-region = <&facelib_mem>; + status = "okay"; +}; + +&dpu_enc1 { + ports { + /delete-node/ port@0; + }; +}; + +&dpu { + status = "okay"; +}; + +&disp1_out { + remote-endpoint = <&hdmi_tx_in>; +}; + +&hdmi_tx { + status = "okay"; + + port@0 { + /* input */ + hdmi_tx_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; +}; + +&lightsound { + status = "okay"; + simple-audio-card,widgets = "Speaker", "Speaker"; + simple-audio-card,routing = + "Speaker", "AW87519 VO", + "AW87519 IN", "ES8156 ROUT"; + simple-audio-card,aux-devs = <&audio_aw87519_pa>; + simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ + reg = <0>; + format = "i2s"; + cpu { + sound-dai = <&i2s1 0>; + }; + codec { + sound-dai = <&es8156_audio_codec>; + }; + }; + simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_sd2 2>; + }; + codec { + sound-dai = <&es7210_audio_codec>; + }; + }; + simple-audio-card,dai-link@2 { /* I2S - HDMI */ + reg = <2>; + format = "i2s"; + cpu { + sound-dai = <&light_i2s 1>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; +}; + +&light_i2s { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa13>, + <&pinctrl_audiopa14>, + <&pinctrl_audiopa15>, + <&pinctrl_audiopa17>, + <&pinctrl_audio_i2s1>; +}; + +&i2s_8ch_sd2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa0>, + <&pinctrl_audio_i2s_8ch_sd2>, + <&pinctrl_audiopa2>, + <&pinctrl_audiopa3>, + <&pinctrl_audiopa8>, + <&pinctrl_audio_i2s_8ch_bus>; +}; + +&i2s_8ch_sd3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa1>, + <&pinctrl_audio_i2s_8ch_sd3>; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-crash.dtsi b/arch/riscv/boot/dts/thead/th1520-crash.dtsi new file mode 100644 index 000000000000..b85dbb37ca32 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-crash.dtsi @@ -0,0 +1,882 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520.dtsi" +#include +#include +#include "th1520-vi-devices.dtsi" +/ { + model = "T-HEAD Light val board"; + compatible = "thead,light-val", "thead,light"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + status = "disabled"; + led0 { + label = "SYS_STATUS"; + gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ + default-state = "off"; + }; + }; + + display-subsystem { + status = "okay"; + }; + + lcd0_backlight: pwm-backlight@0 { + status = "disabled"; + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + light_iopmp: iopmp { + status = "disabled"; + compatible = "thead,light-iopmp"; + + /* config#1: multiple valid regions */ + iopmp_emmc: IOPMP_EMMC { + regions = <0x000000 0x100000>, + <0x100000 0x200000>; + attr = <0xFFFFFFFF>; + dummy_slave= <0x800000>; + }; + + /* config#2: iopmp bypass */ + iopmp_sdio0: IOPMP_SDIO0 { + bypass_en; + }; + + /* config#3: iopmp default region set */ + iopmp_sdio1: IOPMP_SDIO1 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_usb0: IOPMP_USB0 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_ao: IOPMP_AO { + is_default_region; + }; + + iopmp_aud: IOPMP_AUD { + is_default_region; + }; + + iopmp_chip_dbg: IOPMP_CHIP_DBG { + is_default_region; + }; + + iopmp_eip120i: IOPMP_EIP120I { + is_default_region; + }; + + iopmp_eip120ii: IOPMP_EIP120II { + is_default_region; + }; + + iopmp_eip120iii: IOPMP_EIP120III { + is_default_region; + }; + + iopmp_isp0: IOPMP_ISP0 { + is_default_region; + }; + + iopmp_isp1: IOPMP_ISP1 { + is_default_region; + }; + + iopmp_dw200: IOPMP_DW200 { + is_default_region; + }; + + iopmp_vipre: IOPMP_VIPRE { + is_default_region; + }; + + iopmp_venc: IOPMP_VENC { + is_default_region; + }; + + iopmp_vdec: IOPMP_VDEC { + is_default_region; + }; + + iopmp_g2d: IOPMP_G2D { + is_default_region; + }; + + iopmp_fce: IOPMP_FCE { + is_default_region; + }; + + iopmp_npu: IOPMP_NPU { + is_default_region; + }; + + iopmp0_dpu: IOPMP0_DPU { + bypass_en; + }; + + iopmp1_dpu: IOPMP1_DPU { + bypass_en; + }; + + iopmp_gpu: IOPMP_GPU { + is_default_region; + }; + + iopmp_gmac1: IOPMP_GMAC1 { + is_default_region; + }; + + iopmp_gmac2: IOPMP_GMAC2 { + is_default_region; + }; + + iopmp_dmac: IOPMP_DMAC { + is_default_region; + }; + + iopmp_tee_dmac: IOPMP_TEE_DMAC { + is_default_region; + }; + + iopmp_dsp0: IOPMP_DSP0 { + is_default_region; + }; + + iopmp_dsp1: IOPMP_DSP1 { + is_default_region; + }; + + iopmp_audio0: IOPMP_AUDIO0 { + is_default_region; + }; + + iopmp_audio1: IOPMP_AUDIO1 { + is_default_region; + }; + }; + + mbox_910t_client1: mbox_910t_client1 { + compatible = "thead,light-mbox-client"; + mbox-names = "902"; + mboxes = <&mbox_910t 1 0>; + status = "disabled"; + }; + + + mbox_910t_client2: mbox_910t_client2 { + compatible = "thead,light-mbox-client"; + mbox-names = "906"; + mboxes = <&mbox_910t 2 0>; + status = "disabled"; + }; + + lightsound: lightsound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Light-Sound-Card"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + dummy_codec: dummy_codec { + #sound-dai-cells = <0>; + compatible = "thead,light-dummy-pcm"; + sound-name-prefix = "DUMMY"; + status = "okay"; + }; + + reg_vref_1v8: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + reg_tp_pwr_en: regulator-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "PWR_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1_porta 12 1>; + enable-active-high; + regulator-always-on; + }; + + wcn_wifi: wireless-wlan { + compatible = "wlan-platdata"; + clock-names = "clk_wifi"; + ref-clock-frequency = <24000000>; + keep_wifi_power_on; + pinctrl-names = "default"; + wifi_chip_type = "rtl8723ds"; + WIFI,poweren_gpio = <&gpio2_porta 29 0>; + WIFI,reset_n = <&gpio2_porta 24 0>; + status = "okay"; + }; + + wcn_bt: wireless-bluetooth { + compatible = "bluetooth-platdata"; + pinctrl-names = "default", "rts_gpio"; + BT,power_gpio = <&gpio2_porta 25 0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_volume>; + pinctrl-names = "default"; + key-volumedown { + label = "Volume Down Key"; + linux,code = ; + debounce-interval = <1>; + gpios = <&ao_gpio_porta 11 0x1>; + }; + key-volumeup { + label = "Volume Up Key"; + linux,code = ; + debounce-interval = <1>; + gpios = <&ao_gpio_porta 10 0x1>; + }; + }; + + aon: light-aon { + compatible = "thead,light-aon"; + mbox-names = "aon"; + mboxes = <&mbox_910t 1 0>; + status = "okay"; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + c910_cpufreq { + compatible = "thead,light-mpw-cpufreq"; + status = "okay"; + }; + + test: light-aon-test { + compatible = "thead,light-aon-test"; + }; + }; +}; + +&resmem { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tee_mem: memory@1a000000 { + reg = <0x0 0x1a000000 0 0x4000000>; + no-map; + }; + + dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ + reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ + 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ + 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ + 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ + //no-map; + }; + dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ + reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ + 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ + 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ + 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ + //no-map; + }; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */ + 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + no-map; + }; + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; + //no-map; + }; +}; + +&adc { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + touch@5d { + #gpio-cells = <2>; + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio1_porta>; + interrupts = <8 0>; + irq-gpios = <&gpio1_porta 8 0>; + reset-gpios = <&gpio1_porta 7 0>; + AVDD28-supply = <®_tp_pwr_en>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + }; + +}; + +&audio_i2c0 { + clock-frequency = <100000>; + status = "okay"; + + es8156_audio_codec: es8156@8 { + #sound-dai-cells = <0>; + compatible = "everest,es8156"; + reg = <0x08>; + sound-name-prefix = "ES8156"; + status = "disabled"; + }; + + es7210_audio_codec: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + sound-name-prefix = "ES7210"; + status = "disabled"; + }; + + audio_aw87519_pa: amp@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + reset-gpio = <&ao_gpio4_porta 9 0x1>; + sound-name-prefix = "AW87519"; + status = "okay"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&spi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 + rx-sample-delay-ns = <10>; + status = "disabled"; + + spi_norflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + w25q,fast-read; + }; + + spidev@1 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x1>; + spi-max-frequency = <50000000>; + }; +}; + +&uart0 { + clocks = <&dummy_clock_uart_sclk>; + clock-names = "baudclk"; + clock-frequency = <100000000>; +}; + +&qspi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 3 0>; + rx-sample-dly = <4>; + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&qspi1 { + compatible = "snps,dw-apb-ssi"; + num-cs = <1>; + cs-gpios = <&gpio0_porta 1 0>; + status = "disabled"; + + spidev@0 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0>; + spi-max-frequency = <50000000>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_0>; + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_88E1111_0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy_88E1111_1: ethernet-phy@1 { + reg = <0x2>; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_1>; + status = "okay"; +}; + +&emmc { + max-frequency = <198000000>; + non-removable; + mmc-hs400-1_8v; + io_fixed_1v8; + is_emmc; + no-sdio; + no-sd; + pull_up; + bus-width = <8>; + status = "okay"; +}; + +&sdhci0 { + max-frequency = <198000000>; + bus-width = <4>; + pull_up; + wprtn_ignore; + status = "okay"; +}; + +&sdhci1 { + max-frequency = <100000000>; + bus-width = <4>; + pull_up; + no-sd; + no-mmc; + non-removable; + io_fixed_1v8; + rxclk-sample-delay = <80>; + post-power-on-delay-ms = <50>; + wprtn_ignore; + cap-sd-highspeed; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&padctrl0_apsys { /* right-pinctrl */ + light-evb-padctrl0 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart0: uart0grp { + thead,pins = < + FM_UART0_TXD 0x0 0x72 + FM_UART0_RXD 0x0 0x72 + >; + }; + + pinctrl_spi0: spi0grp { + thead,pins = < + FM_SPI_CSN 0x3 0x20a + FM_SPI_SCLK 0x0 0x20a + FM_SPI_MISO 0x0 0x23a + FM_SPI_MOSI 0x0 0x23a + >; + }; + + pinctrl_qspi0: qspi0grp { + thead,pins = < + FM_QSPI0_SCLK 0x0 0x20f + FM_QSPI0_CSN0 0x3 0x20f + FM_QSPI0_CSN1 0x0 0x20f + FM_QSPI0_D0_MOSI 0x0 0x23f + FM_QSPI0_D1_MISO 0x0 0x23f + FM_QSPI0_D2_WP 0x0 0x23f + FM_QSPI0_D3_HOLD 0x0 0x23f + >; + }; + + pinctrl_light_i2s0: i2s0grp { + thead,pins = < + FM_QSPI0_SCLK 0x2 0x208 + FM_QSPI0_CSN0 0x2 0x238 + FM_QSPI0_CSN1 0x2 0x208 + FM_QSPI0_D0_MOSI 0x2 0x238 + FM_QSPI0_D1_MISO 0x2 0x238 + FM_QSPI0_D2_WP 0x2 0x238 + FM_QSPI0_D3_HOLD 0x2 0x238 + >; + }; + + pinctrl_pwm: pwmgrp { + thead,pins = < + FM_GPIO3_2 0x1 0x208 /* pwm0 */ + >; + }; + }; +}; + +&padctrl1_apsys { /* left-pinctrl */ + light-evb-padctrl1 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart3: uart3grp { + thead,pins = < + FM_UART3_TXD 0x0 0x72 + FM_UART3_RXD 0x0 0x72 + >; + }; + + pinctrl_uart4: uart4grp { + thead,pins = < + FM_UART4_TXD 0x0 0x72 + FM_UART4_RXD 0x0 0x72 + FM_UART4_CTSN 0x0 0x72 + FM_UART4_RTSN 0x0 0x72 + >; + }; + + pinctrl_qspi1: qspi1grp { + thead,pins = < + FM_QSPI1_SCLK 0x0 0x20a + FM_QSPI1_CSN0 0x3 0x20a + FM_QSPI1_D0_MOSI 0x0 0x23a + FM_QSPI1_D1_MISO 0x0 0x23a + FM_QSPI1_D2_WP 0x0 0x23a + FM_QSPI1_D3_HOLD 0x0 0x23a + >; + }; + + + pinctrl_iso7816: iso7816grp { + thead,pins = < + FM_QSPI1_SCLK 0x1 0x208 + FM_QSPI1_D0_MOSI 0x1 0x238 + FM_QSPI1_D1_MISO 0x1 0x238 + FM_QSPI1_D2_WP 0x1 0x238 + FM_QSPI1_D3_HOLD 0x1 0x238 + >; + }; + + }; +}; + +&padctrl_aosys { + light-aon-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audiopa1: audiopa1_grp { + thead,pins = < + FM_AUDIO_PA1 0x3 0x72 + >; + }; + + pinctrl_audiopa2: audiopa2_grp { + thead,pins = < + FM_AUDIO_PA2 0x0 0x72 + >; + }; + + pinctrl_volume: volume_grp { + thead,pins = < + FM_AOGPIO_11 0x0 0x208 + FM_AOGPIO_10 0x3 0x208 + >; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; +}; + +&isp0 { + status = "disabled"; +}; + +&isp1 { + status = "disabled"; +}; + +&isp_ry0 { + status = "disabled"; +}; + +&dewarp { + status = "disabled"; +}; + +&dec400_isp0 { + status = "disabled"; +}; + +&dec400_isp1 { + status = "disabled"; +}; + +&dec400_isp2 { + status = "disabled"; +}; + +&bm_visys { + status = "disabled"; +}; + +&bm_csi0 { + status = "disabled"; +}; + +&bm_csi1 { + status = "disabled"; +}; + +&bm_csi2 { + status = "disabled"; +}; + +&vi_pre { + status = "disabled"; +}; + +&xtensa_dsp { + status = "disabled"; +}; + +&xtensa_dsp0 { + status = "disabled"; +}; + +&xtensa_dsp1 { + status = "disabled"; +}; + +&vvcam_flash_led0{ + status = "disabled"; +}; + + +&vvcam_sensor0 { + status = "disabled"; +}; + +&vvcam_sensor1 { + status = "disabled"; +}; + +&vvcam_sensor2 { + status = "disabled"; +}; + +&vvcam_sensor3 { + status = "disabled"; +}; + +&vvcam_sensor4 { + status = "disabled"; +}; + +&vvcam_sensor5 { + status = "disabled"; +}; + +&video0{ + status = "disabled"; +}; + + +&video1{ + status = "disabled"; +}; + +&video2{ + status = "disabled"; +}; + +&video3{ + status = "disabled"; +}; + +&video4{ + status = "disabled"; +}; + +&video5{ + status = "disabled"; +}; + +&video6{ + status = "disabled"; +}; + +&video7{ + status = "disabled"; +}; + + +&video8{ + status = "disabled"; +}; + +&video9{ + status = "disabled"; +}; + + +&video10{ + status = "disabled"; +}; + +&video11{ + status = "disabled"; +}; + +&video12{ + status = "disabled"; +}; + +&trng { + status = "disabled"; +}; + +&eip_28 { + status = "disabled"; +}; + +&vdec { + status = "disabled"; +}; + +&venc { + status = "disabled"; +}; + +&isp_venc_shake { + status = "disabled"; +}; + +&vidmem { + status = "disabled"; +}; + +&gpu { + status = "disabled"; +}; + +&npu { + status = "disabled"; +}; + +&fce { + status = "disabled"; +}; + +&dpu_enc0 { + status = "disabled"; +}; + +&dpu_enc1 { + status = "disabled"; +}; + +&dpu { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dhost_0 { + status = "disabled"; +}; + +&disp1_out { + status = "disabled"; +}; + +&hdmi_tx { + status = "disabled"; +}; + +&lightsound { + status = "disabled"; +}; + +&khvhost { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a-camera-tuning.dts b/arch/riscv/boot/dts/thead/th1520-lpi4a-camera-tuning.dts new file mode 100644 index 000000000000..36cd32e10140 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a-camera-tuning.dts @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-lpi4a-dsi0.dts" + + + +&video10{ // TUNINGTOOL + status = "okay"; + channel0 { + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; // 0=640 480 1=2592x1944 + path_type = "SENSOR_2592x1944_LINER"; + }; + dma { + path_type = "VIPRE_CSI0_ISP0"; + }; + }; +}; + +&video15{ + status = "okay"; + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + channel0 { + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0>; + csi_idx = <0>; + mode_idx = <0>; + path_type = "SENSOR_VGA_RAW12_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_DDR"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a-dsi0.dts b/arch/riscv/boot/dts/thead/th1520-lpi4a-dsi0.dts new file mode 100644 index 000000000000..60f1b0d813da --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a-dsi0.dts @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022-2023 Alibaba Group Holding Limited. + */ + +#include "th1520-lpi4a.dtsi" + +/ { + model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board"; + compatible = "thead,light-val", "thead,light-lpi4a", "thead,light"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x200000 0x1 0xffe00000>; + }; +}; + +&cmamem { + size = <0 0x20000000>; // 512MB on lpi4a (SOM) + alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000] +}; + +&i2c3 { + touch@14 { + #gpio-cells = <2>; + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&ao_gpio_porta>; + interrupts = <3 0>; + irq-gpios = <&ao_gpio_porta 3 0>; + reset-gpios = <&pcal6408ahk_d 0 0>; + AVDD28-supply = <®_tp_pwr_en>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1200>; + tp-size = <9271>; + status = "okay"; + }; +}; + +&dsi0 { + status = "okay"; +}; + +&dhost_0 { + panel0@0 { + compatible = "chongzhou,cz101b4001", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&lcd0_backlight>; + reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */ + hsvcc-supply = <&soc_vdd18_lcd0_en_reg>; + vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a-hx8279.dts b/arch/riscv/boot/dts/thead/th1520-lpi4a-hx8279.dts new file mode 100644 index 000000000000..65218d3e62db --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a-hx8279.dts @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022-2023 Alibaba Group Holding Limited. + */ + +#include "th1520-lpi4a.dtsi" + +/ { + model = "T-HEAD Light Lichee Pi 4A configuration for 8GB DDR board"; + compatible = "thead,light-val", "thead,light-lpi4a", "thead,light"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x200000 0x1 0xffe00000>; + }; +}; + +&cmamem { + size = <0 0x20000000>; // 512MB on lpi4a (SOM) + alloc-ranges = <0 0xd8000000 0 0x20000000>; // [0x0D800_0000 ~ 0x0F800_0000] +}; + +&i2c3 { + touch@14 { + #gpio-cells = <2>; + compatible = "goodix,gt9271"; + reg = <0x14>; + interrupt-parent = <&ao_gpio_porta>; + interrupts = <3 0>; + irq-gpios = <&ao_gpio_porta 3 0>; + reset-gpios = <&pcal6408ahk_d 0 0>; + AVDD28-supply = <®_tp_pwr_en>; + touchscreen-size-x = <1200>; + touchscreen-size-y = <1920>; + tp-size = <9271>; + status = "okay"; + }; +}; + +&dsi0 { + status = "okay"; +}; + + +&dhost_0 { + panel0@0 { + compatible = "himax,hx8279"; + reg = <0>; + backlight = <&lcd0_backlight>; + reset-gpio = <&pcal6408ahk_d 7 0>; /* active low */ + hsvcc-supply = <&soc_vdd18_lcd0_en_reg>; + vspn3v3-supply = <&soc_vdd33_lcd0_en_reg>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a-product-crash.dts b/arch/riscv/boot/dts/thead/th1520-lpi4a-product-crash.dts new file mode 100644 index 000000000000..b8ee1a696db1 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a-product-crash.dts @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Alibaba Group Holding Limited. + */ + +#include "th1520-crash.dtsi" + +&aon { + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a-product-sec.dts b/arch/riscv/boot/dts/thead/th1520-lpi4a-product-sec.dts new file mode 100644 index 000000000000..cfa3412aff9b --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a-product-sec.dts @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-lpi4a-product.dts" + + +&light_iopmp { + status = "disabled"; +}; + +&eip_28 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a-product.dts b/arch/riscv/boot/dts/thead/th1520-lpi4a-product.dts new file mode 100644 index 000000000000..44c48143ad19 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a-product.dts @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520-lpi4a-dsi0.dts" + +&lightsound { + status = "okay"; + simple-audio-card,dai-link@0 { /* I2S - HDMI*/ + reg = <0>; + format = "i2s"; + cpu { + sound-dai = <&light_i2s 1>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&i2s1 0>; + }; + codec { + sound-dai = <&es7210_audio_codec>; + }; + }; + simple-audio-card,dai-link@2 { /* I2S - AUDIO SYS CODEC 8156*/ + reg = <2>; + format = "i2s"; + cpu { + sound-dai = <&i2s1 0>; + }; + codec { + sound-dai = <&es8156_audio_codec>; + }; + }; +}; + +&dpu_enc0 { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lpi4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lpi4a.dtsi new file mode 100644 index 000000000000..88629118203d --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lpi4a.dtsi @@ -0,0 +1,1911 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +/dts-v1/; + +#include "th1520.dtsi" +#include +#include +#include "th1520-vi-devices.dtsi" +/ { + chosen { + bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000"; + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + status = "disabled"; + led0 { + label = "SYS_STATUS"; + gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */ + default-state = "off"; + }; + }; + + display-subsystem { + status = "okay"; + }; + + lcd0_backlight: pwm-backlight@0 { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + light_iopmp: iopmp { + compatible = "thead,light-iopmp"; + + /* config#1: multiple valid regions */ + iopmp_emmc: IOPMP_EMMC { + regions = <0x000000 0x100000>, + <0x100000 0x200000>; + attr = <0xFFFFFFFF>; + dummy_slave= <0x800000>; + }; + + /* config#2: iopmp bypass */ + iopmp_sdio0: IOPMP_SDIO0 { + bypass_en; + }; + + /* config#3: iopmp default region set */ + iopmp_sdio1: IOPMP_SDIO1 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_usb0: IOPMP_USB0 { + attr = <0xFFFFFFFF>; + is_default_region; + }; + + iopmp_ao: IOPMP_AO { + is_default_region; + }; + + iopmp_aud: IOPMP_AUD { + is_default_region; + }; + + iopmp_chip_dbg: IOPMP_CHIP_DBG { + is_default_region; + }; + + iopmp_eip120i: IOPMP_EIP120I { + is_default_region; + }; + + iopmp_eip120ii: IOPMP_EIP120II { + is_default_region; + }; + + iopmp_eip120iii: IOPMP_EIP120III { + is_default_region; + }; + + iopmp_isp0: IOPMP_ISP0 { + is_default_region; + }; + + iopmp_isp1: IOPMP_ISP1 { + is_default_region; + }; + + iopmp_dw200: IOPMP_DW200 { + is_default_region; + }; + + iopmp_vipre: IOPMP_VIPRE { + is_default_region; + }; + + iopmp_venc: IOPMP_VENC { + is_default_region; + }; + + iopmp_vdec: IOPMP_VDEC { + is_default_region; + }; + + iopmp_g2d: IOPMP_G2D { + is_default_region; + }; + + iopmp_fce: IOPMP_FCE { + is_default_region; + }; + + iopmp_npu: IOPMP_NPU { + is_default_region; + }; + + iopmp0_dpu: IOPMP0_DPU { + bypass_en; + }; + + iopmp1_dpu: IOPMP1_DPU { + bypass_en; + }; + + iopmp_gpu: IOPMP_GPU { + is_default_region; + }; + + iopmp_gmac1: IOPMP_GMAC1 { + is_default_region; + }; + + iopmp_gmac2: IOPMP_GMAC2 { + is_default_region; + }; + + iopmp_dmac: IOPMP_DMAC { + is_default_region; + }; + + iopmp_tee_dmac: IOPMP_TEE_DMAC { + is_default_region; + }; + + iopmp_dsp0: IOPMP_DSP0 { + is_default_region; + }; + + iopmp_dsp1: IOPMP_DSP1 { + is_default_region; + }; + + iopmp_audio0: IOPMP_AUDIO0 { + is_default_region; + }; + + iopmp_audio1: IOPMP_AUDIO1 { + is_default_region; + }; + }; + + mbox_910t_client1: mbox_910t_client1 { + compatible = "thead,light-mbox-client"; + mbox-names = "902"; + mboxes = <&mbox_910t 1 0>; + status = "disabled"; + }; + + + mbox_910t_client2: mbox_910t_client2 { + compatible = "thead,light-mbox-client"; + mbox-names = "906"; + mboxes = <&mbox_910t 2 0>; + audio-mbox-regmap = <&audio_mbox>; + status = "okay"; + }; + + lightsound: lightsound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Light-Sound-Card"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + light_rpmsg: light_rpmsg { + compatible = "light,rpmsg-bus", "simple-bus"; + memory-region = <&rpmsgmem>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + rpmsg: rpmsg{ + vdev-nums = <1>; + reg = <0x0 0x1E000000 0 0x10000>; + compatible = "light,light-rpmsg"; + status = "okay"; + }; + }; + + dummy_codec: dummy_codec { + #sound-dai-cells = <0>; + compatible = "thead,light-dummy-pcm"; + status = "okay"; + sound-name-prefix = "DUMMY"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm 1 10000000 0>; + cooling-levels = <0 64 192 255>; + }; + + reg_vref_1v8: regulator-adc-verf { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + status = "okay"; + }; + + reg_tp_pwr_en: regulator-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "regulator-pwr-en"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_d 4 1>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vdd1v2: regulator-hub-vdd12-en { + compatible = "regulator-fixed"; + regulator-name = "regulator-hub-vdd12-en"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pcal6408ahk_d 2 1>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vcc5v: regulator-hub-vcc5v-en { + compatible = "regulator-fixed"; + regulator-name = "regulator-hub-vcc5v-en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6408ahk_d 3 1>; + enable-active-high; + regulator-always-on; + }; + + wcn_wifi: wireless-wlan { + compatible = "wlan-platdata"; + clock-names = "clk_wifi"; + ref-clock-frequency = <24000000>; + keep_wifi_power_on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_wake>; + wifi_chip_type = "rtl8723ds"; + WIFI,poweren_gpio = <&pcal6408ahk_c 4 0>; + status = "okay"; + }; + + wcn_bt: wireless-bluetooth { + compatible = "bluetooth-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_wake>; + BT,power_gpio = <&pcal6408ahk_c 5 0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_volume>; + pinctrl-names = "default"; + key-volumedown { + label = "Volume Down Key"; + linux,code = ; + debounce-interval = <1>; + gpios = <&gpio1_porta 19 0x1>; + }; + key-volumeup { + label = "Volume Up Key"; + linux,code = ; + debounce-interval = <1>; + gpios = <&gpio2_porta 25 0x1>; + }; + }; + + aon: aon { + compatible = "thead,light-aon"; + mbox-names = "aon"; + mboxes = <&mbox_910t 1 0>; + status = "okay"; + + pd: light-aon-pd { + compatible = "thead,light-aon-pd"; + #power-domain-cells = <1>; + }; + + soc_aud_3v3_en_reg: soc_aud_3v3_en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + }; + + soc_aud_1v8_en_reg: soc_aud_1v8_en { + compatible = "regulator-fixed"; + regulator-name = "soc_aud_1v8_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + soc_vdd_3v3_en_reg: soc_vdd_3v3_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0_porta 30 1>; + enable-active-high; + regulator-always-on; + }; + + soc_vdd33_lcd0_en_reg: soc_lcd0_vdd33_en { + compatible = "regulator-fixed"; + regulator-name = "soc_lcd0_vdd33_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6408ahk_d 5 1>; + enable-active-high; + }; + + soc_vdd18_lcd0_en_reg: soc_lcd0_vdd18_en { + compatible = "regulator-fixed"; + regulator-name = "soc_lcd0_vdd18_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_d 6 1>; + enable-active-high; + }; + + soc_vdd5v_se_en_reg: soc_vdd5v_se_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vdd5v_se_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2_porta 14 1>; + enable-active-high; + regulator-always-on; + }; + + soc_wcn33_en_reg: soc_wcn33_en { + compatible = "regulator-fixed"; + regulator-name = "soc_wcn33_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2_porta 29 1>; + enable-active-high; + regulator-always-on; + }; + + soc_vbus_en_reg: soc_vbus_en { + compatible = "regulator-fixed"; + regulator-name = "soc_vbus_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1_porta 22 1>; + enable-active-high; + regulator-always-on; + }; + + + soc_avdd28_rgb_reg: soc_avdd28_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd28_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_b 1 1>; + enable-active-high; + }; + + soc_dovdd18_rgb_reg: soc_dovdd18_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_b 2 1>; + enable-active-high; + }; + + soc_dvdd12_rgb_reg: soc_dvdd12_rgb { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_rgb"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pcal6408ahk_b 0 1>; + enable-active-high; + }; + + soc_avdd25_ir_reg: soc_avdd25_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_avdd25_ir"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + gpio = <&pcal6408ahk_b 5 1>; + enable-active-high; + }; + + soc_dovdd18_ir_reg: soc_dovdd18_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_dovdd18_ir"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_b 3 1>; + enable-active-high; + }; + + soc_dvdd12_ir_reg: soc_dvdd12_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_dvdd12_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pcal6408ahk_b 4 1>; + enable-active-high; + }; + + soc_cam2_avdd25_ir_reg: soc_cam2_avdd25_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_cam2_avdd25_ir"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + gpio = <&pcal6408ahk_b 7 1>; + enable-active-high; + }; + + soc_cam2_dovdd18_ir_reg: soc_cam2_dovdd18_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_cam2_dovdd18_ir"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pcal6408ahk_b 6 1>; + enable-active-high; + }; + + soc_cam2_dvdd12_ir_reg: soc_cam2_dvdd12_ir { + compatible = "regulator-fixed"; + regulator-name = "soc_cam2_dvdd12_ir"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pcal6408ahk_c 0 1>; + enable-active-high; + }; + + aon_reg_dialog: light-dialog-reg { + compatible = "thead,light-dialog-pmic-ant"; + status = "okay"; + + dvdd_cpu_reg: appcpu_dvdd { + regulator-name = "appcpu_dvdd"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + dvddm_cpu_reg: appcpu_dvddm { + regulator-name = "appcpu_dvddm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1570000>; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_aon_reg: soc_dvdd18_aon { + regulator-name = "soc_dvdd18_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd33_usb3_reg: soc_avdd33_usb3 { + regulator-name = "soc_avdd33_usb3"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_aon_reg: soc_dvdd08_aon { + regulator-name = "soc_dvdd08_aon"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ddr_reg: soc_dvdd08_ddr { + regulator-name = "soc_dvdd08_ddr"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 { + regulator-name = "soc_vdd_ddr_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 { + regulator-name = "soc_vdd_ddr_1v1"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 { + regulator-name = "soc_vdd_ddr_0v6"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd18_ap_reg: soc_dvdd18_ap { + regulator-name = "soc_dvdd18_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dvdd08_ap_reg: soc_dvdd08_ap { + regulator-name = "soc_dvdd08_ap"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi { + regulator-name = "soc_avdd08_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi { + regulator-name = "soc_avdd18_mipi_hdmi"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd33_emmc_reg: soc_vdd33_emmc { + regulator-name = "soc_vdd33_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_vdd18_emmc_reg: soc_vdd18_emmc { + regulator-name = "soc_vdd18_emmc"; + regulator-boot-on; + regulator-always-on; + }; + + soc_dovdd18_scan_reg: soc_dovdd18_scan { + regulator-name = "soc_dovdd18_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + soc_dvdd12_scan_reg: soc_dvdd12_scan { + regulator-name = "soc_dvdd12_scan"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + soc_avdd28_scan_en_reg: soc_avdd28_scan_en { + regulator-name = "soc_avdd28_scan_en"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <3600000>; + }; + + }; + + c910_cpufreq { + compatible = "thead,light-mpw-cpufreq"; + status = "okay"; + }; + + test: light-aon-test { + compatible = "thead,light-aon-test"; + }; + }; + + thermal-zones { + cpu-thermal-zone { + sustainable-power = <1600>; + + trips { + fan_config0: fan-trip0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + fan_config1: fan-trip1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + + fan_config2: fan-trip2 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + }; + + cooling-maps { + fan-on { + trip = <&fan_config0>; + cooling-device = + <&fan 1 1>; + }; + fan-faster { + trip = <&fan_config1>; + cooling-device = + <&fan 2 2>; + }; + fan-full { + trip = <&fan_config2>; + cooling-device = + <&fan 3 3>; + }; + }; + }; + + dev-thermal-zone { + sustainable-power = <3000>; + }; + }; + +}; + +&resmem { + #address-cells = <2>; + #size-cells = <2>; + ranges; + //Note: with "no-map" reserv mem not saved in hibernation + tee_mem: memory@1c000000 { + reg = <0x0 0x1c000000 0 0x2000000>; + no-map; + }; + + dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/ + reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/ + 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/ + 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */ + 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/ + }; + dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/ + reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */ + 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */ + 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/ + 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */ + }; + vi_mem: framebuffer@10000000 { + reg = <0x0 0x10000000 0x0 0x6700000>; /* vi_mem_pool_region[0] 44 MB (default) */ + //0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */ + //0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */ + no-map; + }; + facelib_mem: memory@17000000 { + reg = <0x0 0x17000000 0 0x02000000>; + }; + audio_mem: memory@32000000 { + reg = <0x0 0x32000000 0x0 0x6400000>; + }; + rpmsgmem: memory@1E000000 { + reg = <0x0 0x1E000000 0x0 0x10000>; + }; + +}; + +&adc { + vref-supply = <®_vref_1v8>; + #io-channel-cells = <1>; + status = "okay"; +}; + +&audio_i2c0 { + clock-frequency = <100000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa29>, + <&pinctrl_audiopa30>, + <&pinctrl_audio_i2c0>; + + es8156_audio_codec: es8156@8 { + #sound-dai-cells = <0>; + compatible = "everest,es8156"; + reg = <0x08>; + sound-name-prefix = "ES8156"; + AVDD-supply = <&soc_aud_3v3_en_reg>; + DVDD-supply = <&soc_aud_1v8_en_reg>; + PVDD-supply = <&soc_aud_1v8_en_reg>; + }; + + es7210_audio_codec: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + sound-name-prefix = "ES7210"; + MVDD-supply = <&soc_aud_3v3_en_reg>; + AVDD-supply = <&soc_aud_3v3_en_reg>; + DVDD-supply = <&soc_aud_1v8_en_reg>; + PVDD-supply = <&soc_aud_1v8_en_reg>; + }; + + audio_aw87519_pa: amp@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + sound-name-prefix = "AW87519"; + status = "disabled"; + }; + + audio_aw87519_pa1@5b { + compatible = "awinic,aw87519_pa"; + reg = <0x5b>; + status = "disabled"; + }; + +}; + +&audio_i2c1 { + clock-frequency = <100000>; + status = "okay"; + pinctrl-0 = <&pinctrl_audiopa6>, + <&pinctrl_audiopa7>, + <&pinctrl_audio_i2c1>; + + es8156_audio_codec_1: es8156@8 { + #sound-dai-cells = <0>; + compatible = "everest,es8156"; + reg = <0x08>; + status = "disabled"; + }; + + es7210_audio_codec_1: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + status = "disabled"; + }; + + audio_aw87519_pa2@58 { + compatible = "awinic,aw87519_pa"; + reg = <0x58>; + status = "disabled"; + }; + + audio_aw87519_pa3@5b { + compatible = "awinic,aw87519_pa"; + reg = <0x5b>; + status = "disabled"; + }; +}; + +&spi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0 + rx-sample-delay-ns = <10>; + + spi_norflash@0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + w25q,fast-read; + }; + + spidev@1 { + status = "disable"; + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x1>; + spi-max-frequency = <50000000>; + }; +}; + +&uart0 { + clock-frequency = <100000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&qspi0 { + num-cs = <1>; + cs-gpios = <&gpio2_porta 3 0>; + rx-sample-dly = <4>; + status = "disabled"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + + partition@0 { + label = "ubi1"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&qspi1 { + compatible = "snps,dw-apb-ssi"; + num-cs = <1>; + cs-gpios = <&gpio0_porta 1 0>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0>; + spi-max-frequency = <50000000>; + }; + +}; + +&gmac0 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_88E1111_0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy_88E1111_1: ethernet-phy@1 { + reg = <0x2>; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + rx-clk-delay = <0x00>; /* for RGMII */ + tx-clk-delay = <0x00>; /* for RGMII */ + phy-handle = <&phy_88E1111_1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac1>; +}; + +&emmc { + max-frequency = <198000000>; + non-removable; + mmc-hs400-1_8v; + io_fixed_1v8; + is_emmc; + no-sdio; + no-sd; + pull_up; + bus-width = <8>; + status = "okay"; +}; + +&sdhci0 { + max-frequency = <100000000>; + bus-width = <4>; + pull_up; + wprtn_ignore; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdio0>; +}; + +&sdhci1 { + max-frequency = <100000000>; + bus-width = <4>; + pull_up; + no-sd; + no-mmc; + non-removable; + io_fixed_1v8; + post-power-on-delay-ms = <50>; + wprtn_ignore; + cap-sd-highspeed; + wakeup-source; + status = "okay"; +}; + +&padctrl0_apsys { /* right-pinctrl */ + light-evb-padctrl0 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_uart0: uart0grp { + thead,pins = < + FM_UART0_TXD 0x0 0x202 + FM_UART0_RXD 0x0 0x202 + >; + }; + + pinctrl_i2c2: i2c2grp { + thead,pins = < + FM_I2C2_SCL 0x0 0x204 + FM_I2C2_SDA 0x0 0x204 + >; + }; + + pinctrl_i2c3: i2c3grp { + thead,pins = < + FM_I2C3_SCL 0x0 0x204 + FM_I2C3_SDA 0x0 0x204 + >; + }; + + pinctrl_spi0: spi0grp { + thead,pins = < + FM_SPI_CSN 0x3 0x20a + FM_SPI_SCLK 0x0 0x20a + FM_SPI_MISO 0x0 0x23a + FM_SPI_MOSI 0x0 0x23a + >; + }; + + pinctrl_qspi0: qspi0grp { + thead,pins = < + FM_QSPI0_SCLK 0x0 0x20f + FM_QSPI0_CSN0 0x3 0x20f + FM_QSPI0_CSN1 0x0 0x20f + FM_QSPI0_D0_MOSI 0x0 0x23f + FM_QSPI0_D1_MISO 0x0 0x23f + FM_QSPI0_D2_WP 0x0 0x23f + FM_QSPI0_D3_HOLD 0x0 0x23f + >; + }; + + pinctrl_light_i2s0: i2s0grp { + thead,pins = < + FM_QSPI0_SCLK 0x2 0x208 + FM_QSPI0_CSN0 0x2 0x238 + FM_QSPI0_CSN1 0x2 0x208 + FM_QSPI0_D0_MOSI 0x2 0x238 + FM_QSPI0_D1_MISO 0x2 0x238 + FM_QSPI0_D2_WP 0x2 0x238 + FM_QSPI0_D3_HOLD 0x2 0x238 + >; + }; + + pinctrl_gmac1: gmac1grp { + thead,pins = < + FM_GPIO2_18 0x1 0x20f /* GMAC1_TX_CLK */ + FM_GPIO2_19 0x1 0x20f /* GMAC1_RX_CLK */ + FM_GPIO2_20 0x1 0x20f /* GMAC1_TXEN */ + FM_GPIO2_21 0x1 0x20f /* GMAC1_TXD0 */ + FM_GPIO2_22 0x1 0x20f /* GMAC1_TXD1 */ + FM_GPIO2_23 0x1 0x20f /* GMAC1_TXD2 */ + FM_GPIO2_24 0x1 0x20f /* GMAC1_TXD3 */ + FM_GPIO2_25 0x1 0x20f /* GMAC1_RXDV */ + FM_GPIO2_30 0x1 0x20f /* GMAC1_RXD0 */ + FM_GPIO2_31 0x1 0x20f /* GMAC1_RXD1 */ + FM_GPIO3_0 0x1 0x20f /* GMAC1_RXD2 */ + FM_GPIO3_1 0x1 0x20f /* GMAC1_RXD3 */ + >; + }; + + pinctrl_sdio0: sdio0grp { + thead,pins = < + FM_SDIO0_DETN 0x0 0x202 + >; + }; + + pinctrl_pwm: pwmgrp { + thead,pins = < + FM_GPIO3_2 0x1 0x20f /* pwm0 */ + FM_GPIO3_3 0x1 0x20f /* pwm1 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + thead,pins = < + FM_HDMI_SCL 0x0 0x202 + FM_HDMI_SDA 0x0 0x202 + FM_HDMI_CEC 0x0 0x202 + >; + }; + + pinctrl_gmac0: gmac0grp { + thead,pins = < + FM_GMAC0_TX_CLK 0x0 0x20f /* GMAC0_TX_CLK */ + FM_GMAC0_RX_CLK 0x0 0x20f /* GMAC0_RX_CLK */ + FM_GMAC0_TXEN 0x0 0x20f /* GMAC0_TXEN */ + FM_GMAC0_TXD0 0x0 0x20f /* GMAC0_TXD0 */ + FM_GMAC0_TXD1 0x0 0x20f /* GMAC0_TXD1 */ + FM_GMAC0_TXD2 0x0 0x20f /* GMAC0_TXD2 */ + FM_GMAC0_TXD3 0x0 0x20f /* GMAC0_TXD3 */ + FM_GMAC0_RXDV 0x0 0x20f /* GMAC0_RXDV */ + FM_GMAC0_RXD0 0x0 0x20f /* GMAC0_RXD0 */ + FM_GMAC0_RXD1 0x0 0x20f /* GMAC0_RXD1 */ + FM_GMAC0_RXD2 0x0 0x20f /* GMAC0_RXD2 */ + FM_GMAC0_RXD3 0x0 0x20f /* GMAC0_RXD3 */ + FM_GMAC0_MDC 0x0 0x208 /* GMAC0_MDC */ + FM_GMAC0_MDIO 0x0 0x208 /* GMAC0_MDIO */ + FM_GMAC0_COL 0x3 0x232 /* PHY0_nRST */ + FM_GMAC0_CRS 0x3 0x232 /* PHY0_nINT */ + >; + }; + }; +}; + +&padctrl1_apsys { /* left-pinctrl */ + light-evb-padctrl1 { + /* + * Pin Configuration Node: + * Format: + */ + pinctrl_qspi1: qspi1grp { + thead,pins = < + FM_QSPI1_SCLK 0x0 0x20a + FM_QSPI1_CSN0 0x3 0x20a + FM_QSPI1_D0_MOSI 0x0 0x23a + FM_QSPI1_D1_MISO 0x0 0x23a + >; + }; + + pinctrl_i2c0: i2c0grp { + thead,pins = < + FM_I2C0_SCL 0x0 0x204 + FM_I2C0_SDA 0x0 0x204 + >; + }; + + pinctrl_i2c1: i2c1grp { + thead,pins = < + FM_I2C1_SCL 0x0 0x204 + FM_I2C1_SDA 0x0 0x204 + >; + }; + + pinctrl_uart1: uart1grp { + thead,pins = < + FM_UART1_TXD 0x0 0x202 + FM_UART1_RXD 0x0 0x202 + >; + }; + + pinctrl_uart4: uart4grp { + thead,pins = < + FM_UART4_TXD 0x0 0x202 + FM_UART4_RXD 0x0 0x202 + FM_UART4_CTSN 0x0 0x202 + FM_UART4_RTSN 0x0 0x202 + >; + }; + + pinctrl_uart3: uart3grp { + thead,pins = < + FM_UART3_TXD 0x1 0x202 + FM_UART3_RXD 0x1 0x202 + >; + }; + + pinctrl_wifi_wake: wifi_grp { + thead,pins = < + FM_GPIO0_27 0x0 0x202 + >; + }; + + pinctrl_bt_wake: bt_grp { + thead,pins = < + FM_GPIO0_28 0x0 0x202 + >; + }; + + pinctrl_iso7816: iso7816grp { + thead,pins = < + FM_QSPI1_SCLK 0x1 0x208 + FM_QSPI1_D0_MOSI 0x1 0x238 + FM_QSPI1_D1_MISO 0x1 0x238 + FM_QSPI1_D2_WP 0x1 0x238 + FM_QSPI1_D3_HOLD 0x1 0x238 + >; + }; + + pinctrl_volume: volume_grp { + thead,pins = < + FM_CLK_OUT_2 0x3 0x208 + >; + }; + }; +}; + +&padctrl_aosys { + light-aon-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audiopa1: audiopa1_grp { + thead,pins = < + FM_AUDIO_PA1 0x3 0x72 + >; + }; + + pinctrl_audiopa2: audiopa2_grp { + thead,pins = < + FM_AUDIO_PA2 0x0 0x72 + >; + }; + pinctrl_audiopa6: audiopa6 { + thead,pins = < FM_AUDIO_PA6 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa7: audiopa7 { + thead,pins = < FM_AUDIO_PA7 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa14: audiopa14 { + thead,pins = < FM_AUDIO_PA14 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa15: audiopa15 { + thead,pins = < FM_AUDIO_PA15 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa16: audiopa16 { + thead,pins = < FM_AUDIO_PA16 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa17: audiopa17 { + thead,pins = < FM_AUDIO_PA17 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa18: audiopa18 { + thead,pins = < FM_AOGPIO_7 LIGHT_PIN_FUNC_1 0x000 >; + }; + pinctrl_audiopa19: audiopa19 { + thead,pins = < FM_AOGPIO_8 LIGHT_PIN_FUNC_1 0x000 >; + }; + pinctrl_audiopa21: audiopa21 { + thead,pins = < FM_AOGPIO_10 LIGHT_PIN_FUNC_1 0x000 >; + }; + pinctrl_audiopa22: audiopa22 { + thead,pins = < FM_AOGPIO_11 LIGHT_PIN_FUNC_1 0x000 >; + }; + pinctrl_audiopa29: audiopa29 { + thead,pins = < FM_AUDIO_PA29 LIGHT_PIN_FUNC_0 0x000 >; + }; + pinctrl_audiopa30: audiopa30 { + thead,pins = < FM_AUDIO_PA30 LIGHT_PIN_FUNC_0 0x000 >; + }; + + }; +}; + +&padctrl_audiosys { + + status = "okay"; + + light-audio-padctrl { + /* + * Pin Configuration Node: + * Format: + */ + + pinctrl_audio_i2c0: audio_i2c0_grp { + thead,pins = < + FM_AUDIO_IO_PA29 LIGHT_PIN_FUNC_2 0x004 + FM_AUDIO_IO_PA30 LIGHT_PIN_FUNC_2 0x004 + >; + }; + pinctrl_audio_i2c1: audio_i2c1_grp { + thead,pins = < + FM_AUDIO_IO_PA6 LIGHT_PIN_FUNC_2 0x004 + FM_AUDIO_IO_PA7 LIGHT_PIN_FUNC_2 0x004 + >; + }; + pinctrl_audio_i2s1: audio_i2s1_grp { + thead,pins = < + FM_AUDIO_IO_PA14 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA15 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA16 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA17 LIGHT_PIN_FUNC_0 0x008 + >; + }; + pinctrl_audio_i2s2: audio_i2s2_grp { + thead,pins = < + FM_AUDIO_IO_PA18 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA19 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA21 LIGHT_PIN_FUNC_0 0x008 + FM_AUDIO_IO_PA22 LIGHT_PIN_FUNC_0 0x008 + >; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + + pcal6408ahk_b: gpio@20 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + pcal6408ahk_c: gpio@20 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + + pcal6408ahk_d: gpio@20 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; +}; + +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + +&isp_ry0 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; + +&dec400_isp0 { + status = "okay"; +}; + +&dec400_isp1 { + status = "okay"; +}; + +&dec400_isp2 { + status = "okay"; +}; + +&bm_visys { + status = "okay"; +}; + +&bm_csi0 { + status = "okay"; +}; + +&bm_csi1 { + status = "okay"; +}; + +&bm_csi2 { + status = "okay"; +}; + +&vi_pre { + //vi_pre_irq_en = <1>; + status = "okay"; +}; + +&xtensa_dsp { + status = "okay"; +}; + +&xtensa_dsp0 { + status = "okay"; + memory-region = <&dsp0_mem>; +}; + +&xtensa_dsp1 { + status = "okay"; + memory-region = <&dsp1_mem>; +}; + +&vvcam_sensor0 { + sensor_name = "OV12870"; + sensor_regulators = "soc_dovdd18_rgb", "soc_dvdd12_rgb", "soc_avdd28_rgb"; + sensor_regulator_timing_us = <70 50 20>; + sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin + sensor_rst = <&pcal6408ahk_c 1 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x10>; + i2c_bus = /bits/ 8 <0>; + status = "okay"; +}; + +&vvcam_sensor1 {//cam1 csia + sensor_name = "SC132GS"; + sensor_regulators = "soc_dovdd18_ir", "soc_dvdd12_ir", "soc_avdd25_ir"; + sensor_regulator_timing_us = <70 1000 2000>; + i2c_addr = /bits/ 8 <0x30>; + sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin + sensor_rst = <&pcal6408ahk_c 2 0>; + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>; + DVDD12_IR-supply = <&soc_dvdd12_ir_reg>; + AVDD25_IR-supply = <&soc_avdd25_ir_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_bus = /bits/ 8 <1>; + status = "okay"; +}; + +&vvcam_sensor2 {//cam2 csib + sensor_name = "SC132GS"; + sensor_regulators = "soc_cam2_dovdd18_ir", "soc_cam2_dvdd12_ir", "soc_cam2_avdd25_ir"; + sensor_regulator_timing_us = <70 1000 2000>; + i2c_addr = /bits/ 8 <0x30>; + sensor_pdn = <&gpio2_porta 13 0>; //powerdown pin / shutdown pin + sensor_rst = <&pcal6408ahk_c 3 0>; + sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_IR-supply = <&soc_cam2_dovdd18_ir_reg>; + DVDD12_IR-supply = <&soc_cam2_dvdd12_ir_reg>; + AVDD25_IR-supply = <&soc_cam2_avdd25_ir_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_bus = /bits/ 8 <2>; + status = "okay"; +}; + +&vvcam_sensor3 {//cam3 csi0 modified + sensor_name = "OV5693"; + sensor_regulators = "soc_dovdd18_rgb", "soc_dvdd12_rgb", "soc_avdd28_rgb"; + sensor_regulator_timing_us = <70 50 20>; + sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin + sensor_rst = <&pcal6408ahk_c 1 0>; + sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready + DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>; + DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>; + AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>; + i2c_reg_width = /bits/ 8 <2>; + i2c_data_width = /bits/ 8 <1>; + i2c_addr = /bits/ 8 <0x36>; + i2c_bus = /bits/ 8 <0>; + status = "okay"; +}; + +&video2 { + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + status = "okay"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <2600>; + max_height = <2000>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel1 { + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP"; + output { + max_width = <2600>; + max_height = <2000>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; + channel2 { + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP2_BP"; + output { + max_width = <2600>; + max_height = <2000>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + }; +}; + +&video3{ + vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0] + status = "okay"; + channel0 { + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <2600>; + max_height = <2000>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + dw_dst_depth = <2>; + }; + }; + channel1 { + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <2600>; + max_height = <2000>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + dw_dst_depth = <2>; + }; + }; + channel2 { + sensor1 { + subdev_name = "vivcam"; + idx = <3>; + csi_idx = <0>; + mode_idx = <1>; + path_type = "SENSOR_2592x1944_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + output { + max_width = <2600>; + max_height = <2000>; + bit_per_pixel = <12>; + frame_count = <3>; + }; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + dw_dst_depth = <2>; + }; + }; +}; + + +&trng { + status = "disabled"; +}; + +&eip_28 { + status = "okay"; +}; + +&vdec { + status = "okay"; +}; + +&venc { + status = "okay"; +}; + +&isp_venc_shake { + status = "okay"; +}; + +&vidmem { + status = "okay"; + memory-region = <&vi_mem>; +}; + +&gpu { + status = "okay"; +}; + +&npu { + vha_clk_rate = <1000000000>; + status = "okay"; +}; + +&fce { + memory-region = <&facelib_mem>; + status = "okay"; +}; + +&dpu_enc1 { + ports { + /delete-node/ port@0; + }; +}; + +&dpu { + status = "okay"; +}; + +&dhost_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_in: endpoint { + remote-endpoint = <&enc0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&disp1_out { + remote-endpoint = <&hdmi_tx_in>; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + + port@0 { + /* input */ + hdmi_tx_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; +}; + +&lightsound { + status = "okay"; + simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/ + reg = <0>; + format = "i2s"; + cpu { + sound-dai = <&i2s1 0>; + }; + codec { + sound-dai = <&es8156_audio_codec>; + }; + }; + simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/ + reg = <1>; + format = "i2s"; + cpu { + sound-dai = <&i2s1 0>; + }; + codec { + sound-dai = <&es7210_audio_codec>; + }; + }; + simple-audio-card,dai-link@2 { /* I2S - HDMI*/ + reg = <2>; + format = "i2s"; + cpu { + sound-dai = <&light_i2s 1>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; +}; + +&light_i2s { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa14>, + <&pinctrl_audiopa15>, + <&pinctrl_audiopa16>, + <&pinctrl_audiopa17>, + <&pinctrl_audio_i2s1>; + light,mclk_keepon = <1>; +}; + +&i2s2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audiopa18>, + <&pinctrl_audiopa19>, + <&pinctrl_audiopa21>, + <&pinctrl_audiopa22>, + <&pinctrl_audio_i2s2>; +}; + +&usb_1 { + hubswitch-gpio = <&ao_gpio_porta 4 0>; + vbus-supply = <&soc_vbus_en_reg>; + hub1v2-supply = <®_usb_hub_vdd1v2>; + hub5v-supply = <®_usb_hub_vcc5v>; +}; + +&cpus { + c910_0: cpu@0 { + operating-points = < + /* kHz uV */ + 300000 600000 + 400000 700000 + 500000 700000 + 600000 700000 + 702000 700000 + 800000 700000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 400000 800000 + 500000 800000 + 600000 800000 + 702000 800000 + 800000 800000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + }; + c910_1: cpu@1 { + operating-points = < + /* kHz uV */ + 300000 600000 + 400000 700000 + 500000 700000 + 600000 700000 + 702000 700000 + 800000 700000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 400000 800000 + 500000 800000 + 600000 800000 + 702000 800000 + 800000 800000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + }; + c910_2: cpu@2 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 400000 700000 + 500000 700000 + 600000 700000 + 702000 700000 + 800000 700000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 400000 800000 + 500000 800000 + 600000 800000 + 702000 800000 + 800000 800000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + }; + c910_3: cpu@3 { + + operating-points = < + /* kHz uV */ + 300000 600000 + 400000 700000 + 500000 700000 + 600000 700000 + 702000 700000 + 800000 700000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 800000 + 400000 800000 + 500000 800000 + 600000 800000 + 702000 800000 + 800000 800000 + 900000 800000 + 1000000 800000 + 1104000 800000 + 1200000 800000 + 1296000 800000 + 1404000 800000 + 1500000 800000 + 1608000 1000000 + 1704000 1000000 + 1848000 1000000 + >; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-vi-devices.dtsi b/arch/riscv/boot/dts/thead/th1520-vi-devices.dtsi new file mode 100644 index 000000000000..f3f7c00bf8a5 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-vi-devices.dtsi @@ -0,0 +1,948 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021-2022 Alibaba Group Holding Limited. + */ + +&video0{ + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + }; + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_SP"; + }; + }; + channel2 { + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_SP2_BP"; + }; + }; +}; + +&video1{ + status = "disabled"; + channel0 { // VSE0 + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + }; + }; + channel1 { // VSE1 + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + }; + }; + channel2 { // VSE2 + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + }; + }; +}; + +&video2 { + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor2 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + }; + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP"; + }; + }; + channel2 { + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_SP2_BP"; + }; + }; +}; + +&video3 { + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + }; + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + }; + }; + channel2 { + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + }; + }; +}; + +&video4 { + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP"; + }; + }; + channel2 { + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_SP2_BP"; + }; + }; +}; + +&video5 { + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + }; + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + }; + }; + channel2 { + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP1"; + }; + isp { + subdev_name = "isp"; + idx = <1>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + }; + }; +}; + + +&video6 { + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_DSP"; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_VIPRE_ODD"; + }; + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_DSP"; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_VIPRE_EVEN"; + }; + }; +}; + + +&video7{ + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE0"; + }; + + }; + channel1 { + channel_id = <1>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE1"; + }; + }; + channel2 { + channel_id = <2>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_PP"; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_ISP_RY"; + }; + ry { + subdev_name = "ry"; + idx = <0>; + path_type = "ISP_RY_MI_PATH_MP"; + }; + dw { + subdev_name = "dw"; + idx = <0>; + path_type = "DW_DWE_VSE2"; + }; + }; +}; + + +&video8{ + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_DSP"; + }; + dsp { + subdev_name = "dsp"; + idx = <0>; + path_type = "DSP_PATH_VIPRE_DDR"; + }; + }; +}; + + +&video9 { //IR debug + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_DSP"; + }; + dsp { + subdev_name = "dsp"; + idx = <1>; + path_type = "DSP_PATH_VIPRE_DDR"; + }; + }; +}; + + +&video10{ // TUNING TOOL + status = "disabled"; + channel0 { // CSI2X2_B + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + skip_init = <1>; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI1_ISP0"; + }; + }; +}; + + +&video11{ + status = "disabled"; + channel0 { + channel_id = <0>; + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI2_ISP0"; + }; + isp { + subdev_name = "isp"; + idx = <0>; + path_type = "ISP_MI_PATH_MP"; + }; + }; +}; + + +&video12{ // TUNING TOOL + status = "disabled"; + channel0 { // CSI2 + status = "okay"; + sensor0 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + skip_init = <1>; + }; + sensor1 { + subdev_name = "vivcam"; + idx = <0xff>; // invalid + csi_idx = <0xff>; + path_type = "SENSOR_VGA_RAW10_LINER"; + skip_init = <1>; + }; + dma { + subdev_name = "vipre"; + idx = <0>; + path_type = "VIPRE_CSI0_ISP0"; + }; + }; +}; + + diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi new file mode 100644 index 000000000000..5d7fc11e6ffc --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,2840 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "thead,light"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + audio_i2c0 = &audio_i2c0; + audio_i2c1 = &audio_i2c1; + mmc0 = &emmc; + mmc1 = &sdhci0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + spi0 = &spi0; + spi1 = &qspi0; + spi2 = &qspi1; + + flash_led0 = &vvcam_flash_led0; + vivcam0 = &vvcam_sensor0; + vivcam1 = &vvcam_sensor1; + vivcam2 = &vvcam_sensor2; + vivcam3 = &vvcam_sensor3; + vivcam4 = &vvcam_sensor4; + vivcam5 = &vvcam_sensor5; + vivcam6 = &vvcam_sensor6; + vivcam7 = &vvcam_sensor7; + + viv_video0 = &video0; + viv_video1 = &video1; + viv_video2 = &video2; + viv_video3 = &video3; + viv_video4 = &video4; + viv_video5 = &video5; + viv_video6 = &video6; + viv_video7 = &video7; + viv_video8 = &video8; + viv_video9 = &video9; + viv_video10 = &video10; + viv_video11 = &video11; + viv_video12 = &video12; + viv_video13 = &video13; + viv_video14 = &video14; + viv_video15 = &video15; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x200000 0x0 0xffe00000>; + }; + + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + cmamem: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x14000000>; // 320MB by default + alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000] + linux,cma-default; + }; + }; + + aon_iram: aon-iram@ffffef8000 { + compatible = "syscon"; + reg = <0xff 0xffef8000 0x0 0x10000>; + }; + + thermal-zones { + cpu-thermal-zone { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&pvt 0>; + trips { + cpu_threshold: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_target: trip1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: trip2 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + cpu_cdev { + trip = <&cpu_target>; + cooling-device = + <&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + dev-thermal-zone { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&pvt 1>; + + trips { + dev_threshold: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + dev_target: trip1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + dev_crit: trip2 { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + npu_devfreq { + trip = <&dev_target>; + cooling-device = + <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + + dsp0_devfreq { + trip = <&dev_target>; + cooling-device = + <&xtensa_dsp0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + + dsp1_devfreq { + trip = <&dev_target>; + cooling-device = + <&xtensa_dsp1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + c910_0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvsu"; + mmu-type = "riscv,sv39"; + cpu-freq = "1.848Ghz"; + cpu-icache = "64KB"; + cpu-dcache = "64KB"; + cpu-l2cache = "1MB"; + cpu-tlb = "1024 4-ways"; + cpu-cacheline = "64Bytes"; + cpu-vector = "0.7.1"; + #cooling-cells = <2>; + dynamic-power-coefficient = <500>; + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 750000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + clock-latency = <61036>; + clocks = <&clk C910_CCLK>, + <&clk C910_CCLK_I0>, + <&clk CPU_PLL1_FOUTPOSTDIV>, + <&clk CPU_PLL0_FOUTPOSTDIV>; + clock-names = "c910_cclk", "c910_cclk_i0", + "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; + dvdd-supply = <&dvdd_cpu_reg>; + dvddm-supply = <&dvddm_cpu_reg>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + c910_1: cpu@1 { + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvsu"; + mmu-type = "riscv,sv39"; + cpu-freq = "1.848Ghz"; + cpu-icache = "64KB"; + cpu-dcache = "64KB"; + cpu-l2cache = "1MB"; + cpu-tlb = "1024 4-ways"; + cpu-cacheline = "64Bytes"; + cpu-vector = "0.7.1"; + #cooling-cells = <2>; + dynamic-power-coefficient = <500>; + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 750000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + clock-latency = <61036>; + clocks = <&clk C910_CCLK>, + <&clk C910_CCLK_I0>, + <&clk CPU_PLL1_FOUTPOSTDIV>, + <&clk CPU_PLL0_FOUTPOSTDIV>; + clock-names = "c910_cclk", "c910_cclk_i0", + "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; + dvdd-supply = <&dvdd_cpu_reg>; + dvddm-supply = <&dvddm_cpu_reg>; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + c910_2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvsu"; + mmu-type = "riscv,sv39"; + cpu-freq = "1.848Ghz"; + cpu-icache = "64KB"; + cpu-dcache = "64KB"; + cpu-l2cache = "1MB"; + cpu-tlb = "1024 4-ways"; + cpu-cacheline = "64Bytes"; + cpu-vector = "0.7.1"; + #cooling-cells = <2>; + dynamic-power-coefficient = <500>; + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 750000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + clock-latency = <61036>; + clocks = <&clk C910_CCLK>, + <&clk C910_CCLK_I0>, + <&clk CPU_PLL1_FOUTPOSTDIV>, + <&clk CPU_PLL0_FOUTPOSTDIV>; + clock-names = "c910_cclk", "c910_cclk_i0", + "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; + dvdd-supply = <&dvdd_cpu_reg>; + dvddm-supply = <&dvddm_cpu_reg>; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + c910_3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvsu"; + mmu-type = "riscv,sv39"; + cpu-freq = "1.848Ghz"; + cpu-icache = "64KB"; + cpu-dcache = "64KB"; + cpu-l2cache = "1MB"; + cpu-tlb = "1024 4-ways"; + cpu-cacheline = "64Bytes"; + cpu-vector = "0.7.1"; + #cooling-cells = <2>; + dynamic-power-coefficient = <500>; + + operating-points = < + /* kHz uV */ + 300000 600000 + 800000 700000 + 1500000 800000 + 1848000 1000000 + >; + light,dvddm-operating-points = < + /* kHz uV */ + 300000 750000 + 800000 800000 + 1500000 800000 + 1848000 1000000 + >; + clock-latency = <61036>; + clocks = <&clk C910_CCLK>, + <&clk C910_CCLK_I0>, + <&clk CPU_PLL1_FOUTPOSTDIV>, + <&clk CPU_PLL0_FOUTPOSTDIV>; + clock-names = "c910_cclk", "c910_cclk_i0", + "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv"; + dvdd-supply = <&dvdd_cpu_reg>; + dvddm-supply = <&dvddm_cpu_reg>; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + idle_states: idle-states { + CPU_RET_0_0: cpu-retentive-0-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x10000000>; + entry-latency-us = <20>; + exit-latency-us = <40>; + min-residency-us = <80>; + }; + + CPU_NONRET_0_0: cpu-nonretentive-0-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x90000000>; + entry-latency-us = <250>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_RET_0: cluster-retentive-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x11000000>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <250>; + wakeup-latency-us = <130>; + }; + + CLUSTER_NONRET_0: cluster-nonretentive-0 { + compatible = "riscv,idle-state"; + riscv,sbi-suspend-param = <0x91000000>; + local-timer-stop; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; + + display-subsystem { + compatible = "verisilicon,display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + status = "disabled"; + }; + + dpu-encoders { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + dpu_enc0: dpu-encoder@0 { + /* default encoder is DSI */ + compatible = "verisilicon,dsi-encoder"; + reg = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input */ + port@0 { + reg = <0>; + + enc0_in: endpoint { + remote-endpoint = <&disp0_out>; + }; + }; + }; + }; + + dpu_enc1: dpu-encoder@1 { + /* default encoder is DSI */ + compatible = "verisilicon,dsi-encoder"; + reg = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* input */ + port@0 { + reg = <0>; + + enc1_in: endpoint { + remote-endpoint = <&disp1_out>; + }; + }; + }; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reset: reset-sample { + compatible = "thead,reset-sample"; + plic-delegate = <0xff 0xd81ffffc>; + entry-reg = <0xff 0xff019050>; + entry-cnt = <4>; + control-reg = <0xff 0xff015004>; + control-val = <0x1c>; + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>; + }; + + clint0: clint@ffdc000000 { + compatible = "riscv,clint0"; + interrupts-extended = < + &cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + >; + reg = <0xff 0xdc000000 0x0 0x04000000>; + clint,has-no-64bit-mmio; + }; + + intc: interrupt-controller@ffd8000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff &cpu0_intc 9 + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + >; + reg = <0xff 0xd8000000 0x0 0x04000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <240>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + dummy_clock_apb: apb-clock@0 { + compatible = "fixed-clock"; + reg = <0>; /* Not address, just for index */ + clock-frequency = <62500000>; + clock-output-names = "dummy_clock_apb"; + #clock-cells = <0>; + }; + + dummy_clock_ref: ref-clock@1 { + compatible = "fixed-clock"; + reg = <1>; /* Not address, just for index */ + clock-frequency = <50000000>; + clock-output-names = "dummy_clock_ref"; + #clock-cells = <0>; + }; + + dummy_clock_suspend: suspend-clock@2 { + compatible = "fixed-clock"; + reg = <2>; /* Not address, just for index */ + clock-frequency = <50000000>; + clock-output-names = "dummy_clock_suspend"; + #clock-cells = <0>; + }; + + dummy_clock_rtc: rtc-clock@3 { + compatible = "fixed-clock"; + reg = <3>; /* Not address, just for index */ + clock-frequency = <32768>; + clock-output-names = "dummy_clock_rtc"; + #clock-cells = <0>; + }; + + dummy_clock_ahb: ahb-clock@4 { + compatible = "fixed-clock"; + reg = <4>; /* Not address, just for index */ + clock-frequency = <50000000>; + clock-output-names = "dummy_clock_ahb"; + #clock-cells = <0>; + }; + + dummy_clock_gpu: gpu-clock@6 { + compatible = "fixed-clock"; + reg = <6>; /* Not address, just for index */ + clock-frequency = <18000000>; + clock-output-names = "dummy_clock_gpu"; + #clock-cells = <0>; + }; + + dummy_clock_dphy_ref: dphy-ref-clock@7 { + compatible = "fixed-clock"; + reg = <7>; /* Not address, just for index */ + clock-frequency = <24000000>; + clock-output-names = "dummy_clock_dphy_ref"; + #clock-cells = <0>; + }; + + dummy_clock_dphy_cfg: dphy-cfg-clock@8 { + compatible = "fixed-clock"; + reg = <8>; /* Not address, just for index */ + clock-frequency = <24000000>; + clock-output-names = "dummy_clock_dphy_cfg"; + #clock-cells = <0>; + }; + + dummy_clock_dpu_pixel0: dpu-pixel-clock@9 { + compatible = "fixed-clock"; + reg = <9>; + clock-frequency = <72000000>; + clock-output-names = "dummy_clock_dpu_pixel0"; + #clock-cells = <0>; + }; + + dummy_clock_dpu_pixel1: dpu-pixel-clock@10 { + compatible = "fixed-clock"; + reg = <10>; + clock-frequency = <74250000>; + clock-output-names = "dummy_clock_dpu_pixel1"; + #clock-cells = <0>; + }; + + osc_32k: clock-osc-32k@11 { + compatible = "fixed-clock"; + reg = <11>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m@12 { + compatible = "fixed-clock"; + reg = <12>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + rc_24m: clock-rc-24m@13 { + compatible = "fixed-clock"; + reg = <13>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "rc_24m"; + }; + + dummy_clock_eip: eip-clock@14 { + compatible = "fixed-clock"; + reg = <14>; /* Not address, just for index */ + clock-frequency = <400000000>; + clock-output-names = "dummy_clock_eip"; + #clock-cells = <0>; + }; + + dummy_clock_spi: spi-clock@15 { + compatible = "fixed-clock"; + reg = <15>; /* Not address, just for index */ + clock-frequency = <396000000>; + clock-output-names = "dummy_clock_spi"; + #clock-cells = <0>; + }; + + dummy_clock_qspi: spi-clock@16 { + compatible = "fixed-clock"; + reg = <15>; /* Not address, just for index */ + clock-frequency = <792000000>; + clock-output-names = "dummy_clock_qspi"; + #clock-cells = <0>; + }; + + dummy_gmac_ahb: gmac-ahb-clock@16 { + compatible = "fixed-clock"; + reg = <16>; + clock-frequency = <250000000>; + clock-output-names = "dummy_gmac_ahb"; + #clock-cells = <0>; + }; + + dummy_clock_gmac: gmac-clock@17 { + compatible = "fixed-clock"; + reg = <17>; + clock-frequency = <500000000>; + clock-output-names = "dummy_clock_gmac"; + #clock-cells = <0>; + }; + + dummy_clock_sdhci: sdhci-clock@18 { + compatible = "fixed-clock"; + reg = <18>; /* Not address, just for index */ + clock-frequency = <198000000>; + clock-output-names = "dummy_clock_sdhci"; + #clock-cells = <0>; + }; + + dummy_clock_aonsys_clk: aonsys-clk-clock@19 { + compatible = "fixed-clock"; + reg = <19>; /* Not address, just for index */ + clock-frequency = <73728000>; + clock-output-names = "dummy_clock_aonsys_clk"; + #clock-cells = <0>; + }; + + dummy_clock_uart_sclk: uart-sclk-clock@20 { + compatible = "fixed-clock"; + reg = <20>; /* Not address, just for index */ + clock-frequency = <100000000>; + clock-output-names = "dummy_clock_uart_sclk"; + #clock-cells = <0>; + }; + + dummy_clock_visys: visys-dummy-clock@21 { + compatible = "fixed-clock"; + reg = <21>; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + }; + + iso7816: iso7816-card@fff7f30000 { + compatible = "thead,light-iso7816-card"; + reg = <0xff 0xf7f30000 0x0 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_iso7816>; + interrupts = <69>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + teesys_syscon: teesys-reg@ffff200000 { + compatible = "syscon"; + reg = <0xff 0xff200000 0x0 0x10000>; + }; + + visys_reg: visys-reg@ffe4040000 { + compatible = "thead,light-visys-reg", "syscon"; + reg = <0xff 0xe4040000 0x0 0x1000>; + status = "disabled"; + }; + + dspsys_reg: dspsys-reg@ffef040000 { + compatible = "thead,light-dspsys-reg", "syscon"; + reg = <0xff 0xef040000 0x0 0x1000>; + status = "okay"; + }; + + miscsys_reg: miscsys-reg@ffec02c000 { + compatible = "thead,light-miscsys-reg", "syscon"; + reg = <0xff 0xec02c000 0x0 0x1000>; + status = "okay"; + }; + + tee_miscsys_reg: tee_miscsys-reg@fffc02d000 { + compatible = "thead,light-miscsys-reg", "syscon"; + reg = <0xff 0xfc02d000 0x0 0x1000>; + status = "okay"; + }; + + audio_ioctrl: audio_ioctrl@ffcb01d000 { + compatible = "thead,light-audio-ioctrl-reg", "syscon"; + reg = <0xff 0xcb01d000 0x0 0x1000>; + status = "okay"; + }; + + audio_cpr: audio_cpr@ffcb000000 { + compatible = "thead,light-audio-cpr-reg", "syscon"; + reg = <0xff 0xcb000000 0x0 0x1000>; + status = "okay"; + }; + + audio_mbox: audio_mbox@0xffefc48000 { + compatible = "thead,light-audio-mbox-reg", "syscon"; + reg = <0xff 0xefc48000 0x0 0x1000>; + status = "okay"; + }; + + nvmem_controller: efuse@ffff210000 { + compatible = "thead,light-fm-efuse", "syscon"; + reg = <0xff 0xff210000 0x0 0x10000>; + thead,teesys = <&teesys_syscon>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EFUSE_PCLK>; + clock-names = "pclk"; + + gmac0_mac_address: mac-address@176 { + reg = <0xb0 6>; + }; + + gmac1_mac_address: mac-address@184 { + reg = <0xb8 6>; + }; + }; + + misc_sysreg: misc_sysreg@ffec02c000 { + compatible = "thead,light-misc-sysreg", "syscon"; + reg = <0xff 0xec02c000 0x0 0x1000>; + status = "okay"; + }; + + usb3_drd: usb3_drd@ffec03f000 { + compatible = "thead,light-usb3-drd", "syscon"; + reg = <0xff 0xec03f000 0x0 0x1000>; + status = "okay"; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLKGEN_GPIO0_PCLK>, + <&clk CLKGEN_GPIO0_DBCLK>; + clock-names = "bus", "db"; + gpio0_porta: gpio0-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + nr-gpios-snps = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <56>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLKGEN_GPIO1_PCLK>, + <&clk CLKGEN_GPIO1_DBCLK>; + clock-names = "bus", "db"; + gpio1_porta: gpio1-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + nr-gpios-snps = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <57>; + }; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLKGEN_GPIO2_PCLK>, + <&clk CLKGEN_GPIO2_DBCLK>; + clock-names = "bus", "db"; + gpio2_porta: gpio2-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + nr-gpios-snps = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <58>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLKGEN_GPIO3_PCLK>, + <&clk CLKGEN_GPIO3_DBCLK>; + clock-names = "bus", "db"; + gpio3_porta: gpio3-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + nr-gpios-snps = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <59>; + }; + }; + + ao_gpio: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + ao_gpio_porta: ao_gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + nr-gpios-snps = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <76>; + }; + }; + + ao_gpio4: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + ao_gpio4_porta: ao_gpio4-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + nr-gpios-snps = <32>; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <55>; + }; + }; + + padctrl1_apsys: padctrl1-apsys@ffe7f3c000 { + compatible = "thead,light-fm-left-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&clk CLKGEN_PADCTRL1_APSYS_PCLK>; + clock-names = "pclk"; + status = "okay"; + }; + + padctrl0_apsys: padctrl0-apsys@ffec007000 { + compatible = "thead,light-fm-right-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&clk CLKGEN_PADCTRL0_APSYS_PCLK>; + clock-names = "pclk"; + status = "okay"; + }; + + pwm: pwm@ffec01c000 { + compatible = "thead,pwm-light"; + reg = <0xff 0xec01c000 0x0 0x4000>; + #pwm-cells = <2>; + clocks = <&clk CLKGEN_PWM_PCLK>, + <&clk CLKGEN_PWM_CCLK>; + clock-names = "pclk", "cclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <16>; + interrupt-parent = <&intc>; + status = "okay"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <17>; + interrupt-parent = <&intc>; + status = "okay"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <18>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <19>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + padctrl_aosys: padctrl-aosys@fffff4a000 { + compatible = "thead,light-fm-aon-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; + status = "okay"; + }; + + padctrl_audiosys: padctrl-audiosys@ffcb01d000 { + compatible = "thead,light-fm-audio-pinctrl"; + reg = <0xff 0xcb01d000 0x0 0x1000>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <20>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <21>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <22>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&dummy_clock_apb>; + clock-names = "timer"; + clock-frequency = <62500000>; + interrupts = <23>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + uart0: serial@ffe7014000 { /* Normal serial, for C910 log */ + compatible = "snps,dw-apb-uart", "light,uart0"; + reg = <0xff 0xe7014000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <36>; + clocks = <&clk CLKGEN_UART0_SCLK>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + hw-flow-control = "unsupport"; + status = "okay"; + }; + + uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */ + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <37>; + clocks = <&clk CLKGEN_UART1_SCLK>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + hw-flow-control = "unsupport"; + status = "okay"; + }; + + uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */ + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <38>; + clocks = <&clk CLKGEN_UART2_SCLK>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + hw-flow-control = "unsupport"; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */ + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <39>; + clocks = <&clk CLKGEN_UART3_SCLK>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + hw-flow-control = "unsupport"; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */ + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <40>; + clocks = <&clk CLKGEN_UART4_SCLK>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + hw-flow-control = "support"; + status = "okay"; + }; + + uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */ + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <41>; + clocks = <&clk CLKGEN_UART5_SCLK>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + hw-flow-control = "unsupport"; + status = "disabled"; + }; + + adc: adc@0xfffff51000 { + compatible = "thead,light-adc"; + reg = <0xff 0xfff51000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <61>; + clocks = <&dummy_clock_aonsys_clk>; + clock-names = "adc"; + /* ADC pin is proprietary,no need to config pinctrl */ + status = "disabled"; + }; + + spi0: spi@ffe700c000 { + compatible = "snps,dw-apb-ssi"; + reg = <0xff 0xe700c000 0x0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + interrupt-parent = <&intc>; + interrupts = <54>; + clocks = <&clk CLKGEN_SPI_SSI_CLK>, + <&clk CLKGEN_SPI_PCLK>; + clock-names = "sclk", "pclk"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + qspi0: spi@ffea000000 { + compatible = "snps,dw-apb-ssi-quad"; + reg = <0xff 0xea000000 0x0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + interrupt-parent = <&intc>; + interrupts = <52>; + clocks = <&clk CLKGEN_QSPI0_SSI_CLK>, + <&clk CLKGEN_QSPI0_PCLK>; + clock-names = "sclk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + qspi1: spi@fff8000000 { + compatible = "snps,dw-apb-ssi-quad"; + reg = <0xff 0xf8000000 0x0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1>; + interrupt-parent = <&intc>; + interrupts = <53>; + clocks = <&clk CLKGEN_QSPI1_SSI_CLK>, + <&clk CLKGEN_QSPI1_PCLK>; + clock-names = "sclk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + g2d_opp_table:g2d-opp-table { + compatible = "operating-points-v2"; + opp-49500000 { + opp-hz = /bits/ 64 <49500000>; + }; + opp-99000000 { + opp-hz = /bits/ 64 <99000000>; + }; + opp-198000000 { + opp-hz = /bits/ 64 <198000000>; + }; + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + }; + }; + +/* g2d: gc620@ffecc80000 { + compatible = "thead,c910-gc620"; + reg = <0xff 0xecc80000 0x0 0x40000>; + interrupt-parent = <&intc>; + interrupts = <101>; + interrupt-names = "irq_2d"; + clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>, + <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>, + <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>; + clock-names = "pclk", "aclk", "cclk"; + operating-points-v2 = <&g2d_opp_table>; + status = "okay"; + };*/ + + g2d: gpu@13040000 { + compatible = "vivante,gc"; + reg = <0xff 0xecc80000 0x0 0x40000>; + + clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>, + <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>, + <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>; + clock-names = "bus", "core", "shader"; + + interrupt-parent = <&intc>; + interrupts = <101>; + operating-points-v2 = <&g2d_opp_table>; + }; + + dsi0: dw-mipi-dsi0@ffef500000 { + compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; + reg = <0xff 0xef500000 0x0 0x10000>; + status = "disabled"; + + dphy_0: dsi0-dphy { + compatible = "thead,light-mipi-dphy"; + regmap = <&dsi0>; + vosys-regmap = <&vosys_reg>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>, + <&clk OSC_24M>, + <&clk OSC_24M>; + clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; + #phy-cells = <0>; + }; + + dhost_0: dsi0-host { + compatible = "verisilicon,dw-mipi-dsi"; + regmap = <&dsi0>; + interrupt-parent = <&intc>; + interrupts = <129>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>; + clock-names = "pclk", "pixclk"; + phys = <&dphy_0>; + phy-names = "dphy"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dsi1: dw-mipi-dsi1@ffef510000 { + compatible = "thead,light-mipi-dsi", "simple-bus", "syscon"; + reg = <0xff 0xef510000 0x0 0x10000>; + status = "disabled"; + + dphy_1: dsi1-dphy { + compatible = "thead,light-mipi-dphy"; + regmap = <&dsi1>; + vosys-regmap = <&vosys_reg>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>, + <&clk OSC_24M>, + <&clk OSC_24M>; + clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk"; + #phy-cells = <0>; + }; + + dhost_1: dsi1-host { + compatible = "verisilicon,dw-mipi-dsi"; + regmap = <&dsi1>; + interrupt-parent = <&intc>; + interrupts = <129>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>; + clock-names = "pclk", "pixclk"; + phys = <&dphy_1>; + phy-names = "dphy"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vosys_reg: vosys@ffef528000 { + compatible = "thead,light-vo-subsys", "syscon"; + reg = <0xff 0xef528000 0x0 0x1000>; + status = "okay"; + }; + + hdmi_tx: dw-hdmi-tx@ffef540000 { + compatible = "thead,light-hdmi-tx"; + reg = <0xff 0xef540000 0x0 0x40000>; + interrupt-parent = <&intc>; + interrupts = <111>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>; + clock-names = "iahb", "isfr", "cec", "pixclk"; + reg-io-width = <4>; + phy_version = <301>; + /* TODO: add phy property */ + status = "disabled"; + }; + + dpu: dc8200@ffef600000 { + compatible = "verisilicon,dc8200"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff 0xef600000 0x0 0x100>, + <0xff 0xef600800 0x0 0x2000>, + <0xff 0xef630010 0x0 0x60>; + interrupt-parent = <&intc>; + interrupts = <93>; + vosys-regmap = <&vosys_reg>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>, + <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>, + <&clk DPU0_PLL_DIV_CLK>, + <&clk DPU1_PLL_DIV_CLK>, + <&clk DPU0_PLL_FOUTPOSTDIV>, + <&clk DPU1_PLL_FOUTPOSTDIV>; + clock-names = "core_clk", "pix_clk0", "pix_clk1", + "axi_clk", "cfg_clk", "pixclk0", + "pixclk1", "dpu0_pll_foutpostdiv", + "dpu1_pll_foutpostdiv"; + status = "disabled"; + + dpu_disp0: port@0 { + reg = <0>; + + disp0_out: endpoint { + remote-endpoint = <&enc0_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + disp1_out: endpoint { + remote-endpoint = <&enc1_in>; + }; + }; + }; + + watchdog0: watchdog@ffefc30000 { + compatible = "snps,dw-wdt"; + reg = <0xff 0xefc30000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <24>; + clocks = <&clk CLKGEN_WDT0_PCLK>; + clock-names = "tclk"; + resets = <&rst LIGHT_RESET_WDT0>; + status = "okay"; + }; + + watchdog1: watchdog@ffefc31000 { + compatible = "snps,dw-wdt"; + reg = <0xff 0xefc31000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <25>; + clocks = <&clk CLKGEN_WDT1_PCLK>; + clock-names = "tclk"; + resets = <&rst LIGHT_RESET_WDT1>; + status = "okay"; + }; + + rtc: rtc@fffff40000 { + compatible = "apm,xgene-rtc"; + reg = <0xff 0xfff40000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <74>; + clocks = <&dummy_clock_rtc>; + clock-names = "rtc"; + wakeup-source; + status = "okay"; + }; + + usb_1: usb@ffec03f000 { + compatible = "thead,dwc3"; + usb3-misc-regmap = <&misc_sysreg>; + usb3-drd-regmap = <&usb3_drd>; + clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_CTRL_REF_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_PHY_REF_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_USB3_DRD_SUSPEND_CLK>; + clock-names = "drd", "ctrl", "phy", "suspend"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + usb: dwc3@ffe7040000 { + compatible = "snps,dwc3"; + reg = <0xff 0xe7040000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <68>; + reg-shift = <2>; + reg-io-width = <4>; + maximum-speed = "super-speed"; + dr_mode = "host"; + dma-mask = <0xf 0xffffffff>; + snps,usb3_lpm_capable; + snps,usb_sofitpsync; + status = "okay"; + }; + }; + + pmu: pmu { + interrupt-parent = <&cpu0_intc>; + interrupts = <17>; + compatible = "riscv,c910_pmu"; + }; + + clk: clock-controller@ffef010000 { + compatible = "thead,light-fm-ree-clk"; + reg = <0xff 0xef010000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>; + clock-names = "osc_32k", "osc_24m", "rc_24m"; + status = "okay"; + }; + + rst: reset-controller@ffef014000 { + compatible = "thead,light-reset-src","syscon"; + reg = <0xff 0xef014000 0x0 0x1000>; + #reset-cells = <1>; + status = "okay"; + }; + + vpsys_rst: vpsys-reset-controller@ffecc30000 { + compatible = "thead,light-vpsys-reset-src","syscon"; + reg = <0xff 0xecc30000 0x0 0x1000>; + #reset-cells = <1>; + status = "okay"; + }; + + sys_reg: sys_reg@ffef010100 { + compatible = "thead,light_sys_reg"; + reg = <0xff 0xef010100 0x0 0x100>; + status = "okay"; + }; + + dmac0: dmac@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <27>; + clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "okay"; + }; + + dmac1: tee_dmac@ffff340000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xff340000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <150>; + clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "disabled"; + }; + + dmac2: audio_dmac@0xFFC8000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xc8000000 0x0 0x2000>; + interrupt-parent = <&intc>; + interrupts = <167>; + clocks = <&clk CLKGEN_DMAC_CPUSYS_ACLK>, <&clk CLKGEN_DMAC_CPUSYS_HCLK>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <16>; + snps,block-size = <65536 65536 65536 65536 + 65536 65536 65536 65536 + 65536 65536 65536 65536 + 65536 65536 65536 65536>; + snps,priority = <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; // <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "okay"; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <3>; + snps,rd_osr_lmt = <3>; + snps,blen = <16 8 4 0 0 0 0>; + }; + + gmac0: ethernet@ffe7070000 { + compatible = "thead,light-dwmac"; + reg = <0xff 0xe7070000 0x0 0x2000 + 0xff 0xec00301c 0x0 0x4 + 0xff 0xec003020 0x0 0x4 + 0xff 0xec003000 0x0 0x1c>; + reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; + interrupt-parent = <&intc>; + interrupts = <66>; + interrupt-names = "macirq"; + clocks = <&clk CLKGEN_GMAC0_CCLK>, + <&clk CLKGEN_GMAC0_PCLK>, + <&clk CLKGEN_GMAC_AXI_ACLK>, + <&clk CLKGEN_GMAC_AXI_PCLK>; + clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,axi-config = <&stmmac_axi_setup>; + nvmem-cells = <&gmac0_mac_address>; + nvmem-cell-names = "mac-address"; + }; + + gmac1: ethernet@ffe7060000 { + compatible = "thead,light-dwmac"; + reg = <0xff 0xe7060000 0x0 0x2000 + 0xff 0xec00401c 0x0 0x4 + 0xff 0xec004020 0x0 0x4 + 0xff 0xec004000 0x0 0x1c>; + reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg"; + interrupt-parent = <&intc>; + interrupts = <67>; + interrupt-names = "macirq"; + clocks = <&clk CLKGEN_GMAC1_CCLK>, + <&clk CLKGEN_GMAC1_PCLK>, + <&clk CLKGEN_GMAC_AXI_ACLK>, + <&clk CLKGEN_GMAC_AXI_PCLK>; + clock-names = "gmac_pll_clk","pclk","axi_aclk","axi_pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,axi-config = <&stmmac_axi_setup>; + nvmem-cells = <&gmac1_mac_address>; + nvmem-cell-names = "mac-address"; + }; + + emmc: sdhci@ffe7080000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <62>; + interrupt-names = "sdhciirq"; + clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>; + clock-names = "core", "bus"; + }; + + sdhci0: sd@ffe7090000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <64>; + interrupt-names = "sdhci0irq"; + clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>; + clock-names = "core", "bus"; + }; + + sdhci1: sd@ffe70a0000 { + compatible = "snps,dwcmshc-sdhci"; + reg = <0xff 0xe70a0000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <71>; + interrupt-names = "sdhci1irq"; + clocks = <&clk CLKGEN_EMMC_SDIO_REF_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_EMMC_CLK>; + clock-names = "core", "bus"; + }; + + hwspinlock: hwspinlock@ffefc10000 { + compatible = "light,hwspinlock"; + reg = <0xff 0xefc10000 0x0 0x10000>; + status = "disabled"; + }; + + npu: vha@fffc800000 { + compatible = "img,ax3386-nna"; + reg = <0xff 0xfc800000 0x0 0x100000>; + interrupt-parent = <&intc>; + interrupts = <113>; + interrupt-names = "npuirq"; + #cooling-cells = <2>; + dynamic-power-coefficient = <1600>; + power-domains = <&pd LIGHT_AON_NPU_PD>; + clocks = <&clk CLKGEN_TOP_APB_SX_PCLK>, + <&clk CLKGEN_TOP_AXI4S_ACLK>, + <&clk NPU_CCLK>, + <&clk GMAC_PLL_FOUTPOSTDIV>, + <&clk NPU_CCLK_OUT_DIV>; + clock-names = "pclk", "aclk", "cclk", + "gmac_pll_foutpostdiv", + "npu_cclk_out_div"; + operating-points-v2 = <&npu_opp_table>; + vha_clk_rate = <1000000000>; + ldo_vha-supply = <&npu>; + dma-mask = <0xff 0xffffffff>; + resets = <&rst LIGHT_RESET_NPU>; + status = "disabled"; + }; + + npu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <800000>; + }; + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <800000>; + }; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <800000>; + }; + opp-475200000 { + opp-hz = /bits/ 64 <475200000>; + opp-microvolt = <800000>; + }; + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-microvolt = <800000>; + }; + }; + + gpu: gpu@ffef400000 { + compatible = "img,gpu"; + reg = <0xff 0xef400000 0x0 0x100000>; + interrupt-parent = <&intc>; + interrupts = <102>; + interrupt-names = "gpuirq"; + vosys-regmap = <&vosys_reg>; + power-domains = <&pd LIGHT_AON_GPU_PD>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>, + <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>; + clock-names = "cclk", "aclk"; + gpu_clk_rate = <18000000>; + dma-mask = <0xf 0xffffffff>; + status = "disabled"; + }; + + fce: fce@fffcc50000 { + compatible = "thead,light-fce"; + reg = <0xff 0xfcc50000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <100>; + interrupt-names = "fceirq"; + clocks = <&vpsys_clk_gate LIGHT_VPSYS_FCE_ACLK>, + <&vpsys_clk_gate LIGHT_VPSYS_FCE_PCLK>; + clock-names = "aclk", "pclk"; + resets = <&vpsys_rst LIGHT_RESET_FCE>; + dma-mask = <0xf 0xffffffff>; + status = "disabled"; + }; + vdec_opp_table: opp_table_vdec { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <158400000>; + opp-microvolt = <875000>; + }; + opp01 { + opp-hz = /bits/ 64 <198000000>; + opp-microvolt = <875000>; + }; + opp02 { + opp-hz = /bits/ 64 <237600000>; + opp-microvolt = <875000>; + }; + opp03 { + opp-hz = /bits/ 64 <264000000>; + opp-microvolt = <887500>; + }; + opp04 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <937500>; + }; + opp05 { + opp-hz = /bits/ 64 <396000000>; + opp-microvolt = <1012500>; + }; + opp06 { + opp-hz = /bits/ 64 <475200000>; + opp-microvolt = <1037500>; + }; + opp07 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <1050000>; + }; + }; + + venc_opp_table: opp_table_venc { + compatible = "operating-points-v2"; + opp00 { + opp-hz = /bits/ 64 <200000000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + }; + opp02 { + opp-hz = /bits/ 64 <333300000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + }; + }; + + vdec: vdec@ffecc00000 { + compatible = "thead,light-vc8000d"; + reg = <0xff 0xecc00000 0x0 0x8000>; + interrupt-parent = <&intc>; + interrupts = <131>; + power-domains = <&pd LIGHT_AON_VDEC_PD>; + clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>, + <&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>, + <&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>; + clock-names = "aclk", "cclk", "pclk"; + operating-points-v2 = <&vdec_opp_table>; + status = "disabled"; + }; + + venc: venc@ffecc10000 { + compatible = "thead,light-vc8000e"; + reg = <0xff 0xecc10000 0x0 0x8000>; + interrupt-parent = <&intc>; + interrupts = <133>; + power-domains = <&pd LIGHT_AON_VENC_PD>; + clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>, + <&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>, + <&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>; + clock-names = "aclk", "cclk", "pclk"; + operating-points-v2 =<&venc_opp_table>; + status = "disabled"; + }; + + isp_venc_shake: shake@ffe4078000 { + compatible = "thead,light-ivs"; + reg = <0xff 0xe4078000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <158>; + status = "disabled"; + }; + + vidmem: vidmem@ffecc08000 { + compatible = "thead,light-vidmem"; + reg = <0xff 0xecc08000 0x0 0x1000>; + status = "disabled"; + }; + + light_i2s: light_i2s@ffe7034000 { + #sound-dai-cells = <1>; + compatible = "light,light-i2s"; + reg = <0xff 0xe7034000 0x0 0x4000>; + light,mode = "i2s-master"; + light,sel = "ap_i2s"; + interrupt-parent = <&intc>; + interrupts = <70>; + dmas = <&dmac0 35>, <&dmac0 40>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s0: audio_i2s0@0xffcb014000 { + #sound-dai-cells = <1>; + compatible = "light,light-i2s"; + reg = <0xff 0xcb014000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s0"; + interrupt-parent = <&intc>; + interrupts = <174>; + dmas = <&dmac2 9>, <&dmac2 8>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S0>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s1: audio_i2s1@0xffcb015000 { + #sound-dai-cells = <1>; + compatible = "light,light-i2s"; + reg = <0xff 0xcb015000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s1"; + interrupt-parent = <&intc>; + interrupts = <175>; + dmas = <&dmac2 11>, <&dmac2 10>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S1>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s2: audio_i2s2@0xffcb016000 { + #sound-dai-cells = <1>; + compatible = "light,light-i2s"; + reg = <0xff 0xcb016000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s2"; + interrupt-parent = <&intc>; + interrupts = <176>; + dmas = <&dmac2 13>, <&dmac2 12>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S2>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s_8ch_sd0: audio_i2s_8ch_sd0@0xffcb017000 { + #sound-dai-cells = <0>; + compatible = "light,light-i2s-8ch"; + reg = <0xff 0xcb017000 0x0 0x1000>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s_8ch_sd0"; + interrupt-parent = <&intc>; + interrupts = <177>; + dmas = <&dmac2 36>, <&dmac2 14>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s_8ch_sd1: audio_i2s_8ch_sd1@0xffcb017000 { + #sound-dai-cells = <0>; + compatible = "light,light-i2s-8ch"; + reg = <0xff 0xcb017000 0x0 0x1000>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s_8ch_sd1"; + interrupt-parent = <&intc>; + interrupts = <177>; + dmas = <&dmac2 37>, <&dmac2 15>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s_8ch_sd2: audio_i2s_8ch_sd2@0xffcb017000 { + #sound-dai-cells = <0>; + compatible = "light,light-i2s-8ch"; + reg = <0xff 0xcb017000 0x0 0x1000>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s_8ch_sd2"; + interrupt-parent = <&intc>; + interrupts = <177>; + dmas = <&dmac2 38>, <&dmac2 16>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s_8ch_sd3: audio_i2s_8ch_sd3@0xffcb017000 { + #sound-dai-cells = <0>; + compatible = "light,light-i2s-8ch"; + reg = <0xff 0xcb017000 0x0 0x1000>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,sel = "i2s_8ch_sd3"; + interrupt-parent = <&intc>; + interrupts = <177>; + dmas = <&dmac2 39>, <&dmac2 17>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_I2S8CH>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot1: audio_tdm_slot1@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <1>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 28>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot2: audio_tdm_slot2@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <2>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 29>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot3: audio_tdm_slot3@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <3>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 30>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot4: audio_tdm_slot4@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <4>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 31>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot5: audio_tdm_slot5@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <5>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 32>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot6: audio_tdm_slot6@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <6>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 33>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot7: audio_tdm_slot7@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <7>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 34>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + tdm_slot8: audio_tdm_slot8@0xffcb012000 { + #sound-dai-cells = <0>; + compatible = "light,light-tdm"; + reg = <0xff 0xcb012000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + light,mode = "i2s-master"; + light,tdm_slots = <8>; + light,tdm_slot_num = <8>; + interrupt-parent = <&intc>; + interrupts = <178>; + dmas = <&dmac2 35>; + dma-names = "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_TDM>; + clock-names = "pclk"; + status = "disabled"; + }; + + spdif0: audio_spdif0@0xffcb018000 { + #sound-dai-cells = <0>; + compatible = "light,light-spdif"; + reg = <0xff 0xcb018000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + interrupt-parent = <&intc>; + interrupts = <179>; + dmas = <&dmac2 25>, <&dmac2 24>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF0>; + clock-names = "pclk"; + id = <0>; + status = "disabled"; + }; + + spdif1: audio_spdif1@0xffcb019000 { + #sound-dai-cells = <0>; + compatible = "light,light-spdif"; + reg = <0xff 0xcb019000 0x0 0x1000>; + audio-pin-regmap = <&audio_ioctrl>; + audio-cpr-regmap = <&audio_cpr>; + pinctrl-names = "default"; + interrupt-parent = <&intc>; + interrupts = <180>; + dmas = <&dmac2 27>, <&dmac2 26>; + dma-names = "tx", "rx"; + light,dma_maxburst = <4>; + #dma-cells = <1>; + clocks = <&audiosys_clk_gate LIGHT_CLKGEN_AUDIO_SPDIF1>; + clock-names = "pclk"; + id = <1>; + status = "disabled"; + }; + + pvt: pvt@fffff4e000 { + compatible = "moortec,mr75203"; + reg = <0xff 0xfff4e000 0x0 0x80>, + <0xff 0xfff4e080 0x0 0x100>, + <0xff 0xfff4e180 0x0 0x680>, + <0xff 0xfff4e800 0x0 0x600>; + reg-names = "common", "ts", "pd", "vm"; + clocks = <&dummy_clock_aonsys_clk>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + + i2c0: i2c@ffe7f20000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xe7f20000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <44>; + clocks = <&clk CLKGEN_I2C0_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@ffe7f24000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <45>; + clocks = <&clk CLKGEN_I2C1_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@ffec00c000{ + compatible = "snps,designware-i2c"; + reg = <0xff 0xec00c000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <46>; + clocks = <&clk CLKGEN_I2C2_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@ffec014000{ + compatible = "snps,designware-i2c"; + reg = <0xff 0xec014000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <47>; + clocks = <&clk CLKGEN_I2C3_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 18>, <&dmac0 19>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@ffe7f28000{ + compatible = "snps,designware-i2c"; + reg = <0xff 0xe7f28000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = <48>; + clocks = <&clk CLKGEN_I2C4_PCLK>; + clock-names = "pclk"; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x104>; + ss_lcnt = /bits/ 16 <0xec>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x9>; + hs_lcnt = /bits/ 16 <0x11>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + audio_i2c0: i2c@0xffcb01a000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xcb01a000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <182>; + clocks = <&dummy_clock_apb>; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac2 21>, <&dmac2 20>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x82>; + ss_lcnt = /bits/ 16 <0x78>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x5>; + hs_lcnt = /bits/ 16 <0x15>; + #address-cells = <1>; + #size-cells = <0>; + }; + + audio_i2c1: i2c@0xffcb01b000 { + compatible = "snps,designware-i2c"; + reg = <0xff 0xcb01b000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <183>; + clocks = <&dummy_clock_apb>; + clock-frequency = <100000>; + i2c_mode = "dma"; + dmas = <&dmac2 23>, <&dmac2 22>; + dma-names = "tx", "rx"; + #dma-cells = <1>; + ss_hcnt = /bits/ 16 <0x82>; + ss_lcnt = /bits/ 16 <0x78>; + fs_hcnt = /bits/ 16 <0x37>; + fs_lcnt = /bits/ 16 <0x42>; + fp_hcnt = /bits/ 16 <0x14>; + fp_lcnt = /bits/ 16 <0x1a>; + hs_hcnt = /bits/ 16 <0x5>; + hs_lcnt = /bits/ 16 <0x15>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + isp0: isp@ffe4100000 { + compatible = "thead,light-isp"; + reg = <0xff 0xe4100000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <117>,<118>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>; + clock-names = "aclk", "hclk", "isp0_pclk", "cclk"; + status = "disabled"; + }; + + isp1: isp@ffe4110000 { + compatible = "thead,light-isp"; + reg = <0xff 0xe4110000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <120>,<121>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>; + clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk"; + status = "disabled"; + }; + + isp_ry0: isp_ry@ffe4120000 { + compatible = "thead,light-isp_ry"; + reg = <0xff 0xe4120000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <123>,<124>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>; + clock-names = "aclk", "hclk", "cclk"; + status = "disabled"; + }; + + dewarp: dewarp@ffe4130000 { + compatible = "thead,light-dewarp"; + reg = <0xff 0xe4130000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <98>,<99>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>, + <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>, + <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>; + clock-names = "aclk", "hclk", "vseclk", "dweclk"; + status = "disabled"; + }; + + dec400_isp0: dec400@ffe4060000 { + compatible = "thead,dec400"; + reg = <0xff 0xe4060000 0x0 0x8000>; + status = "disabled"; + }; + + dec400_isp1: dec400@ffe4068000 { + compatible = "thead,dec400"; + reg = <0xff 0xe4068000 0x0 0x8000>; + status = "disabled"; + }; + + dec400_isp2: dec400@ffe4070000 { + compatible = "thead,dec400"; + reg = <0xff 0xe4070000 0x0 0x8000>; + status = "disabled"; + }; + + bm_visys: bm_visys@ffe4040000 { + compatible = "thead,light-bm-visys"; + reg = <0xff 0xe4040000 0x0 0x1000>; + status = "disabled"; + }; + + bm_csi0: csi@ffe4000000{ //CSI2 + compatible = "thead,light-bm-csi"; + reg = < 0xff 0xe4000000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <128>; + dphyglueiftester = <0x180>; + sysreg_mipi_csi_ctrl = <0x140>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>; + clock-names = "pclk", "pixclk", "cfg_clk"; + phy_name = "CSI_4LANE"; + status = "disabled"; + }; + + csia_reg: visys-reg@ffe4020000 { + compatible = "thead,light-visys-reg", "syscon"; + reg = < 0xff 0xe4020000 0x0 0x10000>; + status = "okay"; + }; + + bm_csi1: csi@ffe4010000{ //CSI2X2_B + compatible = "thead,light-bm-csi"; + reg = < 0xff 0xe4010000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0 + dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed. + sysreg_mipi_csi_ctrl = <0x148>; + visys-regmap = <&visys_reg>; + csia-regmap = <&csia_reg>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>; + clock-names = "pclk", "pixclk", "cfg_clk"; + phy_name = "CSI_B"; + status = "disabled"; + }; + + bm_csi2: csi@ffe4020000{ //CSI2X2_A + compatible = "thead,light-bm-csi"; + reg = < 0xff 0xe4020000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <127>; + dphyglueiftester = <0x184>; + sysreg_mipi_csi_ctrl = <0x144>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>, + <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>; + clock-names = "pclk", "pixclk", "cfg_clk"; + phy_name = "CSI_A"; + status = "disabled"; + }; + + bm_isp0: bm_isp@ffe4100000 { + compatible = "thead,light-bm-isp"; + reg = <0xff 0xe4100000 0x0 0x10000>; + status = "disabled"; + }; + + bm_isp1: bm_isp@ffe4110000 { + compatible = "thead,light-bm-isp"; + reg = <0xff 0xe4110000 0x0 0x10000>; + status = "disabled"; + }; + + //isp-ry + bm_isp2: bm_isp@ffe4120000 { + compatible = "thead,light-bm-isp"; + reg = <0xff 0xe4120000 0x0 0x10000>; + status = "disabled"; + }; + + vi_pre: vi_pre@ffe4030000 { + compatible = "thead,vi_pre"; + reg = <0xff 0xe4030000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = <134>; + clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>, + <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>, + <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>; + clock-names ="aclk", "pclk", "pixclk"; + status = "disabled"; + }; + + video0: cam_dev@100 { + compatible = "thead,video"; + status = "disabled"; + }; + + video1: cam_dev@200 { + compatible = "thead,video"; + status = "disabled"; + }; + + video2: cam_dev@300 { + compatible = "thead,video"; + status = "disabled"; + }; + + video3: cam_dev@400 { + compatible = "thead,video"; + status = "disabled"; + }; + + video4: cam_dev@500 { + compatible = "thead,video"; + status = "disabled"; + }; + + video5: cam_dev@600 { + compatible = "thead,video"; + status = "disabled"; + }; + + video6: cam_dev@700 { + compatible = "thead,video"; + status = "disabled"; + }; + + video7: cam_dev@800 { + compatible = "thead,video"; + status = "disabled"; + }; + + video8: cam_dev@900 { + compatible = "thead,video"; + status = "disabled"; + }; + + video9: cam_dev@a00 { + compatible = "thead,video"; + status = "disabled"; + }; + + video10: cam_dev@b00 { + compatible = "thead,video"; + status = "disabled"; + }; + + video11: cam_dev@c00 { + compatible = "thead,video"; + status = "disabled"; + }; + video12: cam_dev@d00 { + compatible = "thead,video"; + status = "disabled"; + }; + + video13: cam_dev@e00 { + compatible = "thead,video"; + status = "disabled"; + }; + + video14: cam_dev@f00 { + compatible = "thead,video"; + status = "disabled"; + }; + + video15: cam_dev@f01 { + compatible = "thead,video"; + status = "disabled"; + }; + + vvcam_flash_led0: vvcam_flash_led@0 { + compatible = "thead,light-vvcam-flash_led"; + status = "disabled"; + }; + + vvcam_sensor0: vvcam_sensor@0 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor1: vvcam_sensor@1 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor2: vvcam_sensor@2 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor3: vvcam_sensor@3 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor4: vvcam_sensor@4 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor5: vvcam_sensor@5 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor6: vvcam_sensor@6 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + vvcam_sensor7: vvcam_sensor@7 { + compatible = "thead,light-vvcam-sensor"; + status = "disabled"; + }; + + xtensa_dsp: dsp@01{ + compatible = "thead,dsp-hw-common"; + reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */ + status = "disabled"; + }; + + xtensa_dsp0: dsp@0 { + compatible = "cdns,xrp-hw-simple"; + reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */ + 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */ + 0xff 0xef048000 0x0 0x008000 /* DSP shared memory */ + 0xff 0xe0180000 0x0 0x040000>; /* DSP TCM*/ + dsp = <0>; + dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ + dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ + device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ + device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ + device-irq-mode = <1>; /*level trigger*/ + host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ + host-irq-mode = <1>; /*level trigger */ + host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ + interrupt-parent = <&intc>; + interrupts = <156>; + #cooling-cells = <2>; + firmware-name = "xrp0.elf"; + clocks = <&dspsys_clk_gate CLKGEN_DSP0_PCLK>, + <&dspsys_clk_gate CLKGEN_DSP0_CCLK>; + clock-names = "pclk", "cclk"; + status = "disabled"; + operating-points-v2 = <&dsp_opp_table>; + dynamic-power-coefficient = <1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 + 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 + 0x00 0xfa000000 0xff 0xe0000000 0x00180000 + 0x00 0xe0180000 0xff 0xe0180000 0x00040000 + 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ + dsp@0 { + ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 + 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 + 0x00 0xfa000000 0xff 0xe0000000 0x00180000 + 0x00 0xe0180000 0xff 0xe0180000 0x00040000 + 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ + }; + }; + + xtensa_dsp1: dsp@1 { + compatible = "cdns,xrp-hw-simple"; + reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */ + 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */ + 0xff 0xef050000 0x0 0x008000 /* DSP shared memory */ + 0xff 0xe01C0000 0x0 0x040000>;/* DSP TCM*/ + dsp = <1>; + dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/ + dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/ + device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */ + device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/ + device-irq-mode = <1>; /*level trigger*/ + host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */ + host-irq-mode = <1>; /*level trigger */ + host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/ + interrupt-parent = <&intc>; + interrupts = <157>; + firmware-name = "xrp1.elf"; + #cooling-cells = <2>; + clocks = <&dspsys_clk_gate CLKGEN_DSP1_PCLK>, + <&dspsys_clk_gate CLKGEN_DSP1_CCLK>; + clock-names = "pclk", "cclk"; + status = "disabled"; + operating-points-v2 = <&dsp_opp_table>; + dynamic-power-coefficient = <1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 + 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 + 0x00 0xfa000000 0xff 0xe0000000 0x00180000 + 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 + 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ + dsp@0 { + ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000 + 0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000 + 0x00 0xfa000000 0xff 0xe0000000 0x00180000 + 0x00 0xe0180000 0xff 0xe01C0000 0x00040000 + 0x00 0xffc00000 0xff 0xe4000000 0x00200000 >; /* VISYS_R */ + }; + }; + + + dsp_opp_table: dsp_opp_table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <800000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <800000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <800000>; + opp-suspend; + }; + }; + + pmp: pmp@ffdc020000 { + compatible = "pmp"; + reg = <0xff 0xdc020000 0x0 0x1000>; + }; + + mrvbr: mrvbr@ffff018050 { + compatible = "mrvbr"; + reg = <0xff 0xff019050 0x0 0x1000>; + }; + + mrmr: mrmr@ffff014004 { + compatible = "mrmr"; + reg = <0xff 0xff015004 0x0 0x1000>; + }; + + bmu: ddr-pmu@ffff008000 { + compatible = "thead,light-ddr-pmu"; + reg = <0xff 0xff008000 0x0 0x800 + 0xff 0xff008800 0x0 0x800 + 0xff 0xff009000 0x0 0x800 + 0xff 0xff009800 0x0 0x800 + 0xff 0xff00a000 0x0 0x800>; + interrupt-parent = <&intc>; + interrupts = <87>; + status = "okay"; + }; + + mbox_910t: mbox@ffffc38000 { + compatible = "thead,light-mbox"; + reg = <0xff 0xffc38000 0x0 0x4000>, + <0xff 0xffc44000 0x0 0x1000>, + <0xff 0xffc4c000 0x0 0x1000>, + <0xff 0xffc54000 0x0 0x1000>; + reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2"; + interrupt-parent = <&intc>; + interrupts = <28>; + clocks = <&dummy_clock_apb>; + clock-names = "ipg"; + icu_cpu_id = <0>; + #mbox-cells = <2>; + }; + + trng: rng@ffff300000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0xff 0xff300000 0x0 0x7d>; + interrupt-parent = <&intc>; + interrupts = <149>; + clocks = <&dummy_clock_eip>; + status = "disabled"; + }; + + + eip_28: eip-28@ffff300000 { + compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28"; + reg = <0xff 0xff300000 0x0 0x40000>; + interrupt-parent = <&intc>; + interrupts = <144>,<145>,<146>,<147>; + clocks = <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SI_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SII_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_EIP120SIII_CLK>, + <&miscsys_clk_gate CLKGEN_MISCSYS_EIP150B_HCLK>; + clock-names = "120si_clk","120sii_clk","120siii_clk","hclk"; + status = "disabled"; + }; + + khvhost: khvhost { + compatible = "thead,khv-host"; + interrupt-parent = <&intc>; + interrupts = <215>; /* TEE INT SRC_7 */ + }; + + light_event: light-event { + compatible = "thead,light-event"; + aon-iram-regmap = <&aon_iram>; + status = "okay"; + }; + + aon_suspend_ctrl: aon_suspend_ctrl { + compatible = "thead,light-aon-suspend-ctrl"; + status = "okay"; + }; + + visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */ + compatible = "thead,visys-gate-controller"; + visys-regmap = <&visys_reg>; + #clock-cells = <1>; + status = "okay"; + }; + + vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */ + compatible = "thead,vpsys-gate-controller"; + reg = <0xff 0xecc30000 0x0 0x1000>; + #clock-cells = <1>; + status = "okay"; + }; + + vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */ + compatible = "thead,vosys-gate-controller"; + reg = <0xff 0xef528000 0x0 0x1000>; + #clock-cells = <1>; + status = "okay"; + }; + + dspsys_clk_gate: dspsys-clk-gate { + compatible = "thead,dspsys-gate-controller"; + dspsys-regmap = <&dspsys_reg>; + #clock-cells = <1>; + status = "okay"; + }; + + audiosys_clk_gate: audiosys-clk-gate { + compatible = "thead,audiosys-gate-controller"; + audiosys-regmap = <&audio_cpr>; + #clock-cells = <1>; + status = "okay"; + }; + + miscsys_clk_gate: miscsys-clk-gate { + compatible = "thead,miscsys-gate-controller"; + miscsys-regmap = <&miscsys_reg>; + tee-miscsys-regmap = <&tee_miscsys_reg>; + #clock-cells = <1>; + status = "okay"; + }; + + }; + +}; + diff --git a/arch/riscv/configs/light_defconfig b/arch/riscv/configs/light_defconfig index f9783656bee2..8c91e0807da6 100644 --- a/arch/riscv/configs/light_defconfig +++ b/arch/riscv/configs/light_defconfig @@ -279,8 +279,8 @@ CONFIG_IIO_SW_DEVICE=y CONFIG_PWM=y CONFIG_PWM_LIGHT=y CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y -CONFIG_TEE=y -CONFIG_OPTEE=y +CONFIG_TEE=m +CONFIG_OPTEE=m CONFIG_OPTEE_BENCHMARK=y CONFIG_LIGHT_GPU_VIV=m # CONFIG_LIGHT_NET is not set @@ -347,4 +347,8 @@ CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_ENERGY_MODEL=y +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_DEVFREQ_THERMAL=y diff --git a/arch/riscv/include/asm/assembler.h b/arch/riscv/include/asm/assembler.h new file mode 100644 index 000000000000..44b1457d3e95 --- /dev/null +++ b/arch/riscv/include/asm/assembler.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * + * Author: Jee Heng Sia + */ + +#ifndef __ASSEMBLY__ +#error "Only include this from assembly code" +#endif + +#ifndef __ASM_ASSEMBLER_H +#define __ASM_ASSEMBLER_H + +#include +#include +#include + +/* + * suspend_restore_csrs - restore CSRs + */ + .macro suspend_restore_csrs + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) + csrw CSR_EPC, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) + csrw CSR_STATUS, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) + csrw CSR_TVAL, t0 + REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) + csrw CSR_CAUSE, t0 + .endm + +/* + * suspend_restore_regs - Restore registers (except A0 and T0-T6) + */ + .macro suspend_restore_regs + REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) + REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) + REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) + REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) + REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) + REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) + REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) + REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) + REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) + REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) + REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) + REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) + REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) + REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) + REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) + REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) + REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) + REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) + REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) + REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) + REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) + REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) + REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) + .endm + +/* + * copy_page - copy 1 page (4KB) of data from source to destination + * @a0 - destination + * @a1 - source + */ + .macro copy_page a0, a1 + lui a2, 0x1 + add a2, a2, a0 +1 : + REG_L t0, 0(a1) + REG_L t1, SZREG(a1) + + REG_S t0, 0(a0) + REG_S t1, SZREG(a0) + + addi a0, a0, 2 * SZREG + addi a1, a1, 2 * SZREG + bne a2, a0, 1b + .endm + +#endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 983165ea1ab8..be768bb19271 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -38,9 +38,9 @@ #define SR_XS_DIRTY _AC(0x00018000, UL) #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS|VS|XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS|VS|XS dirty */ #endif #ifdef CONFIG_COMPAT diff --git a/arch/riscv/include/asm/kexec.h b/arch/riscv/include/asm/kexec.h index 1e954101906a..c459f4cb9e67 100644 --- a/arch/riscv/include/asm/kexec.h +++ b/arch/riscv/include/asm/kexec.h @@ -35,6 +35,11 @@ crash_setup_regs(struct pt_regs *newregs, riscv_crash_save_regs(newregs); } +#if defined(CONFIG_KEXEC) && defined(CONFIG_HIBERNATION) +extern bool crash_is_nosave(unsigned long pfn); +#else +static inline bool crash_is_nosave(unsigned long pfn) {return false; } +#endif #define ARCH_HAS_KIMAGE_ARCH diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 64a675c5c30a..0b4fae72a528 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -128,6 +128,8 @@ extern phys_addr_t __phys_addr_symbol(unsigned long x); #define page_to_bus(page) (page_to_phys(page)) #define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr))) +#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x)) + #ifdef CONFIG_FLATMEM #define pfn_valid(pfn) \ (((pfn) >= ARCH_PFN_OFFSET) && (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 9c715283b12b..c0d7d13993cd 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -521,6 +521,8 @@ extern uintptr_t dtb_early_pa; void setup_bootmem(void); void paging_init(void); +extern u64 satp_mode; + #define FIRST_USER_ADDRESS 0 /* diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 8be391c2aecb..02f87867389a 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -21,6 +21,11 @@ struct suspend_context { #endif }; +/* + * Used by hibernation core and cleared during resume sequence + */ +extern int in_suspend; + /* Low-level CPU suspend entry function */ int __cpu_suspend_enter(struct suspend_context *context); @@ -33,4 +38,21 @@ int cpu_suspend(unsigned long arg, /* Low-level CPU resume entry function */ int __cpu_resume_enter(unsigned long hartid, unsigned long context); +/* Used to save and restore the CSRs */ +void suspend_save_csrs(struct suspend_context *context); +void suspend_restore_csrs(struct suspend_context *context); + +/* Low-level API to support hibernation */ +int swsusp_arch_suspend(void); +int swsusp_arch_resume(void); +int arch_hibernation_header_save(void *addr, unsigned int max_size); +int arch_hibernation_header_restore(void *addr); +int __hibernate_cpu_resume(void); + +/* Used to resume on the CPU we hibernated on */ +int hibernate_resume_nonboot_cpu_disable(void); + +asmlinkage void hibernate_restore_image(unsigned long resume_satp, unsigned long satp_temp, + unsigned long cpu_resume); +asmlinkage int hibernate_core_restore_code(void); #endif diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 465275f89ed3..255705b1c3fe 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -75,7 +75,7 @@ static inline void __vstate_clean(struct pt_regs *regs) static inline void vstate_save(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) == SR_VS_DIRTY) { + if ((regs->status & SR_VS) != SR_VS_OFF) { __vstate_save(task); __vstate_clean(regs); } diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index ba6c1520b0d1..03bab40f3259 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o +obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate-asm.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 9691d08bdd8c..9c64bdb35217 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -154,6 +155,11 @@ void asm_offsets(void) OFFSET(PT_CAUSE, pt_regs, cause); OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs); + + OFFSET(HIBERN_PBE_ADDR, pbe, address); + OFFSET(HIBERN_PBE_ORIG, pbe, orig_address); + OFFSET(HIBERN_PBE_NEXT, pbe, next); + #if 0 OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero); OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra); diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S index dd2205473de7..b82e1cb1424c 100644 --- a/arch/riscv/kernel/fpu.S +++ b/arch/riscv/kernel/fpu.S @@ -65,9 +65,19 @@ ENDPROC(__fstate_save) ENTRY(__fstate_restore) li a2, TASK_THREAD_F0 add a0, a0, a2 + + /* Enable FPU */ li t1, SR_FS - lw t0, TASK_THREAD_FCSR_F0(a0) csrs CSR_STATUS, t1 + + /* Restore fcsr[0-7] */ + frcsr t1 + srli t1, t1, 8 + slli t1, t1, 8 + lbu t0, TASK_THREAD_FCSR_F0(a0) + or t0, t1, t0 + + /* Restore f0 - f31 */ fld f0, TASK_THREAD_F0_F0(a0) fld f1, TASK_THREAD_F1_F0(a0) fld f2, TASK_THREAD_F2_F0(a0) diff --git a/arch/riscv/kernel/hibernate-asm.S b/arch/riscv/kernel/hibernate-asm.S new file mode 100644 index 000000000000..effaf5ca5da0 --- /dev/null +++ b/arch/riscv/kernel/hibernate-asm.S @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Hibernation low level support for RISCV. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * + * Author: Jee Heng Sia + */ + +#include +#include +#include +#include + +#include + +/* + * int __hibernate_cpu_resume(void) + * Switch back to the hibernated image's page table prior to restoring the CPU + * context. + * + * Always returns 0 + */ +ENTRY(__hibernate_cpu_resume) + /* switch to hibernated image's page table. */ + csrw CSR_SATP, s0 + sfence.vma + + REG_L a0, hibernate_cpu_context + + suspend_restore_csrs + suspend_restore_regs + + /* Return zero value. */ + mv a0, zero + + ret +END(__hibernate_cpu_resume) + +/* + * Prepare to restore the image. + * a0: satp of saved page tables. + * a1: satp of temporary page tables. + * a2: cpu_resume. + */ +ENTRY(hibernate_restore_image) + mv s0, a0 + mv s1, a1 + mv s2, a2 + REG_L s4, restore_pblist + REG_L a1, relocated_restore_code + + jalr a1 +END(hibernate_restore_image) + +/* + * The below code will be executed from a 'safe' page. + * It first switches to the temporary page table, then starts to copy the pages + * back to the original memory location. Finally, it jumps to __hibernate_cpu_resume() + * to restore the CPU context. + */ +ENTRY(hibernate_core_restore_code) + /* switch to temp page table. */ + csrw satp, s1 + sfence.vma +.Lcopy: + /* The below code will restore the hibernated image. */ + REG_L a1, HIBERN_PBE_ADDR(s4) + REG_L a0, HIBERN_PBE_ORIG(s4) + + copy_page a0, a1 + + REG_L s4, HIBERN_PBE_NEXT(s4) + bnez s4, .Lcopy + + jalr s2 +END(hibernate_core_restore_code) diff --git a/arch/riscv/kernel/hibernate.c b/arch/riscv/kernel/hibernate.c new file mode 100644 index 000000000000..f0f56d3abda4 --- /dev/null +++ b/arch/riscv/kernel/hibernate.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Hibernation support for RISCV + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * + * Author: Jee Heng Sia + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* The logical cpu number we should resume on, initialised to a non-cpu number. */ +static int sleep_cpu = -EINVAL; + +/* Pointer to the temporary resume page table. */ +static pgd_t *resume_pg_dir; + +/* CPU context to be saved. */ +struct suspend_context *hibernate_cpu_context; +EXPORT_SYMBOL_GPL(hibernate_cpu_context); + +unsigned long relocated_restore_code; +EXPORT_SYMBOL_GPL(relocated_restore_code); + +/** + * struct arch_hibernate_hdr_invariants - container to store kernel build version. + * @uts_version: to save the build number and date so that we do not resume with + * a different kernel. + */ +struct arch_hibernate_hdr_invariants { + char uts_version[__NEW_UTS_LEN + 1]; +}; + +/** + * struct arch_hibernate_hdr - helper parameters that help us to restore the image. + * @invariants: container to store kernel build version. + * @hartid: to make sure same boot_cpu executes the hibernate/restore code. + * @saved_satp: original page table used by the hibernated image. + * @restore_cpu_addr: the kernel's image address to restore the CPU context. + */ +static struct arch_hibernate_hdr { + struct arch_hibernate_hdr_invariants invariants; + unsigned long hartid; + unsigned long saved_satp; + unsigned long restore_cpu_addr; +} resume_hdr; + +static void arch_hdr_invariants(struct arch_hibernate_hdr_invariants *i) +{ + memset(i, 0, sizeof(*i)); + memcpy(i->uts_version, init_utsname()->version, sizeof(i->uts_version)); +} + +/* + * Check if the given pfn is in the 'nosave' section. + */ +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = sym_to_pfn(&__nosave_begin); + unsigned long nosave_end_pfn = sym_to_pfn(&__nosave_end - 1); + + return ((pfn >= nosave_begin_pfn) && (pfn <= nosave_end_pfn)) || + crash_is_nosave(pfn); +} + +void notrace save_processor_state(void) +{ + WARN_ON(num_online_cpus() != 1); +} + +void notrace restore_processor_state(void) +{ +} + +/* + * Helper parameters need to be saved to the hibernation image header. + */ +int arch_hibernation_header_save(void *addr, unsigned int max_size) +{ + struct arch_hibernate_hdr *hdr = addr; + + if (max_size < sizeof(*hdr)) + return -EOVERFLOW; + + arch_hdr_invariants(&hdr->invariants); + + hdr->hartid = cpuid_to_hartid_map(sleep_cpu); + hdr->saved_satp = csr_read(CSR_SATP); + hdr->restore_cpu_addr = (unsigned long)__hibernate_cpu_resume; + + return 0; +} +EXPORT_SYMBOL_GPL(arch_hibernation_header_save); + +/* + * Retrieve the helper parameters from the hibernation image header. + */ +int arch_hibernation_header_restore(void *addr) +{ + struct arch_hibernate_hdr_invariants invariants; + struct arch_hibernate_hdr *hdr = addr; + int ret = 0; + + arch_hdr_invariants(&invariants); + + if (memcmp(&hdr->invariants, &invariants, sizeof(invariants))) { + pr_crit("Hibernate image not generated by this kernel!\n"); + return -EINVAL; + } + + sleep_cpu = riscv_hartid_to_cpuid(hdr->hartid); + if (sleep_cpu < 0) { + pr_crit("Hibernated on a CPU not known to this kernel!\n"); + sleep_cpu = -EINVAL; + return -EINVAL; + } + +#ifdef CONFIG_SMP + ret = bringup_hibernate_cpu(sleep_cpu); + if (ret) { + sleep_cpu = -EINVAL; + return ret; + } +#endif + resume_hdr = *hdr; + + return ret; +} +EXPORT_SYMBOL_GPL(arch_hibernation_header_restore); + +int swsusp_arch_suspend(void) +{ + int ret = 0; + + if (__cpu_suspend_enter(hibernate_cpu_context)) { + sleep_cpu = smp_processor_id(); + suspend_save_csrs(hibernate_cpu_context); + ret = swsusp_save(); + } else { + suspend_restore_csrs(hibernate_cpu_context); + flush_tlb_all(); + flush_icache_all(); + + /* + * Tell the hibernation core that we've just restored the memory. + */ + in_suspend = 0; + sleep_cpu = -EINVAL; + } + + return ret; +} + +static int temp_pgtable_map_pte(pmd_t *dst_pmdp, pmd_t *src_pmdp, unsigned long start, + unsigned long end, pgprot_t prot) +{ + pte_t *src_ptep; + pte_t *dst_ptep; + + if (pmd_none(READ_ONCE(*dst_pmdp))) { + dst_ptep = (pte_t *)get_safe_page(GFP_ATOMIC); + if (!dst_ptep) + return -ENOMEM; + + pmd_populate_kernel(NULL, dst_pmdp, dst_ptep); + } + + dst_ptep = pte_offset_kernel(dst_pmdp, start); + src_ptep = pte_offset_kernel(src_pmdp, start); + + do { + pte_t pte = READ_ONCE(*src_ptep); + + if (pte_present(pte)) + set_pte(dst_ptep, __pte(pte_val(pte) | pgprot_val(prot))); + } while (dst_ptep++, src_ptep++, start += PAGE_SIZE, start < end); + + return 0; +} + +static int temp_pgtable_map_pmd(pud_t *dst_pudp, pud_t *src_pudp, unsigned long start, + unsigned long end, pgprot_t prot) +{ + unsigned long next; + unsigned long ret; + pmd_t *src_pmdp; + pmd_t *dst_pmdp; + + if (pud_none(READ_ONCE(*dst_pudp))) { + dst_pmdp = (pmd_t *)get_safe_page(GFP_ATOMIC); + if (!dst_pmdp) + return -ENOMEM; + + pud_populate(NULL, dst_pudp, dst_pmdp); + } + + dst_pmdp = pmd_offset(dst_pudp, start); + src_pmdp = pmd_offset(src_pudp, start); + + do { + pmd_t pmd = READ_ONCE(*src_pmdp); + + next = pmd_addr_end(start, end); + + if (pmd_none(pmd)) + continue; + + if (pmd_leaf(pmd)) { + set_pmd(dst_pmdp, __pmd(pmd_val(pmd) | pgprot_val(prot))); + } else { + ret = temp_pgtable_map_pte(dst_pmdp, src_pmdp, start, next, prot); + if (ret) + return -ENOMEM; + } + } while (dst_pmdp++, src_pmdp++, start = next, start != end); + + return 0; +} + +static int temp_pgtable_map_pud(p4d_t *dst_p4dp, p4d_t *src_p4dp, unsigned long start, + unsigned long end, pgprot_t prot) +{ + unsigned long next; + unsigned long ret; + pud_t *dst_pudp; + pud_t *src_pudp; + + if (p4d_none(READ_ONCE(*dst_p4dp))) { + dst_pudp = (pud_t *)get_safe_page(GFP_ATOMIC); + if (!dst_pudp) + return -ENOMEM; + + p4d_populate(NULL, dst_p4dp, dst_pudp); + } + + dst_pudp = pud_offset(dst_p4dp, start); + src_pudp = pud_offset(src_p4dp, start); + + do { + pud_t pud = READ_ONCE(*src_pudp); + + next = pud_addr_end(start, end); + + if (pud_none(pud)) + continue; + + if (pud_leaf(pud)) { + set_pud(dst_pudp, __pud(pud_val(pud) | pgprot_val(prot))); + } else { + ret = temp_pgtable_map_pmd(dst_pudp, src_pudp, start, next, prot); + if (ret) + return -ENOMEM; + } + } while (dst_pudp++, src_pudp++, start = next, start != end); + + return 0; +} + +static int temp_pgtable_map_p4d(pgd_t *dst_pgdp, pgd_t *src_pgdp, unsigned long start, + unsigned long end, pgprot_t prot) +{ + unsigned long next; + unsigned long ret; + p4d_t *dst_p4dp; + p4d_t *src_p4dp; + + if (pgd_none(READ_ONCE(*dst_pgdp))) { + dst_p4dp = (p4d_t *)get_safe_page(GFP_ATOMIC); + if (!dst_p4dp) + return -ENOMEM; + + pgd_populate(NULL, dst_pgdp, dst_p4dp); + } + + dst_p4dp = p4d_offset(dst_pgdp, start); + src_p4dp = p4d_offset(src_pgdp, start); + + do { + p4d_t p4d = READ_ONCE(*src_p4dp); + + next = p4d_addr_end(start, end); + + if (p4d_none(p4d)) + continue; + + if (p4d_leaf(p4d)) { + set_p4d(dst_p4dp, __p4d(p4d_val(p4d) | pgprot_val(prot))); + } else { + ret = temp_pgtable_map_pud(dst_p4dp, src_p4dp, start, next, prot); + if (ret) + return -ENOMEM; + } + } while (dst_p4dp++, src_p4dp++, start = next, start != end); + + return 0; +} + +static int temp_pgtable_mapping(pgd_t *pgdp, unsigned long start, unsigned long end, pgprot_t prot) +{ + pgd_t *dst_pgdp = pgd_offset_pgd(pgdp, start); + pgd_t *src_pgdp = pgd_offset_k(start); + unsigned long next; + unsigned long ret; + + do { + pgd_t pgd = READ_ONCE(*src_pgdp); + + next = pgd_addr_end(start, end); + + if (pgd_none(pgd)) + continue; + + if (pgd_leaf(pgd)) { + set_pgd(dst_pgdp, __pgd(pgd_val(pgd) | pgprot_val(prot))); + } else { + ret = temp_pgtable_map_p4d(dst_pgdp, src_pgdp, start, next, prot); + if (ret) + return -ENOMEM; + } + } while (dst_pgdp++, src_pgdp++, start = next, start != end); + + return 0; +} + +static unsigned long relocate_restore_code(void) +{ + void *page = (void *)get_safe_page(GFP_ATOMIC); + + if (!page) + return -ENOMEM; + + copy_page(page, hibernate_core_restore_code); + + /* Make the page containing the relocated code executable. */ + set_memory_x((unsigned long)page, 1); + + return (unsigned long)page; +} + +int swsusp_arch_resume(void) +{ + unsigned long end = (unsigned long)pfn_to_virt(max_low_pfn); + unsigned long start = PAGE_OFFSET; + int ret; + + /* + * Memory allocated by get_safe_page() will be dealt with by the hibernation core, + * we don't need to free it here. + */ + resume_pg_dir = (pgd_t *)get_safe_page(GFP_ATOMIC); + if (!resume_pg_dir) + return -ENOMEM; + + /* + * Create a temporary page table and map the whole linear region as executable and + * writable. + */ + ret = temp_pgtable_mapping(resume_pg_dir, start, end, __pgprot(_PAGE_WRITE | _PAGE_EXEC)); + if (ret) + return ret; + + /* Move the restore code to a new page so that it doesn't get overwritten by itself. */ + relocated_restore_code = relocate_restore_code(); + if (relocated_restore_code == -ENOMEM) + return -ENOMEM; + + /* + * Map the __hibernate_cpu_resume() address to the temporary page table so that the + * restore code can jumps to it after finished restore the image. The next execution + * code doesn't find itself in a different address space after switching over to the + * original page table used by the hibernated image. + * The __hibernate_cpu_resume() mapping is unnecessary for RV32 since the kernel and + * linear addresses are identical, but different for RV64. To ensure consistency, we + * map it for both RV32 and RV64 kernels. + * Additionally, we should ensure that the page is writable before restoring the image. + */ + start = (unsigned long)resume_hdr.restore_cpu_addr; + end = start + PAGE_SIZE; + + ret = temp_pgtable_mapping(resume_pg_dir, start, end, __pgprot(_PAGE_WRITE)); + if (ret) + return ret; + + hibernate_restore_image(resume_hdr.saved_satp, (PFN_DOWN(__pa(resume_pg_dir)) | satp_mode), + resume_hdr.restore_cpu_addr); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP_SMP +int hibernate_resume_nonboot_cpu_disable(void) +{ + if (sleep_cpu < 0) { + pr_err("Failing to resume from hibernate on an unknown CPU\n"); + return -ENODEV; + } + + return freeze_secondary_cpus(sleep_cpu); +} +#endif + +static int __init riscv_hibernate_init(void) +{ + hibernate_cpu_context = kzalloc(sizeof(*hibernate_cpu_context), GFP_KERNEL); + + if (WARN_ON(!hibernate_cpu_context)) + return -ENOMEM; + + return 0; +} + +early_initcall(riscv_hibernate_init); diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index e008d8ede4b5..26934db49b99 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -235,3 +235,44 @@ machine_kexec(struct kimage *image) this_hart_id, va_pa_offset); unreachable(); } +#ifdef CONFIG_HIBERNATION +/* + * crash_is_nosave + * + * Return true only if a page is part of reserved memory for crash dump kernel, + * but does not hold any data of loaded kernel image. + * + * Note that all the pages in crash dump kernel memory have been initially + * marked as Reserved as memory was allocated via memblock_reserve(). + * + * In hibernation, the pages which are Reserved and yet "nosave" are excluded + * from the hibernation iamge. crash_is_nosave() does thich check for crash + * dump kernel and will reduce the total size of hibernation image. + */ + +bool crash_is_nosave(unsigned long pfn) +{ + int i; + phys_addr_t addr; + + if (!crashk_res.end) + return false; + + /* in reserved memory? */ + addr = __pfn_to_phys(pfn); + if ((addr < crashk_res.start) || (crashk_res.end < addr)) + return false; + + if (!kexec_crash_image) + return true; + + /* not part of loaded kernel image? */ + for (i = 0; i < kexec_crash_image->nr_segments; i++) + if (addr >= kexec_crash_image->segment[i].mem && + addr < (kexec_crash_image->segment[i].mem + + kexec_crash_image->segment[i].memsz)) + return false; + + return true; +} +#endif diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c index 7a057b5f0adc..89b4c996a9ae 100644 --- a/arch/riscv/kernel/probes/uprobes.c +++ b/arch/riscv/kernel/probes/uprobes.c @@ -182,5 +182,5 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, * architecture needs to do something different it can define * its own version of the function. */ - flush_dcache_page(page); + flush_icache_range(kaddr, kaddr + len); } diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 9ba24fb8cc93..3c89b8ec69c4 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -8,7 +8,7 @@ #include #include -static void suspend_save_csrs(struct suspend_context *context) +void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); context->tvec = csr_read(CSR_TVEC); @@ -29,7 +29,7 @@ static void suspend_save_csrs(struct suspend_context *context) #endif } -static void suspend_restore_csrs(struct suspend_context *context) +void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); csr_write(CSR_TVEC, context->tvec); diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S index 4b07b809a2b8..49eb74a04906 100644 --- a/arch/riscv/kernel/suspend_entry.S +++ b/arch/riscv/kernel/suspend_entry.S @@ -7,6 +7,7 @@ #include #include #include +#include #include .text @@ -82,39 +83,10 @@ ENTRY(__cpu_resume_enter) add a0, a1, zero /* Restore CSRs */ - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) - csrw CSR_EPC, t0 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) - csrw CSR_STATUS, t0 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) - csrw CSR_TVAL, t0 - REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) - csrw CSR_CAUSE, t0 + suspend_restore_csrs /* Restore registers (except A0 and T0-T6) */ - REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) - REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) - REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) - REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) - REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) - REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) - REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) - REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) - REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) - REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) - REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) - REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) - REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) - REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) - REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) - REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) - REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) - REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) - REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) - REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) - REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) - REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) - REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) + suspend_restore_regs /* Return zero value */ add a0, zero, zero diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S index a4d7835d5eb3..3fffce085fad 100644 --- a/arch/riscv/kernel/vector.S +++ b/arch/riscv/kernel/vector.S @@ -69,10 +69,6 @@ ENTRY(__vstate_restore) .word 0x12050c07 /* vlb.v v24, (a0) */ mv a0, t2 - ld t0, TASK_THREAD_VSTART_V0(a0) - csrw CSR_VSTART, t0 - ld t0, TASK_THREAD_VXSAT_V0(a0) - csrw CSR_VXSAT, t0 ld t0, TASK_THREAD_VXRM_V0(a0) csrw CSR_VXRM, t0 ld t0, TASK_THREAD_VL_V0(a0) @@ -80,6 +76,9 @@ ENTRY(__vstate_restore) .word 0x8072fe57 /* vsetvl t3, t0, t2 */ + /* vsetvl & vsetvli would reset vstart to zero */ + ld t0, TASK_THREAD_VSTART_V0(a0) + csrw CSR_VSTART, t0 csrc sstatus, t1 ret ENDPROC(__vstate_restore) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 993ec3d63e97..40e455462db1 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -31,6 +31,13 @@ unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] __page_aligned_bss; EXPORT_SYMBOL(empty_zero_page); +#ifdef CONFIG_64BIT +u64 satp_mode __ro_after_init = SATP_MODE_39; +#else +u64 satp_mode __ro_after_init = SATP_MODE_32; +#endif +EXPORT_SYMBOL(satp_mode); + extern char _start[]; #define DTB_EARLY_BASE_VA PGDIR_SIZE void *dtb_early_va __initdata; diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c index 19fecb362d81..8bc0e8cc79d7 100644 --- a/arch/riscv/mm/pageattr.c +++ b/arch/riscv/mm/pageattr.c @@ -196,3 +196,40 @@ void __kernel_map_pages(struct page *page, int numpages, int enable) __set_memory((unsigned long)page_address(page), numpages, __pgprot(0), __pgprot(_PAGE_PRESENT)); } + +bool kernel_page_present(struct page *page) +{ + unsigned long addr = (unsigned long)page_address(page); + pgd_t *pgd; + pud_t *pud; + p4d_t *p4d; + pmd_t *pmd; + pte_t *pte; + + pgd = pgd_offset_k(addr); + if (!pgd_present(*pgd)) + return false; + if (pgd_leaf(*pgd)) + return true; + + p4d = p4d_offset(pgd, addr); + if (!p4d_present(*p4d)) + return false; + if (p4d_leaf(*p4d)) + return true; + + pud = pud_offset(p4d, addr); + if (!pud_present(*pud)) + return false; + if (pud_leaf(*pud)) + return true; + + pmd = pmd_offset(pud, addr); + if (!pmd_present(*pmd)) + return false; + if (pmd_leaf(*pmd)) + return true; + + pte = pte_offset_kernel(pmd, addr); + return pte_present(*pte); +} diff --git a/drivers/clk/thead/gate/vosys-gate.c b/drivers/clk/thead/gate/vosys-gate.c index e53ba1a3e763..7584b9fe0ca3 100644 --- a/drivers/clk/thead/gate/vosys-gate.c +++ b/drivers/clk/thead/gate/vosys-gate.c @@ -65,7 +65,7 @@ static int light_vosys_clk_probe(struct platform_device *pdev) gates[LIGHT_CLKGEN_MIPIDSI1_CFG_CLK] = thead_clk_light_gate("clkgen_mipidsi1_cfg_clk", NULL, gate_base + 0x50, 16); gates[LIGHT_CLKGEN_MIPIDSI0_REFCLK] = thead_clk_light_gate("clkgen_mipidsi0_refclk", NULL, gate_base + 0x50, 17); gates[LIGHT_CLKGEN_MIPIDSI1_REFCLK] = thead_clk_light_gate("clkgen_mipidsi1_refclk", NULL, gate_base + 0x50, 18); - gates[LIGHT_CLKGEN_GPU_CORE_CLK] = thead_clk_light_gate("clkgen_gpu_core_clk", NULL, gate_base + 0x50, 3); + gates[LIGHT_CLKGEN_GPU_CORE_CLK] = thead_clk_light_gate("clkgen_gpu_core_clk", "vosys_aclk_m", gate_base + 0x50, 3); gates[LIGHT_CLKGEN_GPU_CFG_ACLK] = thead_clk_light_gate("clkgen_gpu_cfg_aclk", NULL, gate_base + 0x50, 4); gates[LIGHT_CLKGEN_DPU_HCLK] = thead_clk_light_gate("clkgen_dpu_hclk", NULL, gate_base + 0x50, 7); gates[LIGHT_CLKGEN_DPU_ACLK] = thead_clk_light_gate("clkgen_dpu_aclk", NULL, gate_base + 0x50, 8); diff --git a/drivers/clk/thead/gate/vpsys-gate.c b/drivers/clk/thead/gate/vpsys-gate.c index 1a01df1f2b3f..57b868c31a44 100644 --- a/drivers/clk/thead/gate/vpsys-gate.c +++ b/drivers/clk/thead/gate/vpsys-gate.c @@ -35,7 +35,8 @@ static int light_vpsys_clk_probe(struct platform_device *pdev) return PTR_ERR(gate_base); // DIV & CDE - gates[LIGHT_VPSYS_G2D_CCLK_DIV] = thead_clk_light_divider("light_vpsys_g2d_cclk_div", "video_pll_foutvco", gate_base + 0x30, 0, 4, 4, MUX_TYPE_DIV, 3, 9); + gates[LIGHT_VPSYS_G2D_CCLK_DIV] = thead_clk_light_divider("light_vpsys_g2d_cclk_div", "video_pll_foutvco", gate_base + 0x30, 0, 4, 4, MUX_TYPE_DIV, 3, 15); + gates[LIGHT_VPSYS_DEC_CCLK_DIV] = thead_clk_light_divider("light_vpsys_dec_cclk_div", "video_pll_foutvco", gate_base + 0x24, 0, 4, 4, MUX_TYPE_DIV, 4, 15); /* G2D clock configuration : Completed the upward configuration of CCLK */ gates[LIGHT_VPSYS_G2D_PCLK] = thead_clk_light_gate_shared("clkgen_vpsys_g2d_pclk", NULL, @@ -51,11 +52,12 @@ static int light_vpsys_clk_probe(struct platform_device *pdev) gates[LIGHT_VPSYS_FCE_ACLK] = thead_clk_light_gate_shared("clkgen_vpsys_fce_aclk", NULL, gate_base + 0x20, 2, &share_cnt_fce_clk_en); + /* VENC&VDEC clock configuration : Completed the upward configuration of CCLK */ gates[LIGHT_VPSYS_VDEC_ACLK] = thead_clk_light_gate("clkgen_vdec_aclk", NULL, gate_base + 0x20, 4); - gates[LIGHT_VPSYS_VDEC_CCLK] = thead_clk_light_gate("clkgen_vdec_cclk", NULL, gate_base + 0x20, 5); + gates[LIGHT_VPSYS_VDEC_CCLK] = thead_clk_light_gate("clkgen_vdec_cclk", "light_vpsys_dec_cclk_div", gate_base + 0x20, 5); gates[LIGHT_VPSYS_VDEC_PCLK] = thead_clk_light_gate("clkgen_vdec_pclk", NULL, gate_base + 0x20, 6); - gates[LIGHT_VPSYS_VENC_CCLK] = thead_clk_light_gate("clkgen_venc_cclk", NULL, gate_base + 0x20, 8); + gates[LIGHT_VPSYS_VENC_CCLK] = thead_clk_light_gate("clkgen_venc_cclk", "clkgen_vpsys_venc_cclk", gate_base + 0x20, 8); gates[LIGHT_VPSYS_VENC_PCLK] = thead_clk_light_gate("clkgen_venc_pclk", NULL, gate_base + 0x20, 9); gates[LIGHT_VPSYS_VENC_ACLK] = thead_clk_light_gate("clkgen_venc_aclk", NULL, gate_base + 0x20, 7); diff --git a/drivers/cpufreq/light-mpw-cpufreq.c b/drivers/cpufreq/light-mpw-cpufreq.c index df9ef3baa377..685f9bba52a1 100644 --- a/drivers/cpufreq/light-mpw-cpufreq.c +++ b/drivers/cpufreq/light-mpw-cpufreq.c @@ -240,6 +240,15 @@ static int light_cpufreq_suspend(struct cpufreq_policy *policy) return ret; } +/* + * skip to siwtch pll during reboot process + */ + mutex_lock(&cpufreq_lock); + if (cpufreq_denied) { + pr_debug("Denied to switch CPU PLL temporarily on reboot\n"); + mutex_unlock(&cpufreq_lock); + return 0; + } /* * Only CPU PLL0 would be active after STR resume. We should switch * CPU PLL to be PLL0 after policy stopped. @@ -247,12 +256,36 @@ static int light_cpufreq_suspend(struct cpufreq_policy *policy) if (_light_get_pllid() == LIGHT_CPU_PLL_IDX(1)) _light_switch_pllid(LIGHT_CPU_PLL_IDX(0), policy->suspend_freq); + /* + * switch pll1 to min_freq, as pll1 also needs to be a known value + * or unexpected errors would come out during recovery. + */ + clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk); + clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, min_freq * 1000); + clk_disable_unprepare(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk); + mutex_unlock(&cpufreq_lock); return 0; } static int light_cpufreq_resume(struct cpufreq_policy *policy) { - return 0; + int ret; + + ret = __cpufreq_driver_target(policy, min_freq, CPUFREQ_RELATION_H); + if (ret) + pr_err("%s: unable to set restore-freq: %u. err: %d\n", + __func__, min_freq, ret); + /* + * CPU PLL0 with 300M would be active after STR resume. As we switch CPU PLL + * to PLL0 with highest frequency when suspend, switch PLL0 with right one + * after resume. + */ + mutex_lock(&cpufreq_lock); + if(_light_get_pllid() == LIGHT_CPU_PLL_IDX(1)) + _light_switch_pllid(LIGHT_CPU_PLL_IDX(0), min_freq); + mutex_unlock(&cpufreq_lock); + + return ret; } static int light_cpufreq_init(struct cpufreq_policy *policy) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index c2928a8ac2cf..25ebe3111336 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -872,6 +872,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, goto err_desc_get; desc->chan = chan; + chan->direction = DMA_MEM_TO_MEM; num = 0; desc->length = 0; while (len) { diff --git a/drivers/firmware/thead/light_aon.c b/drivers/firmware/thead/light_aon.c index ad2d49a0845c..5af7de821e76 100644 --- a/drivers/firmware/thead/light_aon.c +++ b/drivers/firmware/thead/light_aon.c @@ -14,7 +14,8 @@ #include #include -#define MAX_RX_TIMEOUT (msecs_to_jiffies(300)) +/* wait for response for 3000ms instead of 300ms (fix me pls)*/ +#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) #define MAX_TX_TIMEOUT (msecs_to_jiffies(500)) struct light_aon_chan { diff --git a/drivers/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c b/drivers/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c index 549c5a085c40..e4e1c54a4a8f 100644 --- a/drivers/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c +++ b/drivers/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c @@ -16823,9 +16823,32 @@ gckHARDWARE_SetClock( gctUINT32 core = Core; gctUINT32 mcScale = MCScale; gctUINT32 shScale = SHScale; + gceCHIPPOWERSTATE statesStored,state; gcmkHEADER(); + gckHARDWARE_QueryPowerState( + Hardware, &statesStored + ); + switch(statesStored) + { + case gcvPOWER_OFF: + state = gcvPOWER_OFF_BROADCAST; + break; + case gcvPOWER_IDLE: + state = gcvPOWER_IDLE_BROADCAST; + break; + case gcvPOWER_SUSPEND: + state = gcvPOWER_SUSPEND_BROADCAST; + break; + case gcvPOWER_ON: + state = gcvPOWER_ON_AUTO; + break; + default: + state = statesStored; + break; + } + status = gckOS_QueryOption(Hardware->os, "powerManagement", &powerManagement); if (gcmIS_ERROR(status)) { @@ -16838,9 +16861,7 @@ gckHARDWARE_SetClock( Hardware, gcvFALSE )); - gcmkPRINT("Warning: Power management status will be changed forever!\n"); } - gcmkONERROR(gckHARDWARE_SetPowerState( Hardware, gcvPOWER_ON_AUTO )); @@ -16977,6 +16998,15 @@ gckHARDWARE_SetClock( globalAcquired = gcvFALSE; gcmkFOOTER_NO(); + if (powerManagement) + { + gcmkONERROR(gckHARDWARE_EnablePowerManagement( + Hardware, gcvTRUE + )); + } + gckHARDWARE_SetPowerState( + Hardware, state + ); return gcvSTATUS_OK; @@ -16990,7 +17020,6 @@ OnError: } gcmkFOOTER_NO(); - return status; } diff --git a/drivers/gpu-viv/hal/kernel/gc_hal_kernel.h b/drivers/gpu-viv/hal/kernel/gc_hal_kernel.h index 7065d0b75074..52c2922d9dc5 100644 --- a/drivers/gpu-viv/hal/kernel/gc_hal_kernel.h +++ b/drivers/gpu-viv/hal/kernel/gc_hal_kernel.h @@ -599,7 +599,6 @@ struct _gckKERNEL gcsTIMER timers[8]; gctUINT32 timeOut; - #if gcdDVFS gckDVFS dvfs; #endif @@ -662,6 +661,12 @@ struct _gckKERNEL gctSEMAPHORE preemptSema; gcePREEMPTION_MODE preemptionMode; #endif + gctUINT64 cur_on; + gctUINT64 cur_idel; + gctUINT64 cur_off; + gctUINT64 cur_suspend; + gctUINT64 cur_load; + unsigned int cur_freq; }; struct _FrequencyHistory diff --git a/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c b/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c index 1010faa99167..fee3a092a34e 100644 --- a/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c +++ b/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c @@ -61,6 +61,17 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #define _GC_OBJ_ZONE gcvZONE_DEVICE @@ -312,137 +323,36 @@ int gc_load_show(void* m, void* data) { int len = 0; gctUINT32 i = 0; - gceSTATUS status = gcvSTATUS_OK; + gckGALDEVICE device = galDevice; - gceCHIPPOWERSTATE statesStored, state; - gctUINT32 load[gcvCORE_3D_MAX + 1] = {0}; - gctUINT32 hi_total_cycle_count[gcvCORE_3D_MAX + 1] = {0}; - gctUINT32 hi_total_idle_cycle_count[gcvCORE_3D_MAX + 1] = {0}; - static gctBOOL profilerEnable[gcvCORE_3D_MAX + 1] = {gcvFALSE}; - + #ifdef CONFIG_DEBUG_FS void* ptr = m; #else char* ptr = (char*)m; #endif - if (!device) + if (!device) { return -ENXIO; - - for (i = 0; i <= gcvCORE_3D_MAX; i++) - { - if (device->kernels[i]) - { - if (device->kernels[i]->hardware) - { - gckHARDWARE Hardware = device->kernels[i]->hardware; - gctBOOL powerManagement = Hardware->options.powerManagement; - - if (powerManagement) - { - gcmkONERROR(gckHARDWARE_EnablePowerManagement( - Hardware, gcvFALSE - )); - } - - gcmkONERROR(gckHARDWARE_QueryPowerState( - Hardware, &statesStored - )); - - gcmkONERROR(gckHARDWARE_SetPowerState( - Hardware, gcvPOWER_ON_AUTO - )); - - if (!profilerEnable[i]) - { - gcmkONERROR(gckHARDWARE_SetGpuProfiler( - Hardware, - gcvTRUE - )); - - gcmkONERROR(gckHARDWARE_InitProfiler(Hardware)); - - profilerEnable[i] = gcvTRUE; - } - - Hardware->waitCount = 200 * 100; - } - } - } - - for (i = 0; i <= gcvCORE_3D_MAX; i++) - { - if (device->kernels[i]) - { - if (device->kernels[i]->hardware) - { - gcmkONERROR(gckHARDWARE_CleanCycleCount(device->kernels[i]->hardware)); - } - } - } - - for (i = 0; i <= gcvCORE_3D_MAX; i++) - { - if (device->kernels[i]) - { - if (device->kernels[i]->hardware) - { - gcmkONERROR(gckHARDWARE_QueryCycleCount(device->kernels[i]->hardware, &hi_total_cycle_count[i], &hi_total_idle_cycle_count[i])); - } - } } + + - for (i = 0; i <= gcvCORE_3D_MAX; i++) - { - if (device->kernels[i]) + for (i = 0; i <= gcvCORE_2D_MAX; i++) { - if (device->kernels[i]->hardware) + if (device->kernels[i]) { - gckHARDWARE Hardware = device->kernels[i]->hardware; - gctBOOL powerManagement = Hardware->options.powerManagement; - - switch(statesStored) + if (device->kernels[i]->hardware) { - case gcvPOWER_OFF: - state = gcvPOWER_OFF_BROADCAST; - break; - case gcvPOWER_IDLE: - state = gcvPOWER_IDLE_BROADCAST; - break; - case gcvPOWER_SUSPEND: - state = gcvPOWER_SUSPEND_BROADCAST; - break; - case gcvPOWER_ON: - state = gcvPOWER_ON_AUTO; - break; - default: - state = statesStored; - break; - } - Hardware->waitCount = 200; - - if (powerManagement) - { - gcmkONERROR(gckHARDWARE_EnablePowerManagement( - Hardware, gcvTRUE - )); - } - - gcmkONERROR(gckHARDWARE_SetPowerState( - Hardware, state - )); - - load[i] = (hi_total_cycle_count[i] - hi_total_idle_cycle_count[i]) * 100 / hi_total_cycle_count[i]; len += fs_printf(ptr, "core : %d\n", i); - len += fs_printf(ptr + len, "load : %d%%\n",load[i]); + len += fs_printf(ptr + len, "load : %d%%\n",device->kernels[i]->cur_load); len += fs_printf(ptr + len, "\n"); + } } } - } -OnError: return len; } @@ -2419,6 +2329,154 @@ _StopPreemptThread( } #endif +/******************************************************************************\ +******************************* G2D Devfreq support START*********************** +\******************************************************************************/ + +static int gc_df_target(struct device * dev, unsigned long *freq, u32 flags) { + + int i = 0; + gctUINT32 _freq = 64; + gckHARDWARE hardware; + gckGALDEVICE device = galDevice; + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) { + dev_info(dev, "Failed to find opp for %lu Hz\n", *freq); + return PTR_ERR(opp); + } + dev_pm_opp_put(opp); + + switch (*freq) + { + case 396000000: + _freq = 64; + break; + case 198000000: + _freq = 32; + break; + case 99000000: + _freq = 16; + break; + case 49500000: + _freq = 8; + break; + default: + break; + } + + for(i = 0; i < gcvCORE_2D_MAX; i++) { + if(device->kernels[i]) { + hardware = device->kernels[i]->hardware; + if(hardware->clockState) { + gckHARDWARE_SetClock(hardware, i, _freq, _freq); + device->kernels[i]->cur_freq = *freq; + } + } + } + + return 0; + +} + +static int gc_df_status(struct device *dev, struct devfreq_dev_status *stat) { + gckGALDEVICE device = galDevice; + gckKERNEL kernel = _GetValidKernel(device); + gctUINT64 on = 0; + gctUINT64 off = 0; + gctUINT64 idle = 0; + gctUINT64 suspend = 0; + int i = 0; + + gckHARDWARE_QueryStateTimer(kernel->hardware, &on, &off, &idle, &suspend); + for(i = 0; i < gcvCORE_2D_MAX; i++) { + if(device->kernels[i]) { + stat->current_frequency = device->kernels[i]->cur_freq; + stat->busy_time = on - device->kernels[i]->cur_on; + stat->total_time = on - device->kernels[i]->cur_on + + idle - device->kernels[i]->cur_idel + + suspend - device->kernels[i]->cur_suspend + + off - device->kernels[i]->cur_off; + device->kernels[i]->cur_load = stat->busy_time * 100 / stat->total_time; + device->kernels[i]->cur_on = on; + device->kernels[i]->cur_idel = idle; + device->kernels[i]->cur_suspend = suspend; + device->kernels[i]->cur_off = off; + } + } + + return 0; + +} + +static int gc_df_get_cur_freq(struct device *dev, unsigned long *freq) { + int i = 0; + gckGALDEVICE device = galDevice; + for(i = 0; i < gcvCORE_2D_MAX; i++) { + if(device->kernels[i]) { + *freq = device->kernels[i]->cur_freq; + } + } + + return 0; +} + +struct devfreq_simple_ondemand_data galcore_gov_data; + +static struct devfreq_dev_profile gc_df_profile = { + .polling_ms = 500, + .target = gc_df_target, + .get_dev_status = gc_df_status, + .get_cur_freq = gc_df_get_cur_freq, +}; + +gceSTATUS +g2d_EnableDevfreq(void) { + gceSTATUS status = gcvSTATUS_OK; + struct clk *new_clk; + int ret = 0; + gckGALDEVICE device = galDevice; + int i = 0; + + ret = dev_pm_opp_of_add_table(galcore_device); + if(ret) { + gcmkPRINT("add table failed \n"); + } + + new_clk = devm_clk_get(galcore_device, "cclk"); + clk_set_rate(new_clk, 792000000); + for(i = 0; i < gcvCORE_2D_MAX; i++) { + if(device->kernels[i]) { + device->kernels[i]->cur_freq = clk_get_rate(new_clk) / 2; + device->kernels[i]->cur_idel = 0; + device->kernels[i]->cur_off = 0; + device->kernels[i]->cur_on = 0; + device->kernels[i]->cur_suspend = 0; + device->kernels[i]->cur_load = 0; + gc_df_profile.initial_freq = device->kernels[i]->cur_freq; + } + + } + + galcore_gov_data.upthreshold = 80; + galcore_gov_data.downdifferential = 5; + + galDevice->g2d_devfreq = devm_devfreq_add_device(galcore_device, &gc_df_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND, &galcore_gov_data); + + if(IS_ERR(galDevice->g2d_devfreq)) { + gcmkPRINT("Errot: init devgreq %lx\n", (unsigned long)galcore_device); + status = gcvSTATUS_NOT_SUPPORTED; + } + + return status; +} + +/******************************************************************************\ +******************************* G2D Devfreq support END ************************ +\******************************************************************************/ + + /******************************************************************************* ** ** gckGALDEVICE_Construct @@ -2788,6 +2846,8 @@ gckGALDEVICE_Construct( /* Return pointer to the device. */ *Device = galDevice = device; + g2d_EnableDevfreq(); + devfreq_suspend_device(galDevice->g2d_devfreq); OnError: if (gcmIS_ERROR(status)) @@ -3064,6 +3124,7 @@ gckGALDEVICE_Destroy( /* Free the device. */ kfree(Device); + } gcmkFOOTER_NO(); @@ -3218,5 +3279,4 @@ gckGALDEVICE_Stop( OnError: gcmkFOOTER(); return status; -} - +} \ No newline at end of file diff --git a/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h b/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h index d3aa5fdecc38..28e287b932de 100644 --- a/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h +++ b/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h @@ -150,6 +150,11 @@ typedef struct _gckGALDEVICE /* gctsOs object for trust application. */ gctaOS taos; + /*Number of devices opened*/ + atomic_t openNum; + /*object of devfreq add device*/ + struct devfreq *g2d_devfreq; + #if gcdENABLE_DRM void * drm; #endif diff --git a/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c b/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c index 5eab55ae1051..517b4d55c047 100644 --- a/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c +++ b/drivers/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c @@ -62,7 +62,8 @@ #include "gc_hal_driver.h" #include - +#include +#include /* Zone used for header/footer. */ #define _GC_OBJ_ZONE gcvZONE_DRIVER @@ -821,6 +822,8 @@ static int drv_open( filp->private_data = data; /* Success. */ + atomic_inc_return(&galDevice->openNum); + devfreq_resume_device(galDevice->g2d_devfreq); gcmkFOOTER_NO(); return 0; } @@ -887,6 +890,9 @@ static int drv_release( kfree(data); filp->private_data = NULL; + if(atomic_dec_return(&galDevice->openNum) == 0) { + devfreq_suspend_device(galDevice->g2d_devfreq); + } /* Success. */ ret = 0; @@ -1523,6 +1529,7 @@ static int gpu_suspend(struct platform_device *dev, pm_message_t state) status = gckHARDWARE_SetPowerState(device->kernels[i]->hardware, gcvPOWER_OFF); } + if (gcmIS_ERROR(status)) { return -1; diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c index dfef1925f03f..a35d56cd6bbe 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -648,7 +648,9 @@ static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev) * Anytime TX_ABRT is set, the contents of the tx/rx * buffers are flushed. Make sure to skip them. */ - regmap_write(dev->map, DW_IC_INTR_MASK, 0); + if (!dev->dw_i2c_enable_dma) { + regmap_write(dev->map, DW_IC_INTR_MASK, 0); + } goto tx_aborted; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-light.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-light.c index fe31a27605e6..19ac4b4d23f6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-light.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-light.c @@ -36,12 +36,14 @@ /* clock divider for speed */ #define GMAC_CLKDIV_125M (GMAC_CLK_PLLOUT_250M / GMAC_GMII_RGMII_RATE) #define GMAC_CLKDIV_25M (GMAC_CLK_PLLOUT_250M / GMAC_MII_RATE) +#define GMAC_PTP_CLK_RATE 50000000 //50MHz struct thead_dwmac_ops { void (*set_clk_source)(struct plat_stmmacenet_data *plat_dat); void (*set_clk_pll)(struct plat_stmmacenet_data *plat_dat); void (*set_clk_div)(struct plat_stmmacenet_data *plat_dat, unsigned int speed); void (*enable_clk)(struct plat_stmmacenet_data *plat_dat); + void (*set_ptp_div)(struct plat_stmmacenet_data *plat_dat,unsigned int ptp_clk_rate); }; struct thead_dwmac_priv_data { @@ -352,6 +354,35 @@ static void thead_dwmac_light_set_clk_div(struct plat_stmmacenet_data *plat_dat, } } +static void thead_dwmac_light_set_ptp_clk_div(struct plat_stmmacenet_data *plat_dat,unsigned int ptp_clk_rate) +{ + unsigned int div; + unsigned int reg; + struct thead_dwmac_priv_data *thead_plat_dat = plat_dat->bsp_priv; + void __iomem *gmac_clk_reg = thead_plat_dat->gmac_clk_reg; + unsigned long src_freq = thead_plat_dat->gmac_pll_clk_freq; + + if (gmac_clk_reg == NULL) + return; + if(!ptp_clk_rate || !src_freq) + { + pr_warn("invalid gmac pll freq %lu or ptp_clk_rate %d\n", src_freq,ptp_clk_rate); + return; + } + /* disable clk_div */ + reg = readl(gmac_clk_reg + GMAC_CLK_CFG5); + reg &= ~BIT(31); + writel(reg, gmac_clk_reg + GMAC_CLK_CFG5); + + div = src_freq / ptp_clk_rate; + writel(div,gmac_clk_reg + GMAC_CLK_CFG5); + + /* enable clk_div */ + reg = div | BIT(31); + writel(reg, gmac_clk_reg + GMAC_CLK_CFG5); + return ; +} + /* enable gmac clock */ static void thead_dwmac_ice_enable_clk(struct plat_stmmacenet_data *plat_dat) { @@ -659,6 +690,8 @@ int thead_dwmac_clk_init(struct platform_device *pdev, void *bsp_priv) if (thead_plat_dat->ops->enable_clk) thead_plat_dat->ops->enable_clk(plat_dat); + if (thead_plat_dat->ops->set_ptp_div) + thead_plat_dat->ops->set_ptp_div(plat_dat,plat_dat->clk_ptp_rate); //thead_dwmac_dump_priv_reg(pdev,bsp_priv); return ret; } @@ -770,6 +803,8 @@ static int thead_dwmac_probe(struct platform_device *pdev) if (ret) goto err_remove_config_dt; + plat_dat->clk_ptp_rate = GMAC_PTP_CLK_RATE; + ret = thead_dwmac_clk_enable(pdev, plat_dat->bsp_priv); if (ret) goto err_remove_config_dt; @@ -932,6 +967,7 @@ static struct thead_dwmac_ops thead_ice_dwmac_data = { static struct thead_dwmac_ops thead_light_dwmac_data = { .set_clk_div = thead_dwmac_light_set_clk_div, .enable_clk = thead_dwmac_light_enable_clk, + .set_ptp_div = thead_dwmac_light_set_ptp_clk_div, }; static const struct of_device_id thead_dwmac_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index c875310a2ffc..7c77f0bbabf7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -738,6 +738,7 @@ int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) struct timespec64 now; u32 sec_inc = 0; u64 temp = 0; + int ret; if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) return -EOPNOTSUPP; @@ -761,14 +762,26 @@ int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) */ temp = (u64)(temp << 32); priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); - stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); - + ret = stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); + if(ret < 0) + { + netdev_warn(priv->dev, + "failed to config PTP addend: %pe\n", + ERR_PTR(ret)); + return ret; + } /* initialize system time */ ktime_get_real_ts64(&now); /* lower 32 bits of tv_sec are safe until y2106 */ - stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); - + ret = stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); + if(ret < 0) + { + netdev_warn(priv->dev, + "failed to init systime: %pe\n", + ERR_PTR(ret)); + return ret; + } return 0; } EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); @@ -3840,10 +3853,10 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) if(likely(!buf->rx_skbuff)){ len = stmmac_get_rx_buf_frsize(priv); - skb = netdev_alloc_skb(priv->dev, len); + skb = __netdev_alloc_skb(priv->dev, len, gfp); if (!skb){ //priv->dev->stats.rx_dropped += (1ul<<32); - netdev_err(priv->dev, "%s: dalloc_skb failed,dirty ring %d :\n", __func__,dirty); + netdev_dbg(priv->dev, "%s: dalloc_skb failed,dirty ring %d :\n", __func__,dirty); break; } if(stmmac_get_skb_dma_addr(priv,skb,&buf->addr) < 0){ diff --git a/drivers/net/wireless/rtl8723ds/Makefile b/drivers/net/wireless/rtl8723ds/Makefile index cc3a27421d74..c02fc4b2f3cd 100644 --- a/drivers/net/wireless/rtl8723ds/Makefile +++ b/drivers/net/wireless/rtl8723ds/Makefile @@ -129,7 +129,7 @@ CONFIG_PNO_SUPPORT = n CONFIG_PNO_SET_DEBUG = n CONFIG_AP_WOWLAN = n ######### Notify SDIO Host Keep Power During Syspend ########## -CONFIG_RTW_SDIO_PM_KEEP_POWER = y +CONFIG_RTW_SDIO_PM_KEEP_POWER = n ###################### MP HW TX MODE FOR VHT ####################### CONFIG_MP_VHT_HW_TX_MODE = n ###################### ROAMING ##################################### @@ -1189,9 +1189,9 @@ EXTRA_CFLAGS += -DRTW_SUSPEND_TYPE=$(CONFIG_SUSPEND_TYPE) ifeq ($(CONFIG_WOW_STA_MIX), y) EXTRA_CFLAGS += -DRTW_WOW_STA_MIX endif -ifeq ($(CONFIG_SDIO_HCI), y) -EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER -endif +# ifeq ($(CONFIG_SDIO_HCI), y) +# EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER +# endif endif ifeq ($(CONFIG_AP_WOWLAN), y) @@ -1199,9 +1199,9 @@ EXTRA_CFLAGS += -DCONFIG_AP_WOWLAN ifeq ($(CONFIG_AP_MODE), n) EXTRA_CFLAGS += -DCONFIG_AP_MODE endif -ifeq ($(CONFIG_SDIO_HCI), y) -EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER -endif +# ifeq ($(CONFIG_SDIO_HCI), y) +# EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER +# endif endif ifeq ($(CONFIG_LAYER2_ROAMING), y) diff --git a/drivers/net/wireless/rtl8723ds/os_dep/linux/os_intfs.c b/drivers/net/wireless/rtl8723ds/os_dep/linux/os_intfs.c index fe006b57f102..958e6a455a49 100644 --- a/drivers/net/wireless/rtl8723ds/os_dep/linux/os_intfs.c +++ b/drivers/net/wireless/rtl8723ds/os_dep/linux/os_intfs.c @@ -5162,7 +5162,7 @@ int rtw_suspend_normal(_adapter *padapter) if ((rtw_hal_check_ips_status(padapter) == _TRUE) || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) - RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__); + RTW_PRINT("%s: driver in IPS!!!\n", __FUNCTION__); #ifdef CONFIG_CONCURRENT_MODE diff --git a/drivers/soc/thead/pm-light.c b/drivers/soc/thead/pm-light.c index ba89975c8cbc..29acb9b16ee8 100644 --- a/drivers/soc/thead/pm-light.c +++ b/drivers/soc/thead/pm-light.c @@ -90,7 +90,7 @@ static int light_suspend_prepare(void) int ret; aon_pm_ctrl->suspend_flag = true; struct light_aon_msg_pm_ctrl msg = {0}; - ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_REQUIRE_STR, false); + ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_REQUIRE_STR, true); if (ret) { pr_err("[%s,%d]failed to initiate Suspend to Ram process to AON subsystem\n",__func__, __LINE__); return ret; @@ -98,9 +98,15 @@ static int light_suspend_prepare(void) return 0; } -static void light_resume_wake(void) +static void light_resume_finish(void) { + int ret; aon_pm_ctrl->suspend_flag = false; + struct light_aon_msg_pm_ctrl msg = {0}; + ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_RESUME_STR, true); + if (ret) { + pr_err("[%s,%d]failed to clear lowpower state\n",__func__, __LINE__); + } } static int thead_cpuhp_offline(unsigned int cpu) @@ -111,7 +117,7 @@ static int thead_cpuhp_offline(unsigned int cpu) struct light_aon_msg_pm_ctrl msg = {0}; msg.rpc.cpu_info.cpu_id = (u16)cpu; msg.rpc.cpu_info.status = 0; - ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_CPUHP, false); + ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_CPUHP, true); if (ret) { pr_info("failed to notify aon subsys with cpuhp...%08x\n", ret); return ret; @@ -128,7 +134,7 @@ static int thead_cpuhp_online(unsigned int cpu) struct light_aon_msg_pm_ctrl msg = {0}; msg.rpc.cpu_info.cpu_id = (u16)cpu; msg.rpc.cpu_info.status = 1; - ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_CPUHP, false); + ret = light_require_state_pm_ctrl(&msg, LIGHT_AON_MISC_FUNC_CPUHP, true); if (ret) { pr_info("[%s,%d]failed to bring up aon subsys with cpuhp...%08x\n", __func__, __LINE__, ret); return ret; @@ -146,7 +152,37 @@ static const struct platform_suspend_ops light_suspend_ops = { .enter = light_suspend_enter, .valid = suspend_valid_only_mem, .prepare_late = light_suspend_prepare, - .wake = light_resume_wake, + .finish = light_resume_finish, +}; + +#define C906_RESET_REG 0xfffff4403c + +static void boot_audio(void) { + uint64_t *v_addr = ioremap(C906_RESET_REG, 4); + if(!v_addr) { + printk("io remap failed\r\n"); + return; + } + writel(0x37, (volatile void *)v_addr); + writel(0x3f, (volatile void *)v_addr); + iounmap(C906_RESET_REG); +} + +//this is called after dpm_suspend_end,before snapshot +static int light_hibernation_pre_snapshot(void) +{ + return 0; +} +//called before dpm_resume_start after slave cores up +static void light_hibernation_platform_finish(void) +{ + boot_audio(); + return; +} + +static const struct platform_hibernation_ops light_hibernation_allmode_ops = { + .pre_snapshot = light_hibernation_pre_snapshot, + .finish = light_hibernation_platform_finish, }; static int light_pm_probe(struct platform_device *pdev) @@ -161,13 +197,15 @@ static int light_pm_probe(struct platform_device *pdev) aon_pm_ctrl = pm_ctrl; ret = light_aon_get_handle(&(aon_pm_ctrl->ipc_handle)); - if (ret == -EPROBE_DEFER) { - pr_err("[%s, %d]failed to register ipc_handler.\n",__func__, __LINE__); + if (ret == -EPROBE_DEFER) return ret; - } suspend_set_ops(&light_suspend_ops); + /*only save BSS and data section for audio*/ + hibernate_register_nosave_region(__phys_to_pfn(0x32000000), __phys_to_pfn(0x36600000)); + hibernation_set_allmode_ops(&light_hibernation_allmode_ops); + ret = cpuhp_setup_state_nocalls(CPUHP_BP_PREPARE_DYN, "soc/thead:online", thead_cpuhp_online, thead_cpuhp_offline); diff --git a/drivers/tee/optee/call.c b/drivers/tee/optee/call.c index f68399bb79f2..b4ebe669dc4a 100644 --- a/drivers/tee/optee/call.c +++ b/drivers/tee/optee/call.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,8 @@ struct optee_call_waiter { struct completion c; }; +struct kref sess_refcount = KREF_INIT(1); + static void optee_cq_wait_init(struct optee_call_queue *cq, struct optee_call_waiter *w) { @@ -51,7 +54,12 @@ static void optee_cq_wait_init(struct optee_call_queue *cq, static void optee_cq_wait_for_completion(struct optee_call_queue *cq, struct optee_call_waiter *w) { - wait_for_completion(&w->c); + /* + * wait_for_completion but allow hibernation/suspend + * to freeze the waiting task + */ + while (wait_for_completion_interruptible(&w->c)) + try_to_freeze(); mutex_lock(&cq->mutex); @@ -273,6 +281,7 @@ int optee_open_session(struct tee_context *ctx, mutex_lock(&ctxdata->mutex); list_add(&sess->list_node, &ctxdata->sess_list); mutex_unlock(&ctxdata->mutex); + kref_get(&sess_refcount); } else { kfree(sess); } @@ -293,6 +302,15 @@ out: return rc; } +static void session_release(struct kref *ref) +{ +} + +void session_put(void) +{ + kref_put(&sess_refcount, session_release); +} + int optee_close_session(struct tee_context *ctx, u32 session) { struct optee_context_data *ctxdata = ctx->data; @@ -320,6 +338,9 @@ int optee_close_session(struct tee_context *ctx, u32 session) optee_do_call_with_arg(ctx, msg_parg); tee_shm_free(shm); + + session_put(); + return 0; } diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 8d1498fa028b..b19831cda8fa 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -265,6 +266,8 @@ static int optee_open(struct tee_context *ctx) return 0; } +extern void session_put(void); + static void optee_release(struct tee_context *ctx) { struct optee_context_data *ctxdata = ctx->data; @@ -301,6 +304,7 @@ static void optee_release(struct tee_context *ctx) arg->cmd = OPTEE_MSG_CMD_CLOSE_SESSION; arg->session = sess->session_id; optee_do_call_with_arg(ctx, parg); + session_put(); } kfree(sess); } @@ -606,6 +610,8 @@ static optee_invoke_fn *get_invoke_func(struct device *dev) return ERR_PTR(-EINVAL); } +extern struct kref sess_refcount; + static int optee_remove(struct platform_device *pdev) { struct optee *optee = platform_get_drvdata(pdev); @@ -763,6 +769,47 @@ err: return rc; } +#ifdef CONFIG_PM +#ifdef CONFIG_SUSPEND +static int __maybe_unused tee_driver_suspend(struct device *dev) +{ + int ret = 0; + unsigned int ref_count; + + if (pm_suspend_target_state == PM_SUSPEND_MEM) { + pr_info("STR mode suspend in\r\n"); + return 0; + } else { + ref_count = kref_read(&sess_refcount); + if (ref_count > 1) { + pr_info("tee_driver_suspend failed[%d] \r\n", ref_count); + ret = -1; + } else { + pr_info("tee_driver_suspend success[%d] \r\n", ref_count); + ret = 0; + } + } + + return ret; +} + +static int __maybe_unused tee_driver_resume(struct device *dev) +{ + + int ret = 0; + + return ret; +} +#else +#define tee_driver_suspend NULL +#define tee_driver_resume NULL +#endif + +static const struct dev_pm_ops tee_driver_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(tee_driver_suspend, tee_driver_resume) +}; +#endif + static const struct of_device_id optee_dt_match[] = { { .compatible = "linaro,optee-tz" }, {}, @@ -775,10 +822,15 @@ static struct platform_driver optee_driver = { .driver = { .name = "optee", .of_match_table = optee_dt_match, +#ifdef CONFIG_PM + .pm = &tee_driver_pm_ops, +#endif }, }; module_platform_driver(optee_driver); + + MODULE_AUTHOR("Linaro"); MODULE_DESCRIPTION("OP-TEE driver"); MODULE_VERSION("1.0"); diff --git a/drivers/tee/optee/rpc.c b/drivers/tee/optee/rpc.c index ccbcf2c037cb..15a11fc865d7 100644 --- a/drivers/tee/optee/rpc.c +++ b/drivers/tee/optee/rpc.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -46,7 +47,6 @@ static void handle_rpc_func_cmd_get_time(struct optee_msg_arg *arg) ktime_get_real_ts64(&ts); arg->params[0].u.value.a = ts.tv_sec; arg->params[0].u.value.b = ts.tv_nsec; - arg->ret = TEEC_SUCCESS; return; bad: @@ -171,7 +171,12 @@ static void wq_sleep(struct optee_wait_queue *wq, u32 key) struct wq_entry *w = wq_entry_get(wq, key); if (w) { - wait_for_completion(&w->c); + /* + * wait_for_completion but allow hibernation/suspend + * to freeze the waiting task + */ + while (wait_for_completion_interruptible(&w->c)) + try_to_freeze(); mutex_lock(&wq->mu); list_del(&w->link); mutex_unlock(&wq->mu); diff --git a/drivers/tee/optee/supp.c b/drivers/tee/optee/supp.c index 322a543b8c27..13b706f9cfdf 100644 --- a/drivers/tee/optee/supp.c +++ b/drivers/tee/optee/supp.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, Linaro Limited */ #include +#include #include #include #include "optee_private.h" @@ -141,6 +142,7 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params, req->ret = TEEC_ERROR_COMMUNICATION; break; } + try_to_freeze(); } ret = req->ret; diff --git a/include/dt-bindings/clock/light-vpsys.h b/include/dt-bindings/clock/light-vpsys.h index 7ab41376e080..70d18bbad676 100644 --- a/include/dt-bindings/clock/light-vpsys.h +++ b/include/dt-bindings/clock/light-vpsys.h @@ -19,7 +19,8 @@ #define LIGHT_VPSYS_VENC_PCLK 10 #define LIGHT_VPSYS_VENC_ACLK 11 #define LIGHT_VPSYS_G2D_CCLK_DIV 12 -#define LIGHT_VPSYS_CLK_END 13 +#define LIGHT_VPSYS_DEC_CCLK_DIV 13 +#define LIGHT_VPSYS_CLK_END 14 #endif diff --git a/include/linux/firmware/thead/ipc.h b/include/linux/firmware/thead/ipc.h index 231e943262a8..dfda60e76725 100644 --- a/include/linux/firmware/thead/ipc.h +++ b/include/linux/firmware/thead/ipc.h @@ -38,8 +38,9 @@ enum light_aon_misc_func { LIGHT_AON_MISC_FUNC_AON_WDT_OFF = 11, LIGHT_AON_MISC_FUNC_AON_RESERVE_MEM = 12, LIGHT_AON_MISC_FUNC_REQUIRE_STR = 13, - LIGHT_AON_MISC_FUNC_REQUIRE_STD = 14, - LIGHT_AON_MISC_FUNC_CPUHP = 15, + LIGHT_AON_MISC_FUNC_RESUME_STR = 14, + LIGHT_AON_MISC_FUNC_REQUIRE_STD = 15, + LIGHT_AON_MISC_FUNC_CPUHP = 16, }; enum light_aon_pm_func { diff --git a/include/linux/mm.h b/include/linux/mm.h index ff79e257a861..57cb33576917 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -3120,16 +3120,6 @@ static inline bool debug_pagealloc_enabled_static(void) #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_ARCH_HAS_SET_DIRECT_MAP) extern void __kernel_map_pages(struct page *page, int numpages, int enable); -/* - * When called in DEBUG_PAGEALLOC context, the call should most likely be - * guarded by debug_pagealloc_enabled() or debug_pagealloc_enabled_static() - */ -static inline void -kernel_map_pages(struct page *page, int numpages, int enable) -{ - __kernel_map_pages(page, numpages, enable); -} - static inline void debug_pagealloc_map_pages(struct page *page, int numpages) { if (debug_pagealloc_enabled_static()) @@ -3146,8 +3136,6 @@ static inline void debug_pagealloc_unmap_pages(struct page *page, int numpages) extern bool kernel_page_present(struct page *page); #endif /* CONFIG_HIBERNATION */ #else /* CONFIG_DEBUG_PAGEALLOC || CONFIG_ARCH_HAS_SET_DIRECT_MAP */ -static inline void -kernel_map_pages(struct page *page, int numpages, int enable) {} static inline void debug_pagealloc_map_pages(struct page *page, int numpages) {} static inline void debug_pagealloc_unmap_pages(struct page *page, int numpages) {} #ifdef CONFIG_HIBERNATION diff --git a/include/linux/suspend.h b/include/linux/suspend.h index 27321d5d01df..8905ed0c194a 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -445,6 +445,10 @@ extern unsigned long get_safe_page(gfp_t gfp_mask); extern asmlinkage int swsusp_arch_suspend(void); extern asmlinkage int swsusp_arch_resume(void); +extern int hibernate_register_nosave_region(unsigned long start_pfn, unsigned long end_pfn); +extern int hibernate_remove_nosave_region(unsigned long start_pfn, unsigned long end_pfn); + +extern void hibernation_set_allmode_ops(const struct platform_hibernation_ops *ops); extern void hibernation_set_ops(const struct platform_hibernation_ops *ops); extern int hibernate(void); extern bool system_entering_hibernation(void); @@ -460,6 +464,13 @@ static inline int swsusp_page_is_forbidden(struct page *p) { return 0; } static inline void swsusp_set_page_free(struct page *p) {} static inline void swsusp_unset_page_free(struct page *p) {} +static inline int hibernate_register_nosave_region(unsigned long start_pfn, unsigned long end_pfn){ + return 0; +} +static inline int hibernate_remove_nosave_region(unsigned long start_pfn, unsigned long end_pfn){ + return 0; +} +static inline void hibernation_set_allmode_ops(const struct platform_hibernation_ops *ops) {} static inline void hibernation_set_ops(const struct platform_hibernation_ops *ops) {} static inline int hibernate(void) { return -ENOSYS; } static inline bool system_entering_hibernation(void) { return false; } diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c index 731aca37637d..27f97ffd179f 100644 --- a/kernel/power/hibernate.c +++ b/kernel/power/hibernate.c @@ -66,7 +66,8 @@ static int hibernation_mode = HIBERNATION_SHUTDOWN; bool freezer_test_done; static const struct platform_hibernation_ops *hibernation_ops; - +/* for not only in HIBERNATION_PLATFORM mode calling ops*/ +static const struct platform_hibernation_ops *hibernation_all_mode_ops; static atomic_t hibernate_atomic = ATOMIC_INIT(1); bool hibernate_acquire(void) @@ -107,6 +108,27 @@ void hibernation_set_ops(const struct platform_hibernation_ops *ops) } EXPORT_SYMBOL_GPL(hibernation_set_ops); +/** + * hibernation_set_allmode_ops - Set the global hibernate operations for all mode(reboot/shutdown...). + * @ops: Hibernation operations to use in subsequent hibernation transitions. + * Note: This diffs from hibernation_set_ops,hibernation_set_allmode_ops is for not only + * HIBERNATION_PLATFORM + */ +void hibernation_set_allmode_ops(const struct platform_hibernation_ops *ops) +{ + if( !ops && !ops->begin && !ops->end && !ops->pre_snapshot + && !ops->prepare && !ops->finish && !ops->enter && !ops->pre_restore + && !ops->restore_cleanup && !ops->leave ) { + WARN_ON(1); + return; + } + lock_system_sleep(); + hibernation_all_mode_ops = ops; + + unlock_system_sleep(); +} +EXPORT_SYMBOL_GPL(hibernation_set_allmode_ops); + static bool entering_platform_hibernation; bool system_entering_hibernation(void) @@ -140,6 +162,9 @@ static int hibernation_test(int level) { return 0; } */ static int platform_begin(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->begin) + return hibernation_all_mode_ops->begin(PMSG_FREEZE); + return (platform_mode && hibernation_ops) ? hibernation_ops->begin(PMSG_FREEZE) : 0; } @@ -150,6 +175,10 @@ static int platform_begin(int platform_mode) */ static void platform_end(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->end) { + hibernation_all_mode_ops->end(); + return; + } if (platform_mode && hibernation_ops) hibernation_ops->end(); } @@ -164,6 +193,9 @@ static void platform_end(int platform_mode) static int platform_pre_snapshot(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->pre_snapshot) + return hibernation_all_mode_ops->pre_snapshot(); + return (platform_mode && hibernation_ops) ? hibernation_ops->pre_snapshot() : 0; } @@ -179,6 +211,10 @@ static int platform_pre_snapshot(int platform_mode) */ static void platform_leave(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->leave) { + hibernation_all_mode_ops->leave(); + return; + } if (platform_mode && hibernation_ops) hibernation_ops->leave(); } @@ -194,6 +230,10 @@ static void platform_leave(int platform_mode) */ static void platform_finish(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->finish) { + hibernation_all_mode_ops->finish(); + return; + } if (platform_mode && hibernation_ops) hibernation_ops->finish(); } @@ -210,6 +250,10 @@ static void platform_finish(int platform_mode) */ static int platform_pre_restore(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->pre_restore) { + return hibernation_all_mode_ops->pre_restore(); + } + return (platform_mode && hibernation_ops) ? hibernation_ops->pre_restore() : 0; } @@ -227,6 +271,11 @@ static int platform_pre_restore(int platform_mode) */ static void platform_restore_cleanup(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->restore_cleanup) { + hibernation_all_mode_ops->restore_cleanup(); + return; + } + if (platform_mode && hibernation_ops) hibernation_ops->restore_cleanup(); } @@ -237,6 +286,11 @@ static void platform_restore_cleanup(int platform_mode) */ static void platform_recover(int platform_mode) { + if(hibernation_all_mode_ops && hibernation_all_mode_ops->recover) { + hibernation_all_mode_ops->recover(); + return; + } + if (platform_mode && hibernation_ops && hibernation_ops->recover) hibernation_ops->recover(); } @@ -688,10 +742,20 @@ static int load_image_and_restore(void) goto Unlock; error = swsusp_read(&flags); - swsusp_close(FMODE_READ | FMODE_EXCL); - if (!error) - error = hibernation_restore(flags & SF_PLATFORM_MODE); - + if (error == -ENODATA) { //if is crc error of image ,reboot retry + if(0 == swsusp_mark_sign_retry()) { //can retry + pr_warn("WARN:Image load error,reboot retry...\n"); + swsusp_close(FMODE_READ | FMODE_EXCL); + kernel_restart(NULL); + } + else //reach the retry max times + swsusp_close(FMODE_READ | FMODE_EXCL); + } + else { + swsusp_close(FMODE_READ | FMODE_EXCL); + if (!error) + error = hibernation_restore(flags & SF_PLATFORM_MODE); + } pr_err("Failed to load image, recovering.\n"); swsusp_free(); free_basic_memory_bitmaps(); diff --git a/kernel/power/power.h b/kernel/power/power.h index 778bf431ec02..3306ba2f0fa8 100644 --- a/kernel/power/power.h +++ b/kernel/power/power.h @@ -175,6 +175,7 @@ extern void swsusp_free(void); extern int swsusp_read(unsigned int *flags_p); extern int swsusp_write(unsigned int flags); extern void swsusp_close(fmode_t); +extern int swsusp_mark_sign_retry(void); #ifdef CONFIG_SUSPEND extern int swsusp_unmark(void); #endif diff --git a/kernel/power/snapshot.c b/kernel/power/snapshot.c index 6a71543c8523..68d448eb87b5 100644 --- a/kernel/power/snapshot.c +++ b/kernel/power/snapshot.c @@ -76,6 +76,40 @@ static inline void hibernate_restore_protect_page(void *page_address) {} static inline void hibernate_restore_unprotect_page(void *page_address) {} #endif /* CONFIG_STRICT_KERNEL_RWX && CONFIG_ARCH_HAS_SET_MEMORY */ + +/* + * The calls to set_direct_map_*() should not fail because remapping a page + * here means that we only update protection bits in an existing PTE. + * It is still worth to have a warning here if something changes and this + * will no longer be the case. + */ +static inline void hibernate_map_page(struct page *page) +{ + if (IS_ENABLED(CONFIG_ARCH_HAS_SET_DIRECT_MAP)) { + int ret = set_direct_map_default_noflush(page); + + if (ret) + pr_warn_once("Failed to remap page\n"); + } else { + debug_pagealloc_map_pages(page, 1); + } +} + +static inline void hibernate_unmap_page(struct page *page) +{ + if (IS_ENABLED(CONFIG_ARCH_HAS_SET_DIRECT_MAP)) { + unsigned long addr = (unsigned long)page_address(page); + int ret = set_direct_map_invalid_noflush(page); + + if (ret) + pr_warn_once("Failed to remap page\n"); + + flush_tlb_kernel_range(addr, addr + PAGE_SIZE); + } else { + debug_pagealloc_unmap_pages(page, 1); + } +} + static int swsusp_page_is_free(struct page *); static void swsusp_set_page_forbidden(struct page *); static void swsusp_unset_page_forbidden(struct page *); @@ -909,6 +943,7 @@ struct nosave_region { }; static LIST_HEAD(nosave_regions); +static DEFINE_MUTEX(nosave_regions_list_lock); static void recycle_zone_bm_rtree(struct mem_zone_bm_rtree *zone) { @@ -975,6 +1010,87 @@ void __init register_nosave_region(unsigned long start_pfn, unsigned long end_pf ((unsigned long long) end_pfn << PAGE_SHIFT) - 1); } +/** + * hibernate_register_nosave_region - Register a region of unsaveable memory. + * + * Register a range of page frames the contents of which should not be saved + * during hibernation (To be used in the running driver code,before start hibernation). + */ +int hibernate_register_nosave_region(unsigned long start_pfn, unsigned long end_pfn) +{ + struct nosave_region *region; + + if (start_pfn >= end_pfn) + { + pr_warn(": start_pfn should smaller than end_pfn\n", __func__); + return -1; + } + region = kmalloc(sizeof(struct nosave_region), + GFP_KERNEL); + if (!region) + { + pr_err("%s: Failed to allocate %zu bytes\n", __func__, + sizeof(struct nosave_region)); + return -1; + } + region->start_pfn = start_pfn; + region->end_pfn = end_pfn; + mutex_lock(&nosave_regions_list_lock); + list_add_tail(®ion->list, &nosave_regions); + mutex_unlock(&nosave_regions_list_lock); + Report: + pr_info("Registered nosave memory: [mem %#010llx-%#010llx]\n", + (unsigned long long) start_pfn << PAGE_SHIFT, + ((unsigned long long) end_pfn << PAGE_SHIFT) - 1); + return 0; +} +EXPORT_SYMBOL_GPL(hibernate_register_nosave_region); + +/** + * hibernate_remove_nosave_region - UnRegister a region of unsaveable memory. + * + * Remove page frames of which regitstered as unsaveable memory berfore + * (To be used in the running driver code,before start hibernation). + */ +int hibernate_remove_nosave_region(unsigned long start_pfn, unsigned long end_pfn) +{ + struct nosave_region *region, *tmp; + int found = 0; + mutex_lock(&nosave_regions_list_lock); + if (list_empty(&nosave_regions)) + { + mutex_unlock(&nosave_regions_list_lock); + return 0; + } + + list_for_each_entry_safe(region, tmp, &nosave_regions, list) { + if(!region) { + break; + } + /*need to remove all,so not break found first one*/ + if((region->start_pfn == start_pfn) && (region->end_pfn == end_pfn)) { + list_del(®ion->list); + kfree(region); + found++; + pr_info("Unregistered nosave memory: [mem %#010llx-%#010llx]\n", + (unsigned long long) start_pfn << PAGE_SHIFT, + ((unsigned long long) end_pfn << PAGE_SHIFT) - 1); + } + } + mutex_unlock(&nosave_regions_list_lock); + + if(!found) { + pr_warn("Not find nosave memory: [mem %#010llx-%#010llx]\n", + (unsigned long long) start_pfn << PAGE_SHIFT, + ((unsigned long long) end_pfn << PAGE_SHIFT) - 1); + return -1; + } + if(found > 1) + pr_warn("More than one region find in nosave memory,actual find %d\n",found); + return 0; +} +EXPORT_SYMBOL_GPL(hibernate_remove_nosave_region); + /* * Set bits in this map correspond to the page frames the contents of which * should not be saved during the suspend. @@ -1287,6 +1403,20 @@ static struct page *saveable_page(struct zone *zone, unsigned long pfn) if (!pfn_valid(pfn)) return NULL; + /* For no-map reserved mem in Riscv pfn_valid() return true, + * but ARM64 no-map reserved mem pfn_valid() return flase + * (defined in arch/arm64/mm/init.c int pfn_valid(unsigned long pfn) + * like below code) + * ... + * return memblock_is_map_memory(addr); + * + * Thus,for Riscv add check memblock_is_map_memory too. + */ + #ifdef CONFIG_RISCV + if(!memblock_is_map_memory(__pfn_to_phys(pfn))) + return NULL; + #endif + page = pfn_to_online_page(pfn); if (!page || page_zone(page) != zone) return NULL; @@ -1356,9 +1486,9 @@ static void safe_copy_page(void *dst, struct page *s_page) if (kernel_page_present(s_page)) { do_copy_page(dst, page_address(s_page)); } else { - kernel_map_pages(s_page, 1, 1); + hibernate_map_page(s_page); do_copy_page(dst, page_address(s_page)); - kernel_map_pages(s_page, 1, 0); + hibernate_unmap_page(s_page); } } @@ -1412,7 +1542,7 @@ static void copy_data_pages(struct memory_bitmap *copy_bm, { struct zone *zone; unsigned long pfn; - + unsigned long pfn_pre = 0; for_each_populated_zone(zone) { unsigned long max_zone_pfn; @@ -1428,6 +1558,17 @@ static void copy_data_pages(struct memory_bitmap *copy_bm, pfn = memory_bm_next_pfn(orig_bm); if (unlikely(pfn == BM_END_OF_MAP)) break; + + /* show debug info,detail show copied pfn */ + if( (pfn_pre+1) != pfn) + { + if(pfn_pre != 0) + pm_pr_dbg(" end:[%lx]\n",pfn_pre); + pm_pr_dbg(" start:[%lx] %s \n",pfn, + kernel_page_present(pfn_to_page(pfn))? "present":"not-present"); + } + pfn_pre = pfn; + copy_data_page(memory_bm_next_pfn(copy_bm), pfn); } } diff --git a/kernel/power/swap.c b/kernel/power/swap.c index 25e7cb96bb88..642bc5f942bb 100644 --- a/kernel/power/swap.c +++ b/kernel/power/swap.c @@ -35,7 +35,7 @@ #include "power.h" #define HIBERNATE_SIG "S1SUSPEND" - +#define HIBERNATE_SIG2 "S1SUSPEN2" //sign for 2nd time load image /* * When reading an {un,}compressed image, we may restore pages in place, * in which case some architectures need these pages cleaning before they @@ -1489,7 +1489,8 @@ int swsusp_read(unsigned int *flags_p) struct swap_map_handle handle; struct snapshot_handle snapshot; struct swsusp_info *header; - + int retry = 1; +__retry: memset(&snapshot, 0, sizeof(struct snapshot_handle)); error = snapshot_write_next(&snapshot); if (error < (int)PAGE_SIZE) @@ -1506,6 +1507,12 @@ int swsusp_read(unsigned int *flags_p) load_image_lzo(&handle, &snapshot, header->pages - 1); } swap_reader_finish(&handle); + if(retry && (error == -ENODATA)) { + retry = 0; + pr_info("Image load retry for load error %d.\n",error); + goto __retry; + } + end: if (!error) pr_debug("Image successfully loaded\n"); @@ -1513,7 +1520,22 @@ end: pr_debug("Error %d resuming\n", error); return error; } - +bool swsusp_can_retry = true; +int swsusp_mark_sign_retry(void) +{ + int error = 0; + if (swsusp_can_retry) { + memcpy(swsusp_header->sig, HIBERNATE_SIG2, 10); + /* Write swap signature now */ + error = hib_submit_io(REQ_OP_WRITE, REQ_SYNC, + swsusp_resume_block, + swsusp_header, NULL); + if(error) + pr_info("Write swap sign failed %d\n",error); + return error; + } + return -EINVAL; +} /** * swsusp_check - Check for swsusp signature in the resume device */ @@ -1534,7 +1556,12 @@ int swsusp_check(void) if (error) goto put; - if (!memcmp(HIBERNATE_SIG, swsusp_header->sig, 10)) { + if (!memcmp(HIBERNATE_SIG, swsusp_header->sig, 10) || + !memcmp(HIBERNATE_SIG2, swsusp_header->sig, 10) ) { + if(!memcmp(HIBERNATE_SIG, swsusp_header->sig, 10)) + swsusp_can_retry = true; + else + swsusp_can_retry = false; memcpy(swsusp_header->sig, swsusp_header->orig_sig, 10); /* Reset swap signature now */ error = hib_submit_io(REQ_OP_WRITE, REQ_SYNC, diff --git a/sound/soc/codecs/es7210.c b/sound/soc/codecs/es7210.c index 8d5d3a2458a2..79bce2510a07 100644 --- a/sound/soc/codecs/es7210.c +++ b/sound/soc/codecs/es7210.c @@ -756,7 +756,7 @@ static int es7210_pcm_hw_params(struct snd_pcm_substream *substream, return 0; } -#define es7210_RATES SNDRV_PCM_RATE_8000_96000 +#define es7210_RATES SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_64000|SNDRV_PCM_RATE_88200 #define es7210_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE |\ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) @@ -778,7 +778,6 @@ static struct snd_soc_dai_driver es7210_dai0 = { .formats = es7210_FORMATS, }, .ops = &es7210_ops, - .symmetric_rates = 1, }; #endif #if ES7210_CHANNELS_MAX > 4 @@ -792,7 +791,6 @@ static struct snd_soc_dai_driver es7210_dai1 = { .formats = es7210_FORMATS, }, .ops = &es7210_ops, - .symmetric_rates = 1, }; #endif #if ES7210_CHANNELS_MAX > 8 @@ -806,7 +804,6 @@ static struct snd_soc_dai_driver es7210_dai2 = { .formats = es7210_FORMATS, }, .ops = &es7210_ops, - .symmetric_rates = 1, }; #endif #if ES7210_CHANNELS_MAX > 12 @@ -820,7 +817,6 @@ static struct snd_soc_dai_driver es7210_dai3 = { .formats = es7210_FORMATS, }, .ops = &es7210_ops, - .symmetric_rates = 1, }; #endif static struct snd_soc_dai_driver *es7210_dai[] = { diff --git a/sound/soc/codecs/es8156.c b/sound/soc/codecs/es8156.c index 97c4e7abe53e..58198fa494a0 100644 --- a/sound/soc/codecs/es8156.c +++ b/sound/soc/codecs/es8156.c @@ -473,7 +473,6 @@ static struct snd_soc_dai_driver es8156_dai = { .formats = es8156_FORMATS, }, .ops = &es8156_ops, - .symmetric_rates = 1, }; diff --git a/sound/soc/thead/light-i2s-8ch.c b/sound/soc/thead/light-i2s-8ch.c index 1849881139be..10a5c583bbed 100644 --- a/sound/soc/thead/light-i2s-8ch.c +++ b/sound/soc/thead/light-i2s-8ch.c @@ -50,7 +50,7 @@ #define LIGHT_I2S_DMABUF_SIZE (64 * 1024 * 10) -#define LIGHT_RATES SNDRV_PCM_RATE_8000_384000 +#define LIGHT_RATES SNDRV_PCM_RATE_8000_192000 #define LIGHT_FMTS (SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8) #define LIGHT_AUDIO_PAD_CONFIG(idx) (priv->cfg_off + ((idx-25) >> 1) * 4) @@ -194,7 +194,6 @@ static int light_i2s_8ch_dai_trigger(struct snd_pcm_substream *substream, int cm } break; case SNDRV_PCM_TRIGGER_SUSPEND: - regmap_read(priv->regmap, I2S_FUNCMODE, &priv->suspend_funcmode); if (tx) { dmaengine_pause(snd_dmaengine_pcm_get_chan(substream)); // work around for DMAC stop issue light_snd_txctrl(priv, 0); @@ -463,58 +462,6 @@ static const struct snd_soc_dai_ops light_hdmi_dai_ops = { static struct snd_soc_dai_driver light_i2s_8ch_soc_dai[] = { { .probe = light_i2s_8ch_dai_probe, - .name = "light-i2s-dai-8ch-sd0", - .playback = { - .rates = LIGHT_RATES, - .formats = LIGHT_FMTS, - .channels_min = 1, - .channels_max = 2, - }, - .capture = { - .rates = LIGHT_RATES, - .formats = LIGHT_FMTS, - .channels_min = 1, - .channels_max = 2, - }, - .ops = &light_i2s_8ch_dai_ops, - }, - { - .probe = light_i2s_8ch_dai_probe, - .name = "light-i2s-dai-8ch-sd1", - .playback = { - .rates = LIGHT_RATES, - .formats = LIGHT_FMTS, - .channels_min = 1, - .channels_max = 2, - }, - .capture = { - .rates = LIGHT_RATES, - .formats = LIGHT_FMTS, - .channels_min = 1, - .channels_max = 2, - }, - .ops = &light_i2s_8ch_dai_ops, - }, - { - .probe = light_i2s_8ch_dai_probe, - .name = "light-i2s-dai-8ch-sd2", - .playback = { - .rates = LIGHT_RATES, - .formats = LIGHT_FMTS, - .channels_min = 1, - .channels_max = 2, - }, - .capture = { - .rates = LIGHT_RATES, - .formats = LIGHT_FMTS, - .channels_min = 1, - .channels_max = 2, - }, - .ops = &light_i2s_8ch_dai_ops, - }, - { - .probe = light_i2s_8ch_dai_probe, - .name = "light-i2s-dai-8ch-sd3", .playback = { .rates = LIGHT_RATES, .formats = LIGHT_FMTS, @@ -635,10 +582,12 @@ static int light_i2s_8ch_suspend(struct device *dev) { struct light_i2s_priv *priv = dev_get_drvdata(dev); - if(!priv->regmap || priv->state == I2S_STATE_IDLE) { + if(!priv->regmap) { return 0; } + pm_runtime_get_sync(dev); + regmap_read(priv->regmap, I2S_DIV0_LEVEL, &priv->suspend_div0_level); regmap_read(priv->regmap, I2S_DIV3_LEVEL, &priv->suspend_div3_level); regmap_read(priv->regmap, I2S_IISCNF_IN, &priv->suspend_iiscnf_in); @@ -651,6 +600,7 @@ static int light_i2s_8ch_suspend(struct device *dev) regmap_read(priv->regmap, I2S_IMR, &priv->suspend_imr); regmap_read(priv->regmap, I2S_DMATDLR, &priv->suspend_dmatdlr); regmap_read(priv->regmap, I2S_DMARDLR, &priv->suspend_dmardlr); + regmap_read(priv->regmap, I2S_FUNCMODE, &priv->suspend_funcmode); regmap_read(priv->audio_cpr_regmap, CPR_PERI_DIV_SEL_REG, &priv->cpr_peri_div_sel); regmap_read(priv->audio_cpr_regmap, CPR_PERI_CTRL_REG, &priv->cpr_peri_ctrl); @@ -659,7 +609,7 @@ static int light_i2s_8ch_suspend(struct device *dev) regmap_update_bits(priv->audio_cpr_regmap, CPR_IP_RST_REG, CPR_I2S8CH_SRST_N_SEL_MSK, CPR_I2S8CH_SRST_N_SEL(0)); - clk_disable_unprepare(priv->clk); + pm_runtime_put_sync(dev); return 0; } @@ -669,15 +619,11 @@ static int light_i2s_8ch_resume(struct device *dev) struct light_i2s_priv *priv = dev_get_drvdata(dev); int ret; - if(!priv->regmap || priv->state == I2S_STATE_IDLE) { + if(!priv->regmap) { return 0; } - ret = clk_prepare_enable(priv->clk); - if (ret) { - dev_err(priv->dev, "clock enable failed %d\n", ret); - return ret; - } + pm_runtime_get_sync(dev); regmap_update_bits(priv->audio_cpr_regmap, CPR_IP_RST_REG, CPR_I2S8CH_SRST_N_SEL_MSK, CPR_I2S8CH_SRST_N_SEL(1)); @@ -695,6 +641,8 @@ static int light_i2s_8ch_resume(struct device *dev) regmap_write(priv->regmap, I2S_DIV3_LEVEL, priv->suspend_div3_level); regmap_write(priv->audio_cpr_regmap, CPR_PERI_DIV_SEL_REG, priv->cpr_peri_div_sel); + pm_runtime_put_sync(dev); + return ret; } #endif diff --git a/sound/soc/thead/light-i2s.c b/sound/soc/thead/light-i2s.c index c7e9d2b055af..43d763c75d5b 100644 --- a/sound/soc/thead/light-i2s.c +++ b/sound/soc/thead/light-i2s.c @@ -45,7 +45,7 @@ #define LIGHT_I2S_DMABUF_SIZE (64 * 1024) -#define LIGHT_RATES SNDRV_PCM_RATE_8000_384000 +#define LIGHT_RATES SNDRV_PCM_RATE_8000_192000 #define LIGHT_FMTS (SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8) #define LIGHT_AUDIO_PAD_CONFIG(idx) (i2s_priv->cfg_off + ((idx-25) >> 1) * 4) @@ -110,6 +110,7 @@ static void light_i2s_set_div_sclk(struct light_i2s_priv *chip, u32 sample_rate, } div0 = (div + div % sample_rate) / sample_rate / div_val; + writel(div0, chip->regs + I2S_DIV0_LEVEL); light_audio_cpr_set(chip, CPR_PERI_DIV_SEL_REG, CPR_AUDIO_DIV0_SEL_MSK, CPR_AUDIO_DIV0_SEL(cpr_div)); } @@ -235,7 +236,6 @@ static int light_i2s_dai_trigger(struct snd_pcm_substream *substream, int cmd, break; case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - regmap_read(priv->regmap, I2S_FUNCMODE, &priv->suspend_funcmode); if (tx) { dmaengine_pause(snd_dmaengine_pcm_get_chan(substream)); // work around for DMAC stop issue light_snd_txctrl(priv, 0); @@ -318,7 +318,7 @@ static int light_i2s_dai_hw_params(struct snd_pcm_substream *substream, struct s len = 32; break; case SNDRV_PCM_FORMAT_S24_LE: - val |= I2S_DATA_WIDTH_24BIT; + val |= I2S_DATA_24BIT_WIDTH_32BIT; len = 32; break; case SNDRV_PCM_FORMAT_S32_LE: @@ -650,8 +650,7 @@ static int light_i2s_suspend(struct device *dev) { struct light_i2s_priv *priv = dev_get_drvdata(dev); - if (priv->state == I2S_STATE_IDLE) - return 0; + pm_runtime_get_sync(dev); regmap_read(priv->regmap, I2S_DIV0_LEVEL, &priv->suspend_div0_level); regmap_read(priv->regmap, I2S_DIV3_LEVEL, &priv->suspend_div3_level); @@ -665,6 +664,7 @@ static int light_i2s_suspend(struct device *dev) regmap_read(priv->regmap, I2S_IMR, &priv->suspend_imr); regmap_read(priv->regmap, I2S_DMATDLR, &priv->suspend_dmatdlr); regmap_read(priv->regmap, I2S_DMARDLR, &priv->suspend_dmardlr); + regmap_read(priv->regmap, I2S_FUNCMODE, &priv->suspend_funcmode); if (strcmp(priv->name, AP_I2S)) { regmap_read(priv->audio_cpr_regmap, CPR_PERI_DIV_SEL_REG, &priv->cpr_peri_div_sel); @@ -679,7 +679,7 @@ static int light_i2s_suspend(struct device *dev) regmap_update_bits(priv->audio_cpr_regmap, CPR_IP_RST_REG, CPR_I2S2_SRST_N_SEL_MSK, CPR_I2S2_SRST_N_SEL(0)); } - clk_disable_unprepare(priv->clk); + pm_runtime_put_sync(dev); return 0; } @@ -689,14 +689,7 @@ static int light_i2s_resume(struct device *dev) struct light_i2s_priv *priv = dev_get_drvdata(dev); int ret; - if (priv->state == I2S_STATE_IDLE) - return 0; - - ret = clk_prepare_enable(priv->clk); - if (ret) { - dev_err(priv->dev, "clock enable failed %d\n", ret); - return ret; - } + pm_runtime_get_sync(dev); if (strcmp(priv->name, AP_I2S)) { if (!strcmp(priv->name, AUDIO_I2S0)) @@ -718,6 +711,8 @@ static int light_i2s_resume(struct device *dev) regmap_write(priv->regmap, I2S_DIV0_LEVEL, priv->suspend_div0_level); regmap_write(priv->regmap, I2S_DIV3_LEVEL, priv->suspend_div3_level); + pm_runtime_put_sync(dev); + return ret; } #endif diff --git a/sound/soc/thead/light-spdif.c b/sound/soc/thead/light-spdif.c index 2e839c6ff8bc..b8ae4e06f323 100644 --- a/sound/soc/thead/light-spdif.c +++ b/sound/soc/thead/light-spdif.c @@ -330,8 +330,7 @@ static int light_spdif_suspend(struct device *dev) { struct light_spdif_priv *priv = dev_get_drvdata(dev); - if (priv->state == SPDIF_STATE_IDLE) - return 0; + pm_runtime_get_sync(dev); regmap_read(priv->regmap, SPDIF_TX_EN, &priv->suspend_tx_en); regmap_read(priv->regmap, SPDIF_TX_CTL, &priv->suspend_tx_ctl); @@ -354,7 +353,7 @@ static int light_spdif_suspend(struct device *dev) CPR_IP_RST_REG, CPR_SPDIF1_SRST_N_SEL_MSK, CPR_SPDIF1_SRST_N_SEL(0)); } - clk_disable_unprepare(priv->clk); + pm_runtime_put_sync(dev); return 0; } @@ -364,14 +363,7 @@ static int light_spdif_resume(struct device *dev) struct light_spdif_priv *priv = dev_get_drvdata(dev); int ret; - if (priv->state == SPDIF_STATE_IDLE) - return 0; - - ret = clk_prepare_enable(priv->clk); - if (ret) { - dev_err(priv->dev, "clock enable failed %d\n", ret); - return ret; - } + pm_runtime_get_sync(dev); regmap_write(priv->audio_cpr_regmap, CPR_PERI_DIV_SEL_REG, priv->cpr_peri_div_sel); regmap_write(priv->audio_cpr_regmap, CPR_PERI_CTRL_REG, priv->cpr_peri_ctrl); @@ -395,6 +387,8 @@ static int light_spdif_resume(struct device *dev) regmap_write(priv->regmap, SPDIF_RX_CTL, priv->suspend_rx_ctl); regmap_write(priv->regmap, SPDIF_RX_DMA_EN, priv->suspend_rx_dma_en); + pm_runtime_put_sync(dev); + return ret; } #endif diff --git a/sound/soc/thead/light-tdm.c b/sound/soc/thead/light-tdm.c index 50efdaf620f9..26f510282923 100644 --- a/sound/soc/thead/light-tdm.c +++ b/sound/soc/thead/light-tdm.c @@ -123,6 +123,7 @@ static int light_tdm_set_fmt_dai(struct snd_soc_dai *dai, unsigned int fmt) if (priv->slot_num != 1) { return 0; } + printk("%s enter\n", __func__); pm_runtime_resume_and_get(priv->dev); @@ -354,10 +355,12 @@ static int light_tdm_suspend(struct device *dev) { struct light_tdm_priv *priv = dev_get_drvdata(dev); - if (priv->slot_num != 1 || priv->state == TDM_STATE_IDLE) { + if (priv->slot_num != 1) { return 0; } + pm_runtime_get_sync(dev); + regmap_read(priv->regmap, TDM_TDMCTL, &priv->suspend_tdmctl); regmap_read(priv->regmap, TDM_CHOFFSET1, &priv->suspend_choffset1); regmap_read(priv->regmap, TDM_CHOFFSET2, &priv->suspend_choffset2); @@ -377,7 +380,7 @@ static int light_tdm_suspend(struct device *dev) regmap_update_bits(priv->audio_cpr_regmap, CPR_IP_RST_REG, CPR_TDM_SRST_N_SEL_MSK, CPR_TDM_SRST_N_SEL(0)); - clk_disable_unprepare(priv->clk); + pm_runtime_put_sync(dev); return 0; } @@ -387,15 +390,10 @@ static int light_tdm_resume(struct device *dev) struct light_tdm_priv *priv = dev_get_drvdata(dev); int ret; - if (priv->slot_num != 1 || priv->state == TDM_STATE_IDLE) { + if (priv->slot_num != 1) { return 0; } - - ret = clk_prepare_enable(priv->clk); - if (ret) { - dev_err(priv->dev, "clock enable failed %d\n", ret); - return ret; - } + pm_runtime_get_sync(dev); regmap_write(priv->audio_cpr_regmap, CPR_PERI_DIV_SEL_REG, priv->cpr_peri_div_sel); regmap_write(priv->audio_cpr_regmap, CPR_PERI_CLK_SEL_REG, priv->cpr_peri_clk_sel); @@ -416,6 +414,8 @@ static int light_tdm_resume(struct device *dev) regmap_write(priv->regmap, TDM_DMADL, priv->suspend_dmadl); regmap_write(priv->regmap, TDM_DIV0_LEVEL, priv->suspend_div0level); + pm_runtime_put_sync(dev); + return ret; } #endif @@ -442,7 +442,7 @@ static int light_tdm_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int data_register, ret = 0; - + printk("%s enter\n", __func__); tdm_priv = devm_kzalloc(&pdev->dev, sizeof(struct light_tdm_priv), GFP_KERNEL); if (!tdm_priv) { return -ENOMEM;