From: Craig Topper <craig.topper@sifive.com>
Date: Thu, 23 Sep 2021 17:10:44 +0000 (-0700)
Subject: [RISCV] Add more tests for (and (srl x, C2), C1) that can be improved by using a... 
X-Git-Tag: upstream/15.0.7~30700
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=19734ae6f05498a75d4bb3960be06f5d704f8528;p=platform%2Fupstream%2Fllvm.git

[RISCV] Add more tests for (and (srl x, C2), C1) that can be improved by using a pair of shifts. NFC

These tests have C1 as a shifted mask having C2 leading zeros and some
number of trailing zeros, C3. We can select this as
(slli (srli x, C2+C3), C3) or (slli (srliw x, C2+C3), C3).
---

diff --git a/llvm/test/CodeGen/RISCV/shift-and.ll b/llvm/test/CodeGen/RISCV/shift-and.ll
new file mode 100644
index 0000000..9eefb18
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/shift-and.ll
@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I
+
+; Test for handling of AND with constant followed by a shift by constant. Often
+; we can replace these with a pair of shifts to avoid materializing a constant
+; for the and.
+
+define i32 @test1(i32 %x) {
+; RV32I-LABEL: test1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 5
+; RV32I-NEXT:    andi a0, a0, -8
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 5
+; RV64I-NEXT:    lui a1, 32768
+; RV64I-NEXT:    addiw a1, a1, -8
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = lshr i32 %x, 5
+  %b = and i32 %a, 134217720
+  ret i32 %b
+}
+
+define i64 @test2(i64 %x) {
+; RV32I-LABEL: test2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a2, a1, 27
+; RV32I-NEXT:    srli a0, a0, 5
+; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    srli a1, a1, 5
+; RV32I-NEXT:    andi a0, a0, -8
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 5
+; RV64I-NEXT:    andi a0, a0, -8
+; RV64I-NEXT:    ret
+  %a = lshr i64 %x, 5
+  %b = and i64 %a, 576460752303423480
+  ret i64 %b
+}
+
+define i32 @test3(i32 %x) {
+; RV32I-LABEL: test3:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a0, a0, 6
+; RV32I-NEXT:    lui a1, 16380
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 6
+; RV64I-NEXT:    lui a1, 16380
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = lshr i32 %x, 6
+  %b = and i32 %a, 67092480
+  ret i32 %b
+}
+
+define i64 @test4(i64 %x) {
+; RV32I-LABEL: test4:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a2, a1, 26
+; RV32I-NEXT:    srli a0, a0, 6
+; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    srli a1, a1, 6
+; RV32I-NEXT:    lui a2, 1048572
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test4:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 6
+; RV64I-NEXT:    lui a1, 1048572
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = lshr i64 %x, 6
+  %b = and i64 %a, 288230376151695360
+  ret i64 %b
+}