From: Bjorn Helgaas Date: Thu, 15 Oct 2020 19:30:30 +0000 (-0500) Subject: PCI/ASPM: Use 'parent' and 'child' for readability X-Git-Tag: v5.10.7~1352^2~25^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=190cd42cc1db1d7c9f3f326e03f74d1c7a3a4588;p=platform%2Fkernel%2Flinux-rpi.git PCI/ASPM: Use 'parent' and 'child' for readability Other users of link->pdev and link->downstream, e.g., pcie_aspm_cap_init(), pcie_config_aspm_l1ss(), and pcie_config_aspm_link(), use "parent" and "child" as local names. Do the same in aspm_calc_l1ss_info() for readability. No functional change intended. Link: https://lore.kernel.org/r/20201015193039.12585-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas --- diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 386b45e..0725511 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -501,6 +501,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, struct aspm_register_info *upreg, struct aspm_register_info *dwreg) { + struct pci_dev *child = link->downstream, *parent = link->pdev; u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; @@ -522,13 +523,13 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - if (calc_l1ss_pwron(link->pdev, scale1, val1) > - calc_l1ss_pwron(link->downstream, scale2, val2)) { + if (calc_l1ss_pwron(parent, scale1, val1) > + calc_l1ss_pwron(child, scale2, val2)) { link->l1ss.ctl2 |= scale1 | (val1 << 3); - t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); + t_power_on = calc_l1ss_pwron(parent, scale1, val1); } else { link->l1ss.ctl2 |= scale2 | (val2 << 3); - t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); + t_power_on = calc_l1ss_pwron(child, scale2, val2); } /*