From: Doug Evans Date: Mon, 19 Jan 1998 21:14:14 +0000 (+0000) Subject: * Make-common.in (cgen-{arch,cpu,decode}): New targets. X-Git-Tag: gdb-4_18~3815 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=189e2694ad699b902669c1bc4b3c0112223d3282;p=external%2Fbinutils.git * Make-common.in (cgen-{arch,cpu,decode}): New targets. * cgen.sh: New file. * cgen-scache.h: Deleted. * cgen-scache.c: Only compile contents if WITH_SCACHE. (scache_init): Use runtime computed size of SCACHE. (scache_flush): Likewise. * cgen-mem.h (GETIMEMU[QHSD]I): Declare. ([GS]ETT{QI,UQI,HI,UHI,SI,USI,DI,UDI}): Declare. * cgen-sim.h: Scache support moved here. (PC): Redo definition. (ARGBUF,SCACHE,PARALLEL_EXEC): Provide forward decls. (DECODE): Add parallel execution support. Only include semantic label members if using switch. (SWITCH,CASE,BREAK,DEFAULT,ENDSWITCH): Portable computed goto support. (CGEN_CPU): Delete members exec_state, halt_sigrc, halt_jmp_buf. (IADDR,CIA,SEM_ARG,EX_FN_NAME,SEM_FN_NAME,RECORD_IADDR,SEM_ARGBUF, SEM_NEXT_PC,SEM_BRANCH_VIA_{CACHE,ADDR},SEM_NEW_PC_ADDR): Moved here from cgen-types.h. (engine_{stop,run,resume,halt,signal}): Delete decls. * cgen-types.h (CGEN_{XCAT3,CAT3}): Delete. (argbuf,scache): Delete forward decls. (STATE): Delete decl. * cgen-utils.c: Don't include decode.h, mem-ops.h, sem-ops.h. Include cgen-mem.h, cgen-ops.h. (engine_halt,engine_signal): Delete. ({ex,exc,sem,semc}_illegal): Delete. (sim_disassemble_insn): Result of extract fn is in bits. * genmloop.sh: Rewrite. --- diff --git a/sim/common/.Sanitize b/sim/common/.Sanitize index 3490715..fc5d179 100644 --- a/sim/common/.Sanitize +++ b/sim/common/.Sanitize @@ -28,10 +28,10 @@ Make-common.in Makefile.in aclocal.m4 callback.c +cgen.sh cgen-mem.h cgen-ops.h cgen-scache.c -cgen-scache.h cgen-sim.h cgen-trace.c cgen-trace.h diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index acfabae..59408c3 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,47 @@ +Mon Jan 19 12:45:45 1998 Doug Evans + + * Make-common.in (cgen-{arch,cpu,decode}): New targets. + * cgen.sh: New file. + * cgen-scache.h: Deleted. + * cgen-scache.c: Only compile contents if WITH_SCACHE. + (scache_init): Use runtime computed size of SCACHE. + (scache_flush): Likewise. + * cgen-mem.h (GETIMEMU[QHSD]I): Declare. + ([GS]ETT{QI,UQI,HI,UHI,SI,USI,DI,UDI}): Declare. + * cgen-sim.h: Scache support moved here. + (PC): Redo definition. + (ARGBUF,SCACHE,PARALLEL_EXEC): Provide forward decls. + (DECODE): Add parallel execution support. + Only include semantic label members if using switch. + (SWITCH,CASE,BREAK,DEFAULT,ENDSWITCH): Portable computed goto support. + (CGEN_CPU): Delete members exec_state, halt_sigrc, halt_jmp_buf. + (IADDR,CIA,SEM_ARG,EX_FN_NAME,SEM_FN_NAME,RECORD_IADDR,SEM_ARGBUF, + SEM_NEXT_PC,SEM_BRANCH_VIA_{CACHE,ADDR},SEM_NEW_PC_ADDR): Moved here + from cgen-types.h. + (engine_{stop,run,resume,halt,signal}): Delete decls. + * cgen-types.h (CGEN_{XCAT3,CAT3}): Delete. + (argbuf,scache): Delete forward decls. + (STATE): Delete decl. + * cgen-utils.c: Don't include decode.h, mem-ops.h, sem-ops.h. + Include cgen-mem.h, cgen-ops.h. + (engine_halt,engine_signal): Delete. + ({ex,exc,sem,semc}_illegal): Delete. + (sim_disassemble_insn): Result of extract fn is in bits. + * genmloop.sh: Rewrite. + + * cgen-trace.c (trace_insn): Set printed_result_p=0 if not tracing + line numbers. + + * sim-base.h (sim_state_base): Delete member `model'. + (sim_cpu_base): Add member `model'. + * sim-model.h (IMP_PROPERTIES): New type. + (MACH): New members imp_props, models. + (models): Delete decl. + * sim-model.c (set_model): Update. + * sim-profile.c (profile_print_model): Update. + + * sim-utils.c (sim_state_alloc): Delete setting of cpu backlink here. + Fri Jan 16 12:33:09 1998 Nick Clifton * cgen-trace.c (trace_insn): Call CGEN_INSN_MNEMONIC() rather than diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in index fb1cf8f..9ed1bb3 100644 --- a/sim/common/Make-common.in +++ b/sim/common/Make-common.in @@ -300,10 +300,11 @@ sim-bits.o: $(srccom)/sim-bits.c $(sim-bits_h) $(sim-n-bits_h) \ $(CC) -c $(srccom)/sim-bits.c $(ALL_CFLAGS) sim-config.o: $(srccom)/sim-config.c $(sim-config_h) \ - $(SIM_EXTRA_DEPS) + $(SIM_EXTRA_DEPS) $(CC) -c $(srccom)/sim-config.c $(ALL_CFLAGS) -sim-core.o: $(srccom)/sim-core.c $(sim-core_h) $(sim-n-core_h) \ +sim-core.o: $(srccom)/sim-core.c $(sim_main_headers) \ + $(sim-core_h) $(sim-n-core_h) \ $(SIM_EXTRA_DEPS) $(CC) -c $(srccom)/sim-core.c $(ALL_CFLAGS) @@ -478,4 +479,51 @@ stamp-h: config.in config.status .gdbinit: # config.status $(srccom)/gdbinit.in CONFIG_FILES=$@:../common/gdbinit.in CONFIG_HEADERS= $(SHELL) ./config.status +# CGEN support + +SCHEME = @SCHEME@ +SCHEME = guile-ss +SCHEME = guile +#SCHEMEFLAGS = -b +SCHEMEFLAGS = -s +srccgen = $(srcroot)/cgen + +CGEN_VERBOSE = -v +CGEN_MAIN_SCM = $(srccgen)/object.scm \ + $(srccgen)/utils.scm $(srccgen)/utils-cgen.scm \ + $(srccgen)/mode.scm \ + $(srccgen)/cpu.scm $(srccgen)/mach.scm \ + $(srccgen)/ifield.scm $(srccgen)/iformat.scm \ + $(srccgen)/operand.scm $(srccgen)/insn.scm \ + $(srccgen)/sim.scm +CGEN_CPU_SCM = $(srccgen)/sim-cpu.scm $(srccgen)/sem-ccode.scm +CGEN_DECODE_SCM = $(srccgen)/decode.scm + +# Various choices for which cpu specific files to generate. +CGEN_CPU_EXTR = -E tmp-ext.c1 +CGEN_CPU_READ = -R tmp-read.c1 +CGEN_CPU_SEM = -S tmp-sem.c1 +CGEN_CPU_SEMSW = -W tmp-semsw.c1 + +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter with gdb/binutils. Maybe we never will. + +cgen-arch: force + $(SHELL) $(srccom)/cgen.sh arch $(srcdir) \ + $(SCHEME) $(SCHEMEFLAGS) \ + $(srccgen) $(CGEN_VERBOSE) \ + $(arch) "$(FLAGS)" ignored ignored ignored ignored + +cgen-cpu: force + $(SHELL) $(srccom)/cgen.sh cpu $(srcdir) \ + $(SCHEME) $(SCHEMEFLAGS) \ + $(srccgen) $(CGEN_VERBOSE) \ + $(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" "$(EXTRAFILES)" + +cgen-decode: force + $(SHELL) $(srccom)/cgen.sh decode $(srcdir) \ + $(SCHEME) $(SCHEMEFLAGS) \ + $(srccgen) $(CGEN_VERBOSE) \ + $(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" ignored + ## End COMMON_POST_CONFIG_FRAG diff --git a/sim/common/cgen.sh b/sim/common/cgen.sh new file mode 100644 index 0000000..00baa04 --- /dev/null +++ b/sim/common/cgen.sh @@ -0,0 +1,125 @@ +#! /bin/sh +# Generate CGEN simulator files. +# +# Usage: /bin/sh cgen.sh {"arch"|"cpu"|"decode"} srcdir \ +# scheme schemeflags \ +# cgendir cgenflags \ +# arch archflags cpu mach suffix extrafiles +# +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter with gdb/binutils. Maybe we never will. + +# We want to behave like make, any error forces us to stop. +set -e + +action=$1 +srcdir=$2 +scheme=$3 +schemeflags=$4 +cgendir=$5 +cgenflags=$6 +arch=$7 +archflags=$8 +cpu=$9 +mach=${10} +suffix=${11} +extrafiles=${12} + +lowercase='abcdefghijklmnopqrstuvwxyz' +uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +# FIXME: May have to rewrite this. +ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"` +CPU=`echo ${cpu} | tr "${lowercase}" "${uppercase}"` + +rootdir=${srcdir}/../.. + +case $action in +arch) + rm -f tmp-arch.h1 tmp-arch.h + rm -f tmp-arch.c1 tmp-arch.c + rm -f tmp-all.h1 tmp-all.h + + ${scheme} ${schemeflags} ${cgendir}/cgen-sim.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${archflags}" \ + -m all \ + -a ${arch} \ + -A tmp-arch.h1 \ + -B tmp-arch.c1 \ + -N tmp-all.h1 + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-arch.h1 > tmp-arch.h + ${rootdir}/move-if-change tmp-arch.h ${srcdir}/arch.h + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-arch.c1 > tmp-arch.c + ${rootdir}/move-if-change tmp-arch.c ${srcdir}/arch.c + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-all.h1 > tmp-all.h + ${rootdir}/move-if-change tmp-all.h ${srcdir}/cpuall.h + + rm -f tmp-arch.h1 tmp-arch.c1 tmp-all.h1 + ;; + +cpu) + rm -f tmp-cpu.h1 tmp-ext.c1 tmp-read.c1 tmp-sem.c1 tmp-semsw.c1 tmp-mod.c1 + rm -f tmp-cpu.h tmp-ext.c tmp-read.c tmp-sem.c tmp-semsw.c tmp-mod.c + + ${scheme} ${schemeflags} ${cgendir}/cgen-sim.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${archflags}" \ + -m ${mach} \ + -a ${arch} \ + -C tmp-cpu.h1 \ + -M tmp-mod.c1 \ + ${extrafiles} + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-cpu.h1 > tmp-cpu.h + ${rootdir}/move-if-change tmp-cpu.h ${srcdir}/cpu${suffix}.h + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-mod.c1 > tmp-mod.c + ${rootdir}/move-if-change tmp-mod.c ${srcdir}/model${suffix}.c + if test -f tmp-ext.c1 ; then \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-ext.c1 > tmp-ext.c ; \ + ${rootdir}/move-if-change tmp-ext.c ${srcdir}/extract${suffix}.c ; \ + fi + if test -f tmp-read.c1 ; then \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-read.c1 > tmp-read.c ; \ + ${rootdir}/move-if-change tmp-read.c ${srcdir}/read${suffix}.c ; \ + fi + if test -f tmp-sem.c1 ; then \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-sem.c1 > tmp-sem.c ; \ + ${rootdir}/move-if-change tmp-sem.c ${srcdir}/sem${suffix}.c ; \ + fi + if test -f tmp-semsw.c1 ; then \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-semsw.c1 > tmp-semsw.c ; \ + ${rootdir}/move-if-change tmp-semsw.c ${srcdir}/sem${suffix}-switch.c ; \ + fi + + rm -f tmp-cpu.h1 tmp-mod.c1 + rm -f tmp-read.c1 tmp-ext.c1 tmp-sem.c1 tmp-semsw.c1 + ;; + +decode) + rm -f tmp-dec.h1 tmp-dec.h tmp-dec.c1 tmp-dec.c + + ${scheme} ${schemeflags} ${cgendir}/cgen-sim.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${archflags}" \ + -m ${mach} \ + -a ${arch} \ + -T tmp-dec.h1 \ + -D tmp-dec.c1 + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-dec.h1 > tmp-dec.h + ${rootdir}/move-if-change tmp-dec.h ${srcdir}/decode${suffix}.h + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@CPU@/${CPU}/g" -e "s/@cpu@/${cpu}/g" < tmp-dec.c1 > tmp-dec.c + ${rootdir}/move-if-change tmp-dec.c ${srcdir}/decode${suffix}.c + + rm -f tmp-dec.h1 tmp-dec.c1 + ;; + +*) + echo "cgen.sh: bad action: ${action}" >&2 + exit 1 + ;; + +esac + +exit 0